LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 LP3950 Color LED Driver with Audio Synchronizer CheckforSamples:LP3950 FEATURES DESCRIPTION 1 • AudioSynchronizationforColorLEDswith The LP3950 is a color LED driver with a built-in audio 2 synchronization feature for any analog audio input TwoModes:AmplitudeandFrequency such as polyphonic ring tones and MP3 music. LEDs • ProgrammableFrequencyandAmplitude can be synchronized to an audio signal with two ResponsewithTrackingSpeedControl methods - amplitude and frequency. Also several fine • AutomaticGainControlorSelectableGainfor tuning options are available for differentiation InputSignalOptimization purposes. The chip also has an unique AGC (Automatic Gain Control) feature which tracks the • RGBPatternGeneratorSimilarto input signal level and automatically adjusts the gain LP3933/LP3936 toanoptimalvalue. • MagneticDC-DCBoostConverterwith The LP3950 has a high efficiency magnetic DC/DC ProgrammableBoostOutputVoltage converter with programmable output voltage and • SelectableSPIorI2CCompatibleInterface switching frequency. The converter has high output • OnePinDefaultEnableforNon-SerialInterface current capability so it is also able to drive flash LEDs Users.OnePinSelectorforSynchronization incameraphoneapplications. Mode The LP3950 is similar to LP3933 and LP3936 in that • SpaceEfficient32-PinTLGAPackage the color LEDs (or RGB LEDs) can also be programmed to generate light patterns APPLICATIONS (programmable color, intensity, on/off timing, slope andblinkingcycle). • CellularPhones All functions are software controllable through a SPI • MP3/CD/MinidiscPlayers or I2C compatible interface but the device also • Toys supports one pin control for enabling predefined (default)audiosynchronizationmode. Typical Application 2.8V VIN L1 CVDD1 CVDD2 CVDDA CIN 4.7 PH D1 100 nF 100 nF 100 nF 10 PF C1 VDD1 VDD2 VDDA SINGLE-ENDED ASE SW AUDIO SIGNAL 10 nF FB COUT C2 RR1 10 PF R1 AD1 RG1 DIFFERENTIAL 10 nF G1 AUDIO SIGNAL C3 RB1 AD2 B1 10 nF LP3950 RR2 4 R2 SERIAL RG2 INTERFACE G2 NRST RB2 B2 MICROCONTROLLER PWM_LED RT RT IF_SEL 82k VREF VDD_IO CVREF 100 nF DME AMODE GNDs CVDD_IO 100 nF 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2004–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Connection Diagrams TopView BottomView Figure1. 32-LeadTLGAPackage 4.5x5.5x0.8mm,0.5mmPitch,SeePackageNumberNPC0032A 2 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 PINDESCRIPTIONS Pin# Name Type Description 1 FB Input Boostconverterfeedback. 2 GND_BOOST Ground Powerswitchground. 3 SW Output Opendrain,boostconverterpowerswitch. 4 V Power Supplyvoltageforinternaldigitalcircuits. DD2 5 GND2 Ground GroundreturnforV (internaldigital). DD2 6 DME LogicInput Defaultmodeenable(internalpulldown1MΩ). 7 AMODE LogicInput Audiomodeselection(internalpulldown1MΩ). 8 V Power Supplyvoltageforaudiocircuits. DDA 9 ASE Input Analogaudioinput,single-ended. 10 AD1 Input Analogaudioinput,differential. 11 AD2 Input Analogaudioinput,differential. 12 GNDA Ground Groundforanalogaudioinputs. 13 RT Input Oscillatorresistor. 14 V Power Supplyvoltageforinternalanalogcircuits. DD1 15 GND1 Ground Ground. 16 V Output Internalreferencebypasscapacitor. REF 17 GND3 Ground Ground. 18 NRST LogicInput Lowactiveresetinput. 19 SS/SDA LogicI/O SPIslaveselect/I2Cdataline. 20 SO LogicOutput SPIserialdataoutput. 21 SI LogicInput SPIserialdatainput. 22 SCK/SCL LogicInput SPI/I2Cclock. 23 PWM_LED LogicInput DirectPWMcontrolforLEDs. 24 V Power SupplyvoltageforlogicIOsignals. DDIO 25 IF_SEL LogicInput SPI/I2Cselect(IF_SEL=1inSPImode). 26 B2 Output Opendrainoutput,blueLED2. 27 G2 Output Opendrainoutput,greenLED2. 28 R2 Output Opendrainoutput,redLED2. 29 GND_RGB Ground RGBdriverground. 30 R1 Output Opendrainoutput,redLED1. 31 G1 Output Opendrainoutput,greenLED1. 32 B1 Output Opendrainoutput,blueLED1. Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Absolute Maximum Ratings(1)(2)(3) V(SW,FB,R1–2,G1–2,B1–2) (4) (5) −0.3Vto+7.2V V ,V ,V ,V −0.3Vto+6.0V DD1 DD2 DDIO DDA VoltageonASE,AD1,AD2 −0.3VtoV +0.3Vwith6.0Vmax DD1 VoltageonLogicPins −0.3VtoV +0.3Vwith6.0Vmax DD_IO I(R1,G1,B1,R2,G2,B2) (6) 150mA I(V ) 10µA REF ContinuousPowerDissipation (7) InternallyLimited JunctionTemperature(T ) 125°C J-MAX StorageTemperatureRange −65°Cto+150°C MaximumLeadTemperature 260°C (Reflowsoldering,3times) (8) ESDRating (9) HumanBodyModel: 2kV MachineModel: 200V (1) AllvoltagesarewithrespecttothepotentialattheGNDpins(GND1–3,GND_BOOST,GND_RGB,GNDA). (2) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothecomponentmayoccur.OperatingRatingsareconditionsunder whichoperationofthedeviceisguaranteed.OperatingRatingsdonotimplyguaranteedperformancelimits.Forguaranteed performancelimitsandassociatedtestconditions,seetheElectricalCharacteristicstables. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications. (4) Battery/Chargervoltageshouldbeabove6.0Vnomorethan10%oftheoperationallifetime. (5) VoltagetoleranceofLP3950above6.0VreliesonfactthatV ,V andV (2.8V)areavailable(ON)atallconditions.IfV , DD1 DD2 DDA DD1 V andV arenotavailable(ON)atallconditions,TexasInstrumentsdoesnotguaranteeanyparametersorreliabilityforthis DD2 DDA device.Also,V ,V andV mustbeatthesameelectricpotential. DD1 DD2 DDA (6) Thetotalloadcurrentoftheboostconvertershouldbelimitedto300mA. (7) Internalthermalshutdowncircuitryprotectsthedevicefrompermanentdamage.ThermalshutdownengagesatT =160°C(typ.)and J disengagesatT =140°C(typ.). J (8) Fordetailedpackageandsolderingspecificationsandinformation,pleaserefertoTexasInstrumentsApplicationNote1125(SNAA002): LaminateCSP/FBGA. (9) TheHumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin.Themachinemodelisa200pF capacitordischargeddirectlyintoeachpin.MIL-STD-8833015.7 Operating Ratings(1)(2) V(SW,FB,R1–2,G1–2,B1–2) 0Vto6.0V V ,V ,V (3) 2.7Vto2.9V DD1 DD2 DDA V 1.65VtoV V DDIO DD1,2 VoltageonASE,AD1,AD2 0.1VtoV -0.1V DD1 RecommendedLoadCurrent 0mAto300mA JunctionTemperature(T)Range −40°Cto+125°C J AmbientTemperature(T )Range (4) −40°Cto+85°C A (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothecomponentmayoccur.OperatingRatingsareconditionsunder whichoperationofthedeviceisguaranteed.OperatingRatingsdonotimplyguaranteedperformancelimits.Forguaranteed performancelimitsandassociatedtestconditions,seetheElectricalCharacteristicstables. (2) AllvoltagesarewithrespecttothepotentialattheGNDpins(GND1–3,GND_BOOST,GND_RGB,GNDA). (3) VoltagetoleranceofLP3950above6.0VreliesonfactthatV ,V andV (2.8V)areavailable(ON)atallconditions.IfV , DD1 DD2 DDA DD1 V andV arenotavailable(ON)atallconditions,TexasInstrumentsdoesnotguaranteeanyparametersorreliabilityforthis DD2 DDA device.Also,V ,V andV mustbeatthesameelectricpotential. DD1 DD2 DDA (4) Inapplicationswherehighpowerdissipationand/orpoorpackagethermalresistanceispresent,themaximumambienttemperaturemay havetobederated.Maximumambienttemperature(T )isdependentonthemaximumoperatingjunctiontemperature(T = A-MAX J-MAX-OP 125°C),themaximumpowerdissipationofthedeviceintheapplication(P ),andthejunction-toambientthermalresistanceofthe D-MAX part/packageintheapplication(θ ),asgivenbythefollowingequation:T =T −(θ xP ). JA A-MAX J-MAX-OP JA D-MAX 4 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Thermal Properties Junction-to-AmbientThermalResistance 72°C/W (θ ),NPC0032APackage (1) JA (1) Junction-to-ambientthermalresistanceishighlyapplicationandboard-layoutdependent.Inapplicationswherehighmaximumpower dissipationexists,specialcaremustbepaidtothermaldissipationissuesinboarddesign. Electrical Characteristics (1)(2) LimitsinstandardtypefaceareforT =+25°C.Limitsinboldfacetypeapplyovertheoperatingambienttemperaturerange J (−40°C≤T ≤+85°C).Unlessotherwisenoted,specificationsapplytoFigure2with:V =V =V =2.8V,C = A DD1 DD2 DDA VDD1 C =C =C =100nF,C =C =10µF,C =100nF,L =4.7µHandf =2.0MHz (3). VDD2 VDDA VDDIO OUT IN VREF 1 BOOST Symbol Parameter Condition Min Typ Max Units I StandbySupplyCurrent NSTBY=L(register) 1 5 µA VDD (V +V +V current) SCK,SS,SI,NRST=H DD1 DD2 DDA No-LoadSupplyCurrent NSTBY=H(reg.) 300 400 µA (V +V +V current,boostoff) EN_BOOST=L(reg.) DD1 DD2 DDA SCK,SS,SI,NRST=H FullLoadSupplyCurrent NSTBY=H(reg.) 850 µA (V +V +V current,booston)(4) EN_BOOST=H(reg.) DD1 DD2 DDA SCK,SS,SI,NRST=H AllOutputsActive I V SupplyCurrent 1.0MHzSCKFrequency 20 µA VDDIO DDIO C =50pFatSOPin L I AudioCircuitrySupplyCurrent(5) INPUT_SEL=[10](register) 550 µA VDDA V ReferenceVoltage(6) I ≤1.0nAOnlyforTestPurpose 1.230 V REF REF (1) AllvoltagesarewithrespecttothepotentialattheGNDpins(GND1–3,GND_BOOST,GND_RGB,GNDA). (2) MinandMaxlimitsareguaranteedbydesign,test,orstatisticalanalysis.Typicalnumbersarenotguaranteed,butdorepresentthe mostlikelynorm. (3) Low-ESRSurface-MountCeramicCapacitorsareusedinsettingelectricalcharacteristics. (4) Audioblockinactive. (5) Insingle-endedandindifferentialmodeoneaudiobufferonlyisactiveandI willbereducedby90µA(typ). VDDA (6) V pin(Bandgapreferenceoutput)isforinternaluseonly.AcapacitorshouldalwaysbeplacedbetweenV andGND1. REF REF Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Block Diagram IMAX = 300 mA 2L.D8OV 1C0V0D nDF1 1C0V0D nDF2 C10V0D DnAF BATTERY -+ 10C IPNF VOLU1T = 4.1V TO 5.3V 4.7 PH VDD1 VDD2 VDDA D1 SW VREF CVREF OSC THSD FB COUT 10 PF 100 nF GND_BOOST RT LP3950 SINGLE ENDED RT VREF EN BOOST AUDIO SIGNAL 82k 10 nF ASE FREQ R1 RR1 10 nF AD1 ADC AGC PWM RG1 AMPL G1 AD2 10 nF RB1 B1 GNDA D ADUIFDFIEOR SEINGTNIAALL SPI RGB PATTERN RIVE R2 RR2 CTRL R I2C GENERATOR S RG2 G2 RB2 B2 LEVEL SHIFTER GND_RGB IF_SEL SCK/SCL SS/SDA SI SO NRST WM_LED DME AMODE VDDIO GND1 GND2 GND3 P MICROCONTROLLER CVDDIO 100 nF Figure2. LP3950BlockDiagram Modes of Operation RESET: IntheRESETmodealltheinternalregistersareresettothedefaultvalues.RESETisenteredalwaysif inputNRSTisLOWorinternalPowerOnResetisactive. STANDBY: TheSTANDBYmodeisenterediftheregisterbitNSTBYisLOWandRESETisnotactive.Thisis thelowpowerconsumptionmode,whenallthecircuitfunctionsaredisabled.Registerscanbewrittenin thismodeandthecontrolbitsareeffectiveimmediatelyafterstartup. STARTUP: INTERNALSTARTUPSEQUENCEpowersupalltheneededinternalblocks(V ,oscillator,etc.). REF Toensurethecorrectoscillatorinitialization,a10msdelayisgeneratedbytheinternalstate-machine. Thermalshutdown(THSD)disablesthechipoperationandStartupmodeisentereduntilnothermal shutdowneventispresent. BOOSTSTARTUP:SoftstartforboostoutputisgeneratedintheBOOSTSTARTUPmode.Inthismodethe boostoutputisraisedinPFMmodeduringthe10msdelaygeneratedbythestate-machine.AllRGB outputsareoffduringthe10msdelaytoensuresmoothstartup.TheBooststartupisenteredfrom InternalStartupSequenceifEN_BOOSTisHIGHorfromNormalmodewhenEN_BOOSTiswritten HIGH. NORMAL: DuringtheNORMALmodetheusercontrolsthechipusingthecontrolregisters.Registerscanbe writteninanysequenceandanynumberofbitscanbealteredinaregisterwithinonewritecycle.Ifthe defaultmodeisselected,defaultcontrolregistervaluesareused. 6 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 RESET NRST = L or NSTBY=L and POR = H DME=L and NRST=H STANDBY (NSTBY=aHn do r DME=H) (NSTBY=H or DME=H) NSaTnBdY=L and NRST=H DME=L NRST=H and NRST=H INTERNAL STARTUP SEQUENCE THSD = H VREF = 95% OK1 ~10 ms DELAY DME=H or DME=L and EN_BOOST=H1 EN_BOOST = L1 BOOST STARTUP EN_BOOST RISING EDGE1 ~10 ms DELAY NORMAL MODE 1) THSD = L Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Logic Interface Characteristics(1) Symbol Parameter Conditions Min Typ Max Units LOGICINPUTSSS,SI,SCK/SCL,PWM_LED,IF_SEL V InputLowLevel 0.5 V IL V InputHighLevel V −0.5 V IH DDIO I LogicInputCurrent −1.0 1.0 µA I f ClockFrequency I2CMode 400 kHz SCL SPIMode 8 MHz LOGICOUTPUTSO V OutputLowLevel I =3.0mA 0.3 0.5 V OL SO V OutputHighLevel I =−3.0mA V −0.5 V −0.3 V OH SO DDIO DDIO I OutputLeakageCurrent V =2.8V 1.0 µA L SO LOGICI/OSDA V OutputLowLevel I =3.0mA 0.3 0.5 V OL SDA LOGICINPUTSDME,AMODE(Internalpulldown1MΩ) V InputLowLevel 0.5 V IL V InputHighLevel V −0.5 V IH DDIO I LogicInputCurrent −1.0 6.0 µA I (1) (1.80V≤V ≤V V).LimitsinstandardtypefaceareforT =+25°C.Limitsinboldfacetypeapplyovertheoperatingambient DDIO DD1,2 J temperaturerange(−40°C≤T ≤+85°C). A Logic Interface Characteristics, Low I/O Voltage(1) Symbol Parameter Conditions Min Typ Max Units LOGICINPUTSSCL,PWM_LED,IF_SEL V InputLowLevel 0.35 V IL V InputHighLevel V −0.35 V IH DDIO I LogicInputCurrent −1.0 1.0 µA I f ClockFrequency I2CMode 200 kHz SCL LOGICI/OSDA V OutputLowLevel I =3.0mA 0.3 0.5 V OL SDA LOGICINPUTSDME,AMODE(Internalpulldown1MΩ) V InputLowLevel 0.35 V IL V InputHighLevel V −0.35 V IH DDIO I LogicInputCurrent −1.0 6.0 µA I (1) (1.65V≤V <1.80V).I2Ccompatibleinterfaceonly. DDIO Logic Input NRST Characteristics(1) Symbol Parameter Conditions Min Typ Max Units V InputLowLevel 0.5 V IL V InputHighLevel 1.3 V IH I LogicInputCurrent −1.0 1.0 µA I t ResetPulseWidth Note:Guaranteedby NRST 10 µs design (1) (1.65V≤V ≤V V). DDIO DD1,2 8 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Control Interface TheLP3950supportsthreedifferentinterfacemodes: 1. SPIinterface(4wire,serial) 2. I2Ccompatibleinterface(2wire,serial) 3. Directenable(2wire,enablelines) User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both interfacemodes.NotethatthepinconfigurationswillbebasedonthestatusoftheIF_SELpin. IF_SEL Interface PinConfiguration Comment HIGH SPI SCK (clock) SI (datain) SO (dataout) SS (chipselect) LOW I2CCompatible SCL (clock) UsepullupresistorforSCL. SDA (datain/out) UsepullupresistorforSDA. SI (I2address) SIHIGH→addressis51'h; SO (NC) SILOW→addressis50'h; UnusedpinSOcanbeleftunconnected. SPI Interface The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO output is normally in high-impedance state and it is active only during when data is sent out during a read cycle. A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current consumptioninthecircuitry. The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be low during the cycle transmission. SS resets the interface when high and it has to be taken high between successive cycles. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the fallingedgeofSCK. SS SCK SI A6 A5 A4 A3 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0 R/W SO Figure3. SPIWriteCycle SS SCK R/W SI A6 A5 A4 A3 A2 A1 A0 0 Don't Care SO D7 D6 D5 D4 D3 D2 D1 D0 Figure4. SPIReadCycle Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com SS 2 1 5 3 12 4 SCK 7 6 SI MSB IN BIT 14 BIT 9 BIT 8 BIT 7 BIT 1 LSB IN 8 10 11 9 SO MSB OUT BIT 1 LSB OUT Address R/W Data Figure5. SPITimingDiagram Table1.SPITimingParameters(1) Limit Symbol Parameter Units Min Max 1 CycleTime 80 ns 2 EnableLeadTime 40 ns 3 EnableLagTime 40 ns 4 ClockLowTime 40 ns 5 ClockHighTime 40 ns 6 DataSetupTime 0 ns 7 DataHoldTime 20 ns 8 DataAccessTime 27 ns 9 OutputDisableTime 27 ns 10 OutputDataValid 37 ns 11 OutputDataHoldTime 0 ns 12 SSInactiveTime 15 ns (1) Dataguaranteedbydesign. I2C Compatible Interface I2CSIGNALS In I2C compatible mode, the LP3950 pin SCL is used for the I2C clock and the SDA pin is used for the I2C data. Both these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the capacitance of the bus (typ. 1.8k). Signal timing specifications are shown in Table 2. Unused pin SO can be left unconnected and pin SI must be connected to V or GND (address selector). Maximum bit DDIO rate is 400 kbit/s (V 1.80V to V V). I2C compatible interface can be used down to 1.65 V with DDIO DD1,2 DDIO maximumbitrateof200kbit/s. I2CDATAVALIDITY The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state ofthedatalinecanonlybechangedwhenCLKisLOW. SCL SDA data data data data data change valid change valid change allowed allowed allowed Figure6. I2CSignals:DataValidity 10 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 I2CSTARTANDSTOPCONDITIONS STARTandSTOPbitsclassifythebeginningandtheendoftheI2Csession.STARTconditionisdefinedasSDA signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, the I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. SDA SCL S P START condition STOPcondition Figure7. StartandStopConditions TRANSFERRINGDATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressedmustgenerateanacknowledgeaftereachbytehasbeenreceived. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3950 address is 50'h or 51'h. The selection of the address is done by connecting SI pin to V (51 hex) or GND (50 hex). For the eighth bit, a “0” indicates a WRITE and a DDIO “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte containsdatatowritetotheselectedregister. MSB LSB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 1 0 1 1 0 I2C SLAVE address (chip address) Figure8. I2CChipAddress ack from slave ack from slave ack from slave start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop SCL SDA start Id = 36h w ack addr = 02h ack DGGUHVV(cid:3)K¶02 data ack stop w=write(SDA=“0”) r=read(SDA=“1”) ack=acknowledge(SDApulleddownbyeithermasterorslave) rs=repeatedstart id=chipaddress,50'hor51'hforLP3950. Figure9. I2CWriteCycle Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure10. ack from slave ack from slave repeated start ack from slave data from slave ack from master start msb Chip Address lsb w msb Register Add lsb rs msb Chip Address lsb r msb DATA lsb stop SCL SDA start Id = 36h w ack addr = K¶00 ack rs Id = 36h r ack $GGUHVV(cid:3)K¶00 data ack stop Figure10. I2CReadCycle SDA 10 8 7 6 8 1 7 2 SCL 1 5 3 4 9 Figure11. I2CTimingDiagram Table2.I2CTimingParameters(1) Symbol Parameter Limit Units Min Max 1 HoldTime(repeated)STARTCondition 0.6 µs 2 ClockLowTime(1.65V≤V <1.80V) 3.2 µs DDIO 2 ClockLowTime(1.80V≤V ≤V V) 1.3 µs DDIO DD1,2 3 ClockHighTime(1.65V≤V <1.80V) 1200 ns DDIO 3 ClockHighTime(1.80V≤V ≤V V) 600 ns DDIO DD1,2 4 SetupTimeforaRepeatedSTARTCondition 600 ns 5 DataHoldTime(dataoutput,delaygeneratedbyLP3950) 300 900 ns 5 DataHoldTime(datainput) 0 900 ns 6 DataSetupTime 100 ns 7 RiseTimeofSDAandSCL 20+0.1C 300 ns b 8 FallTimeofSDAandSCL 15+0.1C 300 ns b 9 Set-upTimeforSTOPcondition 600 ns 10 BusFreeTimebetweenaSTOPandaSTARTCondition 1.3 µs C CapacitiveLoadParameterforEachBusLine. 10 200 ns b LoadofOnePicofaradCorrespondstoOneNanosecond. (1) Dataguaranteedbydesign 12 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Magnetic Boost DC/DC Converter The boost DC/DC converter generates a 4.1V–5.3V output voltage to drive LEDs from a single Li-Ion battery (3.0V to 4.5V). The output voltage is controlled with an eight-bit register in nine steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter has three options for switchingfrequency,1.0MHz,1.67MHzand2.0MHz(default),whenthetimingresistorRTis82kΩ. The LP3950 boost converter uses an unique pulse-skipping elimination method to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An internal active load is used to remove the excess charge from the output capacitor when needed (see NOTE below). The boost convertershouldbedisabledwhenthereisnoloadtoavoididlecurrentconsumption. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The output voltage control changes the resistor dividerinthefeedbackloop. Figure 12 shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. Overvoltageprotection,limitsthemaximumoutputvoltage – Keepstheoutputbelowbreakdownvoltage – Preventsboostoperationifthebatteryvoltageismuchhigherthandesiredoutput 2. Overcurrentprotection,limitsthemaximuminductorcurrent – VoltageoverswitchingNMOSismonitored;toohighvoltagesturntheswitchoff 3. Feedback(FB)protectionfornoconnection 4. Dutycyclelimitfunction,donewithdigitalcontrol NOTE Whenthebatteryvoltageisclosetotheoutputvoltage,theoutputvoltagemayriseslightly over programmed value if the load on output is small and pulse-skipping elimination is active. 2 MHz clock Duty control VIN VOUT SW FBNCCOMP FB + R - S OVPCOMP R + SWITCH - R RESETCOMP + - - R + ERRORAMP + ACTIVE - R LOAD SLOPER + OLPCOMP LOOPC - Figure12. BoostConverterFunctionalBlockDiagram Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Magnetic Boost DC/DC Converter Electrical Characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Units I LoadCurrent 3.0V≤V ≤4.5V LOAD IN 0 300 mA V =5.0V OUT V OutputVoltageAccuracy 1.0mA≤I ≤300mA OUT LOAD (FBPin) 3.0V≤V ≤4.5V −5 +5 % IN V =5.0V(targetvalue),autoloadOFF OUT OutputVoltage 1.0mA≤I ≤300mA LOAD (FBPin) 3.0V<V <5.0V+V 5.0 V IN (SCHOTTKY), autoloadOFF 1.0mA≤I ≤300mA LOAD V –V V V >5V+V IN (SCHOTTKY) IN (SCHOTTKY) RDS SwitchONResistance V =2.8V,I =0.5A 0.4 0.7 Ω ON DD1,2 SW f PWMModeSwitching RT=82kΩ PWF 2.0 MHz Frequency freq_sel[2:0]=1XX FrequencyAccuracy 2.7≤VDD ≤2.9 −6 ±3 +6 1,2 % RT=82kΩ −9 +9 t SwitchPulseMinimum NoLoad 25 ns PULSE Width t StartupTime 15 ms STARTUP I SWPinCurrentLimit 700 800 900 CL_OUT mA 500 1000 (1) LimitsinstandardtypefaceareforT =+25°C.Limitsinboldfacetypeapplyovertheoperatingambienttemperaturerange(−40°C≤T J A ≤+85°C).Unlessotherwisenoted,specificationsapplytoFigure2with:V =V =V =2.8V,C =C =C =C = DD1 DD2 DDA VDD1 VDD2 VDDA VDDIO 100nF,C =C =10µF,C =100nF,L =4.7µHandf =2.0MHz. OUT IN VREF 1 BOOST (2) Low-ESRSurface-MountCeramicCapacitorsareusedinsettingelectricalcharacteristics. Boost Standby Mode User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in PFM (Pulse Frequency Modulation) mode for 10 ms and then goes to PWM (Pulse Width Modulation ) mode. All RGB outputsareoffduringthe10msdelay. Boost Output Voltage Control User can control the boost output voltage by eight-bit boost output voltage register according to the following table. BOOST[7:0] BOOSTOutputVoltage Register0D'h (typical) Binary Hex 00000000 00 4.10 00000001 01 4.25 00000011 03 4.40 00000111 07 4.55 00001111 0F 4.70 00011111 1F 4.85 00111111 3F 5.00Default 01111111 7F 5.15 11111111 FF 5.30 14 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Boost Frequency Control Theregister‘boostfrequency’hasaddress0C’h.Thedefaultvalueafterresetis07’h. ‘x’meansdon’tcare. FREQ_SEL[2:0] Frequency 1xx 2.00MHz 01x 1.67MHz 001 1.00MHz Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Boost Converter Typical Performance Characteristics V =3.6V,V =5.0Vifnototherwisestated. IN OUT BoostFrequency vs BoostConverterEfficiency RTResistor Figure13. Figure14. BatteryCurrent BatteryCurrent vs vs Voltage Voltage Figure15. Figure16. 16 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Boost Converter Typical Performance Characteristics (continued) V =3.6V,V =5.0Vifnototherwisestated. IN OUT BoostTypicalWaveformsat100mALoad BoostStartupwithNoLoad 0VV) 5.DI = V/ Tm VOU(10 A GEDIV) ICOIL 100 mVERA0 mA/ A0 1 ( CH V) WIT V/DI VS (5 TIME (200 ns/DIV) Figure17. Figure18. BoostLineRegulation BoostLoadTransientResponse,50mAto100mA Figure19. Figure20. Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com RGB LED Pattern Generator TheLP3950RGBoutputscanbecontrolledeitherwithaudiosynchronizationorwithRGBpatterngenerator. The pattern generator of LP3950 drives three independently controlled LED outputs (for example, R1, G1 and B1).ThefunctionalityissimilarcomparedtoRGBfunctionalityofLP3936andLP3933. The output of RGB pattern generator can be selected to drive RGB1 (R1-G1-B1), RGB2 (R2-G2-B2) or RGB1 andRGB2(R1&R2 – G1&G2– B1&B2)outputs. Programmable Pattern Mode UserhascontroloverthefollowingparametersseparatelyforeachLED: ONandOFF(startandstoptimeinblinkingcycle) DUTY (PWMbrightnesscontrol) SLOPE (dimmingslope) ENABLE (outputenablecontrol) Themainblinkingcycleiscontrolledwiththree-bitCYCLEcontrol(0.25/0.5/1.0/2.0/4.0s). LED ON[3:0] brightness OFF[3:0] SLOPE[3:0] DUTY[3:0] SLOPE[3:0] Duty increases Duty constant Duty decreases PWM current pulses Blinking period Figure21. RGBPWMOperatingPrinciple RGB_START is the master control for the whole RGB function. The internal PWM and blinking control can be disabledbysettingtheRGB_PWMcontrolLOW.Inthiscasetheindividualenablecontrolscanbeusedtoswitch outputsonandoff.PWM_ENinputcanbeusedforexternalhardwarePWMcontrol. In the normal PWM mode the R, G and B switches are controlled in 3 phases (one phase per driver). During each phase the peak current set by an external ballast resistor is driven through the LED for the time defined by DUTY setting (0 µs to 50 µs). As a time averaged current this means 0% to 33% of the peak current. The PWM periodis150µsandthepulsefrequencyis6.67kHzinnormalmode. R1 1111 G1 0110 B1 1100 3 1 2 3 1 2 150 Ps/6.7 kHz Combined PWM cycle Figure22. NormalModePWMWaveformsatDifferentDutySettings In the FLASH mode all the outputs are controlled in one phase and the PWM period is 50 µs. The time averaged FLASHmodecurrentisthreetimesthenormalmodecurrentatthesameDUTYvalue. 18 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 ON<OFF R1 ON OFF ON OFF G1 OFF<ON OFF ON OFF ON B1 ON=OFF=0 First cycle Next cycles Figure23. ExampleBlinkingWaveforms Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com RGB Driver Characteristics (R1,G1,B1,R2,G2,B2outputs).LimitsinstandardtypefaceareforT =+25°C.Limitsinboldfacetypeapplyoverthe J operatingambienttemperaturerange(−40°C≤T ≤+85°C). A Symbol Parameter Conditions Min Typ Max Units R ONResistance 3.5 6.0 Ω DS-ON I OffStateLeakageCurrent V =5.0V,LEDdriveroff 0.03 1.0 µA LEAKAGE FB t MaximumSlopePeriod AtMaximumDutySetting 0.93 s SMAX t MinimumSlopePeriod AtMaximumDutySetting 31 ms SMIN t SlopeResolution AtMaximumDutySetting 62 ms SRES t Start/StopResolution Cycle1.0s 1/16 s START/STOP Duty DutyStepSize 1/16 t BlinkingCycleAccuracy −6 ±3 +6 % BLINK D DutyCycleRange EN_FLASH=1 0 99.6 % CYCF D DutyCycleRange EN_FLASH=0 0 33.2 % CYC D DutyResolution EN_FLASH=1(4-bit) 6.64 % RESF D DutyResolution EN_FLASH=0(4-bit) 2.21 % RES f PWMFrequency EN_FLASH=1 20 kHz PWMF f PWMFrequency EN_FLASH=0 6.67 kHz PWM 20 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 Table3.RGBLEDPWMControl (1) RDUTY[3:0] DUTYsetsthebrightnessoftheLEDbyadjustingthedutycycleofthePWMdriver.TheminimumDUTYcycleis0% GDUTY[3:0] [0000]andthemaximumintheflashmodeis100%[1111].Thepeakpulsecurrentisdeterminedbytheexternal BDUTY[3:0] resistor,LEDforwardvoltagedropandtheboostvoltage.Inthenormalmodethemaximumdutycycleis33%. RSLOPE[3:0] SLOPEsetstheturn-onandturn-offslopes.Fastestslopeissetby[0000]andslowestby[1111].SLOPEchangesthe GSLOPE[3:0] dutycycleatconstant,programmablerate.Foreachslopesettingthemaximumslopetimeappearsatmaximum BSLOPE[3:0] DUTYsetting.WhenDUTYisreduced,theslopetimedecreasesproportionally.Forexample,incaseofmaximum DUTY,theslopingtimecanbeadjustedfrom31ms[0000]to930ms[1111].ForDUTY[0111]theslopingtimeis14 ms[0000]to434ms[1111].TheblinkingcyclehasnoeffectonSLOPE. RON[3:0] ONsetsthebeginningtimeoftheturn-onslope.Theon-timeisrelativetotheselectedblinkingcyclelength.On- GON[3:0] settingN(N=0–15)setstheon-timetoN/16*cyclelength. BON[3:0] ROFF[3:0] OFFsetsthebeginningtimeoftheturn-offslope.Off-timeisrelativetoblinkingcyclelengthinthesamewayason- GOFF[3:0] time. BOFF[3:0] ROFF[3:0] GOFF[3:0] BOFF[3:0] IfON=0,OFF=0andRGB_PWM=1,thenRGBoutputsarecontinuouslyon(noblinking),theDUTYsetting controlsthebrightnessandtheSLOPEcontrolisignored. IfONandOFFarethesame,butnot0,RGBoutputsareturnedoff. CYCLE[2:0] CYCLEsetstheblinkingcycle:[000]for0.25s,[001]for0.5s,[010]for1.0s,[011]for2.0s.and[1XX]for4.0sCYCLE effectstoallRGBLEDs. RSW1 EnableforR1switch GSW1 EnableforG1switch BSW1 EnableforB1switch RSW2 EnableforR2switch GSW2 EnableforG2switch BSW2 EnableforB2switch RGB_START MasterSwitchforbothRGBdrivers: RGB_START=0→RGBOFF RGB_START=1→RGBON,startsthenewcyclefromt=0 RGB_PWM RGB_PWM=0→RSW,GWSandBSWcontroldirectlytheRGBoutputs(on/offcontrolonly) RGB_PWM=1→NormalPWMRGBfunctionality(duty,slope,on/offtimes,cycle) EN_FLASH FlashmodeenablecontrolforRGB1andRGB2.Intheflashmode(EN_FLASH=1)RGBoutputsarePWMcontrolled simultaneously,notin3-phasesystemasinthenormalmode. R1_PWM xx_PWM=0→ExternalPWMcontrolfromPWM_LEDpinisdisabled G1_PWM xx_PWM=1→ExternalPWMcontrolfromPWM_LEDpinisenabled B1_PWM InternalPWMcontrol(DUTY)canbeusedindependentlyofexternalPWMcontrol.ExternalPWMhasthesameeffect R2_PWM onallenabledoutputs. G2_PWM B2_PWM (1) TheLP3933sharesthesamepatterngenerator.ApplicationNoteAN-1291(SNVA069),“DrivingRGBLEDsUsingLP3933Lighting ManagementSystem”containsathoroughdescriptionoftheRGBdriverfunctionalityincludingprogrammingexamples. PWM_LED input can be used as a direct on/off or PWM brightness control for selected RGB outputs. For example it can trigger the flash using a flash signal from the camera. If PWM_LED input is not used, it must be tiedtoV . DDIO Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com AUDIO SYNCHRONIZATION The LEDs connected to the RGB outputs can be synchronized to incoming audio signal with Audio Synchronization feature. Audio Synchronization has two modes. Amplitude mode synchronizes LEDs based on the peak amplitude of the input signal. In the amplitude mode the user can select one of three amplitude mapping options. The frequency mode synchronizes the LEDs based on bass, middle and treble amplitudes (= low pass, band pass and high pass filters). The user can select between two different responses of frequency for best audio-visual user experience. Both of the modes provide a control for speed of the mapping with four different speed configurations. Programmable gain and AGC (Automatic Gain Control) function are also available for adjustment of the optimum audio signal mapping. The Audio Synchronization functionality is described more closelybelow. INPUTSIGNALTYPE TheLP3950supportfourtypesofanalogaudioinputsignalsforaudiosynchronization 1. Singleendedaudio 2. Differentialaudio 3. Stereo 4. Singleendedanddifferentialaudio. Figure24showshowtowiretheLP3950audioinputscasebycase(NC=NotConnected). USINGADIGITALPWMAUDIOSIGNALASANAUDIOSYNCHRONIZATIONSOURCE If the input signal is a PWM signal, use a first or second order low pass filter to convert the digital PWM audio signal into an analog waveform. There are two parameters that need to be known to get the filter to work successfully: frequency of the PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency (-3dB)shouldbearound2kHzto4kHzandthestop-bandattenuationatsamplingfrequencyshouldbearound- 48dBorbetter.Usearesistordividertoreducethedigitalsignalamplitudetomeetthespecificationoftheanalog audio input. Because a low-order low-pass filter attenuates the high-frequency components from audio signal, MODE_CONTROL=[01] selection is recommended when frequency synchronization mode is enabled. Figure 33 shows an example of a second order RC-filter for 29 kHz PWM signal with 3.3V amplitude. Active filters, such as a Sallen-Key filter, may also be applied. An active filter gives better stop-band attenuation and cut-off frequency canbehigherthanforaRC-filter. To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the audio synchronization feature, set manual gain to maximum, apply the PWM signal to the filter input and keep an eye on LEDs. If they are blinking without an audio signal (modulation), a sharper roll-off after the cut-off frequency,morestop-bandattenuation,orsmalleramplitudeofthePWMsignalisrequired. BUFFERS BUFFERS SEL SEL 10 nF ASE 10 nFASE AD1 MIX/ 10 nFAD1 MIX/ NC MUX MUX AD2 AD2 NC 10 nF SINGLE-ENDED STEREO BUFFERS BUFFERS SEL SEL ASE 10 nFASE NC 10 nFAD1 MIX/ 10 nFAD1 MIX/ MUX MUX AD2 AD2 10 nF 10 nF DIFFERENTIAL SINGLE ENDED AND DIFFERENTIAL Figure24. WiringDiagramforLP3950AudioInputs 22 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 INPUTBUFFERING Figure 25 describes the LP3950 audio input buffering structure in high level. The electric parameters of the buffers are described in Table 4. Operational amplifiers for both buffers are rail-to-rail input opamps. The single ended buffer is simply a voltage follower. DC level of the input signal is generated by a resistor divider. The differentialamplifierisabasicdifferential-to-single-endedconverter. VDDA 1.0 M: 10 nFASE - + 1.0 M: 500 k: 10 nF AD1 500 k: - + 10 nFAD2 500 k: VDDA 1.0 M: 1.0 M: Figure25. AudioInputBufferStructure AUDIOSYNCHRONIZATIONSIGNALPATH LP3950 audio synchronization is mainly done digitally and it consists of the following signal path blocks (see Figure26): • Inputbuffers • Multiplexer • ADconverter • DCremover • Automaticgaincontrol(AGC)/programmablegain • 3banddigitalfilter • Peakdetector • Look-uptables(LUT) • Modeselector • Integrators • PWMgenerator FunctionalBlockDiagram FILTER CONTROL MODE BUFFERS SEL EN GAIN ASE FILTERS LUT R AD1 MMUIXX/ ADC REMDOCV ER COGNATIRNO L MSYONDCE INT PWM FETS G SEL B AD2 PEAK LUT DETECTOR Figure26. SignalPathBlockDiagram Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com The digitized input signal has a DC component that is removed by the digital DC REMOVER (-3 dB @ 400 Hz). The automatic GAIN CONTROL adjusts the input signal to suitable range automatically. User can disable AGC and the gain can be set manually with PROGRAMMABLE GAIN. The LP3950 has two audio synchronization modes: amplitude and frequency. For amplitude based synchronization the PEAK DETECTION method is used. For frequency based synchronization the three-way crossover FILTER separates high pass, low pass and band pass signals. For both modes, a predefined lookup table (LUT) is used to match the audio visual effect. The MODE SELECTOR selects the synchronization mode. Reaction speed can be selected using INTEGRATOR speedvariables.FinallyPWMGENERATORsetsthedriverFETsdutycycles. Table4.AudioSynchronizationCharacteristics Symbol Parameter Conditions Min Typ Max Units Zin InputImpedanceofAD1,AD2,ASEpins 200 500 kΩ A AudioInputLevelRange(peak-to-peak), IN_SINGLE 0.1 V −0.1 V SingleEndedAudio DDA A AudioInputLevelRange(peak-to-peak), IN_DIFF 0.1 V −0.1 V DifferentialAudio DDA f CrossoverFrequencies(−3dB) 3dB NarrowFrequencyResponse LowPass 0.5 BandPass 1.0and1.5 HighPass 2.0 kHz WideFrequencyResponse LowPass 1.0 BandPass 2.0and3.0 HighPass 4.0 CONTROLOFAUDIOSYNCHRONIZATION The following table describes the controls required for audio synchronization. Note that these controls are functional when using serial interface (I2C or SPI) for device control. Also LP3950 audio synchronization functionalityisillustratedinFigure27. Table5. AudioSynchronizationControl EN_SYNC Audiosynchronizationenabled.SetEN_SYNC=1toenableaudiosynchronizationor0todisable. SYNC_MODE Synchronizationmodeselector.SetSYNC_MODE=0foramplitudesynchronization.SetSYNC_MODE =1forfrequencysynchronization. MODE_CTRL[1:0] Seebelow:Modecontrol EN_AGC Automaticgaincontrol.SetEN_AGC=1toenableautomaticcontrolor0todisable.WhenEN_AGCis disabled,theaudioinputsignalgainvalueisdefinedbyGAIN_SEL. GAIN_SEL[2:0] Inputsignalgaincontrol.Gainhasarangefrom0dBto21dBwith3dBsteps: [000]...0dB [011]...9dB [110]...18dB [001]...3dB [100]...12dB [111]...21dB [010]...6dB [101]...15dB INPUT_SEL[1:0] [00]...Singleendedinputsignal,ASE. [01]...Differentialinputsignal,AD1andAD2. [10]...Stereoinputorsingleendedanddifferentialinputsignal. Note:Sumofinputsignalsdividedby2. [11]...Noinput PleaseseeFigure24forwiring. SPEED_CTRL[1:0] Controlforspeedofthemapping.Setsthereactionspeed(or"samplingrate")fortheaudioinputsignal: [00]...FASTEST [01]...FAST [10]...MEDIUM [11]...SLOW Intheamplitudemodef =3.8Hz,inthefrequencymodef =7.6Hz. MAX MAX 24 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 LP3950 AUDIO SYNCHRONIZATION SYNC_MODE = 0 SYNC_MODE = 1 AMPLITUDE FREQUENCY SYNC. SYNC. MODE0 MODE1 MODE2 MODE0 MODE1 FASTEST FASTEST FASTEST FASTEST FASTEST FAST FAST FAST FAST FAST MEDIUM MEDIUM MEDIUM MEDIUM MEDIUM SLOW SLOW SLOW SLOW SLOW Figure27. LP3950AudioSynchronizationFunctionality MODECONTROLINTHEFREQUENCYMODE During the frequency mode (SYNC_MODE = 1) the user can select between two filter options by MODE_CTRL[1:0] as shown below (Figure 29). User can select the filters based on the music type and light effect requirements. Filter options: Left figure, wide frequency response; MODE_CTRL[1:0] is set to [00], [10] or [11]. Right figure, narrow frequency response: MODE_CTRL[1:0] set to [01]. Signal passed through the lowpass filter is used to control the duty cycle of red LEDs (R1 and/or R2 PWM outputs), the signal passed through the bandpass filter is used to control green LEDs (G1 and/or G2 PWM outputs) and high pass signal controls blue LEDs (B1 and/or B2 PWM outputs). Finally, the user can select the desired mapping speed by SPEED_CTRL[1:0]. Of course, the user can connect any color LED to any output in his/her own application (i.e. the red output does not need to drive a red LED). Maximum duty cycle is 100% as in the Flash mode (not 33% asinthenormalmodeofthepatterngenerator,whichisdescribedinTable3). 0 0 -10 BANDPASS -10 BANDPASS LOWPASS LOWPASS -20 HIPASS -20 HIPASS -30 -30 -40 -40 B -50 B -50 d d -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 kHz kHz Figure28.Cross-overFrequency Figure29.Cross-overFrequency Left:WideFrequencyResponse Right:NarrowFrequencyResponse MODECONTROLINTHEAMPLITUDEMODE During the amplitude synchronization mode (SYNC_MODE = 0) the user can select between three different amplitude mappings by using MODE_CTRL[1:0] select. These three mapping options give different light responses as shown in Figure 30. Again, the user can select the desired mapping speed by SPEED_CTRL[1:0]. Maximum duty cycle is 100%. If MODE_CTRL[1:0] = 11 and SYNC_MODE = 0, audio synchronization is inactive. Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com MODE_CTRL[1:0]=[00]=MODE0 MODE_CTRL[1:0]=[01]=MODE1 MODE_CTRL[1:0]=[10]=MODE2 Thisfigureisforillustratingpurposeonlyanddoesnotnecessarilyrepresenttheaccuratefunctionofthecircuit. Figure30. AmplitudeSynchronizationMappingOptions 26 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 MODECONTROLINTHEDEFAULTMODE One of the main benefits of LP3950 is the default mode, which enables user to build applications without I2C or SPI control. The LP3950 is set to the default mode when DME pin is high. DME pin high –state forces registers NSTBY and EN_SYNC to the high [1] state so that the start-up sequence get started (see start-up sequence on Modes of Operation). Function of LP3950 in the default mode of operation is controlled by AMODE pin. If AMODE is pulled low the LP3950 is in the amplitude synchronization mode. If the AMODE pin is pulled high the LP3950 is in the frequency synchronization mode. In the default mode default control register values are used, seeTable8.PleaserefertoFigure32inTypicalApplicationsforwiring. RGBOUTPUTSELECTOR The usage of RGB outputs (RGB1 and RGB2) can be selected with RGB_SEL[1:0] control bits. Audio synchronization and RGB pattern generator output can be connected to RGB ports as shown in the following table. Table6.RGBOutputControl RGB_SEL[0] RGB_SEL[1] RGB1OutputControl RGB2OutputControl 0 0 PatternGenerator PatternGenerator 1 0 AudioSync PatternGenerator 0 1 PatternGenerator AudioSync 1 1 AudioSync AudioSync RecommendedExternalComponents OUTPUTCAPACITOR,C OUT The output capacitor C directly affects the magnitude of the output ripple voltage. In general, the higher the OUT value of C , the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR (Equivalent OUT SeriesResistance)arethebestchoice.Atthelighterloads,thelowESRceramicsofferamuchlowerV ripple OUT than the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower V OUT ripplemagnitudethanthetantalumsofthesamevalue.However,thedv/dtoftheV ripplewiththeceramicsis OUT much lower that the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is recommended. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied voltage. The capacitance value can fall to below half of the nominal capacitance.Toolowoutputcapacitancecanmaketheboostconverterunstable. INPUTCAPACITOR,C IN The input capacitor C directly affects the magnitude of the input ripple voltage and to a lesser degree the V IN OUT ripple. A higher value C will give a lower V ripple. Capacitor voltage rating must be sufficient, 10V is IN IN recommended. OUTPUTDIODE,D 1 A Schottky diode should be used for the output diode. To maintain high efficiency the average current rating of the schottky diode should be larger than the peak inductor current (1.0A). Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switchingspeedsandlongrecoverytimescausetheefficiencyandtheloadregulationtosuffer. Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com INDUCTOR,L 1 LP3950'shighswitchingfrequencyenablestheuseofasmallsurfacemountinductor.A4.7µHshieldedinductor is suggested for 2.0 MHz switching frequency. Values below 2.2 µH should not be used at 2.0 MHz. At lower switching frequencies 4.7 µH inductors should always be used. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (1.0A). Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and, thus, may interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW pin as close to the IC as possible. Examples of suitable inductors are TDK type VLF4012AT- 4R7M1R1 and Coilcraft type MSS4020- 472MLD. Table7.ListofRecommendedExternalComponents Symbol SymbolExplanation Value Unit Type C V BypassCapacitor 100 nF Ceramic,X5R VDD1 DD1 C V BypassCapacitor 100 nF Ceramic,X5R VDD2 DD2 C OutputCapacitorfromFBtoGND 10±10% µF Ceramic,X5R OUT C InputCapacitorfromBatteryVoltagetoGND 10±10% µF Ceramic,X5R IN C V BypassCapacitor 100 nF Ceramic,X5R VDDIO DD_IO C V BypassCapacitor 100 nF Ceramic,X5R VDDA DDA C AudioInputCapacitors 10 nF Ceramic,X5R 1,2,3 R OscillatorFrequencyBiasResistor 82 kΩ 1% (1) T R SOOutputPull-upResistor 100 kΩ SO C ReferenceVoltageCapacitor,betweenV and 100 nF Ceramic,X5R VREF REF GND L BoostConverterInductor 4.7 µH Shielded,LowESR, 1 I 1.0A SAT D RectifyingDiode,V @Maxload 0.3 V SchottkyDiode 1 F RGBLED Red,Green,BlueorWhiteLEDs UserDefined R ,R ,R CurrentLimitResistors RX GX BX (1) ResistorRTtolerancechangewillchangethetimingaccuracyofRGBblock.Alsotheboostconverterswitchingfrequencywillbe affected. PCBDesignGuidelines Printed circuit board layout is critical to low noise operation and good performance of the LP3950. Bypass capacitors should be close to the V pins of the integrated circuit. Special attention must be given to the routing DD of the switching loops. Lengths of these loops should be minimized. It is essential to place the input capacitor, the output capacitor, the inductor and the schottky diode very close to the integrated circuit and use wide routings for those components. Sensitive components should be placed far from those components with high pulsatingcurrent.Agroundplaneisrecommended. The power switch loop (the switch is on) has the greatest affect on noise generation. The loop is formed by the input capacitor, the inductor, the SW pin, the GND_BOOST pin and the ground plane, as shown by the dashed line in Figure 31. The other switching loop, the rectifier loop, is formed by the input capacitor, the inductor, the diode, the output capacitor and the ground plane, as shown by the dotted line. Arrange the components so that the switching current loops curl in the same direction (see arrows in Figure 31). See also Application Note AN 1149,LayoutGuidelinesforSwitchingModePowerSupplies. 28 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 L1 SW D1 CIN COUT GND_BOOST Figure31. TheCurrentLoops TypicalApplications VDD = 2.7V TO 2.9V CVDD1 CVDD2 CVDDA 100 nF 100 nF 100 nF VIN= 3.0V TO 4.5V CVDD_IO VVDDDD1_IO VDD2 VDDA -+ TTERY 1C0I NPF 4.L71 PH D1 100 nF BA SW DME FB RED COUT NRST RR1 LEDS 10 PF RR2 PWM_LED R1 NOT CONNECTED SO RR3 ASE LEFT CHANNEL C1 AUDIO SIGNAL 10 nF GREEN RG1 LEDS AD1 RG2 RAIGUHDTIO C SHIAGNNNAELL 1C02 nF C310 nF LP3950 G1 RG3 AD2 RT82k RT BLUE CVREF RB1 LEDS 100 nF RB2 VREF B1 SDA RB3 SI HIGH IF_SEL CURRENT SCL RR4 RGB LED R2 AMODE RG4 GND_RGB G2 RB4 GND_BOOST B2 GNDA GND1GND2 GND3 Figure32. TheLP3950SettotheDefaultMode Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com VDD = 2.7V TO 2.9V CVDD1 CVDD2 CVDDA 100 nF 100 nF 100 nF VIN= 3.0V TO 4.5V VDDIO CVDD_IO VVDDDD1_IO VDD2 VDDA -+ TTERY 1C0I NPF 4.L71 PH D1 100 nF BA SW IF_SEL FB RED COUT RSO RR1 LEDS 10 PF 100 k: RR2 R1 SO RR3 PWM_LED SCK MICROCONTROLLER GREEN SI RG1 LEDS SS RG2 NRST G1 LP3950 RG3 R110 k: R210 k: C110nF SINGLE ASE EPNWDEMD 1C0 3nF 10C n2F NC AD1 RB1 BLELUDES SIGNAL NC AD2 RT82k B1 RB2 RT RB3 CVREF 100 nF HIGH VREF CURRENT DME RR4 RGB LED R2 AMODE RG4 GND_RGB G2 RB4 GND_BOOST B2 GNDA GND1GND2 GND3 NC=NotConnected Figure33. TypicalApplicationofLP3950WhentheSPIInterfaceIsUsed Here,asecondorderRC-filterisusedontheASEinputtoconvertaPWMsignaltoananalogwaveform. 30 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 VDD = 2.7V TO 2.9V CVDD1 CVDD2 CVDDA 100 nF 100 nF 100 nF VIN= 3.0V TO 4.5V VDDIO CVDD_IO VVDDDD1_IO VDD2 VDDA -+ TTERY 1C0I NPF 4.L71 PH D1 100 nF BA SW IF_SEL FB COUT RSO 10 PF 100 k: BACKLIGHT LEDS RR1 SO RR2 PWM_LED SCK R1 RR3 MICROCONTROLLER SI RR4 SS NRST KEYPAD LEDS VDD= 2.7V TO 2.9V RG1 RG2 R3 LP3950 G1 R4 100 k: RG3 100 k: + LMV321C110nF RB1 - ASE RB2 B1 C4 R1 1R002 k: RB3 100 nF10 k: NC AD1 SINGE ENDED AUDIO SIGNAL NC AD2 AUDIO SYNC. FUNLIGHT RT82k RT RR5 CVREF R2 RR6 100 nF VREF RG4 DME G2 RG5 AMODE GND_RGB RB4 GND_BOOST B2 RB5 GNDA GND1GND2 GND3 Figure34. BacklightandKeypadLEDsControlledbythePatternGenerator FunlightLEDsControlledbyAudioSynchronization There may be cases where the audio input signal going into the LP3950 is too weak for audio synchronization. This figure presents a single-supply inverting amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mV audio signal. Because the amplifier (LMV321) is p-p operating in single supply voltage, a voltage divider using R and R is implemented to bias the amplifier so the 3 4 input signal is within the input common-mode voltage range of the amplifier. The capacitor C is placed between 4 theinvertinginputandresistorR toblocktheDCsignalgoingintotheaudiosignalsource.ThevaluesofR and 1 1 C affect the cutoff frequency, f = 1/(2*Pi*R *C ), in this case it is around 160 Hz. As a result, the LMV321 4 c 1 4 output signal is centered around mid-supply, that is V /2. The output can swing to both rails, maximizing the DD signal-to-noiseratioinalowvoltagesystem Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LP3950

LP3950 SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 www.ti.com Table8.LP3950ControlRegisterNamesandDefaultValues ADDR SETUP D7 D6 D5 D4 D3 D2 D1 D0 (HEX) 00 RGB RGBPWM RGB RSW1 GSW1 BSW1 RSW2 GSW2 BSW2 CONTROL 0 START 0 0 0 0 0 0 0 01 RED RON[3] RON[2] RON[1] RON[0] ROFF[3] ROFF[2] ROFF[1] ROFF[0] ON/OFF 0 0 0 0 0 0 0 0 02 GREEN GON[3] GON[2] GON[1] GON[0] GOFF[3] GOFF[2] GOFF[1] GOFF[0] ON/OFF 0 0 0 0 0 0 0 0 03 BLUE BON[3] BON[2] BON[1] BON[0] BOFF[3] BOFF[2] BOFF[1] BOFF[0] ON/OFF 0 0 0 0 0 0 0 0 04 RED RSLOPE[3] RSLOPE[2] RSLOPE[1] RSLOPE[0] RDUTY[3] RDUTY[2] RDUTY[1] RDUTY[0] SLOPE& 0 0 0 0 0 0 0 0 DUTY CYCLE 05 GREEN GSLOPE[3] GSLOPE[2] GSLOPE[1] GSLOPE[0] GDUTY[3] GDUTY[2] GDUTY[1] GDUTY[0] SLOPE& 0 0 0 0 0 0 0 0 DUTY CYCLE 06 BLUE BSLOPE[3] BSLOPE[2] BSLOPE[1] BSLOPE[0] BDUTY[3] BDUTY[2] BDUTY[1] BDUTY[0] SLOPE& 0 0 0 0 0 0 0 0 DUTY CYCLE 07 CYCLE CYCLE[1] CYCLE[0] R1_PWM G1_PWM B1_PWM R2_PWM G2_PWM B2_PWM PWM 0 0 0 0 0 0 0 0 0B ENABLES CYCLE[2] NSTBY EN_BOOST EN_FLASH AUTOLOAD RGB_SEL[1 RGB_SEL[0 0 0 0 0 _EN ] ] 1 1 1 0C BOOST FREQ_SEL[ FREQ_SEL[ FREQ_SEL[ FREQUEN 2] 1] 0] CY 1 1 1 0D BOOST BOOST[7] BOOST[6] BOOST[5] BOOST[4] BOOST[3] BOOST[2] BOOST[1] BOOST[0] OUTPUT 0 0 1 1 1 1 1 1 VOLTAGE 2A AUDIO GAIN_SEL[2] GAIN_SEL[ GAIN_SEL[ SYNC_MO EN_AGC EN_SYNC INPUT_SEL INPUT_SEL SYNC 1 1] 0] DE 1 0 [0] [0] CONTROL 0 1 0 1 0 1 2B AUDIO MODE_CT MODE_CT SPEED_CT SPEED_CT SYNC RL[1] RL[0] RL[1] RL[0] CONTROL 0 1 0 1 2 32 SubmitDocumentationFeedback Copyright©2004–2013,TexasInstrumentsIncorporated ProductFolderLinks:LP3950

LP3950 www.ti.com SNVS331C–NOVEMBER2004–REVISEDAPRIL2013 REVISION HISTORY ChangesfromRevisionB(April2013)toRevisionC Page • ChangedlayoutofNationalDataSheettoTIformat.......................................................................................................... 32 Copyright©2004–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LP3950

PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) LP3950SL/NOPB ACTIVE TLGA NPC 32 1000 Green (RoHS NIAU Level-3-260C-168 HR -40 to 85 LP3950SL & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP3950SL/NOPB TLGA NPC 32 1000 178.0 12.4 4.8 5.8 1.3 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP3950SL/NOPB TLGA NPC 32 1000 210.0 185.0 35.0 PackMaterials-Page2

MECHANICAL DATA NPC0032A www.ti.com

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