Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 LP38853 3-A Fast-Response High-Accuracy Adjustable LDO Linear Regulator With Enable and Soft Start 1 Features 3 Description • WideV SupplyOperatingRange:3Vto5.5V The LP38853 is a high-current, fast-response 1 BIAS regulator that can maintain output voltage regulation • AdjustableV Range:0.8Vto1.8V OUT with extremely low input-to-output voltage drop. • DropoutVoltageof240mV(Typical)at3-ALoad Fabricated on a CMOS process, the device operates Current from two input voltages: V provides voltage to BIAS • PrecisionVADJAcrossAllLineandLoad drive the gate of the NMOS power transistor; VIN is the input voltage which supplies power to the load. Conditions: The use of an external bias rail allows the device to – ±1.5%V forT =25°C ADJ J operate from ultra-low V voltages. Unlike bipolar IN – ±2%V for0°C ≤T ≤ +125°C regulators, the CMOS architecture consumes ADJ J – ±3%V for –40°C≤ T ≤ +125°C extremely low quiescent current at any output load ADJ J current. The use of an NMOS power transistor results • OvertemperatureandOvercurrentProtection in wide bandwidth, yet minimum external capacitance • Stablewith10-µFCeramicCapacitors isrequiredtomaintainloopstability. • −40°Cto+125°COperatingJunctionTemperature The fast transient response of this device makes it Range suitable for use in powering DSP and microcontroller core voltages, and switch-mode power-supply post 2 Applications regulators. • ASICPowerSuppliesin: • Dropout Voltage: 240 mV (typical) at 3-A load current – Desktops,Notebooks,GraphicsCards,and • Low Ground Pin Current: 10 mA (typical) at 3-A Servers loadcurrent – GamingSet-TopBoxes,Printers,andCopiers • SoftStart:Programmablesoft-starttime • ServerCoreandI/OSupplies • DSPandFPGAPowerSupplies DeviceInformation(1) • SMPSPost-Regulator PART PACKAGE BODYSIZE(NOM) NUMBER DDPAK/TO-263(7) 10.10mm×8.89mm LP38853 TO-220(7) 14.986×10.16mm SOPowerPAD™(8) 4.89mm×3.90mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic LP38853 VIN IN OUT VOUT CIN CFF R1 VBIAS BIAS VEN CBIAS EN ADJ R2 COUT SS GND CSS GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................11 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................14 3 Description............................................................. 1 8 ApplicationandImplementation........................ 15 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................15 8.2 TypicalApplication .................................................15 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 19 6 Specifications......................................................... 4 10 Layout................................................................... 19 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................19 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExamples...................................................19 6.4 ThermalInformation..................................................5 11 DeviceandDocumentationSupport................. 20 6.5 ElectricalCharacteristics...........................................5 11.1 DocumentationSupport........................................20 6.6 TimingRequirements................................................6 11.2 CommunityResources..........................................20 6.7 TypicalCharacteristics..............................................7 11.3 Trademarks...........................................................20 7 DetailedDescription............................................ 11 11.4 ElectrostaticDischargeCaution............................20 7.1 Overview.................................................................11 11.5 Glossary................................................................20 7.2 FunctionalBlockDiagram.......................................11 12 Mechanical,Packaging,andOrderable Information........................................................... 20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(November2015)toRevisionF Page • correctedlayoutdrawings..................................................................................................................................................... 19 ChangesfromRevisionD(April2015)toRevisionE Page • ChangedpartnumbertoLP38853throughoutdatasheet .................................................................................................... 1 • AddedDeviceInformationandPinConfigurationandFunctionssections,ESDRatingsandThermalInformation tables,FeatureDescription,DeviceFunctionalModes,ApplicationandImplementation,PowerSupply Recommendations,Layout,DeviceandDocumentationSupport,andMechanical,Packaging,andOrderable Informationsections................................................................................................................................................................ 1 • DeletedLeadtemperaturefromAbsMaxtable;itisinPOA ................................................................................................ 4 • Addedupdatedthermalinformation ...................................................................................................................................... 5 • Deletedout-of-dateheatsinkingsubsections....................................................................................................................... 17 ChangesfromRevisionC(April2013)toRevisionD Page • ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 19 2 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 5 Pin Configuration and Functions KTWPackage NDZPackage 7-PinDDPAK/TO-263 7-PinTO-220 Top TopView SS 1 TAB SS 1 TAB EN 2 IS EN 2 IS L GND L GND IN 3 P IN 3 P 3 3 GND 4 8 GND 4 8 8 8 ADJ 5 53 ADJ 5 53 S T OUT 6 OUT 6 BIAS 7 BIAS 7 DDAPackage 8-PinSOPowerPAD TopView ADJ 1 8 N/C OUT 2 7 IN BIAS 3 6 EN GND 4 5 SS DAP Connect to GND PinFunctions PIN TYPE DESCRIPTION NAME DDPAK/TO-263 TO-220 SOPowerPAD-8 ADJ 5 5 1 O Thefeedbackconnectiontosettheoutputvoltage BIAS 7 7 3 I Thesupplyfortheinternalcontrolandreferencecircuitry. EN 2 2 6 I Deviceenable,High=On,Low=Off. TheSOPowerPADDAPisathermalconnectiononlythatis DAP — — DAP — physicallyattachedtothebacksideofthedie,andusedasa thermalheat-sinkconnection. GND 4 4 4 GND Ground IN 3 3 7 I Theunregulatedvoltageinput N/C — — 8 — Nointernalconnection OUT 6 6 2 O Theregulatedoutputvoltage Soft-startcapacitorconnection.UsedtocontroltherisetimeofV SS 1 1 5 O OUT atturnon. TheKTWandNDZTABisathermalandelectricalconnectionthat TAB TAB TAB — — isphysicallyattachedtothebacksideofthedie,andusedasa thermalheat-sinkconnection. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT V supplyvoltage(survival) −0.3 6 V IN V supplyvoltage(survival) −0.3 6 V BIAS V soft-startvoltage(survival) −0.3 6 V SS V voltage(survival) −0.3 6 V OUT I current(survival) InternallyLimited OUT Junctiontemperature −40 150 °C Powerdissipation(3) InternallyLimited Storagetemperature,T −65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTISalesOffice/Distributorsforavailabilityandspecifications. (3) Devicepowerdissipationmustbede-ratedbasedondevicepowerdissipation(P ),ambienttemperature(T ),andpackagejunction-to- D A ambientthermalresistance(R ).Additionalheatsinkingmayberequiredtoensurethatthedevicejunctiontemperature(T )doesnot θJA J exceedthemaximumoperatingrating.SeetheApplicationandImplementationsectionfordetails. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT (V +V ) V supplyvoltage(survival) OUT DO V IN toV BIAS 0.8V≤V ≤1.2V 3 5.5 V V supplyvoltage(survival)(2) OUT BIAS 1.2V<V ≤1.8V 4.5 5.5 V OUT V voltage 0 V V EN BIAS I 0 3 mA OUT Junctiontemperature(3) −40 125 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability (2) V cannotexceedeitherV or4.5V,whichevervalueislower. IN BIAS (3) Devicepowerdissipationmustbede-ratedbasedondevicepowerdissipation(P ),ambienttemperature(T ),andpackagejunctionto D A ambientthermalresistance(R ).Additionalheat-sinkingmayberequiredtoensurethatthedevicejunctiontemperature(T )doesnot θJA J exceedthemaximumoperatingrating.SeetheApplicationandImplementationsectionfordetails. 4 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 6.4 Thermal Information LP38853 THERMALMETRIC(1) KTW(DDPAK/TO-263) NDZ(TO-220) DDA(SOPowerPAD) UNIT 7PINS 7PINS 8PINS RθJA Junction-to-ambientthermalresistance 34.3 34.0 48.4 °C/W RθJC(top) Junction-to-case(top)thermalresistance 37.6 36.4 54.6 °C/W RθJB Junction-to-boardthermalresistance 25.3 25.0 29.1 °C/W ψJT Junction-to-topcharacterizationparameter 6.6 6.3 9.6 °C/W ψJB Junction-to-boardcharacterizationparameter 24.0 23.6 29.0 °C/W RθJC(bot) Junction-to-case(bottom)thermalresistance n/a n/a 4.3 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics Unlessotherwisespecified:V =0.8V,V =V +1V,V =3V,V =V ,I =10mA,C =C =10µF, OUT IN OUT(NOM) BIAS EN BIAS OUT IN OUT C =1µF,C =open;typical(TYP)limitsareforT =25°Conly,andminimum(MIN)andmaximum(MAX)limitsapply BIAS SS J overthejunctiontemperature(T )rangeof–40°Cto+125°C.MinimumandMaximumlimitsarespecifiedthroughtest, J design,orstatisticalcorrelation.TypicalvaluesrepresentthemostlikelyparametricnormatT =25°C,andareprovidedfor J referencepurposesonly. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V +1V≤V ≤V ≤4.5V(1) OUT(NOM) IN BIAS 3V≤V ≤5.5V,10mA≤I ≤3A 492.5 500 507.5 BIAS OUT T =25°C J V +1V≤V ≤V ≤4.5V(1) OUT(NOM) IN BIAS 485 515 V V accuracy 3V≤V ≤5.5V,10mA≤I ≤3A mV ADJ ADJ BIAS OUT V +1V≤V ≤V ≤4.5V(1) OUT(NOM) IN BIAS 3V≤V ≤5.5V, BIAS 490 500 510 10mA≤I ≤3A, OUT 0°C≤T ≤125°C J 3V≤V ≤5.5V 0.8 1.2 BIAS V V range V OUT OUT 4.5V≤V ≤5.5V 0.8 1.8 BIAS ΔV /ΔV Lineregulation,V (2) V +1V≤V ≤V 0.04 %/V OUT IN IN OUT(NOM) IN BIAS ΔV /ΔV Lineregulation,V (2) 3V≤V ≤5.5V 0.1 %/V OUT BIAS BIAS BIAS Outputvoltageload ΔVOUT/ΔIOUT regulation(3) 10mA≤IOUT≤3A 0.2 %/A I =3A,T =25°C 240 300 V Dropoutvoltage(4) OUT J mV DO I =3A 450 OUT V =0.8V,V =3V OUT BIAS 10mA≤I ≤3A 7 8.5 OUT TJ=25°C mA IGND(IN) QfroumiesVcIeNnstucpuprlryentdrawn V10OUmTA=≤0.I8OUVT,≤VB3IAAS=3V 9 V ≤0.5V,T =25°C 1 100 EN J μA V ≤0.5V 300 EN 10mA≤I ≤3A,T =25°C 3 3.8 OUT J mA Quiescentcurrentdrawn 10mA≤IOUT≤3A 4.5 I GND(BIAS) fromVBIASsupply VEN≤0.5V,TJ=25°C 100 170 μA V ≤0.5V 200 EN (1) V cannotexceedeitherV or4.5V,whichevervalueislower. IN BIAS (2) Outputvoltagelineregulationisdefinedasthechangeinoutputvoltagefromnominalvalueresultingfromachangeininputvoltage. (3) Outputvoltageloadregulationisdefinedasthechangeinoutputvoltagefromnominalvalueastheloadcurrentincreasesfromnoload tofullload. (4) Dropoutvoltageisdefinedastheinputtooutputvoltagedifferential(V –V )wheretheinputvoltageislowenoughtocausethe IN OUT outputvoltagetodrop2%fromthenominalvalue. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Electrical Characteristics (continued) Unlessotherwisespecified:V =0.8V,V =V +1V,V =3V,V =V ,I =10mA,C =C =10µF, OUT IN OUT(NOM) BIAS EN BIAS OUT IN OUT C =1µF,C =open;typical(TYP)limitsareforT =25°Conly,andminimum(MIN)andmaximum(MAX)limitsapply BIAS SS J overthejunctiontemperature(T )rangeof–40°Cto+125°C.MinimumandMaximumlimitsarespecifiedthroughtest, J design,orstatisticalcorrelation.TypicalvaluesrepresentthemostlikelyparametricnormatT =25°C,andareprovidedfor J referencepurposesonly. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V risinguntildeviceisfunctional,T = UVLO Undervoltagelockout 25B°IACS J 2.2 2.45 2.7 V threshold V risinguntildeviceisfunctional 2 2.9 BIAS V fallingfromUVLOthresholduntil BIAS deviceisnon-functional 60 150 300 UVLO(HYS) Uhynsdteerrevosilstagelockout TJ=25°C mV V fallingfromUVLOthresholduntil BIAS 50 350 deviceisnon-functional V =V +1V,V =3V,V = I Outputshort-circuitcurrent IN OUT(NOM) BIAS OUT 5.8 A SC 0V SOFT-START r Soft-startinternalresistance 11 13.5 16 kΩ SS Soft-starttime t C =10nF 675 μs SS t =C ×r ×5 SS SS SS SS ENABLE V =V 0.01 EN BIAS I ENABLEpincurrent V =0V,V =5.5V,T =25°C –19 –30 –40 μA EN EN BIAS J V =0V,V =5.5V –13 –51 EN BIAS V risinguntiloutput=ON,T =25°C 1 1.25 1.5 EN J V Enablevoltagethreshold V EN(ON) V risinguntiloutput=ON 0.9 1.55 EN V fallingfromV untilOutput=OFF EN EN(ON) 50 100 150 VEN(HYS) Enablevoltagehysteresis TJ=25°C mV V fallingfromV untilOutput=OFF 30 200 EN EN(ON) ACPARAMETERS V =V +1V, IN OUT(NOM) 80 PSRR RipplerejectionforV input ƒ=120Hz IN (VIN) voltage VIN=VOUT(NOM)+1V, 70 ƒ=1kHz dB V =V +3V, BIAS OUT(NOM) 58 PSRR RipplerejectionforV ƒ=120Hz BIAS (VBIAS) voltage VBIAS=VOUT(NOM)+3V, 58 ƒ=1kHz Outputnoisedensity ƒ=120Hz 1 µV/√Hz e BW=10Hz−100kHz 150 n Outputnoisevoltage µV RMS BW=300Hz−300kHz 90 THERMALPARAMETERS Thermalshutdownjunction T 160 SD temperature °C T Thermalshutdownhysteresis 10 SD(HYS) 6.6 Timing Requirements MIN NOM MAX UNIT t Turnoffdelaytime,R xC <<t 20 µs OFF LOAD OUT OFF t Turnondelaytime,R xC <<t 15 µs ON LOAD OUT ON 6 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 6.7 Typical Characteristics RefertotheSimplifiedSchematic.Unlessotherwisespecified:T =25°C,R1=1.4kΩ,R2=1kΩ,C =0.01µF,V = J FF IN V +1V,V =3V,I =10mA,C =10-µFceramic,C =10-µFceramic,C =1-µFceramic,C =open. OUT(NOM) BIAS OUT IN OUT BIAS SS Figure1.BIASGroundPinCurrent(I )vsV Figure2.BIASGroundPinCurrent(I )vs GND(BIAS) BIAS GND(BIAS) Temperature Figure3.INGroundPinCurrentvsTemperature Figure4.LoadRegulationvsTemperature Figure5.DropoutVoltage(V )vsTemperature Figure6.OutputCurrentLimit(I )vsTemperature DO SC Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) RefertotheSimplifiedSchematic.Unlessotherwisespecified:T =25°C,R1=1.4kΩ,R2=1kΩ,C =0.01µF,V = J FF IN V +1V,V =3V,I =10mA,C =10-µFceramic,C =10-µFceramic,C =1-µFceramic,C =open. OUT(NOM) BIAS OUT IN OUT BIAS SS Figure7.V vsTemperature Figure8.V vsV OUT OUT IN Figure9.UVLOThresholdsvsTemperature Figure10.Soft-StartR VariationvsTemperature SS 10nFto47nF Figure11.VOUTvsCSS Figure12.EnableThresholds(VEN)vsTemperature 8 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 Typical Characteristics (continued) RefertotheSimplifiedSchematic.Unlessotherwisespecified:T =25°C,R1=1.4kΩ,R2=1kΩ,C =0.01µF,V = J FF IN V +1V,V =3V,I =10mA,C =10-µFceramic,C =10-µFceramic,C =1-µFceramic,C =open. OUT(NOM) BIAS OUT IN OUT BIAS SS Figure13.EnablePulldownCurrent(I )vsTemperature Figure14.EnablePullupResistor(R )vsTemperature EN EN Figure15.V LineTransientResponse Figure16.V LineTransientResponse IN IN Figure17.V LineTransientResponse Figure18.V LineTransientResponse BIAS BIAS Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) RefertotheSimplifiedSchematic.Unlessotherwisespecified:T =25°C,R1=1.4kΩ,R2=1kΩ,C =0.01µF,V = J FF IN V +1V,V =3V,I =10mA,C =10-µFceramic,C =10-µFceramic,C =1-µFceramic,C =open. OUT(NOM) BIAS OUT IN OUT BIAS SS Figure19.V PSRR Figure20.V PSRR BIAS IN Figure21.OutputNoise 10 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 7 Detailed Description 7.1 Overview The LP38853 is a high-current, low-dropout, fast-response linear regulator capable of sourcing a 3-A load with only 240-mV dropout. This device operates from two input voltages: V provides voltage to internal circuit, BIAS while V is the input voltage supplying power to load. The use of an external bias rail allows the part to operate IN from ultra low V voltages. The fast transient response of this device makes it suitable for powering DSP, IN microcontrollercores,andpostregulators. 7.2 Functional Block Diagram IN OUT LP38853 BIAS Undervoltage Lockout Thermal rEN Shutdown ADJ EN Enable 1.2 V rSS SS VREF ILIMIT GND 0.5 V 7.3 Feature Description 7.3.1 UndervoltageLockout(UVLO) The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is belowtheUVLOthresholdofapproximately2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is approximately150mVofhysteresisbuiltintotheUVLOthresholdtoprovidenoiseimmunity. When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V the device isfunctional,buttheoperatingparametersarenotbewithinthespecifiedlimits. 7.3.2 SupplySequencing ThereisnorequirementfortheorderthatV orV areappliedorremoved. IN BIAS One practical limitation is that the soft-start circuit starts charging C when both V rises above the UVLO SS BIAS threshold and the EN pin is above the V threshold. If the application of V is delayed beyond this point the EN(ON) IN benefitsofsoftstartarecompromised. In any case, the output voltage cannot be ensured until both V and V are within the range of specified IN BIAS operatingvalues. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin mustbediodeclampedtoground.ASchottkydiodeisrecommendedforthisdiodeclamp. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) 7.3.3 ReverseVoltage A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the IN pin. Typically this happens when V is abruptly taken low and C continues to hold a sufficient charge such that IN OUT theinputtooutputvoltagebecomesreversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there is no reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when V is below the UVLO threshold, or when the EN pin is held BIAS low. When V is above the UVLO threshold, and the EN pin is above the V threshold, the control circuitry is BIAS EN(ON) active and attempts to regulate the output voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass element to the full V potential when the output voltage begins to fall. BIAS In this condition, reverse current flows from the OUT pin to the IN pin , limited only by the R of the pass DS(ON) element and the output-to-input voltage differential. Discharging an output capacitor up 1000 µF in this manner does not damage the device as the current rapidly decays. However, continuous reverse current must be avoided. 7.3.4 Soft-Start The LP38853 incorporates a soft-start function that reduces the start-up current surge into the output capacitor (C ) by allowing V to rise slowly to the final value. This is accomplished by controlling V at the SS pin. OUT OUT REF The soft-start timing capacitor (C ) is internally held to ground until both V rises above the UVLO threshold SS BIAS andtheENpinishigherthantheV threshold. EN(ON) V rises at an RC rate defined by the internal resistance of the SS pin (r ) and the external capacitor REF SS connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficientlyclosetothefinalsteady-statevalue.Duringthesoft-starttimetheoutputcurrentcanrisetothebuilt-in currentlimit. Soft-StartTime=C ×r ×5 (1) SS SS Because the V rise is exponential, not linear, the in-rush current peaks during the first time constant (τ), and OUT V requiresfouradditionaltimeconstants(4τ)toreachthefinalvalue(5τ). OUT After achieving normal operation, if either V fall below the ULVO threshold, or the EN pin fall below the BIAS V threshold, the device output is disabled, and the soft-start capacitor (C ) discharge circuit becomes EN(OFF) SS active. The C discharge circuit remains active until V falls to 500 mV (typical). When V falls below 500 SS BIAS BIAS mV(typical),theC dischargecircuitceasestofunctionduetoalackofsufficientbiasingtothecontrolcircuitry. SS Because V appears on the SS pin, any leakage through C causes V to fall, thus affecting V . A REF SS REF OUT leakage of 50 nA (about 10 MΩ) through C causes V to be approximately 0.1% lower than nominal, while a SS OUT leakage of 500 nA (about 1 MΩ) causes V to be approximately 1% lower than nominal. Typical ceramic OUT capacitors have a factor of 10× difference in leakage between 25°C and 85°C, so the maximum ambient temperaturemustbeincludedinthecapacitorselectionprocess. Typical C values are in the range of 1 nF to 100 nF, providing typical soft-start times in the range of 70 μs to 7 SS ms (5τ). Values less than 1 nF may be used, but the soft-start effect will be minimal. Values larger than 100 nF provide soft start but may not be fully discharged if V falls from the UVLVO threshold to less than 500 mV in BIAS lessthan100µs. Figure22showstherelationshipbetweentheC valueandatypicalC value. OUT SS 12 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 Feature Description (continued) Figure22. TypicalC vsC Values SS OUT The C capacitor must be connected to a clean ground path back to the device ground pin. No components, SS otherthanC ,mustbeconnectedtotheSSpin,astherecouldbeadverseeffectstoV . SS OUT If the soft-start function is not needed the SS pin must be left open, although some minimal capacitance value is alwaysrecommended. 7.3.5 SettingTheOutputVoltage The output voltage is set using the external resistive divider R1 and R2 (see Figure 23). The output voltage is givenbyEquation2: § • §R1• V =V x ¤1+¤ ‚‚¤ OUT ADJ ' 'R2„„ (2) The resistors used for R1 and R2 must be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of V is specified, the use of low-quality ADJ resistorsforR1andR2caneasilyproduceaV valuethatisunacceptable. OUT It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F pole set by R1 and Z C . FF ((R1×R2)/(R1+R2))≤10kΩ (3) Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for C , for a range of V values. Other values of R1, R2, and C are available that give FF OUT FF similarresults. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com Table1.SuggestedResistorValues V R1 R2 C F OUT FF Z 0.8V 1.07kΩ 1.78kΩ 12nF 12.4kHz 0.9V 1.50kΩ 1.87kΩ 8.2nF 12.9kHz 1V 1.00kΩ 1.00kΩ 12nF 13.3kHz 1.1V 1.65kΩ 1.37kΩ 8.2nF 11.8kHz 1.2V 1.40kΩ 1.00kΩ 10nF 11.4kHz 1.3V 1.15kΩ 715Ω 12nF 11.5kHz 1.4V 1.07kΩ 590Ω 12nF 12.4kHz 1.5V 2.00kΩ 1.00kΩ 6.8nF 11.7kHz 1.6V 1.65kΩ 750Ω 8.2nF 11.8kHz 1.7V 2.55kΩ 1.07kΩ 5.6nF 11.1kHz 1.8V 2.94kΩ 1.13kΩ 4.7nF 11.5kHz Refer to the TI Application Note AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable Regulators(SNVA112)foradditionalinformationonhowresistortolerancesaffectthecalculatedV value. OUT 7.3.6 Enable(EN)Operation The EN pin provides a mechanism to enable, or disable, the regulator output stage. The EN pin has an internal pullup, through a typical 180-kΩ resistor, to V . The EN pin can be left open or connected V if the enable BIAS BIAS functionisnotneeded. 7.4 Device Functional Modes 7.4.1 InputVoltage The input voltage (V ) is the high-current external voltage rail that is regulated down to a lower voltage, which is IN appliedtotheload.TheinputvoltagemustbeatleastV +V ,andnohigherthanwhatevervalueisusedfor OUT DO V . BIAS For applications where V is higher than 4.5 V, V must be no greater than 4.5 V, otherwise output voltage BIAS IN accuracymaybeaffected. 7.4.2 BiasVoltage The bias voltage (V ) is a low-current external voltage rail required to bias the control circuitry and provide BIAS gate drive for the N-FET pass transistor. When V is set to 1.2 V, or less, V may be anywhere in the OUT BIAS operating range of 3 V to 5.5 V. If V is set higher than 1.2 V, V must be between 4.5 V and 5.5 V to OUT BIAS ensureproperoperationofthedevice. 7.4.3 EnableOperation If the EN pin is actively driven, pulling the EN pin above the V threshold of 1.25 V (typical) turns on the EN regulator output; pulling the EN pin below the V threshold turns off the regulator output. There is approximately EN 100mVofhysteresisbuiltintotheenablethresholdprovidenoiseimmunity. If the enable function is not needed the EN pin must be left open, or connected directly to V . If the EN pin is BIAS left open, stray capacitance on this pin must be minimized; otherwise, the output turnon is delayed while the straycapacitanceischargedthroughtheinternalresistance(r ). EN 14 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The typical applications of the LP38853 include DSP supplies, microcontroller supplies, and post regulators. Figure23showsthetypicalapplicationcircuitforLP38853. 8.2 Typical Application LP38853 VIN IN OUT VOUT CIN 10 PF CFF R1 VBIAS BIAS VEN C1 BPIAFS EN ADJ R2 C10O UPTF SS GND CSS GND GND Figure23. LP38853TypicalApplication 8.2.1 DesignRequirements Fortypicallinearregulatorapplications,usetheparameterslistedinTable2. Table2.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltage 1.8V Outputvoltage 0.8V Outputcurrent 3A 8.2.2 DetailedDesignProcedure 8.2.2.1 ExternalCapacitors Toassureregulatorstability,inputandoutputcapacitorsarerequiredasshownintheFigure23. 8.2.2.1.1 InputCapacitor The input capacitor must be at least 10 µF, but can be increased without limit. Its purpose is to provide a low sourceimpedancefortheregulatorinput.Aceramiccapacitor,X5RorX7R,isrecommended. Tantalum capacitors may also be used at the input pin. There is no specific equivalent series resistance (ESR) limitationontheinputcapacitor(thelower,thebetter). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com 8.2.2.1.2 OutputCapacitor A minimum output capacitance of 10-µF ceramic is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the OUT pin of the device andreturnedtothedevicegroundpinwithacleananalogground. Only high-quality ceramic types such as X5R or X7R must be used, as the Z5U and Y5F types do not provide sufficientcapacitanceovertemperature. Tantalum capacitors also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10-µF ceramic capacitor at the output allows unlimited capacitance, tantalum or aluminum, to be addedinparallel. 8.2.2.1.3 BiasCapacitor The capacitor on the bias pin must be at least 1 µF and can be any good-quality capacitor (ceramic is recommended). 8.2.2.1.4 SetTheOutputVoltage AccordingtoTable1,R1issetto1.07kΩ,R2issetto1.78kΩ. 8.2.2.1.5 FeedForwardCapacitor,C FF When using a ceramic capacitor for C , the typical ESR value may be too small to provide any meaningful OUT positive phase compensation, F , to offset the internal negative phase shifts in the gain loop (see Figure 23 and Z Equation4). F =(1/(2×π×C ×ESR)) (4) Z OUT A capacitor placed across the gain resistor R1 provides additional phase margin to improve load transient response of the device. This capacitor, C , in parallel with R1, forms a zero in the loop response given by FF Equation5: F =(1/(2×π×C ×R1)) (5) Z FF For optimum load transient response select C so the zero frequency, F , falls between 10 kHz and 15 kHz as FF Z showninEquation6: (C =(1/(2×π×R1×F ) (6) FF Z The phase lead provided by C diminishes as the DC gain approaches unity, or V approaches V . This is FF OUT ADJ becauseC alsoformsapolewithafrequencyshowninEquation7: FF F =(1/(2×π×C ×(R1||R2))) (7) P FF NOTE It is important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far apart in frequency. At lower output voltages the frequency of the pole and the zero move closer together. The phase lead provided from C diminishes FF quickly as the output voltage is reduced, and has no effect when V = V . For this OUT ADJ reason, relying on this compensation technique alone is adequate only for higher output voltages. For the LP38853, the practical minimum V is 0.8 V when a ceramic capacitor OUT isusedforC . OUT 16 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 Figure24.F andF vsGain ZERO POLE 8.2.2.2 PowerDissipationandHeatSinking Additional copper area for heat sinking may be required, depending on the maximum device dissipation (P ) and D the maximum anticipated ambient temperature (T ) for the device. Under all possible conditions, the junction A temperaturemustbewithintherangespecifiedunderoperatingconditions. Thetotalpowerdissipationofthedeviceisthesumofthreedifferentpointsofdissipationinthedevice. ThefirstpartisthepowerthatisdissipatedintheNMOSpasselementandcanbedeterminedwithEquation8: P =(V –V )×I (8) D(PASS) IN OUT OUT The second part is the power that is dissipated in the bias and control circuitry and can be determined with Equation9: P =V ×I D(BIAS) BIAS GND(BIAS) where • I istheportionoftheoperatinggroundcurrentofthedevicethatisrelatedtoV . (9) GND(BIAS) BIAS The third part is the power that is dissipated in portions of the output stage circuitry and can be determined with Equation10: P =V ×I D(IN) IN GND(IN) where • I istheportionoftheoperatinggroundcurrentofthedevicethatisrelatedtoV . (10) GND(IN) IN ThetotalpowerdissipationisshownbyEquation11: P =P +P +P (11) D D(PASS) D(BIAS) D(IN) The maximum allowable junction temperature rise (ΔT ) depends on the maximum anticipated ambient J temperature (T ) for the application, and the maximum allowable operating junction temperature A(MAX) (T )(seeEquation12): J(MAX) ΔT =T –T (12) J J(MAX) A(MAX) The maximum allowable value for junction-to-ambient thermal resistance, R , can be calculated using θJA Equation13: ’T RTJAd PDJ (13) Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com 8.2.3 ApplicationCurves Figure25.LoadTransientResponse Figure26.LoadTransientResponse Figure27.LoadTransientResponse Figure28.LoadTransientResponse Figure29.LoadTransientResponse Figure30.LoadTransientResponse 18 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

LP38853 www.ti.com SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 9 Power Supply Recommendations TheLP38853deviceisdesignedtooperatefromaninputvoltagesupplyrangefrom3Vand5.5V.Theinput voltagerangeprovidesadequateheadroominorderforthedevicetohavearegulatedoutput.Thisinputsupply mustbewellregulated.Aninputcapacitorofatleast10 μFisrequired. 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and therebyreducesloadcurrenttransients,minimizesnoise,andincreasescircuitstability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread heat from the LDO device when connectedtothePowerPAD.Inmostapplications,thisgroundplaneisnecessarytomeetthermalrequirements. 10.2 Layout Examples S N N D J T S S E I N D U A G A O BI CSS 1 2 3 4 5 6 7 CBIAS R1 R2 V CFF V EN BIAS V CIN COUT V IN OUT GND GND Figure31. LP38853DDPAK/TO-263andTO-220LayoutExample GND R2 1 ADJ NC 8 COUT CIN VOUT CFFR1 2 OUT IN 7 VIN VBIAS 3 BIAS EN 6 VEN CBIAS 4 GND SS 5 GND CSS Figure32. LP38853SOPowerPADLayoutExample Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP38853

LP38853 SNVS335F–DECEMBER2006–REVISEDNOVEMBER2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Foradditionalinformation,seethefollowing: AN-1378MethodforCalculatingOutputVoltageTolerancesinAdjustableRegulators 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP38853

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP38853MR-ADJ NRND SO PowerPAD DDA 8 95 TBD Call TI Call TI -40 to 125 L38853 MRADJ LP38853MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS SN Level-3-260C-168 HR -40 to 125 L38853 & no Sb/Br) MRADJ LP38853MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 L38853 & no Sb/Br) MRADJ LP38853S-ADJ NRND DDPAK/ KTW 7 45 TBD Call TI Call TI -40 to 125 LP38853S TO-263 ADJ LP38853S-ADJ/NOPB ACTIVE DDPAK/ KTW 7 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP38853S TO-263 & no Sb/Br) ADJ LP38853SX-ADJ/NOPB ACTIVE DDPAK/ KTW 7 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP38853S TO-263 & no Sb/Br) ADJ LP38853T-ADJ/NOPB ACTIVE TO-220 NDZ 7 45 Green (RoHS SN Level-1-NA-UNLIM -40 to 125 LP38853T & no Sb/Br) ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP38853MRX-ADJ/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Power PAD LP38853SX-ADJ/NOPB DDPAK/ KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP38853MRX-ADJ/NOPB SOPowerPAD DDA 8 2500 367.0 367.0 35.0 LP38853SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DDA0008A PowerPAD T M SOIC - 1.7 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.2 TYP 5.8 SEATING PLANE A PIN 1 ID 0.1 C AREA 6X 1.27 8 1 5.0 2X 4.8 3.81 NOTE 3 4 5 0.51 8X 0.31 B 4.0 1.7 MAX 3.8 0.25 C A B NOTE 4 0.25 TYP 0.10 SEE DETAIL A 4 5 EXPOSED THERMAL PAD 0.25 2.34 2.24 GAGE PLANE 0.15 0 - 8 1.27 0.00 1 8 0.40 DETAIL A 2.34 TYPICAL 2.24 4218825/A 05/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012. www.ti.com

EXAMPLE BOARD LAYOUT DDA0008A PowerPAD T M SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.95) NOTE 9 SOLDER MASK (2.34) DEFINED PAD SOLDER MASK OPENING SEE DETAILS 8X (1.55) 1 8 8X (0.6) SYMM (2.34) (1.3) SOLDER MASK TYP OPENING (4.9) NOTE 9 6X (1.27) 5 4 (R0.05) TYP SYMM METAL COVERED ( 0.2) TYP BY SOLDER MASK VIA (1.3) TYP (5.4) LAND PATTERN EXAMPLE SCALE:10X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL SOLDER MASK METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4218825/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DDA0008A PowerPAD T M SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.34) BASED ON 0.125 THICK STENCIL 8X (1.55) (R0.05) TYP 1 8 8X (0.6) SYMM (2.34) BASED ON 0.125 THICK STENCIL 6X (1.27) 5 4 METAL COVERED BY SOLDER MASK SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.4) THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.62 X 2.62 0.125 2.34 X 2.34 (SHOWN) 0.150 2.14 X 2.14 0.175 1.98 X 1.98 4218825/A 05/2016 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA NDZ0007B TA07B (Rev E) www.ti.com

MECHANICAL DATA KTW0007B TS7B (Rev E) BOTTOM SIDE OF PACKAGE www.ti.com

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