LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 (cid:2) Low Power Drain...900 μW Typical With LP211...D PACKAGE 5-V Supply LP311...D, P, OR PS PACKAGE (cid:2) Operates From ±15 V or From a Single (TOP VIEW) Supply as Low as 3 V EMIT OUT 1 8 VCC+ (cid:2) Output Drive Capability of 25 mA IN+ 2 7 COL OUT (cid:2) Emitter Output Can Swing Below Negative IN− 3 6 BAL/STRB Supply VCC− 4 5 BALANCE (cid:2) Response Time...1.2 μs Typ (cid:2) Low Input Currents: Offset Current ...2 nA Typ Bias Current...15 nA Typ (cid:2) Wide Common-Mode Input Range: −14.5 V to 13.5 V Using ±15-V Supply (cid:2) Offset Balancing and Strobe Capability (cid:2) Same Pinout as LM211, LM311 (cid:2) Designed To Be Interchangeable With Industry-Standard LP311 description/ordering information The LP211 and LP311 devices are low-power versions of the industry-standard LM211 and LM311 devices. They take advantage of stable, high-value, ion-implanted resistors to perform the same function as the LM311 series, with a 30:1 reduction in power consumption, but only a 6:1 slowdown in response time. They are well suited for battery-powered applications and all other applications where fast response times are not needed. They operate over a wide range of supply voltages, from ±18 V down to a single 3-V supply with less than 300-μA current drain, but are still capable of driving a 25-mA load. The LP211 and LP311 are quite easy to apply free of oscillation if ordinary precautions are taken to minimize stray coupling from the output to either input or to the trim pins. In addition, offset balancing is available to minimize input offset voltage. Strobe capability also is provided to turn off the output (regardless of the inputs) by pulling the strobe pin low. The LP211 is characterized for operation from −25°C to 85°C. The LP311 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION TA VAITO 2m5°aCx PACKAGE† POARRDT ENRUAMBBLEER MTOAPR-KSIINDGE PDIP (P) Tube of 50 LP311P LP311P Tube of 75 LP311D −00°°CC ttoo 7700°°CC 77.55 mmVV SSOOIICC ((DD)) LLPP331111 Reel of 2500 LP311DR SOP (PS) Reel of 2000 LP311PSR L311 Tube of 75 LP211D −2255°°CC ttoo 8855°°CC 77.55 mmVV SSOOIICC ((DD)) LLPP221111 Reel of 2500 LP211DR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 functional block diagram BALANCE BAL/STRB IN+ COL OUT IN− EMIT OUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (see Note 1): V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V CC+ V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V CC− Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V ID Input voltage, V (either input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V I Voltage from emitter output to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V CC− Voltage from collector output to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V CC− Voltage from collector output to emitter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Package thermal impedance, θ (see Notes 5 and 6): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W JA P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC−. 2. Differential input voltages are at IN+ with respect to IN−. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage of ±15 V, whichever is less. 4. The output may be shorted to ground or to either power supply. θ 5. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX UNIT (|VCC±| ≤ 15 V) Input voltage VCC− + 0.5 VCC+ − 1.5 V VCC+ − VCC− Supply voltage 3.5 30 V 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP† MAX UNIT 25°C 2 7.5 VVID IInnppuutt ooffffsseett vvoollttaaggee RRSS < 110000 kkΩΩ, SSeeee NNoottee 77 Full range 10 mmVV VVIIDD << −1100 mmVV,, IIOOLL == 2255 mmAA,, 2255°°CC 00.44 11.55 See Note 8 VOL Low-level output voltage VCC = 4.5 V, VCC− = 0, V VVID << −1100 mmVV, IIOL = 11.66 mmAA, FFuullll rraannggee 00.11 00.44 See Note 8 25°C 2 25 IIIO IInnppuutt ooffffsseett ccuurrrreenntt SSeeee NNoottee 77 Full range 35 nnAA 25°C 15 100 IIIB IInnppuutt bbiiaass ccuurrrreenntt Full range 150 nnAA LLooww-lleevveell ssttrroobbee ccuurrrreenntt VV((ssttrroobbee)) == 00..33 VV,, VVIIDD << −1100 mmVV,, 2255°°CC 110000 330000 μAA See Note 9 IO(off) Output off-state current VID > 10 mV, VCE = 35 V 25°C 0.2 100 nA LLaarrggee-ssiiggnnaall ddiiffffeerreennttiiaall-vvoollttaaggee AAVD amplification RRL = 55 kkΩΩ 2255°°CC 4400 110000 VV//mmVV ICC+ Supply current from VCC+ VID = −50 mV, RL = ∞ Full range 150 300 μA ICC− Supply current from VCC− VID = 50 mV, RL = ∞ Full range − 80 − 180 μA †All typical values are at VCC± = ±15 V, TA = 25°C. NOTES: 7. The offset voltages and offset currents given are the maximum values required to drive the output within 1 V of either supply with a 1-mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and input impedance. 8. Voltages are with respect to EMIT OUT and VCC− tied together. 9. The strobe should not be shorted to ground; it should be current driven at 100 μA to 300 μA. switching characteristics, VCC± = ±5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP UNIT Response time See Note 10 1.2 μs NOTE 10:The response time is specified for a 100-mV input step with 5-mV overdrive. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 TYPICAL APPLICATION CIRCUIT VCC+ 3 kΩ BAL/STRB 3 kΩ TTL Strobe 2N2222 BAL/ BALANCE STRB 15 kΩ NOTE: Do not connect strobe pin directly to ground, because the NOTE: If offset balancing is not used, output is turned off whenever the BALANCE and BAL/STRB current is pulled from the strobe pins should be shorted together. pin. Figure 1. Offset Balan cing Figure 2. Strobing 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP211D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 & no Sb/Br) LP211DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 & no Sb/Br) LP211DRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 & no Sb/Br) LP211DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 & no Sb/Br) LP311D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 & no Sb/Br) LP311DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 & no Sb/Br) LP311DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 & no Sb/Br) LP311P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 LP311P & no Sb/Br) LP311PE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 LP311P & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP211DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 LP311DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP211DR SOIC D 8 2500 340.5 338.1 20.6 LP311DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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