Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 LP2954, LP2954A 5-V and Adjustable Micropower LDOs 1 Features 3 Description • 5-VOutputwithin1.2%OverTemperature The LP2954 is a 5-V micropower LDO with very low 1 quiescent current (90 μA typical at 1-mA load) and (AGrade) very low dropout voltage (typically 60 mV at light • Adjustable1.23-Vto29-VOutputVoltage loadsand470mVat250-mAloadcurrent). Available(LP2954IMandLP2954AIM) The quiescent current increases only slightly at • Ensured250-mAOutputCurrent dropout(120μAtypical),whichprolongsbatterylife. • ExtremelyLowQuiescentCurrent The LP2954 with a fixed 5-V output is available in • LowDropoutVoltage three-pin TO-220 and DDPAK/TO-263 packages. The • ReverseBatteryProtection adjustable LP2954 is provided in an 8-pin, small- • ExtremelyTightLineandLoadRegulation outline SOIC package. The adjustable version also provides a resistor network which can be pin • VeryLowTemperatureCoefficient strapped to set the output to any voltage from to • CurrentandThermalLimiting 1.23Vto29V. • PinCompatiblewithLM2940andLM340 ReversebatteryprotectionisprovidedfortheINpin. (5-VVersionOnly) The tight line and load regulation (0.04% typical), as • AdjustableVersionAddsERROR FlagtoWarnof well as very low output temperature coefficient make OutputDropandaLogic-ControlledShutdown the LP2954 well suited for use as a low-power voltagereference. 2 Applications Output accuracy is ensured at both room temperature • High-EfficiencyLinearRegulator andovertheentireoperatingtemperaturerange. • LowDropoutBattery-PoweredRegulator DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(8) 4.90mm×3.91mm LP2954 DDPAK/TO-263(3) 10.18mm×8.41mm TO-220(3) 14.986mm×10.16mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic V IN OUT V IN OUT GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 13 2 Applications........................................................... 1 8.1 ApplicationInformation............................................13 3 Description............................................................. 1 8.2 TypicalApplication .................................................13 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 17 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 18 6 Specifications......................................................... 4 10.1 LayoutGuidelines.................................................18 6.1 AbsoluteMaximumRatings......................................4 10.2 LayoutExample....................................................18 6.2 ESDRatings..............................................................4 11 DeviceandDocumentationSupport................. 19 6.3 RecommendedOperatingConditions.......................4 11.1 RelatedDocumentation .......................................19 6.4 ThermalInformation..................................................4 11.2 RelatedLinks........................................................19 6.5 ElectricalCharacteristics...........................................5 11.3 ReceivingNotificationofDocumentationUpdates19 6.6 TypicalCharacteristics..............................................7 11.4 CommunityResources..........................................19 7 DetailedDescription............................................ 10 11.5 Trademarks...........................................................19 7.1 Overview.................................................................10 11.6 ElectrostaticDischargeCaution............................19 7.2 FunctionalBlockDiagrams.....................................10 11.7 Glossary................................................................19 7.3 FeatureDescription.................................................11 12 Mechanical,Packaging,andOrderable Information........................................................... 20 7.4 DeviceFunctionalModes........................................12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(March2013)toRevisionE Page • Changed"voltageregulator"to"LDO".................................................................................................................................... 1 • AddedDeviceInformationandPinConfigurationandFunctionssections,ESDRatingsandThermalInformation tables,FeatureDescription,DeviceFunctionalModes,ApplicationandImplementation,PowerSupply Recommendations,Layout,DeviceandDocumentationSupport,andMechanical,Packaging,andOrderable Informationsections;addedtopnaviconforTIDesigns....................................................................................................... 1 • ChangedR valueforDDPAK/TO-263from"73°C/W"to"44.3°C/W";TO-220from"60°C/W"to"80.3°C/W";SOIC θJA from"160°C/W"to"105.0°C/W".ThesevalueswereinformerFN3toAbsMaxtable......................................................... 4 • AddedPowerDissipation..................................................................................................................................................... 15 • AddedEstimatingJunctionTemperature............................................................................................................................. 15 ChangesfromRevisionC(March2013)toRevisionD Page • ChangedlayoutofNationalSemiconductordatasheettoTIformat.................................................................................... 18 2 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 5 Pin Configuration and Functions NDEPackage KTTPackage 3-PinTO-220 3-PinDDPAK/TO-263 FrontView FrontView DPackage 8-PinSOIC Top PinFunctions PIN I/O DESCRIPTION NAME NDE KTT D ERROR — — 5 O Erroroutput FEEDBACK — — 7 I Voltagefeedbackinput IN 1 1 8 I Unregulatedinputvoltage GND 2 2 4 — Ground Regulatedoutputvoltage.Thispinrequiresanoutputcapacitorto OUT 3 3 1 O maintainstability.SeeDetailedDesignProcedureforoutputcapacitor details SENSE — — 2 I Outputvoltagesense SHUTDOWN — — 3 I Disabledevice 5VTAP — — 6 O Internalresistordivider Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT Inputsupplyvoltage –20 30 V Powerdissipation(1) InternallyLimited Storagetemperature,T –65 150 °C stg (1) Atelevatedtemperatures,devicepowerdissipationmustbederatedbasedonpackagethermalresistanceandheatsinkvalues(ifa heatsinkisused).Ifpowerdissipationcausesthejunctiontemperaturetoexceedspecifiedlimits,thedevicegoesintothermal shutdown. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Operatingjunctiontemperature –40 125 °C 6.4 Thermal Information LP2954,LP2954A THERMALMETRIC(1) KTT(DDPAK/TO-263) NDE(TO-220) D(SOIC) UNIT 3PINS 3PINS 8PINS R (2) Junction-to-ambientthermalresistance,High-K 44.3 80.3(3) 105.0 °C/W θJA R Junction-to-case(top)thermalresistance 44.8 38.6 47.3 °C/W θJC(top) R Junction-to-boardthermalresistance 23.8 73.1 45.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 10.6 13.5 6.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 22.7 73.1 45.2 °C/W JB R Junction-to-case(bottom)thermalresistance 1.0 0.9 — °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seeSemiconductorandICPackageThermalMetrics. (2) ThermalresistancevalueR isbasedontheEIA/JEDECHigh-KprintedcircuitboarddefinedbyJESD51-7-HighEffectiveThermal θJA ConductivityTestBoardforLeadedSurfaceMountPackages. (3) TheTO-220(NDE)packageisverticallymountedincenterofJEDECHigh-Ktestboard(JESD51-7)withnoadditionalheatsink.Thisis athrough-holepackage;thisisNOTasurfacemountpackage. 4 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 6.5 Electrical Characteristics LimitsarespecifiedbyproductiontestingorcorrelationtechniquesusingstandardStatisticalQualityControl(SQC)methods. Unlessotherwisenoted:T =25°C,V =6V,I =1mA,C =2.2μF J IN L L LP2954AI LP2954I PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX 4.975 5 5.025 4.95 5 5.05 −40°Cto125°C 4.94 5.06 4.9 5.1 VO Outputvoltage(1) 1mA≤IL≤250mA 5 5 V 1mA≤I ≤250mA L 4.93 5.07 4.88 5.12 −40°Cto125°C ΔV /ΔT Outputvoltagetemperature See(2),–40°C≤T ≤125°C 20 100 20 150 ppm/°C O coefficient J V =6Vto30V 0.03% 0.1% 0.03% 0.2% IN ΔVO/VO Lineregulation VIN=6Vto30V 0.2% 0.3% –40°C≤T ≤125°C J I =1to250mA IL=0.1to1mA(3) 0.04% 0.16% 0.04% 0.2% L ΔVO/VO Loadregulation IL=1to250mA I =0.1to1mA 0.2% 0.3% L –40°C≤T ≤125°C J I =1mA 60 100 60 100 L I =1mA L 150 150 –40°C≤T ≤125°C J I =50mA 240 300 240 300 L I =50mA, L 420 420 –40°C≤T ≤125°C V –V Dropoutvoltage(4) J mV IN O I =100mA 310 400 310 400 L I =100mA L 520 520 –40°C≤T ≤125°C J I =250mA 470 600 470 600 L I =250mA L 800 800 –40°C≤T ≤125°C J I =1mA 90 150 90 150 L I =1mA µA L 180 180 –40°C≤T ≤125°C J I =50mA 1.1 2 1.1 2 L I =50mA L 2.5 2.5 –40°C≤T ≤125°C I Groundpincurrent(5) J GND I =100mA 4.5 6 4.5 6 L I =100mA mA L 8 8 –40°C≤T ≤125°C J I =250mA 21 28 21 28 L I =250mA L 33 33 –40°C≤T ≤125°C J V =4.5V 120 170 120 170 IN Groundpincurrentat IGND dropout(5) VIN=4.5V 210 210 µA –40°C≤T ≤125°C J (1) Whenusedindual-supplysystemswheretheregulatorloadisreturnedtoanegativesupply,theoutputvoltagemustbediode-clamped toground. (2) Outputvoltagetemperaturecoefficientisdefinedastheworst-casevoltagechangedividedbythetotaltemperaturerange. (3) Regulationismeasuredatconstantjunctiontemperatureusinglowdutycyclepulsetesting.Partsaretestedseparatelyforload regulationintheloadranges0.1mAto1mAand1mAto250mA.Changesinoutputvoltageduetoheatingeffectsarecoveredbythe thermalregulationspecification. (4) Dropoutvoltageisdefinedastheinput-to-outputdifferentialatwhichtheoutputvoltagedrops100mVbelowthevaluemeasuredwitha 1-Vdifferential. (5) GNDpincurrentistheregulatorquiescentcurrent.ThetotalcurrentdrawnfromthesourceisthesumoftheloadcurrentplustheGND pincurrent. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com Electrical Characteristics (continued) LimitsarespecifiedbyproductiontestingorcorrelationtechniquesusingstandardStatisticalQualityControl(SQC)methods. Unlessotherwisenoted:T =25°C,V =6V,I =1mA,C =2.2μF J IN L L LP2954AI LP2954I PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX V =0V 380 500 380 500 O ILIMIT Currentlimit VO=0V 530 530 mA –40°C≤T ≤125°C J ΔV /ΔP Thermalregulation See(6) 0.05 0.2 0.05 0.2 %/W O D I =100mA,C =2.2µF 400 400 L L Outputnoise e I =100mA,C =33µF 260 260 μV n 10Hzto100kHz L L RMS I =100mA,C =33µF(7) 80 80 L L ADDITIONALSPECIFICATIONSFORTHEADJUSTABLEDEVICE(LP2954AIMandLP2954IM) See(8) 1.215 1.23 1.245 1.205 1.23 1.255 VREF Referencevoltage See(8) 1.205 1.255 1.19 1.27 V –40°C≤T ≤125°C J V =2.5VtoV +1V 0.03% 0.1% 0.03% 0.2% IN O(NOM) ΔV / Referencevoltageline REF VREF regulation V30IN=V(29).5(8)V–4t0o°VCO≤(NTOM≤)+1125V°Cto 0.2% 0.4% J Referencevoltage See(2) ΔV /ΔT 20 ppm/°C REF temperaturecoefficient –40°C≤T ≤125°C J 20 40 20 40 I Feedbackpinbiascurrent nA B(FB) –40°C≤T ≤125°C 60 60 J Groundpincurrentat IGND shutdown(5) VSHUTDOWN≤1.1V 105 140 105 140 μA See(10) 30 30 mA OutputOFFpulldown IO(SINK) current See(10) 20 20 –40°C≤T ≤125°C J DROPOUTDETECTIONCOMPARATOR V =30V 0.01 1 0.01 1 OH OutputHIGHleakage IOH current VOH=30V,–40°C≤TJ≤ 2 2 µA 125°C V =V −0.5V IN O(NOM) I =400μA 150 250 150 250 O(COMP) VOL OutputLOWvoltage –40°C≤TJ≤125°C mV 400 400 See(11) –80 –60 –35 –80 –60 –35 VTHR(MAX) Upperthresholdvoltage See(11) mV –95 –25 –95 –25 –40°C≤T ≤125°C J V See(11) –110 –85 –55 –110 –85 –55 THR(MIN) Lowerthresholdvoltage See(11) mV –160 –40 –160 –40 –40°C≤T ≤125°C J HYST Hysteresis See(11) 15 15 mV (6) ThermalregulationisdefinedasthechangeinoutputvoltageatatimeTafterachangeinpowerdissipationisapplied,excludingload orlineregulationeffects.Specificationsarefor200-mAloadpulseatV =20V(3-Wpulse)forT=10ms. IN (7) Connecta0.1-μFcapacitorfromtheOUTpintotheFEEDBACKpin. (8) V ≤V ≤(V −1V),2.3V≤V ≤30V,100μA≤I ≤250mA. REF OUT IN IN L (9) Twoseparatetestsareperformed,onecoveringV =2.5VtoV +1VandtheothertestforV =2.5VtoV +1Vto30V. IN O(NOM) IN O(NOM) (10) V ≤1.1V,V =V . SHUTDOWN OUT O(NOM) (11) ComparatorthresholdsareexpressedintermsofavoltagedifferentialattheFEEDBACKpinbelowthenominalreferencevoltage measuredatV =V +1V.Toexpressthesethresholdsintermsofoutputvoltagechange,multiplybytheerroramplifiergain, IN O(NOM) whichisV /V =(R1+R2)/R2. OUT REF 6 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 Electrical Characteristics (continued) LimitsarespecifiedbyproductiontestingorcorrelationtechniquesusingstandardStatisticalQualityControl(SQC)methods. Unlessotherwisenoted:T =25°C,V =6V,I =1mA,C =2.2μF J IN L L LP2954AI LP2954I PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX SHUTDOWNINPUT V (ReferredtoV ) −7.5 ±3 7.5 −7.5 ±3 7.5 OS REF Inputoffsetvoltage (ReferredtoV ),–40°C≤T –10 10 –10 10 mV REF J ≤125°C HYST Hysteresis 6 6 mV I V =0Vto5V –30 10 30 –30 10 30 B IN(SHUTDOWN) Inputbiascurrent V =0Vto5V, nA IN(SHUTDOWN) –50 50 –50 50 –40°C≤T ≤125°C J 6.6 Typical Characteristics Figure1.QuiescentCurrent Figure2.QuiescentCurrent Figure3.GroundPinCurrentvsLoad Figure4.GroundPinCurrent Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com Typical Characteristics (continued) Figure5.GroundPinCurrent Figure6.OutputNoiseVoltage Figure7.RippleRejection Figure8.RippleRejection Figure9.RippleRejection Figure10.OutputImpedance 8 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 Typical Characteristics (continued) Figure11.DropoutCharacteristics Figure12.ThermalResponse Figure13.Short-CircuitOutputCurrentandMaximum Figure14.MaximumPowerDissipation(DDPAK/TO-263) OutputCurrent Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com 7 Detailed Description 7.1 Overview The LP2954 is a 5-V micropower LDO with very low quiescent current (90 μA typical at 1-mA load) and very low dropoutvoltage(typically60mVatlightloadsand470mVat250-mAloadcurrent). 7.2 Functional Block Diagrams Figure15. LP2954TO-220andTO-263FunctionalBlockDiagram Figure16. LP2954SOICFunctionalBlockDiagram 10 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 7.3 Feature Description 7.3.1 DropoutVoltage Thedropoutvoltageoftheregulatorisdefinedastheminimuminput-to-outputvoltagedifferentialrequiredforthe output voltage to stay within 100 mV of the output voltage measured with a 1-V differential. The dropout voltages forvariousvaluesofloadcurrentarelistedunderElectricalCharacteristics. If the regulator is powered from a rectified AC source with a capacitive filter, the minimum AC line voltage and maximumloadcurrentmustbeusedtocalculatetheminimumvoltageattheinputoftheregulator.Theminimum input voltage, including AC ripple on the filter capacitor, must not drop below the voltage required to keep the LP2954 in regulation. It is also advisable to verify operating at minimum operating ambient temperature, because the increasing ESR of the filter capacitor makes this a worst-case test for dropout voltage due to increased ripple amplitude. 7.3.2 DropoutDetectionComparator This comparator produces a logic LOW whenever the output falls out of regulation by more than about 5%. The 5% value is from the comparators built-in offset of 60 mV divided by the 1.23-V reference. The 5% low trip level remains constant regardless of the programmed output voltage. An out-of-regulation condition can result from lowinputvoltage,currentlimiting,orthermallimiting. Figure 17 gives a timing diagram showing the relationship between the output voltage, the ERROR output, and inputvoltageastheinputvoltageisrampedupanddowntoaregulatorprogrammedfor5-Voutput.The ERROR signal becomes low at about 1.3-V input. It goes high at about 5-V input, where the output equals 4.75 V. Because the dropout voltage is load dependent, the input voltage trip points vary with load current. The output voltagetrippointdoesnotvary. The comparator has an open-collector output which requires an external pullup resistor. This resistor may be connected to the regulator output or some other supply voltage. Using the regulator output prevents an invalid HIGH on the comparator output which occurs if it is pulled up to an external voltage while the regulator input voltage is reduced below 1.3 V. In selecting a value for the pullup resistor note that, while the output can sink 400 μA, this current adds to battery drain. Suggested values range from 100 kΩ to 1 MΩ. This resistor is not requirediftheoutputisunused. When V ≤ 1.3 V, the ERROR pin becomes a high impedance, allowing the error flag voltage to rise to its pullup IN voltage. Using V as the pullup voltage (rather than an external 5-V source) keeps the error flag voltage below OUT 1.2 V (typical) in this condition. The user may wish to divide down the error flag voltage using equal-value resistors(10kΩsuggested)toensurealow-levellogicsignalduringanyfaultcondition,whilestillallowingavalid highlogiclevelduringnormaloperation. *Inshutdownmode,ERRORgoeshighifithasbeenpulleduptoanexternalsupply.Toavoidthisinvalidresponse, pulluptoregulatoroutput. **Exactvaluedependsondropoutvoltage.(SeeDropoutVoltage) Figure17. ERROR OutputTiming 7.3.3 OutputIsolation Theregulatoroutputcanbeleftconnectedtoanactivevoltagesource(suchasabattery)withtheregulatorinput power turned off, as long as the regulator ground pin is connected to ground. If the ground pin is left floating, damagetotheregulatorcanoccuriftheoutputispulledupbyanexternalvoltagesource. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com Feature Description (continued) 7.3.4 ReducingOutputNoise In reference applications it may be advantageous to reduce the AC noise present on the output. One method is to reduce regulator bandwidth by increasing output capacitance. This is relatively inefficient, because large increasesincapacitancearerequiredtogetsignificantimprovement. Noise can be reduced more effectively by a bypass capacitor placed across R1 (refer to Figure 19). The formula forselectingthecapacitortobeusedis: C =1/2πR1×20Hz (1) B This gives a value of about 0.1 μF. When this is used, the output capacitor must be 6.8 μF (or greater) to maintain stability. The 0.1-μF capacitor reduces the high frequency gain of the circuit to unity, lowering the output noise from 260 μV to 80 μV using a 10-Hz to 100-kHz bandwidth. Also, noise is no longer proportional to the outputvoltage,soimprovementsaremorepronouncedathighoutputvoltages. 7.4 Device Functional Modes 7.4.1 ShutdownInput Alogic-levelsignalshutsofftheregulatoroutputwhenaLOW(< 1.2V)isappliedtothe SHUTDOWNinput. To prevent possible mis-operation, the SHUTDOWN input must be actively terminated. If the input is driven from open-collector logic, a pullup resistor (TI recommends 20 kΩ to 100 kΩ) must be connected from the SHUTDOWNinputtotheregulatorinput. If the SHUTDOWN input is driven from a source that actively pulls high and low (like an operational amplifier), thepullupresistorisnotrequired,butmaybeused. If the shutdown function is not to be used, the cost of the pullup resistor can be saved by simply tying the SHUTDOWNinputdirectlytotheregulatorinput. IMPORTANT: Because the Absolute Maximum Ratings state that the SHUTDOWN input cannot go more than 0.3 V below ground, the reverse-battery protection feature that protects the regulator input is sacrificed if the SHUTDOWNinputistieddirectlytotheregulatorinput. If reverse-battery protection is required in an application, the pullup resistor between the SHUTDOWN input and the regulator input must be used. The recommended 20 kΩ to 100 kΩ provides adequate protection of the SHUTDOWNpinduringnegativevoltagetransitionsattheINpin. 12 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The LP2954-N is a linear voltage regulator operating from 2.3 V to 30 V on the input and regulated output voltage of 5 V with typical 0.5% accuracy (LP2954AI) and 250 mA maximum output current. For linear voltage regulator the efficiency is defined by the ratio of output voltage to input voltage (efficiency = V /V ). To OUT IN achieve high efficiency, the dropout voltage (V – V ) must be as small as possible, thus requiring a very low IN OUT dropout LDO. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to ensure a solid design. If timing, start-up, noise, PSRR, or any other transientspecificationisrequired,thedesignbecomesmorechallenging. 8.2 Typical Application 5 V OUT V IN OUT IN GND LOAD 1 µF 2.2 µF Figure18. LP2954TypicalApplication 8.2.1 DesignRequirements FortypicalLDOapplications,usetheparameterslistedinTable1. Table1.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltage 2.5Vto30V Outputvoltage 1.23Vto29V Outputcurrent 250mA(maximum) RMSnoise,10Hzto100kHz 260μV RMS 8.2.2 DetailedDesignProcedure 8.2.2.1 ExternalCapacitors A 2.2 μF (or greater) capacitor is required between the OUT pin and GND to assure stability (refer to Figure 20). Without this capacitor, the device may oscillate. Most types of tantalum or aluminum electrolytic capacitors work here. Film-type capacitors work, but are more expensive. Many aluminum electrolytics contain electrolytes which freeze at −30°C, which requires the use of solid tantalums below −25°C. The important parameters of the capacitor are an equivalent series resistance (ESR) of about 5 Ω or less and a resonant frequency above 500 kHz (the ESR may increase by a factor of 20 or 30 as the temperature is reduced from 25°C to −30°C). The value of this capacitor may be increased without limit. At lower values of output current, less output capacitance isrequiredforstability.Thecapacitorcanbereducedto0.68 μFforcurrentsbelow10mAor0.22 μFforcurrents below1mA. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com Place a 1-μF capacitor from the IN pin to GND if there is more than 10 inches of wire between the input and the ACfiltercapacitororifabatteryinputisused. Programming the output for voltages below 5 V runs the error amplifier at lower gains requiring more output capacitance for stability. At 3.3-V output, a minimum of 4.7 μF is required. For the worst case condition of 1.23-V outputand250mAofloadcurrent,a6.8-μF(orlarger)capacitormustbeused. Stray capacitance to the FEEDBACK pin can cause instability. This problem is most likely to appear when using high value external resistors to set the output voltage. Adding a 100-pF capacitor between the OUT and FEEDBACKpinsandincreasingtheoutputcapacitanceto6.8 μF(orgreater)solvestheproblem. 8.2.2.2 MinimumLoad When setting the output voltage using an external resistive divider, TI recommends a minimum current of 1 μA throughtheresistorstoprovideaminimumload. It should be noted that a minimum load current is specified in several of the electrical characteristic test conditions, so this value must be used to obtain correlation on these tested limits. The part is parametrically testeddownto100μA,butisfunctionalwithnoload. 8.2.2.3 ProgrammingTheOutputVoltage The SOIC version of the LP2954 regulator may be pin strapped for 5-V operation using its internal resistive dividerbytyingtheOUTandSENSEpinstogetherandalsotyingtheFEEDBACKand5VTAPpinstogether. Alternatively, it may be programmed for any voltage between the 1.23-V reference and the 30-V maximum rating usinganexternalpairofresistors(seeFigure19).Thecompleteequationfortheoutputvoltageis: V =V ×(1+R1/R2)+(I ×R1) (2) OUT REF FB where V is the 1.23-V reference and I is the FEEDBACK pin bias current (−20 nA typical). The minimum REF FB recommended load current of 1 μA sets an upper limit of 1.2 MΩ on the value of R2 in cases where the regulator must work with no load (see Minimum Load). I produces a typical 2% error in V which can be eliminated at FB OUT room temperature by trimming R1. For better accuracy, choosing R2 = 100 kΩ reduces this error to 0.17% while increasing the resistor program current to 12 μA. Because the typical quiescent current is 120 μA, this added currentisnegligible. *DrivewithTTL-lowtoshutdown Figure19. AdjustableRegulator 14 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 8.2.2.4 PowerDissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and loadconditionsandcanbecalculatedwithEquation3. P =(V –V )×I (3) D(MAX) IN(MAX) OUT OUT Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (V ). However, keep in mind that higher DO voltagedropsresultinbetterdynamic(thatis,PSRRandtransient)performance. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R ) of the combined PCB and device package and the temperature of the ambient air (T ), according to θJA A Equation4orEquation5: T =T +(R ×P ) (4) J(MAX) A(MAX) θJA D(MAX) P =(T –T )/R (5) D(MAX) J(MAX) A(MAX) θJA Unfortunately, this R is highly dependent on the heat-spreading capability of the particular PCB design, and θJA therefore varies according to the total copper area, copper weight, and location of the planes. The R recorded θJA in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper- spreading area, and is to be used only as a relative measure of package thermal performance. For a well- designed thermal layout, R is actually the sum of the package junction-to-case (bottom) thermal resistance θJA (R )plusthethermalresistancecontributionbythePCBcopperareaactingasaheatsink. θJCbot 8.2.2.5 EstimatingJunctionTemperature The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (Ψ and Ψ ) are given in Thermal Information and are JT JB usedinaccordancewithEquation6orEquation7. T =T +(Ψ ×P ) J(MAX) TOP JT D(MAX) where • P isexplainedinEquation5 D(MAX) • T isthetemperaturemeasuredatthecenter-topofthedevicepackage. (6) TOP T =T +(Ψ ×P ) J(MAX) BOARD JB D(MAX) where • P isexplainedinEquation5. D(MAX) • T isthePCBsurfacetemperaturemeasured1-mmfromthedevicepackageandcenteredonthe BOARD packageedge. (7) For more information about the thermal characteristics Ψ and Ψ , Semiconductor and IC Package Thermal JT JB Metrics; for more information about measuring T and T , see Using New Thermal Metrics; and for more TOP BOARD information about the EIA/JEDEC JESD51 PCB used for validating R , see Thermal Characteristics of Linear θJA andLogicPackagesUsingJEDECPCBDesigns.Theseapplicationnotesareavailableatwww.ti.com. 8.2.2.6 HeatsinkingtheTO-220Package A heat sink may be required with the LP2954IT depending on the maximum power dissipation and maximum ambienttemperatureoftheapplication.Underallpossibleoperatingconditions,thejunctiontemperaturemustbe withintherangespecifiedunderRecommendedOperatingConditions. To determine if a heat sink is required, the maximum power dissipated by the regulator, P , must be (MAX) calculated. It is important to remember that if the regulator is powered from a transformer connected to the AC line, the maximum specified AC input voltage must be used (because this produces the maximum DC input voltage to the regulator). Figure 20 shows the voltages and currents that are present in the circuit. The formula forcalculatingthepowerdissipatedintheregulatorisalsoshowninFigure20. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com *SeeExternalCapacitors P =(((V –V )×I )+(V ×I )) D IN OUT OUT IN G Figure20. Basic5-VRegulatorCircuit The next parameter which must be calculated is the maximum allowable temperature rise, T . This is R(MAX) calculatedbyusingtheformula: T =T −T R(MAX) J(MAX) A(MAX) where • T isthemaximumallowablejunctiontemperature J(MAX) • T isthemaximumambienttemperature (8) A(MAX) Using the calculated values for T and P , the required value for junction-to-ambient thermal resistance, R(MAX) (MAX) R ,cannowbefound: θJA R =T /P (9) θJA R(MAX) (MAX) If the calculated value is 60°C/W or higher , the regulator may be operated without an external heat sink. If the calculated value is below 60°C/W, an external heatsink is required. The required thermal resistance for this heat sinkcanbecalculatedusingtheformula: R =R −R −R θHA θJA θJC(bot) θCH where • R isthejunction-to-casethermalresistance,whichisspecifiedas0.9°C/WmaximumfortheLP2954IT θJC(bot) • R isthecase-to-heat-sinkthermalresistance,whichisdependentontheinterfacingmaterial(ifused).For θCH detailsandtypicalvaluesinTable2andTable3. • R istheheatsink-to-ambientthermalresistance.Itisthisspecification(listedontheheat-sink θ(H-A) manufacturersdatasheet)whichdefinestheeffectivenessoftheheatsink.Theheatsinkselectedmusthave athermalresistancewhichisequaltoorlowerthanthevalueofR calculatedfromtheabovelisted θHA formula. (10) Table2. TypicalValuesofCase-To-HeatsinkThermal Resistance(R )(DatafromAavidEngineering) θCH UNIT (C°/W) Siliconegrease 1 Dryinterface 1.3 Micawithgrease 1.4 Table3. TypicalValuesOfCase-To-HeatsinkThermal Resistance(R )(DatafromThermalloy) θCH UNIT (C°/W) ThermasilIII 1.3 ThermasilII 1.5 Thermalfilm(0.002)withgrease 2.2 16 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 8.2.3 ApplicationCurves Figure21.LineTransientResponse Figure22.LineTransientResponse Figure23.LoadTransientResponse Figure24.LoadTransientResponse 9 Power Supply Recommendations The LP2954 is designed to operate from a minimum input voltage supply of either 2.5 V or V + 1 V, OUT(NOM) whichever is higher. The maximum input supply voltage is 30 V, but may be limited by thermal dissipation of the selected package. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors withlowESRcanhelp.improvetheoutputnoiseperformance. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com 10 Layout 10.1 Layout Guidelines For best overall performance, place all the circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and therebyreducesload-currenttransients,minimizesnoise,andincreasescircuitstability. TI also recommends a ground reference plane and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread heat from the LDO device. In most applications, thisgroundplaneisnecessarytomeetthermalrequirements. 10.2 Layout Example Ground 1 2 3 D IN GN OUT Input Output Capacitor Capacitor VIN VOUT Figure25. LP2954TO-263BoardLayout Output Input Capacitor Capacitor OUT IN VIN VOUT SENSE FEEDBACK Ground SHUTDOWN 5V TAP Error Pullup Resistor GND ERROR VOUT Figure26. LP2954SOICBoardLayout 18 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A www.ti.com SNVS096E–JUNE1999–REVISEDJULY2016 11 Device and Documentation Support 11.1 Related Documentation Foradditionalinformation,seethefollowing: • SemiconductorandICPackageThermalMetrics • UsingNewThermalMetrics • ThermalCharacteristicsofLinearandLogicPackagesUsingJEDECPCBDesigns 11.2 Related Links Table 4 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY LP2954 Clickhere Clickhere Clickhere Clickhere Clickhere LP2954A Clickhere Clickhere Clickhere Clickhere Clickhere 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP2954 LP2954A

LP2954,LP2954A SNVS096E–JUNE1999–REVISEDJULY2016 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:LP2954 LP2954A

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2954AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LP295 4AIM LP2954AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP295 & no Sb/Br) 4AIM LP2954AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP295 & no Sb/Br) 4AIM LP2954AIS/NOPB ACTIVE DDPAK/ KTT 3 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP2954AIS TO-263 & no Sb/Br) LP2954AISX/NOPB ACTIVE DDPAK/ KTT 3 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP2954AIS TO-263 & no Sb/Br) LP2954AIT/NOPB ACTIVE TO-220 NDE 3 45 Green (RoHS SN Level-1-NA-UNLIM -40 to 125 LP2954AIT & no Sb/Br) LP2954IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP29 & no Sb/Br) 54IM LP2954IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP29 & no Sb/Br) 54IM LP2954IS/NOPB ACTIVE DDPAK/ KTT 3 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP2954IS TO-263 & no Sb/Br) LP2954ISX/NOPB ACTIVE DDPAK/ KTT 3 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP2954IS TO-263 & no Sb/Br) LP2954IT/NOPB ACTIVE TO-220 NDE 3 45 Green (RoHS SN Level-1-NA-UNLIM -40 to 125 LP2954IT & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP2954AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2954AISX/NOPB DDPAK/ KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 LP2954IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2954ISX/NOPB DDPAK/ KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP2954AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2954AISX/NOPB DDPAK/TO-263 KTT 3 500 367.0 367.0 45.0 LP2954IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2954ISX/NOPB DDPAK/TO-263 KTT 3 500 367.0 367.0 45.0 PackMaterials-Page2

MECHANICAL DATA NDE0003B www.ti.com

MECHANICAL DATA KTT0003B TS3B (Rev F) BOTTOM SIDE OF PACKAGE www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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