Product Order Technical Tools & Support & Folder Now Documents Software Community LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 LP295x-N Series of Adjustable Micropower Voltage Regulators 1 Features 3 Description • InputVoltageRange:2.3Vto30V The LP2950-N and LP2951-N are micropower 1 voltage regulators with very low quiescent current • 5-V,3-V,and3.3-VOutputVoltageVersions (75 µA typical) and very low dropout voltage (typical Available 40 mV at light loads and 380 mV at 100 mA). They • HighAccuracyOutputVoltage are ideally suited for use in battery-powered systems. • Ensured100-mAOutputCurrent Furthermore, the quiescent current of the device increases only slightly in dropout, prolonging battery • ExtremelyLowQuiescentCurrent life. • LowDropoutVoltage Careful design of the LP2950-N/LP2951-N has • ExtremelyTightLoadandLineRegulation minimized all contributions to the error budget. This • VeryLowTemperatureCoefficient includes a tight initial tolerance (0.5% typical), • UseasRegulatororReference extremely good load and line regulation (0.05% typical) and a very low output voltage temperature • NeedsMinimumCapacitanceforStability coefficient, making the part useful as a low-power • CurrentandThermalLimiting voltagereference. • StableWithLow-ESROutputCapacitors(10mΩ One such feature is an error flag output which warns to6 Ω) of a low output voltage, often due to falling batteries • LP2951-NVersionsOnly: on the input. It may be used for a power-on reset. A – ErrorFlagWarnsofOutputDropout second feature is the logic-compatible shutdown input which enables the regulator to be switched on and – Logic-ControlledElectronicShutdown off. Also, the part may be pin-strapped for a 5-V, 3-V, – OutputProgrammableFrom1.24Vto29V or 3.3-V output (depending on the version), or programmed from 1.24 V to 29 V with an external 2 Applications pairofresistors. • High-EfficiencyLinearRegulator The LP2950-N is available in the surface-mount TO- • RegulatorwithUndervoltageShutdown 252 package and in the popular 3-pin TO-92 package for pin-compatibility with older 5-V regulators. The 8- • LowDropoutBattery-poweredRegulator pin LP2951-N is available in plastic, ceramic dual-in- • Snap-ON/Snap-OFFRegulator line, WSON, or metal can packages and offers space additionalsystemfunctions. space DeviceInformation(1) space PARTNUMBER PACKAGE BODYSIZE(NOM) space TO-92(3) 4.30mm×4.30mm space LP2950-N TO-252(3) 9.91mm×6.58mm space SOIC(8) 4.90mm×3.91mm space VSSOP(8) 3.00mm×3.00mm LP2951-N space WSON(8) 4.00mm×4.00mm space PDIP(8) 9.81mm×6.35mm (1) For all available packages, see the orderable addendum at LP2951SimplifiedSchematic theendofthedatasheet. LP2951 VOUT VIN LP2950-NSimplifiedSchematic OUT IN COUT CIN LP2950 2.2 µF 1 µF SENSE FEEDBACK VIN IN OUT VOUT SHUTDOWN SHUTDOWN VTAP VFEEDBACK GND ERROR 33R0 1k(cid:13)VOUT C1 IµNF GND C2.O2U µTF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................18 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 19 3 Description............................................................. 1 9.1 ApplicationInformation............................................19 4 RevisionHistory..................................................... 2 9.2 TypicalApplications................................................20 5 VoltageOptions..................................................... 3 10 PowerSupplyRecommendations..................... 32 6 PinConfigurationandFunctions......................... 4 11 Layout................................................................... 32 11.1 LayoutGuidelines.................................................32 7 Specifications......................................................... 5 11.2 LayoutExample....................................................32 7.1 AbsoluteMaximumRatings......................................5 11.3 WSONMounting...................................................33 7.2 ESDRatings..............................................................5 12 DeviceandDocumentationSupport................. 34 7.3 RecommendedOperatingConditions.......................5 7.4 ThermalInformation:LP2950-N................................6 12.1 DocumentationSupport .......................................34 7.5 ThermalInformation:LP2951-N................................6 12.2 RelatedLinks........................................................34 7.6 ElectricalCharacteristics...........................................7 12.3 CommunityResources..........................................34 7.7 TypicalCharacteristics............................................10 12.4 Trademarks...........................................................34 12.5 ElectrostaticDischargeCaution............................34 8 DetailedDescription............................................ 16 12.6 Glossary................................................................34 8.1 Overview.................................................................16 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagrams.....................................16 Information........................................................... 34 8.3 FeatureDescription.................................................17 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionP(May2016)toRevisionQ Page • ChangedLP2951-NESDparameterpinreferencesandaddedSENSEpinrowtoLP2951-NESDparameterinESD Ratingstable........................................................................................................................................................................... 5 ChangesfromRevisionO(December2014)toRevisionP Page • AddedrowstoESDRatingstabletodifferentiatevaluesforpins3and7oftheLP2951-Ndevice...................................... 5 • Addedfootnotes2and3tobothThermalInformationtables ............................................................................................... 6 ChangesfromRevisionN(May2013)toRevisionO Page • AddedDeviceInformationandESDRatingtables,FeatureDescription,DeviceFunctionalModes,Applicationand Implementation,PowerSupplyRecommendations,Layout,DeviceandDocumentationSupport,andMechanical, Packaging,andOrderableInformationsections;movedsomecurvestoApplicationCurvessection;updatepin names;changepackagenomenclaturefromNationaltoTI.................................................................................................. 1 ChangesfromRevisionM(April2013)toRevisionN Page • ChangedlayoutofNationalDataSheettoTIformat ............................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 5 Voltage Options DEVICENUMBER PACKAGE VOLTAGEOPTION(V) 3(±0.5%,±1%) TO-92(LP) 3.3(±0.5%,±1%) 5(±0.5%,±1%) LP2950-N 3(±1%) TO-252(NDP) 3.3(±1%) 5(±1%) 3(±0.5%,±1%) SOIC(D) 3.3(±0.5%,±1%) 5(±0.5%,±1%) 3(±0.5%,±1%) VSSOP(DGK) 3.3(±0.5%,±1%) LP2951-N 5(±0.5%,±1%) 3(±0.5%,±1%) WSON(NGT) 3.3(±0.5%,±1%) 5(±0.5%,±1%) PDIP(P) 5(±0.5%,±1%) Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 6 Pin Configuration and Functions LPPackage 3-PinTO-92 NDPPackage BottomView 3-PinTO-252 FrontView P,D,DGKPackages 8-PinPDIP,SOIC,VSSOP TopView NGTPackage 8-PinWSON TopView OUT 1 8 IN SENSE 2 7 FEEDBACK DAP SHUTDOWN 3 6 VTAP GND 4 5 ERROR ConnectDAPtoGNDatdevicepin4. PinFunctions:LP2950-N PIN LP2950 I/O DESCRIPTION NAME LP NDP GND 2 2 — Ground IN 3 1 I Inputsupplyvoltage OUT 1 3 O Regulatedoutputvoltage PinFunctions:LP2951-N PIN LP2951 I/O DESCRIPTION NAME D,DGK,P NGT ERROR 5 5 O Erroroutput FEEDBACK 7 7 I Voltagefeedbackinput GROUND 4 4 — Ground IN 8 8 I Inputsupplyvoltage OUT 1 1 O Regulatedoutputvoltage SENSE 2 2 I Outputvoltagesense SHUTDOWN 3 3 I Disabledevice VTAP 6 6 O Internalresistordivider 4 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT Inputsupplyvoltage-SHUTDOWNinputvoltageerrorcomparatoroutputvoltage(3) –0.3 30 V FEEDBACKinputvoltage(3)(4) –1.5 30 V Powerdissipation InternallyLimited Junctiontemperature,T 150 J Wave 4seconds,260 °C Solderingdwelltime,temperature Infrared 10seconds,240 Vaporphase 75seconds,219 Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) Mayexceedinputsupplyvoltage. (4) Whenusedindual-supplysystemswheretheoutputterminalseesloadsreturnedtoanegativesupply,theoutputvoltageshouldbe diode-clampedtoground. 7.2 ESD Ratings VALUE UNIT LP2950-N V Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V (ESD) discharge LP2951-N IN,OUT,GND,ERROR ±2500 Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS- SHUTDOWN ±2000 V(ESD) discharge 001(1) SENSE ±1500 V VTAP,FEEDBACK ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Maximuminputsupplyvoltage 30 V LP2950AC-XX,LP2950C-XX –40 125 °C Junctiontemperature,T (2) LP2951 –55 150 °C J LP2951AC-XX,LP2951C-XX –40 125 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thejunction-to-ambientthermalresistancesareasfollows:157.4°C/WfortheTO-92(LP)package,51.3°C/WfortheTO-252(NDP) package,56.3°C/WforthemoldedPDIP(P),117.7°C/WforthemoldedplasticSOIC(D),171°C/WforthemoldedplasticVSSOP (DGK).TheabovethermalresistancesfortheP,D,andDGKpackagesapplywhenthepackageissoldereddirectlytothePCB.The valueofR fortheWSON(NGT)packageistypically43.3°C/WbutisdependentonthePCBtracearea,tracematerial,andthe θJA numberoflayersandthermalvias.FordetailsofthermalresistanceandpowerdissipationfortheWSONpackage,seeAN-1187 LeadlessLeadframePackage(LLP). Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 7.4 Thermal Information: LP2950-N LP2950-N THERMALMETRIC(1) LP(TO-92) NDP(TO-252) UNIT 3PINS 3PINS R (2) Junction-to-ambientthermalresistance,High-K 157.4 51.3(3) °C/W θJA R Junction-to-case(top)thermalresistance 81.2 53.5 °C/W θJC(top) R Junction-to-boardthermalresistance 153.6 30.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 25.2 5.5 °C/W JT ψ Junction-to-boardcharacterizationparameter n/a 30 °C/W JB R Junction-to-case(bottom)thermalresistance n/a 2.2 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ThermalresistancevalueR isbasedontheEIA/JEDECHigh-KprintedcircuitboarddefinedbyJESD51-7-HighEffectiveThermal θJA ConductivityTestBoardforLeadedSurfaceMountPackages. (3) ThePCBfortheTO-252(NDP)packageR includestwelve(12)thermalviasunderthetabperEIA/JEDECJESD51-5. θJA 7.5 Thermal Information: LP2951-N LP2951-N THERMALMETRIC(1) P(PDIP) D(SOIC) DGK NGT UNIT (VSSOP) (WSON) 8PINS 8PINS 8PINS 8PINS R (2) Junction-to-ambientthermalresistance,HighK 56.3 117.7 171.0 43.3(3) °C/W θJA R Junction-to-case(top)thermalresistance 45.7 63.7 62.3 35.0 °C/W θJC(top) R Junction-to-boardthermalresistance 33.5 57.9 91.4 23.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 22.9 15.9 8.9 0.5 °C/W JT ψ Junction-to-boardcharacterizationparameter 33.3 57.5 90.1 20.5 °C/W JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a 9.1 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ThermalresistancevalueR isbasedontheEIA/JEDECHigh-KprintedcircuitboarddefinedbyJESD51-7-HighEffectiveThermal θJA ConductivityTestBoardforLeadedSurfaceMountPackages. (3) ThePCBfortheWSON(NGT)packageR includessix(6)thermalviasundertheexposedthermalpadperEIA/JEDECJESD51-5. θJA 6 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 7.6 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) LP2951(2) LP2950AC-XX LP2950C-XX PARAMETER TESTCONDITIONS(1) LP2951AC-XX LP2951C-XX UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 3-VVERSIONS(3) T =25°C 2.985 3 3.015 2.985 3 3.015 2.970 3 3.030 V(4) J −25°C≤T ≤85°C 2.970 3 3.030 2.955 3 3.045 V(5) J Outputvoltage Fulloperating 2.964 3 3.036 V(4) temperaturerange 2.964 3 3.036 2.940 3 3.060 V(5) 100µA≤I ≤100mA, 2.955 3 3.045 V(4) L Outputvoltage 100µA≤I ≤100mA, T ≤T L 2.958 3 3.042 2.928 3 3.072 V(5) J JMAX 3.3-VVERSIONS(3) T =25°C 3.284 3.3 3.317 3.284 3.3 3.317 3.267 3.3 3.333 V(4) J −25°C≤T ≤85°C 3.3 3.267 3.3 3.333 3.251 3.3 3.350 V(5) J Outputvoltage Fulloperating 3.260 3.3 3.340 V(4) temperaturerange 3.260 3.3 3.340 3.234 3.3 3.366 V(5) 100µA≤I ≤100mA,T 3.251 3.3 3.350 V(4) Outputvoltage L J ≤TJMAX 3.254 3.3 3.346 3.221 3.3 3.379 V(5) 5-VVERSIONS(3) T =25°C 4.975 5 5.025 4.975 5 5.025 4.95 5 5.05 V(4) J −25°C≤T ≤85°C 5 4.95 5 5.05 4.925 5 5.075 V(5) J Outputvoltage Fulloperating 4.94 5 5.06 V(4) temperaturerange 4.94 5 5.06 4.9 5 5.1 V(5) 100µA≤I ≤100mA,T 4.925 5 5.075 V(4) Outputvoltage L J ≤TJMAX 4.925 5 5.075 4.88 5 5.12 V(5) ALLVOLTAGEOPTIONS Outputvoltage See(6),–40°C≤T ≤ 20 120 ppm/°C(4) temperature J coefficient 125°C 20 100 50 150 ppm/°C(5) (VV(O8)NOM+1V)≤Vin≤30 0.03% 0.1% 0.03% 0.11% 0.04% 0.2% See(4) Lineregulation(7) (V NOM+1V)≤V ≤30 0.03% 0.5% See(4) O in V(8),–40°C≤TJ≤125°C 0.03% 0.2% 0.04% 0.4% (5) 100µA≤I ≤100mA 0.04% 0.1% 0.04% 0.1% 0.1% 0.2% See(4) L Loadregulation(7) 100µA≤I ≤100mA, 0.04% 0.3% See(4) L –40°C≤TJ≤125°C 0.04% 0.2% 0.1% 0.3% See(5) (1) Unlessotherwisenoted,alllimitsapplyforT =T =25°CaswellasspecifiedforV =(V NOM+1V),I =100µAandC =1µFfor A J IN O L L 5-Vversionsand2.2µFfor3-Vand3.3-Vversions.Additionalconditionsforthe8-pinversionsareFEEDBACKtiedtoVTAP,OUTPUT tiedtoSENSE,andV ≤0.8V. SHUTDOWN (2) AMilitaryRETSspecificationisavailableonrequest. (3) AllLP2950deviceshavethenominaloutputvoltagecodedasthelasttwodigitsofthepartnumber.IntheLP2951products,the3-V and3.3-Vversionsaredesignatedbythelasttwodigits,butthe5-Vversionisdenotedwithnocodeatthislocationofthepartnumber (refertothePackageOptionAddendumatendofdatasheet). (4) Ensuredand100%productiontested. (5) Ensuredbutnot100%productiontested.TheselimitsarenotusedtocalculateoutgoingAQLlevels. (6) Outputorreferencevoltagetemperaturecoefficientisdefinedastheworstcasevoltagechangedividedbythetotaltemperaturerange. (7) Regulationismeasuredatconstantjunctiontemperature,usingpulsetestingwithalowdutycycle.Changesinoutputvoltagedueto heatingeffectsarecoveredunderthespecificationforthermalregulation. (8) LineregulationfortheLP2951-Nistestedat150°CforI =1mA.ForI =100µAandT =125°C,lineregulationisspecifiedbydesign L L J to0.2%.SeeTypicalCharacteristicsforlineregulationversustemperatureandloadcurrent. Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) LP2951(2) LP2950AC-XX LP2950C-XX PARAMETER TESTCONDITIONS(1) LP2951AC-XX LP2951C-XX UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX I =100µA 50 80 50 80 50 80 mV(4) L I =100µA,–40°C≤T ≤ 150 mV(4) L J 125°C 150 150 mV(5) Dropoutvoltage(9) I =100mA 380 450 380 450 380 450 mV(4) L I =100mA,–40°C≤T ≤ 600 600 600 mV(4) L J 125°C 600 600 mV(5) I =100µA 75 120 75 120 75 120 µA(4) L I =100µA,–40°C≤T ≤ 140 µA(4) L J 125°C 140 140 µA(5) Groundcurrent I =100mA 8 12 8 12 8 12 mA(4) L I =100mA,–40°C≤T ≤ 14 mA(4) L J 125°C 14 14 mA(5) VIN=(VONOM−0.5)V,IL 110 170 110 170 110 170 µA(4) =100µA Dropoutground current VIN=(VONOM−0.5V),IL 200 200 200 µA(4) =100µA,–40°C≤T ≤ 125°C J 200 200 µA(5) V =0V 160 200 160 200 160 200 mA(4) OUT Currentlimit V =0V,–40°C≤T ≤ 220 mA(4) OUT J 125°C 220 220 mA(5) Thermalregulation See(10) 0.05 0.2 0.05 0.2 0.05 0.2 %/W(4) C =1µF(5VOnly) 430 430 430 µV L RMS C =200µF 160 160 160 µV Outputnoise L RMS 10Hzto100kHz CL=3.3µF (Bypass=0.01µF 100 100 100 µV RMS Pins7to1(LP2951-N) 8-PINVERSIONSONLY LP2951 LP2951AC-XX LP2951C-XX 1.22 1.235 1.25 1.22 1.235 1.25 1.21 1.235 1.26 V(4) Referencevoltage 1.2 1.26 V(4) –40°C≤T ≤125°C J 1.2 1.261 1.2 1.27 V(5) See(11),–40°C≤T ≤ 1.19 1.27 V(4) Referencevoltage J 125°C 1.19 1.27 1.185 1.285 V(5) 20 40 20 40 20 40 nA(4) Feedbackpinbias 60 nA (4) current –40°C≤T ≤125°C J 60 60 nA(5) Referencevoltage temperature See(6) 20 20 50 ppm/°C coefficient Feedbackpinbias current 0.1 0.1 0.1 nA/°C temperature coefficient (9) Dropoutvoltageisdefinedastheinputtooutputdifferentialatwhichtheoutputvoltagedrops100mVbelowitsnominalvaluemeasured at1-Vdifferential.Atverylowvaluesofprogrammedoutputvoltage,theminimuminputsupplyvoltageof2V(2.3Vovertemperature) mustbetakenintoaccount. (10) ThermalregulationisdefinedasthechangeinoutputvoltageatatimeTafterachangeinpowerdissipationisapplied,excludingload orlineregulationeffects.Specificationsarefora50mAloadpulseatV =30V(1.25-Wpulse)forT=10ms. IN (11) V ≤V ≤(V −1V),2.3V≤V ≤30V,100µA≤I ≤100mA,T ≤T . REF OUT IN IN L J JMAX 8 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Electrical Characteristics (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) LP2951(2) LP2950AC-XX LP2950C-XX PARAMETER TESTCONDITIONS(1) LP2951AC-XX LP2951C-XX UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX ERRORCOMPARATOR V =30V 0.01 1 0.01 1 0.01 1 µA(4) OH Ocuurtrpeunttleakage VOH=30V,–40°C≤TJ≤ 2 µA(4) 125°C 2 2 µA(5) VIN=(VONOM−0.5V), 150 250 150 250 150 250 mV(4) I =400µA OL Outputlowvoltage V =(V NOM−0.5V), 400 400 400 mV(4) IN O I =400µA, –O4L0°C≤T ≤125°C 400 400 mV(5) J See(12) 40 60 40 60 40 60 mV(4) Uvoplptaegrethreshold See(12),–40°C≤TJ≤ 25 mV(4) 125°C 25 25 mV(5) See(12) 75 95 75 95 75 95 mV(4) Lvoolwtaegrethreshold See(12),–40°C≤TJ≤ 140 mV(4) 125°C 140 140 mV(5) Hysteresis See(12) 15 15 15 mV SHUTDOWNINPUT Input 1.3 1.3 1.3 V Low(RegulatorON), 0.6 V(4) Logicvoltage –40°C≤TJ≤125°C 0.7 0.7 V(5) High(RegulatorOFF), 2 V(4) Logicvoltage –40°C≤TJ≤125°C 2 2 V(5) V =2.4V 30 50 30 50 30 50 µA(4) shutdown V =2.4V 100 µA(4) shutdown Shutdownpininput –40°C≤TJ≤125°C 100 100 µA(5) current V =30V 450 600 450 600 450 600 µA(4) shutdown V =30V, 750 µA(4) shutdown –40°C≤TJ≤125°C 750 750 µA(5) See(13) 3 10 3 10 3 10 µA(4) Regulatoroutput currentin 20 µA(4) shutdown –40°C≤TJ≤125°C 20 20 µA(5) (12) ComparatorthresholdsareexpressedintermsofavoltagedifferentialattheFEEDBACKpinbelowthenominalreferencevoltage measuredatV =(V +1)V.Toexpressthesethresholdsintermsofoutputvoltagechange,multiplybytheerroramplifiergain= IN O(NOM) V /V =(R1+R2)/R2.Forexample,ataprogrammedoutputvoltageof5V,theERRORoutputisspecifiedtogolowwhenthe OUT REF outputdropsby95mV×5V/1.235V=384mV.ThresholdsremainconstantasapercentofV asV isvaried,withthedropout OUT OUT warningoccurringattypically5%belownominal,7.5%ensured. (13) V ≥2V,V ≤30V,V =0,FEEDBACKpintiedtoV . SHUTDOWN IN OUT TAP Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 7.7 Typical Characteristics Figure1.QuiescentCurrent Figure2.DropoutCharacteristics Figure3.InputCurrent Figure4.InputCurrent Figure5.OutputVoltagevs.Temperatureof3 Figure6.QuiescentCurrent RepresentativeUnits 10 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Typical Characteristics (continued) Figure7.QuiescentCurrent Figure8.QuiescentCurrent Figure9.QuiescentCurrent Figure10.ShortCircuitCurrent Figure11.DropoutVoltage Figure12.DropoutVoltage Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com Typical Characteristics (continued) Figure13.LP2951-NMinimumOperatingVoltage Figure14.LP2951-NFeedbackBiasCurrent Figure15.LP2951-NFeedbackPinCurrent Figure16.LP2951-NErrorComparatorOutput Figure17.LP2951-NComparatorSinkCurrent Figure18.LP2951-NEnableTransient 12 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Typical Characteristics (continued) Figure19.OutputImpedance Figure20.RippleRejection Figure21.RippleRejection Figure22.RippleRejection Figure23.LP2951-NOutputNoise Figure24.LP2951-NDividerResistance Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com Typical Characteristics (continued) Figure25.ShutdownThresholdVoltage Figure26.LineRegulation Figure27.LP2951-NMaximumRatedOutputCurrent Figure28.LP2950-NMaximumRatedOutputCurrent Figure29.ThermalResponse Figure30.OutputCapacitorESRRange 14 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Typical Characteristics (continued) 120 120 VSD= 2.0V VSD= 2.0V A) 100 Output Load = Open A) 100 Output Load = Short to Ground (cid:29) (cid:29) (N (N T, II 80 T, II 80 N N E E R R R 60 R 60 U U C C N 40 N 40 PI PI UT Ta= -50°C UT Ta= -50°C P 20 Ta= -40°C P 20 Ta= -40°C N Ta= +25°C N Ta= +25°C I Ta= +125°C I Ta= +125°C 0 0 0 5 10 15 20 25 30 0 5 10 15 20 25 30 INPUT PIN VOLTAGE, VIN(V) INPUT PIN VOLTAGE, VIN(V) Figure31.LP2951-NInputPinCurrentvsInputVoltage Figure32.LP2951-NInputPinCurrentvsInputVoltage Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 8 Detailed Description 8.1 Overview The LP2950-N and LP2951-N are very high accuracy micro power voltage regulators with low quiescent current (75 µA typical) and low dropout voltage (typical 40 mV at light loads and 380 mV at 100 mA). They are ideally suitedforuseinbattery-poweredsystems. TheLP2950-NandLP2951-Nblockdiagramcontainsseveralfeatures,including: • Veryhighaccuracy1.23-Vreference; • Fixed5-V,3-V,and3.3-Vversions;and • Internalprotectioncircuitry,suchasfoldbackcurrentlimit,andthermalshutdown. TheLP2951-NVERSIONSONLY: • Fixed 5-V, 3-V, and 3.3-V versions and programmable output version from 1.24 V to 29 V with an external pairofresistors; • Shutdowninput,allowingturnofftheregulatorwhentheSHUTDOWNpinispulledlow;and • Errorflagoutput,whichmaybeusedforapower-onreset. 8.2 Functional Block Diagrams Figure33. LP2950-NFunctionalBlockDiagram Figure34. LP2951-NFunctionalBlockDiagram 16 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 8.3 Feature Description 8.3.1 FixedVoltageOptionsandProgrammableVoltageVersion The LP2950-N and LP2951-N provide 3 fixed output options: 3 V, 3.3 V, and 5 V. Please consult factory for custom voltages. In order to meet different application requirements, LP2951-N can also be used as a programmable voltage regulator, with an external resistors network; please refer to Application and Implementationformoredetails. 8.3.2 HighAccuracyOutputVoltage With special carful design to minimize all contributions to the output voltage error, the LP2950-N/LP2951-N distinguisheditselfasaveryhighoutputvoltageaccuracymicropowerLDO.Thisincludesatightinitialtolerance (0.5% typical), extremely good load and line regulation (.05% typical) and a very low output voltage temperature coefficient,makingthepartanidealalow-powervoltagereference. 8.3.3 LowDropoutVoltage Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (V = V – V ), where the main current pass-FET is fully on in the ohmic region of operation and is DO IN OUT characterized by the classic R of the FET. V indirectly specifies a minimum input voltage above the DS(ON) DO nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. 8.3.4 ShutdownMode When the SHUTDOWN pin is pulled to high level, LP2951-N enters shutdown mode and a very low quiescent current is consumed. This function is designed for the application which needs a shutdown mode to effectively enhancebatterylifecycle. 8.3.5 ErrorDetectionComparatorOutput The LP2951-N generates a logic low output whenever its output falls out of regulation by more than approximately5%.PleaserefertoApplicationandImplementation formoredetails. 8.3.6 InternalProtectionCircuitry 8.3.6.1 Short-CircuitProtection(CurrentLimit) TheinternalcurrentlimitcircuitisusedtoprotecttheLDOagainsthigh-loadcurrentfaultsorshortingevents.The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output. A fold back feature limits the short-circuit current to protect the regulator from damage under all load conditions. If OUT is forced below 0 V before EN goes high and the load current requiredexceedsthefoldbackcurrentlimit,thedevicemaynotstartupcorrectly. 8.3.6.2 ThermalProtection The device contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. The thermal time-constant of the semiconductor die is fairly short, and thus the output cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced. The internal protection circuitry of the device is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown degrades itsreliability. 8.3.7 EnhancedStability The LP2950-N and LP2951-N is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the regulator to be stable across the entire range of output current with an output capacitor whose ESRisaslowas6mΩ.Foroutputcapacitorrequirement,pleaserefertoApplicationandImplementation. Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 8.4 Device Functional Modes 8.4.1 Operationwith30V ≥ V >V )+1V IN OUT(TARGET The device operate if the input voltage is equal to, or exceeds V + 1 V. At input voltages below the OUT(TARGET) minimumV requirement,thedevicesdonotoperatecorrectlyandoutputvoltagemaynotreachtargetvalue. IN 8.4.2 OperationwithShutdownControl If the voltage on the SHUTDOWN pin is higher than 1.3 V, the device is disabled. Decreasing shutdown below 0.7Vinitiatesthestart-upsequenceofthedevice. 18 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The LP2950-N and LP2951-N are linear voltage regulator operating from 2.3 V to 30 V on the input and regulates voltages between 1.24 V to 29 V with 0.5% accuracy and 160 mA maximum outputs current. Efficiency is defined by the ratio of output voltage to input voltage because the LP2950-N and LP2951-N is a linear voltage regulator. To achieve high efficiency, the dropout voltage (V – V ) must be as small as possible, thus IN OUT requiring a very low dropout LDO. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to ensure a solid design. If timing, start-up,noise,PSRR,oranyothertransientspecificationisrequired,thedesignbecomesmorechallenging. Figure35. SchematicDiagram Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 9.2 Typical Applications 9.2.1 1-ARegulatorwith1.2-VDropout Figure36. 1-ARegulatorwith1.2-VDropout 9.2.1.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable1astheinputparameters. Table1.DesignParameters DESIGNPARAMETER DESIGNREQUIREMENT Inputvoltage 6.5V,±10%,providedbytheDC-DCconverterswitchingat1MHz Outputvoltage 5V,±1% Outputcurrent 100mA(maximum),1mA(minimum) RMSnoise,10Hzto100kHz <200µV RMS PSRRat1KHz >50dB 9.2.1.2 DetailedDesignProcedure At 100-mA loading, the dropout of the LP2950-N/LP2951-N has 600 mV maximum dropout over temperature, thusan1500-mVheadroomissufficientforoperationoverbothinputandoutputvoltageaccuracy.Theefficiency of the LP2950-N/LP2951-N in this configuration is V / V = 76.9%. To achieve the smallest form factor, the OUT IN TO-92 package is selected. Input and output capacitors are selected in accordance with the Capacitor Recommendation section. Ceramic capacitances of 1 µF for the input and one 2.2-µF capacitors for the output are selected. With an efficiency of 73.3% and a 100-mA maximum load, the internal power dissipation is 150 mW, which corresponds to a 18.9°C junction temperature rise for the TO-92 package. With an 85°C maximum ambient temperature, the junction temperature is at 103.9°C. To minimize noise, a bypass capacitance (C ) BYPASS of0.01-µFisselectedbetweenpin7topin1forLP2951-N. 9.2.1.2.1 OutputCapacitorRequirements A 1-µF (or greater) capacitor is required between the output and ground for stability at output voltages of 5 V or higher. At lower output voltages, more capacitance is required (2.2 µF or more is recommended for 3-V and 3.3-V versions). Without this capacitor the device oscillates. Most types of tantalum or aluminum electrolytic work fine here; even film types work but are not recommended for reasons of cost. Many aluminum electrolytics have electrolytes that freeze at about −30°C, so solid tantalums are recommended for operation below −25°C. The importantparametersofthecapacitorareanESRofabout5 Ωorlessandaresonantfrequencyabove500kHz. Thevalueofthiscapacitormaybeincreasedwithoutlimit. 20 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Figure37. OutputCapacitorESRRange The reason for the lower ESR limit is that the loop compensation of the feedback loop relies on the capacitance value and the ESR value of the output capacitor to provide the zero that gives added phase lead (See Figure37). f =(1/(2×π×C ×ESR)) (1) Z OUT Using the 2.2 µF value from the Output Capacitor ESR Range curve (Figure 37), a useful range for f can be Z estimated: f =(1/(2xπ×2.2µFx5Ω))=14.5kHz (2) Z(MIN) f =(1/(2xπ×2.2µFx0.05Ω))=318kHz (3) Z(MAX) For ceramic capacitors, the low ESR produces a zero at a frequency that is too high to be useful, so meaningful phase lead does not occur. A ceramic output capacitor can be used if a series resistance is added (recommended value of resistance about 0.1 Ω to 2 Ω) to simulate the needed ESR. Only X5R, X7R, or better, MLCCtypesshouldbeused,andshouldhaveaDCvoltageratingatleasttwicetheV value. OUT(NOM) At lower values of output current, less output capacitance is required for stability. The capacitor can be reduced to0.33 µFforcurrentsbelow10mAor0.1 µFforcurrentsbelow1mA.Usingtheadjustableversionsatvoltages below 5 V runs the error amplifier at lower gains so that more output capacitance is needed. For the worst-case situation of a 100-mA load at 1.23 V output (output shorted to Feedback) a 3.3-µF (or greater) capacitor should beused. Unlike many other regulators, the LP2950-N remains stable and in regulation with no load in addition to the internal voltage divider. This is especially important in CMOS RAM keep-alive applications. When setting the outputvoltageoftheLP2951-Nversionswithexternalresistors,aminimumloadof1 µAisrecommended. Applications having conditions that may drive the LP2950-N/51 into nonlinear operation require special consideration. Nonlinear operation occurs when the output voltage is held low enough to force the output stage into output current limiting while trying to pull the output voltage up to the regulated value. The internal loop responsetimecontrolshowlongittakesforthedevicetoregainlinearoperationwhentheoutputhasreturnedto the normal operating range. There are three significant nonlinear conditions that need to be considered, all can force the output stage into output current limiting mode, all can cause the output voltage to over-shoot with low value output capacitors when the condition is removed, and the recommended generic solution is to set the output capacitor to a value not less than 10 µF. Although the 10 µF value for C may not eliminate the output OUT voltage over-shoot in all cases, it should lower it to acceptable levels (< 10% of V ) in the majority of OUT(NOM) cases. In all three of these conditions, applications with lighter load currents are more susceptible to output voltageover-shootthanapplicationswithhigherloadcurrents. 1. Atpower-up,withtheinputvoltagerisingfasterthanoutputstagecanchargetheoutputcapacitor. V t >((C /100mA)×ΔV ) IN RISE(MIN) OUT IN where • ΔV =V +1V (4) IN OUT(NOM) 2. Recoveryfromanoutputshortcircuittogroundcondition. C ≈(160mA–I )/((V /10)/25µs)) (5) OUT(MIN) LOAD(NOM) OUT(NOM) 3. TogglingtheLP2951-NSHUTDOWNpinfromhigh(OFF)tolow(ON). C ≈(160mA–I )/((V /10)/25µs)) (6) OUT(MIN) LOAD(NOM) OUT(NOM) Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com Figure38. LP2951-NEnableTransient 9.2.1.2.2 InputCapacitorRequirements A minimum 1 µF tantalum, ceramic or aluminum electrolytic capacitor should be placed from the LP2950- N/LP2951-N input pin to ground if there is more than 10 inches of wire between the input and the AC filter capacitororifabatteryisusedastheinput. 9.2.1.2.3 ErrorDetectionComparatorOutput The comparator produces a logic low output whenever the LP2951-N output falls out of regulation by more than approximately 5%. This figure is the comparator's built-in offset of about 60 mV divided by the 1.235 reference voltage. (Refer to the block diagram in the front of the datasheet.) This trip level remains “5% below normal” regardless of the programmed output voltage of the 2951. For example, the error flag trip level is typically 4.75 V for a 5-V output or 11.4 V for a 12-V output. The out of regulation condition may be due either to low input voltage,currentlimiting,orthermallimiting. Figure 39 below gives a timing diagram depicting the ERROR signal and the regulated output voltage as the LP2951-Ninputisrampedupanddown.For5Vversions,the ERROR signalbecomesvalid(low)atabout1.3-V input. It goes high at about 5-V input (the input voltage at which V = 4.75 V). Because the LP2951-N dropout OUT voltage is load-dependent (see curve in typical performance characteristics), the input voltage trip point (about 5V)varieswiththeloadcurrent.Theoutputvoltagetrippoint(approx.4.75V)doesnotvarywithload. The error comparator has an open-collector output which requires an external pull up resistor. This resistor may be returned to the output or some other supply voltage depending on system requirements. In determining a value for this resistor, note that while the output is rated to sink 400 µA, this sink current adds to battery drain in a low battery condition. Suggested values range from 100 k to 1 MΩ. The resistor is not required if this output is unused. *WhenV ≤1.3V,theerrorflagpinbecomesahighimpedance,andtheerrorflagvoltagerisestoitspullupvoltage. IN UsingV asthepullupvoltage(seeFigure40),ratherthananexternal5-Vsource,keepstheerrorflagvoltage OUT under1.2V(typical)inthiscondition.Theusermaywishtodividedowntheerrorflagvoltageusingequal-value resistors(10kΩsuggested),toensurealow-levellogicsignalduringanyfaultcondition,whilestillallowingavalid highlogiclevelduringnormaloperation. Figure39. ERROR OutputTiming 22 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 9.2.1.2.4 ProgrammingtheOutputVoltage(LP2951-N) The LP2951-N may be pin-strapped for the nominal fixed output voltage using its internal voltage divider by tying the output and sense pins together, and also tying the FEEDBACK and VTAP pins together. Alternatively, it may be programmed for any output voltage between its 1.235-V reference and its 30-V maximum rating. As seen in Figure40,anexternalpairofresistorsisrequired. Thecompleteequationfortheoutputvoltageis where • V isthenominal1.235-VreferencevoltageandI istheFEEDBACKpinbiascurrent,nominally–20nA (7) REF FB The minimum recommended load current of 1 µA forces an upper limit of 1.2 MΩ on the value of R , if the 2 regulatormustworkwithnoload(aconditionoftenfoundinCMOSinstandby).I producesa2%typicalerrorin FB V which may be eliminated at room temperature by trimming R . For better accuracy, choosing R = 100 kΩ OUT 1 2 reduces this error to 0.17% while increasing the resistor program current to 12 µA. Because the LP2951-N typicallydraws60µAatnoloadwithpin2open-circuited,thisisasmallpricetopay. *DrivewithTTL-hightoshutdown.Groundorleaveopenifshutdownfeatureisnottobeused. Note:Pins2and6areleftopen. Figure40. AdjustableRegulator Stray capacitance to the LP2951-N FEEDBACK pin can cause instability. This may especially be a problem when using high value external resistors to set the output voltage. Adding a 100-pF capacitor between the OUT pinandtheFEEDBACKpin,andincreasingtheoutputcapacitortoatleast3.3 µF,fixesthisproblem. 9.2.1.2.5 ReducingOutputNoise InreferenceapplicationsitmaybeadvantageoustoreducetheACnoisepresentattheoutput.Onemethodisto reduce the regulator bandwidth by increasing the size of the output capacitor. This is the only way noise can be reduced on the 3-lead LP2950-N but is relatively inefficient, as increasing the capacitor from 1 µF to 220 µF only decreasesthenoisefrom430µV to160µV fora100-kHzbandwidthat5-Voutput. RMS RMS NoisecanbereducedfourfoldbyabypasscapacitoracrossR1,becauseitreducesthehighfrequencygainfrom 4tounity.Pick (8) or about 0.01 µF. When doing this, the output capacitor must be increased to 3.3 µF to maintain stability. These changes reduce the output noise from 430 µV to 100 µV rms for a 100-kHz bandwidth at 5-V output. With the bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at higheroutputvoltages. Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 9.2.1.3 ApplicationCurves Figure41.LineTransientResponse Figure42.LoadTransientResponse Figure43.LoadTransientResponse 24 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 9.2.2 300-mARegulatorwith0.75-VDropout In Figure 44, by paralleling the LP2951 together with 2x2N5432 (150-mA N channel JFET), a user can get a higheroutputcurrentcapabilityaround300mA. Figure44. 300-mARegulatorwith0.75-VDropout 9.2.3 WideInputVoltageRangeCurrentLimiter The LP2951 can be used as a 160-mA current limiter as Figure 45. When FB is connected to ground, the pass element is fully turned on and out voltage will be close to input voltage. Input-output voltage ranges from 40 mV to400mV,dependingonloadcurrent. *Minimuminput-outputvoltagerangesfrom40mVto400mV,dependingonloadcurrent.Currentlimitistypically 160mA. Figure45. WideInputVoltageRangeCurrentLimiter Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 9.2.4 LowDriftCurrentSource The LP2951 can be used as a low drift current source as Figure 46 shows. By connected V to FB, V will out out regulatedat1.235V,andcurrentconsumptionatRisI =1.23/R. L Figure46. LowDriftCurrentSource 9.2.5 5-VCurrentLimiter The LP2950 internal current limit function can be leveraged to build 5-V current limiter as Figure 47 shows. The minimum input-output voltage ranges from 40 mV to 400 mV, depending on load current. Current limit is typically 160mA. *Minimuminput-outputvoltagerangesfrom40mVto400mV,dependingonloadcurrent.Currentlimitistypically 160mA. Figure47. 5-VCurrentLimiter 26 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 9.2.6 RegulatorwithEarlyWarningandAuxiliaryOutput The LP2951 can be used to build a Regulator with early warning and auxiliary output as Figure 48 shows. it has belowfeatures: • Earlywarningflagonlowinputvoltage • Mainoutputlatchesoffatlowerinputvoltages • Batterybackuponauxiliaryoutput • Operation: V of regulator 1 is programmed one diode drop above 5 V. Its error flag becomes active when OUT V ≤ 5.7 V. When V drops below 5.3 V, the error flag of regulator 2 becomes active and via Q1 latches the IN IN main output off. When V again exceeds 5.7 V regulator 1 is back in regulation and the early warning signal IN rises,unlatchingregulator2viaD3. Figure48. RegulatorWithEarlyWarningandAuxiliaryOutput 9.2.7 LatchOffWhenErrorFlagOccurs AsFigure49presents,alatchoffwhenerrorflagoccurscircuitworksinbelowtwomode: When output is within ±95% of V option, the error flag pin keep output high, which turns off PNP bipolar and OUT pullsSDpintolow,thentheLP2951keepsoutputregulatedvoltage. When output drop to less than 95% of V option, it triggers error flag output a low voltage, which turns on PNP OUT bipolar and pulls SD pin to high, then the device enters shutdown mode and turns off output voltage. During a shutdownsequence,theERROR pincontinuesoutputlow,andtheLP2951devicelatchesinshutdownmode. Figure49. LatchOffWhenErrorFlagOccurs Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 9.2.8 2-ALowDropoutRegulator AsFigure50shows,the2-Alowdropoutregulatorhasbelowfeatures: For5V ,useinternalresistors.Wirepin6topin7andwirepin2to+V bus. OUT OUT Figure50. 2-ALowDropoutRegulator 9.2.9 5-VRegulatorwith2.5-VSleepFunction InFigure51,the5-Vregulatorwith2.5-Vsleepfunctionworksinbelowmode: Whensleepinputislow,C-MOSoutputahighvoltageand2N3906isoff,thenV =(1+300KΩ/100KΩ)×V out FB ≈5V when sleep input is high, C-MOS output a low voltage, turns on 2N3906, then 200-KΩ resistor is bypassed from circuit,andV =(1+100KΩ/100KΩ)×V ≈ 2.5V. OUT FB 28 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 *HighinputlowersV to2.5V. out Figure51. 5-VRegulatorwith2.5-VSleepFunction 9.2.10 OpenCircuitDetectorfor4 →20-mACurrentLoop Figure 52 shows the open circuit detector for 4 → 20-mA current loop. The circuit outputs a high level while input currentislessthan3.5mA. Figure52. OpenCircuitDetectorfor4→20-mACurrentLoop 9.2.11 RegulatorwithState-of-ChargeIndicator In Figure 53, the LP339, a quad comparator, is used to indicate battery voltage state. The comparator’s negative input voltage is equal to the LP2951 1.235-V feedback voltage. By adjusting R3, we can adjust positive input voltageofC1~C3totargetvalue. Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com *Optionallatchoffwhendropoutoccurs.AdjustR3forC2SwitchingwhenV is6V. in **OutputsgolowwhenV dropsbelowdesignatedthresholds. IN Figure53. RegulatorwithState-of-ChargeIndicator 30 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 9.2.12 LowBatteryDisconnect In Figure 54, a band-gap voltage reference LM385 is used to generate shutdown signal, when V < 5.5 V, the in LP2951turnsoffandturnsonagainwhenV >6V. IN Forvaluesshown,regulatorshutsdownwhenV <5.5Vandturnsonagainat6V.Currentdrainindisconnected in modeisapproximately150µA. *Setsdisconnectvoltage. **Setsdisconnecthysteresis. Figure54. LowBatteryDisconnect 9.2.13 SystemOvertemperatureProtectionCircuit In Figure 55, temperature sensors LM34/35's output voltage is linearly proportional to the Celsius (Centigrade) temperature. At room temperature, LM34/35's output voltage is lower than 1.235-V feedback voltage, the internal pass transistorfullyturnson,andtheLP2951outputvoltageisclosetoV . IN When ambient temperature raise higher than protection target, LM34/35's output voltage is higher than 1.235-V feedbackvoltage,theinternalpasstransistorturnsoff,andtheLP2951outputgoesoff. LM34for125°Fshutdown LM35for125°Cshutdown Figure55. SystemOvertemperatureProtectionCircuit Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 10 Power Supply Recommendations The LP2950-N and LP2951-N are designed to operate from an input voltage supply range between 2.3 V and 30 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. Thisinputsupplymustbewellregulated.Iftheinputsupplyisnoisy,additionalinputcapacitorswithlowESRcan helpimprovetheoutputnoiseperformance. 11 Layout 11.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and therebyreducesload-currenttransients,minimizesnoise,andincreasescircuitstability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In mostapplications,thisgroundplaneisnecessarytomeetthermalrequirements. 11.2 Layout Example Output Input Capacitor Capacitor Ground OUT IN VIN VOUT SENSE FEEDBACK Ground 1 2 3 SHUTDOWN VTAP D IN GN OUT ErRroers Pisutollrup GND ERROR VOUT Input Output Capacitor Capacitor VIN VOUT Figure56.LP2950BoardLayout Figure57.LP2951VSSOPBoardLayout 32 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N www.ti.com SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 Layout Example (continued) Ground Output Input Capacitor Capacitor OUT 1 Exposed 8 IN VIN Thermal Pad VOUT SENSE 2 7 FEEDBACK SHUTDOWN 3 6 VTAP Error Pullup Resistor GND 4 6 Thermal Vias 5 ERROR VOUT Ground Figure58.LP2951WSONBoardLayout 11.3 WSON Mounting The NGT (no pullback) 8-lead WSON package requires specific mounting techniques which are detailed in AN- 1187 Leadless Leadframe Package (LLP). Referring to the PCB Design Recommendations section, note that the pad style which should be used with the WSON package is the NSMD (non-solder mask defined) type. Additionally, TI recommends that the PCB terminal pads to be 0.2 mm longer than the package pads to create a solderfillettoimprovereliabilityandinspection. The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amountofadditionalcopperareaconnectedtotheDAP. FortheLP2951-NintheNGT8-leadWSONpackage,thejunction-to-casethermalrating,R ,is35°C/W,where θJC thecaseisthebottomofthepackageatthecenteroftheDAP. TheDAP(exposedpad)onthebottomoftheWSONpackageisconnectedtothediesubstratewithaconductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the eight pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 4 (that is, GND). Alternately, but not recommended, the DAP may be left floating (that is, no electrical connection). The DAP must not be connected to any potential otherthanground. Copyright©2000–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LP2950-N LP2951-N

LP2950-N,LP2951-N SNVS764Q–JANUARY2000–REVISEDDECEMBER2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: AN-1187LeadlessLeadframePackage(LLP) 12.2 Related Links Table 2 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY LP2950-N Clickhere Clickhere Clickhere Clickhere Clickhere LP2951-N Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 34 SubmitDocumentationFeedback Copyright©2000–2017,TexasInstrumentsIncorporated ProductFolderLinks:LP2950-N LP2951-N

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2950ACZ-3.0/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950A & no Sb/Br) CZ3.0 LP2950ACZ-3.3/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950A & no Sb/Br) CZ3.3 LP2950ACZ-5.0/LFT1 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950A & no Sb/Br) CZ5.0 LP2950ACZ-5.0/LFT3 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950A & no Sb/Br) CZ5.0 LP2950ACZ-5.0/LFT7 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950A & no Sb/Br) CZ5.0 LP2950ACZ-5.0/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950A & no Sb/Br) CZ5.0 LP2950CDT-3.0/NOPB ACTIVE TO-252 NDP 3 75 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-3.0 LP2950CDT-3.3 NRND TO-252 NDP 3 75 TBD Call TI Call TI -40 to 125 LP2950 CDT-3.3 LP2950CDT-3.3/NOPB ACTIVE TO-252 NDP 3 75 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-3.3 LP2950CDT-5.0/NOPB ACTIVE TO-252 NDP 3 75 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-5.0 LP2950CDTX-3.0/NOPB ACTIVE TO-252 NDP 3 2500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-3.0 LP2950CDTX-3.3/NOPB ACTIVE TO-252 NDP 3 2500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-3.3 LP2950CDTX-5.0/NOPB ACTIVE TO-252 NDP 3 2500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 LP2950 & no Sb/Br) CDT-5.0 LP2950CZ-3.0/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950 & no Sb/Br) CZ3.0 LP2950CZ-3.3/LFT3 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950 & no Sb/Br) CZ3.3 LP2950CZ-3.3/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950 & no Sb/Br) CZ3.3 LP2950CZ-5.0/LFT1 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950 & no Sb/Br) CZ5.0 Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2950CZ-5.0/LFT3 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950 & no Sb/Br) CZ5.0 LP2950CZ-5.0/LFT7 ACTIVE TO-92 LP 3 2000 Green (RoHS SN N / A for Pkg Type 2950 & no Sb/Br) CZ5.0 LP2950CZ-5.0/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS SN N / A for Pkg Type -40 to 125 2950 & no Sb/Br) CZ5.0 LP2951ACM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2951 ACMC LP2951ACM-3.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951A & no Sb/Br) CM30C LP2951ACM-3.3 NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2951A CM33C LP2951ACM-3.3/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951A & no Sb/Br) (CM33>D, CM33C) LP2951ACM/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951 & no Sb/Br) ACM>D LP2951ACMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L0DA LP2951ACMM-3.0 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L0BA LP2951ACMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0BA & no Sb/Br) LP2951ACMM-3.3 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L0CA LP2951ACMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0CA & no Sb/Br) LP2951ACMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0DA & no Sb/Br) LP2951ACMMX-3.0/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0BA & no Sb/Br) LP2951ACMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0CA & no Sb/Br) LP2951ACMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0DA & no Sb/Br) LP2951ACMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 2951 (ACM>D, ACMC) LP2951ACMX-3.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951A & no Sb/Br) CM30C Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2951ACMX-3.3/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951A & no Sb/Br) (CM33>D, CM33C) LP2951ACMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951 & no Sb/Br) (ACM>D, ACMC) LP2951ACN/NOPB ACTIVE PDIP P 8 40 Green (RoHS Call TI | SN Level-1-NA-UNLIM -40 to 125 LP & no Sb/Br) 2951ACN LP2951ACSD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2951AC & no Sb/Br) LP2951ACSDX-3.3/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 51AC33 & no Sb/Br) LP2951ACSDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 2951AC & no Sb/Br) LP2951CM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2951 CMC LP2951CM-3.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951C & no Sb/Br) M30C LP2951CM-3.3/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951C & no Sb/Br) M33>D LP2951CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951 & no Sb/Br) (CM>D, CMC) LP2951CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L0DB LP2951CMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0BB & no Sb/Br) LP2951CMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0CB & no Sb/Br) LP2951CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0DB & no Sb/Br) LP2951CMMX NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 125 L0DB LP2951CMMX-3.0/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0BB & no Sb/Br) LP2951CMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0CB & no Sb/Br) LP2951CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 L0DB & no Sb/Br) LP2951CMX-3.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951C & no Sb/Br) M30C Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2951CMX-3.3/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951C & no Sb/Br) (M33>D, M33C) LP2951CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 125 2951 & no Sb/Br) CM>D LP2951CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS Call TI | SN Level-1-NA-UNLIM -40 to 125 LP & no Sb/Br) 2951CN LP2951CSD-3.0/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 51AC30B & no Sb/Br) LP2951CSD-3.3/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 51AC33B & no Sb/Br) LP2951CSD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2951ACB & no Sb/Br) LP2951CSDX-3.3/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 51AC33B & no Sb/Br) LP2951CSDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2951ACB & no Sb/Br) LP2951D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LP2951 & no Sb/Br) LP2951DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LP2951 & no Sb/Br) LP2951DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LP2951 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LP2951-N : •Automotive: LP2951-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP2950CDTX-3.0/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP2950CDTX-3.3/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP2950CDTX-5.0/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP2951ACMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMM-3.0 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMM-3.3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMMX-3.0/NOP VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 B LP2951ACMMX-3.3/NOP VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 B LP2951ACMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951ACMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951ACMX-3.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951ACMX-3.3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951ACMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951ACSD/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2019 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP2951ACSDX-3.3/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2951ACSDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2951CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMMX-3.0/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMMX-3.3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2951CMX-3.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951CMX-3.3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2951CSD-3.0/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LP2951CSD-3.3/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2951CSD/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LP2951CSDX-3.3/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2951CSDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LP2951DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP2950CDTX-3.0/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP2950CDTX-3.3/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP2950CDTX-5.0/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP2951ACMM VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMM-3.0 VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMM-3.3 VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951ACMMX-3.0/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951ACMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951ACMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951ACMX SOIC D 8 2500 367.0 367.0 35.0 LP2951ACMX-3.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951ACMX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951ACMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951ACSD/NOPB WSON NGT 8 1000 203.0 203.0 35.0 LP2951ACSDX-3.3/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LP2951ACSDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LP2951CMM VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951CMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951CMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2951CMMX VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951CMMX-3.0/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951CMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2951CMX-3.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951CMX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2951CSD-3.0/NOPB WSON NGT 8 1000 203.0 203.0 35.0 LP2951CSD-3.3/NOPB WSON NGT 8 1000 210.0 185.0 35.0 LP2951CSD/NOPB WSON NGT 8 1000 203.0 203.0 35.0 LP2951CSDX-3.3/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LP2951CSDX/NOPB WSON NGT 8 4500 346.0 346.0 35.0 LP2951DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page3

MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.com

PACKAGE OUTLINE NDP0003B TO-252 - 2.55 mm max height SCALE 1.500 TRANSISTOR OUTLINE 10.42 9.40 6.22 1.27 B 5.97 0.88 A (2.345) 1 2.285 (2.5) 2 5.46 6.73 4.57 4.96 6.35 3 0.88 3X 0.64 1.02 PKG OPTIONAL 0.64 0.25 C A B 8 8 TOP & BOTTOM 1.14 0.89 C 2.55 MAX SEATING PLANE 0.88 0.17 0.60 0.46 0.46 0.51 MIN 4.32 MIN 3 2 4 1 4219870/A 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-252. www.ti.com

EXAMPLE BOARD LAYOUT NDP0003B TO-252 - 2.55 mm max height TRANSISTOR OUTLINE SEE SOLDER MASK DETAIL 2X (2.15) 2X (1.3) (5.7) 1 4 SYMM (4.57) (5.5) 3 (R0.05) TYP (4.38) (2.285) PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X 0.07 MAX METAL EDGE 0.07 MIN ALL AROUND ALL AROUND METAL UNDER EXPOSED SOLDER MASK METAL EXPOSED METAL SOLDER MASK SOLDER MASK OPENING OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAIL 4219870/A 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004). 5. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN NDP0003B TO-252 - 2.55 mm max height TRANSISTOR OUTLINE (1.35) TYP 2X (2.15) (0.26) 2X (1.3) (R0.05) TYP (1.32) TYP (4.57) 16X (1.12) 16X (1.15) (4.38) PKG SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 8X 4219870/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE LP0003A TO-92 - 5.34 mm max height SCALE 1.200 SCALE 1.200 TO-92 5.21 4.44 EJECTOR PIN OPTIONAL 5.34 4.32 (1.5) TYP (2.54) SEATING 2X NOTE 3 PLANE 4 MAX (0.51) TYP 6X 0.076 MAX SEATING PLANE 3X 12.7 MIN 0.43 2X 0.55 3X 3X 0.35 2.6 0.2 0.38 2X 1.27 0.13 FORMED LEAD OPTION OTHER DIMENSIONS IDENTICAL STRAIGHT LEAD OPTION TO STRAIGHT LEAD OPTION 2.67 3X 2.03 4.19 3.17 3 2 1 3.43 MIN 4215214/B 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Lead dimensions are not controlled within this area. 4. Reference JEDEC TO-226, variation AA. 5. Shipping method: a. Straight lead option available in bulk pack only. b. Formed lead option available in tape and reel or ammo pack. c. Specific products can be offered in limited combinations of shipping medium and lead options. d. Consult product folder for more information on available options. www.ti.com

EXAMPLE BOARD LAYOUT LP0003A TO-92 - 5.34 mm max height TO-92 FULL R TYP 0.05 MAX (1.07) ALL AROUND METAL 3X ( 0.85) HOLE TYP TYP 2X METAL (1.5) 2X (1.5) 2X SOLDER MASK OPENING 1 2 3 (R0.05) TYP 2X (1.07) (1.27) SOLDER MASK (2.54) OPENING LAND PATTERN EXAMPLE STRAIGHT LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X 0.05 MAX ( 1.4) 2X ( 1.4) ALL AROUND METAL TYP 3X ( 0.9) HOLE METAL 2X (R0.05) TYP 1 2 3 SOLDER MASK OPENING (2.6) SOLDER MASK OPENING (5.2) LAND PATTERN EXAMPLE FORMED LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X 4215214/B 04/2017 www.ti.com

TAPE SPECIFICATIONS LP0003A TO-92 - 5.34 mm max height TO-92 13.7 11.7 32 23 (2.5) TYP 0.5 MIN 16.5 15.5 11.0 9.75 8.5 8.50 19.0 17.5 2.9 6.75 3.7-4.3 TYP TYP 2.4 5.95 13.0 12.4 FOR FORMED LEAD OPTION PACKAGE 4215214/B 04/2017 www.ti.com

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