LNK454/456-458/460 LinkSwitch™-PL Family LED Driver IC with TRIAC Dimming, Single-Stage PFC and Constant Current Control for Non-Isolated Applications Product Highlights Dramatically Simplifies Off-line LED Drivers • Flicker-free phase-controlled TRIAC dimming • Single-stage power factor correction and accurate constant current (CC) output • Very low component count with small non-electrolytic bulk capacitor for compact replacement lamp designs AC • Compact SO8, eSOP, and eDIP packages IN D LinkSwitch-PL • Completely eliminates control loop compensation CONTROL BP Advanced Performance Features S FB • Optimized for non-isolated flyback designs • Frequency jitter greatly reduces EMI filter size and costs • Low dissipation direct sensing of LED current PI-5835-060710 Advanced Protection and Safety Features Figure 1. Basic Application Schematic. • Cycle skipping regulation for abnormally low output power to clamp peak output current delivered Output Power Table • 725 V integrated power MOSFET allows small bulk capacitance and maximizes power capability 85-265 VAC • Short-circuit, overload, open feedback and output overvoltage Product2 Minimum Output Maximum Output protection Power Power1 • Hysteretic thermal shutdown LNK454D 1.5 W 3 W • Meets high-voltage creepage between DRAIN and all other pins LNK456D 3 W 6 W both on PCB and at package LNK457D/K/V 4 W 8 W LNK458K/V 6 W 11.5 W EcoSmart™ - Energy Efficient LNK460K/V 8 W 16 W • High power factor optimizes system lumen per input VA Table 1. Output Power Table. • Control algorithm balances switching and conduction losses Notes: over line and load to maintain optimum efficiency 1. Maximum practical continuous power in an open frame design with adequate heat sinking, measured at +50 °C ambient (see Key Applications Considerations for more information). Description 2. Packages: D: SO-8C, K: eSOP-12, V: eDIP-12. The LinkSwitch-PL family enables a very small and low cost single-stage power factor corrected constant current driver for Output Current solid state lighting. Optimized for direct LED current sensing, the Number of 350 mA 500 mA 700 mA 1000 mA LinkSwitch-PL operates over a wide input voltage range delivering Serial LEDs an output power of up to 16 W. The LinkSwitch-PL control 1 LNK454 LNK454 LNK454 LNK456 algorithm provides flicker-free TRIAC dimming with minimal 2 LNK454 LNK456 LNK456 LNK457 external components. 3 LNK456 LNK456 LNK457 LNK458 4 LNK456 LNK457 LNK458 LNK460 Each device incorporates a 725 V rated power MOSFET, a novel 5 LNK457 LNK458 LNK460 discontinuous mode variable frequency variable on-time controller, 6 LNK457 LNK458 LNK460 frequency jitter, cycle-by-cycle current limit and hysteretic thermal 7 LNK458 LNK460 shutdown in a monolithic 4-pin IC, available in SO-8C, eSOP-12, 8 LNK458 LNK460 and eDIP-12 packages. 9 LNK458 LNK460 10 LNK460 11 LNK460 12 LNK460 Figure 2. Device Selection Based on Length of Output LED Series String and Current. A Typical Voltage Drop of 3.5 V per LED is Assumed. www.powerint.com October 2011

LNK454/456-458/460 DRAIN (D) REGULATOR BYPASS (BP) 5.85 V UV 4.9 V ILIM ILIM + V_ILIM SOA CURRENT LIMIT QSETS STATES MOAACHINE VFB(SK) + QCLRR UV VFB(LO) + IFB VREF DAC MEAPSHUARSEEMENT Zero Crossing + V_ZLIM 1 µA FILTER DIGITAL FEEDBACK (FB) + INTEGRATOR AUTO-RESTART Update INC/DEC CLK FREQUENCY/ SSETQ DUTY CYCLE CONTROLLER RCLRQ ON-TIME EXTENSION PI-5893-091010 SOURCE (S) Figure 2. Functional Block Diagram. Pin Functional Description DRAIN (D) Pin: D Package (SO-8C) High-voltage power MOSFET drain connection. The internal 1 8 start-up bias current is drawn from this pin through a switched FB S Exposed Pad (On Bottom) high-voltage current source. Drain current sensing and BP 2 7 S ISnOteUrnRaClEly PCionnnected to associated controller functions are also performed using this pin. 6 K Package S (eSOP-12) SOURCE (S) Pin: 4 5 D S NC 1 12 S Power MOSFET source connection. Ground reference for FB 2 11 S BYPASS and FEEDBACK pins. BP 3 10 S BYPASS (BP) Pin: NC 4 9 S Connection point for the external bypass capacitor for the 8 S internally generated 5.85 V supply. D 6 7 S Exposed Pad Internally FEEDBACK (FB) Pin: Connected to SOURCE Pin LED current sensing pin. During normal operation the 290 mV V Package (eDIP-12) threshold determines the average value of the current flowing S 12 1 NC through the load sense resistor. S 11 2 FB A second threshold clamps excessive output current ripple. S 10 3 BP S 9 4 NC A third higher threshold is used to protect against output S 8 short-circuit and overvoltage conditions (see Figure 5). S 7 6 D PI-5836a-061311 Figure 3. Pin Configuration (Top View). 2 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 D DZ ES OV AC RES ROV IN D LinkSwitch-PL CONTROL BP S FB C R F F R SENSE PI-5837-060710 Figure 4. Typical Application Schematic. Functional Description The LinkSwitch-PL combines a high-voltage power MOSFET Auto-restart protection is triggered by a FEEDBACK pin voltage switch with a power supply controller in one device. The IC in excess of 2 V. This feature can be used to provide output provides a single-stage power factor correction plus LED overvoltage protection (via DZ and R , in Figure 4), which OV OV current control. The LinkSwitch-PL controller consists of an triggers the IC to enter auto-restart. oscillator, feedback (sense and logic) circuit, 5.85 V regulator, hysteretic over-temperature protection, frequency jittering, cycle-by-cycle current limit, loop compensation circuitry, auto- restart, switching on-time extension, power factor and constant current control. Auto-Restart In a direct LED current sensing configuration, the average 2 V FEEDBACK pin voltage is a replica of the LED current, scaled by the sense resistor (R in Figure 4). A small low-pass filter SENSE (R and C in Figure 4) reduces high frequency noise at the F F FEEDBACK pin. Cycle Skipping Figure 5 illustrates the operating regions of the FEEDBACK pin Mode voltage. The LinkSwitch-PL sets its operating point such that the average FEEDBACK pin voltage in steady-state operation is 290 mV. This threshold is set low to minimize the sensing resistor dissipation. The internal MOSFET switching frequency and on-time are updated once every input AC half-cycle to regulate the output current and maintain high power factor. 550 mV If the FEEDBACK pin peak voltage exceeds 550 mV, cycle Normal Operation skipping mode is triggered and the power processed by the 290 mV integrated power MOSFET is clamped on a cycle-by-cycle basis. Switching frequency may vary during an input voltage half-cycle to reduce thermal stress on the output LEDs. PI-5838-060111 Figure 5. FEEDBACK Pin Operational Voltage Thresholds. 3 www.powerint.com Rev. C 10/11

LNK454/456-458/460 V FB ϕOS ϕOL ϕOL ϕOS VFB(ϕ) VFB(ϕ) Phase Phase Angle Angle 0° 180° 0° 180° V LINE V TRIAC ϕ Phase ϕ Phase Angle Angle 0° Phase Conduction 0° Conduction Phase Angle Angle Angle Angle Leading Edge Trailing Edge TRIAC Dimmers Dimmers PI-5894a-091010 Figure 6. Feedback Voltage vs. Phase Angle Dimming Characteristics. TRIAC (Phase-Controlled) Dimming The LinkSwitch-PL integrates several features to improve (jOS) threshold is exceeded, V and the output LED current FB dimming range and reduce external circuit complexity when are reduced until a second phase angle threshold is reached. using a phase-controlled TRIAC dimmer. The output LED At this point, with the TRIAC conduction angle being very current is controlled by the FEEDBACK pin voltage which limited, the IC runs open loop at constant frequency and duty changes proportionally to the TRIAC dimmer conduction angle. cycle (jOL region) and the integrated power MOSFET processes When the conduction angle decreases, the voltage at the as much power as the heavily chopped input voltage will allow FEEDBACK pin decreases causing the average LED current to creating a light output that is deeply dimmed. decrease. The 520 mV clamping feedback threshold is also linearly reduced The FEEDBACK pin reference voltage adjustment is initiated at during dimming to control LED current ripple. approximately 25% of the AC line half-cycle duration. When this 4 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 IC Supply and BYPASS Pin Overload Protection The internal 5.85 V regulator charges the bypass capacitor In case of overload, the system will increase the operating connected to the BYPASS pin to 5.85 V by drawing current frequency and on-time each AC half-cycle until the maximum from the voltage on the DRAIN pin whenever the power MOSFET frequency and maximum on-time are reached. When this state is off. The BYPASS pin is the internal supply voltage node. is reached, the controller enters auto-restart protection, thus When the power MOSFET is on, the device operates from the inhibiting the gate of the power MOSFET for approximately energy stored in the bypass capacitor. Extremely low power 1.28 s if the main line frequency is 50 Hz, 1.02 s if it is 60 Hz. consumption of the internal circuitry allows LinkSwitch-PL to After this auto-restart off-time expires, the power MOSFET is operate continuously from current it takes from the DRAIN pin. re-enabled and a normal start-up is initiated, i.e. at f and MIN A bypass capacitor value of 1 µF is sufficient for both high t , stepping up until regulation is achieved again. In case of ON(MIN) frequency decoupling and energy storage. Dimming a persistent overload condition, the auto-restart duty cycle DC AR applications may require a higher bypass capacitor value. is ~33%. During phase angle dimming when the conduction angle is Overload protection is inhibited during phase dimming when the small the AC input voltage is present for only short periods of TRIAC conduction duty cycle is less than 60%. time. In that case the IC should not rely on the integrated high-voltage current source, but instead external bias circuitry Output Overvoltage Protection should be used to supply the IC from the output (D and R in If a no-load condition is present on the output of the supply, the ES ES Figure 4). If the output voltage is less than 7 V, external bias output overvoltage Zener (DZ in Figure 4) will conduct once its OV circuitry should be implemented. This is accomplished by threshold is reached. A voltage V in excess of V = 2 V will OV FB(AR) adding an auxiliary winding on the transformer, which is then appear across the FEEDBACK pin and the IC will enter auto- rectified and filtered via a diode (ultrafast) and capacitor. The restart. winding voltage (turns) should be selected such that the maximum Output Short-Circuit IC consumption can be supported at the lowest operating If the output of the supply (i.e. the LED load) is short-circuited, output current. then a large amount of energy will be delivered to the sense Start-up, Switching Frequency and On-time Range resistor, generating a high-voltage at the FEEDBACK pin. If this At start-up the controller uses an initial switching frequency f condition develops more than 2 V on the FEEDBACK pin, then MIN and minimum on-time t . The charging of the output the IC will interpret this event as an output short-circuit and will ON(MIN) capacitor together with the energy delivery to the output LEDs enter auto-restart. determines a step-by-step increase of the power MOSFET Safe Operating Area (SOA) Protection switching frequency and on-time updated every half-cycle of the If 3 consecutive cycles of the power MOSFET are prematurely AC input voltage. terminated due to the power MOSFET current exceeding the current limit after the leading edge blanking time, SOA protection The steady-state switching frequency and on-time are mode is triggered and the IC will enter auto-restart. determined by the line voltage, voltage drop across the LEDs and converter efficiency. Hysteretic Thermal Shutdown The thermal shutdown circuitry senses the die junction At light load when the device reaches the minimum frequency temperature. The thermal shutdown threshold is set to 142 °C f and on-time t , the controller regulates by skipping MIN ON(MIN) typical with a 75 °C hysteresis. When the die temperature rises cycles. In this mode of operation the input current is not power above this threshold (142 °C) the power MOSFET is disabled factor corrected and the average output current is not guaranteed and remains disabled until the die temperature falls by 75 °C, at to fall within the normal range. A properly designed supply will which point the power MOSFET is re-enabled. not operate in this mode under normal load conditions. A power supply designed correctly will operate within the switching frequency range [f … f ], with an on-time falling MIN MAX between t and t when connected to a normal load. ON(MIN) ON(MAX) 5 www.powerint.com Rev. C 10/11

LNK454/456-458/460 LinkSwitch-PL Application Example The circuit shown in Figure 7 provides a single constant current Due to the much lower power consumed by LED lighting output of 350 mA with an LED string voltage of 15 V. The compared to incandescent lighting, the current drawn by the output current can be reduced using a standard AC mains lamp is below the holding current of the TRIAC dimmer. This TRIAC dimmer down to 1% (3 mA) without instability and causes undesirable behavior such as limited dimming range flickering of the LED load. The board is compatible with both and/or flickering. Inrush current that flows to charge the input low cost leading edge and more sophisticated trailing edge capacitance when the TRIAC turns on causes current ringing. dimmers. This too can cause similar undesirable behavior as the ringing may cause the TRIAC current to fall to zero and turn off for the The board was optimized to operate over the universal AC input remainder of the AC cycle or rapidly turn on and off. voltage range (85 VAC to 265 VAC, 47 Hz to 63 Hz) but suffers no damage over an input range of 0 VAC to 300 VAC. This To overcome these issues the design includes three circuit increases field reliability and lifetime during line sags and swells. blocks, a passive damper, an active damper and a bleeder. The LinkSwitch-PL based designs provide high power factor (>0.9 drawback of these blocks is increased power dissipation and at 115 VAC / 230 VAC) and low THD (<15% at 230 VAC, <10% therefore reduced efficiency of the supply. In this design, the at 115 VAC) enabling compliance to all current international values selected allow flicker-free operation with a single lamp requirements and enabling a single design to be used connected to a single dimmer at high-line. For flicker-free worldwide. operation with multiple lamps in parallel or at low line voltages only (100/115 VAC) then the values may be optimized to reduce The form factor of the board was chosen to meet the requirements dissipation and increase efficiency. for standard pear shaped (A19) LED replacement lamps. The output is non-isolated and requires the mechanical design of As these blocks are only required for dimming applications, for the enclosure to isolate both the supply and the LED load from non-dimming designs these components can simply be omitted the user. with jumpers used to replace R7, R8 and R20. PI Part Selection Active and Passive Damper Circuits One device size larger than required was selected to increase Resistor R20 forms a passive damper that together with the efficiency and reduce device thermal rise. This typically gives active damper limits the peak inrush current when the TRIAC the highest efficiency. Further increasing the device size often fires on each half-cycle. It should be a flameproof type to safely results in the same or lower efficiency due to the larger fail during a single point fault (e.g. failure of a bridge diode). switching losses associated with a larger power MOSFET. The active damper circuit connects a series resistance (R7 and AC Line TRIAC Dimmer Interface Circuits R8) with the input rectifier for a period of each AC half-cycle, it is The requirement to provide output dimming with low cost, then bypassed for the remainder of the AC cycle by a parallel TRIAC based, leading edge phase dimmers introduces a SCR (Q3). Resistor R3, R4 and C3 determines the delay before number of trade-offs in the design. the turn-on of Q3 which then shorts out the damper resistors R7 and R8. C10 R17 1 nF R9 27 Ω 100 V Active Damper 4.7 kΩ Bleeder 15 V, 350 mA 1 7 2.2L 2mH 10R01 k2Ω 16030C007 VpF SS1D150-TP C11 2 3 680 µF 25 V R3 R10 750 kΩ 510 Ω R13 4.7 Ω 6 MBBR61S UDS21J ETE116 0.R8128 Ω RTN 600 V 1% F1 L 3.15 A 75R0 4kΩ 6232C0 4n VF 4608C0 5n VF 4608C0 6n VF DLD46006 3R.31 k5Ω BAVD149WS 90 - 265 RV1 VAC 275 VAC 4.R7 2kΩ LinkSwitch-PL VR2 U1 MAZS2000ML LNK457DG 20 V D N 4R72 Ω0 2.2L 1mH CONTROL BP 1R k2Ω1 R14 Passive Damper 5R101 1Ω S FB 1 kΩ 252C0 3 nVF R7 Q3R8 150C0 8 nVF 21C5 µ9 VF 1R0 1k6Ω 240 Ω 240 Ω PI-6171a-102910 Figure 7. Schematic of a 5 W, 15 V LED Driver for A19 Incandescent Lamp Replacement. 6 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 Bleeder Circuit limits the maximum capacitance on the DC side of the input Resistor R10, R11 and C6 form a bleeder network which bridge rectifier. Typically the maximum capacitance value ensures the initial input current is high enough meet the TRIAC needed for high power factor also results in meeting the 19 V holding current requirement, especially during small conduction limit however during development, this should be verified on an angles. For non-dimming application R10, R11 and C6 may be oscilloscope. omitted. If a reduction in capacitance is required and this results in Input Rectifier and EMI Filter increased conducted EMI then capacitance may be added EMI filtering is provided by L1 and a pi (π) filter formed by C4, L2 before the input rectifier which effectively isolates it from the bus and C5. Resistors R2 and R9 dampen the self resonances of capacitance. the filter stages and reduce the resultant peaks in the conducted EMI spectrum. As shown the design meets For applications intended for use with leading edge TRIAC EN55015 conducted limits with >20 dB margin. dimmers, film capacitors are recommended as ceramic capacitors typically create audible noise. The incoming AC is rectified by BR1 and filtered by C4 and C5. The total effective input capacitance, the sum of C4 and C5, Output Capacitor Selection was selected to ensure correct zero crossing detection of the Output capacitance has a direct effect on the output load (LED) AC input by the LinkSwitch-PL device, necessary for correct ripple current. The larger the capacitance, the lower the ripple dimming operation. current. Excessive capacitance can prevent the output reaching regulation within the auto-restart time and either cause failure to Primary Components start or require several start-up attempts (hiccups). Too little The LNK457DG device (U1) incorporates the power switching capacitance can cause the voltage of the FEEDBACK pin to device, oscillator, CC control engine, start-up, and protection exceed the cycle skipping mode threshold, degrading PF and functions. The integrated 725 V power MOSFET provides causing output flicker while dimming. extended design margin, improving robustness during line surge events even in high-line applications. The device is Therefore the output capacitance value should be selected powered from the BYPASS pin via the decoupling capacitor C9. such that the ripple voltage across the output current sense At start-up, C9 is charged by U1 from an internal current source resistor (R18 in Figure 7) and fed into the FEEDBACK pin is via the DRAIN pin and then during normal operation it is supplied within the range of 100 mVp-p ≤ V ≤ 400 mVp-p with a FEEDBACK by the output via R15 and D4. For non-dimming designs D4 target value of 290 mVp-p. and R15 may be omitted. The output capacitor type is not critical. Non-electrolytic The rectified and filtered input voltage is applied to one end of capacitors are attractive in terms of lifetime (ceramics and solid the primary winding of T1. The other side of the transformer’s dielectric types do not have an electrolyte that evaporates over primary winding is driven by the integrated power MOSFET in time) however electrolytic types offer the best volumetric U1. The leakage inductance drain voltage spike is limited by an efficiency vs. cost. If multi-layer ceramics are selected, verify RCD-R clamp consisting of D2, R13, R12, and C7. the data sheet curves of capacitance vs. applied voltage and temperature coefficient. The typical capacitance value may be Diode D6 is used to protect the IC from negative ringing (drain 50% lower across temperature and/or close to rated voltage. voltage below source voltage) when the power MOSFET is off For all capacitor types verify the capacitor(s) selected are rated and the input voltage is below the reflected output voltage (V ). for the output ripple current. For electrolytic types, this requires OR selecting a low ESR type. A temperature rating of 105 °C or Output Rectification higher is recommended for long lifetime. For typical designs The secondary of the transformer is rectified by D5, a Schottky there is minimal self heating of the output capacitor and barrier type for higher efficiency, and filtered by C11. Resistor therefore lifetime is determined by the internal ambient R17 and C10 damp high frequency ringing and improve temperature and broadly follows the Arrhenius equation, i.e. conducted and radiated EMI. lifetime doubles for every 10 °C drop in operating temperature. For example the selection of a capacitor with a rated life of Output Feedback 5,000 hours at 105 °C would have an expected lifetime of The CC mode set-point is determined by the voltage drop that 40,000 hours at 75 °C. End of life is typically defined for an appears across R18 which is then fed to the FEEDBACK pin of electrolytic capacitor as a doubling of the ESR and the capacitance U1. Output overvoltage protection is provided by VR2 and R21. reducing by 20%. This often has little impact to the performance Application Considerations seen by the end user and extends the fit for purpose lifetime. Input Capacitor Selection Feedback Pin Signal During normal non-dimming (full power) operation, the FEEDBACK For correct operation during dimming, the LinkSwitch-PL device pin threshold voltage (the voltage developed across the current must detect line voltage zero crossing. This is sensed internally sense resistor) is 290 mV. For best output current regulation, via the drain node at the point the DC bus falls to <19 V. The between 100 mVp-p to 400 mVp-p of voltage ripple is recommended. requirement for the DC bus to reach this level on each half-cycle This can be achieved through selecting the appropriate value of 7 www.powerint.com Rev. C 10/11

LNK454/456-458/460 output capacitance and the value of the current sense resistor. Figure 8 shows the line voltage and current at the input of a If the peak of the ripple voltage exceeds 550 mV, the device will leading edge TRIAC dimmer. In this example, the TRIAC enter cycle skipping mode which will reduce PFC performance conducts at 90 degrees. (lower PF and increase THD). Figure 9 shows the desired rectified bus voltage and current. Transformer Considerations for use with Leading Edge TRIAC Dimmers 350 PI-5984-060810 0.35 Audible noise can be created in the transformer due to the Voltage amfrbeinrquiumpetinz cechdiea sbn.yg eCs eoinler eflcsut ixnw gwit hch oelornen stgh wen aiTthrRr ohIAwigC hle etgur srmn sseh coohnua.l dn T ibchaeis l a rcevaosnoid nbeaedn t oltage (V) 320500 Current 00..325 urrent (A) (aen.gd. pErEoLd utycpee lse).s sR aMu dainbdle o nthoeisre p tohta cno EreE tcyopreess a froer gthoeo ds acmhoei cfleusx put V 200 0.2 put C n 150 0.15 n density. Reducing the core flux density (BM) also reduces d I d I aeulimdiibnlaet enso iasney g neoniesrea gtioenn.e r Aat ivoanlu beu bt erelodwu c1e5s0 t0h eG apuoswse ur sually ctifie 100 0.1 ctifie e e capability of a given core size. R 50 0.05 R Working with TRIAC Dimmers 0 0 0 50 100 150 200 250 300 350 400 The requirement to provide output dimming with low cost, TRIAC based, leading edge phase dimmers introduces a Conduction Angle (°) number of trade-offs in the design. Figure 9. Resultant Waveforms Following Rectification of Ideal TRIAC Dimmer Output. For correct operation incandescent phase angle dimmers Figure 10 shows undesired rectified bus voltage and current typically have a specified minimum load, typically ~40 W for a with the TRIAC turning off prematurely and restarting. On the 230 VAC rated unit. This is to ensure that the current through first half-cycle this is due to the input current ringing below the the internal TRIAC stays above its specified holding current holding current of the TRIAC, excited by the initial inrush current. threshold. The second half-cycle also shows the TRIAC turning off due to the current falling below the holding current towards the end of Due to the much lower power consumed by LED lighting the the conduction angle. This difference in behavior on alternate input current drawn by the lamp is below the holding current of half-cycles is often seen due to a difference in the holding the TRIAC within the dimmer. The input capacitance of the current of the TRIAC between the two operating quadrants. driver allows large inrush currents to flow when the TRIAC fires. This then generates input current ringing with the input stage 350 PI-5985-102810 0.35 and line inductance which may cause the current to fall below Voltage tuflhincedk TeerRsiinIrAagCb.l eh obledhinagv icour rsruecnht. a Bs olitmh iotef dth deimsem minegc hraanngisem asn dca/ours e oltage (V) 320500 Current 00..325 urrent (A) V 200 0.2 C To overcome these issues two circuit blocks, damper and ut ut p p bleeder, are incorporated in dimming applications. The n 150 0.15 n drawback of these circuits is increased dissipation and ed I ed I therefore reduced efficiency of the supply. ctifi 100 0.1 ctifi e e R 50 0.05 R put) (V) 325500 PVCIou-5lrt9rae8g3ne-t060810 00..3255 mer) (A) 0 0 50 100 150 200 250 300 350 4000 n m Conduction Angle (°) mer I 150 0.15 h Di Figure 10. Example of Phase Angle Dimmer Showing Erratic Firing. m 50 0.05 ug ge (at Di -500.5 50 100 150 200 250 300 350 400-0.05 nt (Thro Irrfea tqphuiedi rlTye Rdtu.IArnCin igs tounr nainngd ooffff btheefonr ae bthleee ednedr aonf dth de ahmalpf-ecry ccilrec ouirt are a-150 -0.15 e Line Volt--235500 --00..2355 Line Curr Iinnc greenaeserasl, asso p dooweesr ddiimssmipeart ecdo min pthaeti bbillietye.d er and damper circuits Initially install a bleeder network across the rectified power bus Conduction Angle (°) (R10, R11 and C6 in Figure 7) with initial values of 0.1 µF and a Figure 8. Ideal Input Voltage and Current Waveforms for a Leading Edge TRIAC Dimmer at 90° Conduction Angle. total resistance of 1 kW and power rating of 2 W. 8 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 Reduce the capacitance value to find the minimum acceptable 350 PI-5986-060810 0.35 value. Reducing the capacitance value reduces power dissipation and therefore increases efficiency. V) 250 Voltage 0.25 A) If the bleeder circuit does not maintain conduction in the TRIAC, oltage ( 150 Current 0.15 urrent ( then add a damper. The purpose of the damper is to limit the V C inrush current (as the input capacitance charges) and associated ut 50 0.05 ut p p ringing that occurs when the TRIAC turns on. ut -50 0 50 100 150 200 250 300 350 -0.05 ut O O er -150 -0.15 er Initially add a passive damper which is a simple resistor in series m m m m with the AC input (R20 in Figure 7). Values in the range of 10 W Di-250 -0.25 Di – 100 W are typical with the upper range being limited by the allowed dissipation / temperature rise and reduction in efficiency. -350 -0.35 Values below 10 W may also be used but are less effective Conduction Angle (°) especially in high AC line input designs. Figure 11. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing Edge Dimmer at 90° Conduction Angle. If a passive damper is insufficient to prevent incorrect TRIAC operation then an active damper can be added. This is typical in high-line applications due to the much larger inrush current current surges and line ringing are not an issue. Use of these that flows when the TRIAC turns on. A low cost active damper types of dimmers typically does not require damper and circuit is formed by R3, R4, C3, Q3, R7 and R8 in Figure 7. bleeder circuits. Resistor R7 and R8 limit the inrush current and can be a much higher value than the passive case as they are in circuit for only Thermal Considerations a fraction of the line cycle. Silicon controlled rectifier (SCR) Q3 Lighting applications present unique thermal challenges for the shorts R7 and R8 after a delay defined by R3, R4 and C3. The power supply designer. In many cases the LED load and delay is adjusted to give the shortest time that provides associated heat sink determine the power supply ambient acceptable dimmer performance to minimize the dissipation in temperature. Therefore it is important to properly heat sink and the resistors. The SCR is a low current, low cost device available verify the operating temperatures of all devices. For the in TO-92 packages with very low gate current requirements. LinkSwitch-PL device a SOURCE pin (D package) or exposed The gate drive requirement of the selected SCR together with the pad (K or V package) temperature of <115 °C is recommended minimum specified line voltage defines the maximum value of to allow margin for unit to unit variation. Worst case conditions R7 and R8. are typically maximum output power, maximum external ambient and either minimum or maximum input voltage. It’s common for different dimmers to behave differently across Layout Considerations manufacturers and power ratings. For example a 300 W dimmer requires less dampening and requires less power loss Primary Side Connections in the bleeder than a 600 W or 1000 W dimmer due to the use of a lower current rating TRIAC which typically have lower The BYPASS pin capacitor should be located as close to the holding currents. Line impedance differences can also cause BYPASS pin and connected as close to the SOURCE pin as variation in behavior so during development the use of an AC possible. The SOURCE pin trace should not be shared with the source is recommended for consistency however testing using main power MOSFET switching currents. All FEEDBACK pin AC mains power should also be performed. components that connect to the SOURCE pin should follow the same guideline as for the BYPASS pin capacitor. Electronic Trailing Edge Dimmers Figure 11 shows the line voltage and current at the input of the It is critical that the main power MOSFET switching currents power supply with a trailing edge electronic dimmer. In this return to the bulk capacitor with the shortest path possible. Long example, the dimmer conducts at 90 degrees. This type of high current paths create excessive conducted and radiated dimmer typically uses a power MOSFET or IGBT to provide the noise. switching function and therefore no holding current is necessary. Also since the conduction begins at the zero crossing, high 9 www.powerint.com Rev. C 10/11

LNK454/456-458/460 Secondary Side Connections Maximum Drain Current The output rectifier and output filter capacitor should be as Measure the peak drain current under all operation conditions close as possible. The transformer output return pin should including start-up and fault conditions. Look for signs of have a short trace to the return side of the output filter capacitor. transformer saturation (usually occurs at high ambient These currents should not flow through the primary side source temperatures). Verify that the peak current is less than stated in pin currents. The primary side source pin and secondary side the Absolute Maximum Ratings section. return should be connected with a short trace. Thermal Check Quick Design Checklist At maximum output power, both minimum and maximum line voltage and ambient temperature; verify that temperature Maximum Drain Voltage specifications are not exceeded for the LinkSwitch-PL, Verify that the peak V does not exceed 700 V under all transformer, output diodes, output capacitors and drain clamp DS operating conditions including start-up and fault conditions. components. Switching Current Loop (Primary) Transformer U1 Bulk Capacitor Output Filter Copper Heat Sink Area Capacitor PI-6212-112410 Figure 12. RD-251 PCB Top View. Bulk Capacitor Connection Between Switching Primary and Secondary Current Loop (Secondary) Transformer U1 PI-6213-112410 Figure 13. RD-251 PCB Bottom View. 10 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 Absolute Maximum Ratings(1,4) DRAIN Pin Peak Current(5): LNK454 ...............400 mA (750 mA) Notes: LNK456 ..............850 mA (1450 mA) 1. All voltages referenced to SOURCE, T = 25 °C. A LNK457 ...........1350 mA (2000 mA) 2. Normally limited by internal circuitry. LNK458 ............1750 mA (2650 mA) 3. 1/16 in. from case for 5 seconds. LNK460 ............2700 mA (5100 mA) 4. The Absolute Maximum Ratings specified may be applied, DRAIN Pin Voltage ……………………… ............. -0.3 V to 725 V one at a time without causing permanent damage to the FEEDBACK Pin Voltage ……………………… ............ -0.3 to 9 V product. Exposure to Absolute Maximum Ratings for BYPASS Pin Voltage ……………………… ................. -0.3 to 9 V extended periods of time may affect product reliability. Lead Temperature(3) ....................................................... .........260 °C 5. The higher peak Drain current (in parentheses) is allowed Storage Temperature …………………. ..................-65 to 150 °C while the Drain voltage is simultaneously less than 400 V. Operating Junction Temperature(2) .........................-40 to 150 °C Thermal Resistance Thermal Resistance: D (SO-8C) Package: Notes: (q ) ..................................100 °C/W(1), 80 °C/W(2) 1. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610g/m2) copper clad, JA (q ) ................................................. .......30 °C/W(3) with no external heat sink attached. JC K (eSOP) Package: 2. Soldered to 1 sq. in. (645 mm2), 2 oz. (610g/m2) copper clad, (q ) ....................................69 °C/W(1), 49 °C/W(2) with no external heat sink attached. JA (q ) ................................................. ..........2 °C/W(4) 3. Measured on the SOURCE pin close to plastic interface. JC V (eDIP) Package: 4. Measured at the surface of exposed pad. (q ) .....................................76 °C/W(1), 64 °C/W(2) JA (q ) ................................................. ..........2 °C/W(4) JC Conditions Parameter Symbol SOURCE = 0 V; T = -40 to +125 °C Min Typ Max Units J (Unless Otherwise Specified) Control Functions Average 110 122 134 kHz Maximum Output f T = 25 °C Frequency MAX J Peak-Peak Jitter 6 % Average 25.8 29.6 33.4 kHz Minimum Output f T = 25 °C Frequency MIN J Peak-Peak Jitter 6 % Maximum Switch t T = 25 °C 5.74 µs ON-Time ON(MAX) J Minimum Switch t T = 25 °C 1.2 µs ON-Time ON(MIN) J Maximum Duty Cycle DC 70 % MAX T = 25 °C FEEDBACK Pin Voltage V J 280 290 300 mV FB Non-dimming (full power) operation FEEDBACK Pin Voltage Triggering Cycle V 550 mV FB(SK) Skipping Mode FEEDBACK Pin Voltage V 2 V for IC Auto-Restart FB(AR) Feedback Pull-up I -1.3 -1.0 -0.7 µA Current FB 11 www.powerint.com Rev. C 10/11

LNK454/456-458/460 Conditions Parameter Symbol SOURCE = 0 V; T = -40 to +125 °C Min Typ Max Units J (Unless Otherwise Specified) Control Function (cont.) V > V I FB FB(SK) 450 µA S1 (MOSFET not switching) LNK454 530 DRAIN Supply Current LNK456 585 V = 0 V FB I (MOSFET switching LNK457 650 µA S2 at f ) MAX LNK458 730 LNK460 1050 LNK454 -5.9 -4.2 -2.5 V = 0 V, I BP LNK456/457/458 -8.3 -5.9 -3.5 mA CH1 T = 25 °C J BYPASS Pin LNK460 -11.9 -8.5 -5.1 Charge Current LNK454 -3.4 -2.4 -1.4 V = 4 V, I BP LNK456/457/458 -5.2 -3.7 -2.2 mA CH2 T = 25 °C J LNK460 -8.0 -5.7 -3.4 BYPASS Pin Voltage V 5.60 5.85 6.15 V BP BYPASS Pin V I = 2 mA 5.9 6.2 6.6 V Shunt Voltage SHUNT BP Circuit Protection di/dt = 160 mA/µs LNK454 255 290 325 T = 25 °C J di/dt = 325 mA/µs LNK456 510 580 650 T = 25 °C J di/dt = 490 mA/µs Current Limit I LNK457 800 910 1020 mA LIMIT T = 25 °C J di/dt = 650 mA/µs LNK458 1012 1150 1288 T = 25 °C J di/dt = 980 mA/µs LNK460 1637 1860 2083 T = 25 °C J Leading Edge t T = 25 °C 160 200 ns Blanking Time LEB J Current Limit Delay t T = 25 °C 150 ns ILD J Thermal Shutdown T 135 142 150 °C Temperature SD Thermal Shutdown T 75 °C Hysteresis SD(H) BYPASS Pin Power-up V 4.9 V Reset Threshold Voltage BP(RESET) 12 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 Conditions Parameter Symbol SOURCE = 0 V; T = -40 to +125 °C Min Typ Max Units J (Unless Otherwise Specified) Output T = 25 °C 23.1 26.6 LNK454 J I = 26 mA D T = 100 °C 34.4 39.8 J T = 25 °C 11.7 13.5 LNK456 J I = 53 mA D T = 100 °C 17.5 20.2 J T = 25 °C 6.9 7.9 LNK457 J ON-State Resistance R W DS(ON) I = 85 mA D T = 100 °C 10.4 11.9 J T = 25 °C 4.4 5.1 LNK458 J I = 110 mA D T = 100 °C 6.7 7.6 J T = 25 °C 2.2 2.6 LNK460 J I = 170 mA D T = 100 °C 3.3 3.9 J V = 6.2 V, V > V , V = 580 V, OFF-State Leakage I BP FB FB(SK) DS 50 µA DSS1 T = 125 °C J Breakdown Voltage BV V = 6.2 V, V > V , T = 25 °C 725 V DSS BP FB FB(SK) J DRAIN Supply Voltage 50 V f = 50 Hz 1.28 MAIN Auto-Restart OFF-Time t s AR(OFF) f = 60 Hz 1.02 MAIN Auto-Restart Duty Cycle DC 33 % AR 13 www.powerint.com Rev. C 10/11

LNK454/456-458/460 Typical Performance Characteristics nce (pF)1010000 LLLLL SNNNNNcaKKKKKl44444in55556g46780 F ac00113to.....36051rs5: PI-6005-060210 nt (A) 01..182 PI-6006-060210 a e cit urr 0.6 Scaling Factors: apa N C LLNNKK445546 00..36 N C 10 RAI 0.4 LLNNKK445578 11..055 AI D LNK460 3.1 R D 0.2 LNK457 T = 25 °C CASE LNK457 T = 100 °C CASE 0 0 0 100 200 300 400 500 600 0 2 4 6 8 10 12 14 16 18 20 DRAIN Voltage (V) DRAIN Voltage (V) Figure 7. Drain Capacitance vs. Drain Voltage. Figure 8. Drain Current vs. Drain Voltage. wn Voltage ed to 25 C) °11..10 PI-2213-012301 nt Limited to 25 C)°1001...286 PI-6209-102910 akdomaliz Curremaliz0.4 reor or BN N ( (0.2 0.9 0 -50 -25 0 25 50 75 100 125 150 -50 0 50 100 150 Junction Temperature (°C) Temperature (°C) Figure 9. Breakdown vs. Temperature. Figure 10. Standard Current Limit vs. Temperature. 14 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 SO-8C (D Package) 0.10 (0.004) C A-B 2X 2 DETAIL A 4 B 4.90 (0.193) BSC A 4 D 8 5 GAUGE PLANE SEATING PLANE 2 3.90 (0.154) BSC 6.00 (0.236) BSC C 0 - 8o 0.25 (0.010) 1.04 (0.041) REF BSC 0.10 (0.004) C D 0.40 (0.016) 2X Pin 1 ID 1 4 0.20 (0.008) C 1.27 (0.050) 1.27 (0.050) BSC 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M CA-BD 1.35 (0.053) 1.25 - 1.65 DETAIL A 1.75 (0.069) (0.049 - 0.065) 0.10 (0.004) 0.10 (0.004) C H 0.25 (0.010) 7X SEATING PLANE 0.17 (0.007) C 0.25 (0.010) Reference Solder Pad + Dimensions Notes: 1. JEDEC reference: MS-012. 2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. + + + 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. D07C 1.27 (0.050) 0.60 (0.024) PI-4526-040110 15 www.powerint.com Rev. C 10/11

LNK454/456-458/460 eSOP-12B (K Package) 0.010 [0.25] 0.356 [9.04] Ref. 0.055 [1.40] Ref. Ref. 2 0.004 [0.10] C A 2X Pin #1 I.D. 0.400 [10.16] 0.325 [8.26] H (Laser Marked) 2X 7 Max. 7 12 0.010 [0.25] 0.004 [0.10] C B Gauge Plane Seating Plane 0.R05e9f, [T1y.5p0] 2 0 ° -8° 0.034 [0.85] C 0.460 [11.68] 0.350 [8.89] 0.225 [5.72] 0.026 [0.65] 0.059 [1.50] Max. 7 Ref, Typ DETAIL A (Scale = 9X) 0.008 [0.20] C 1 2 3 4 6 B 6 1 0.049 [1.23] 2X, 5/6 Lead Tips 0.023 [0.58] 113× 4 0.120 [3.05] Ref 0.02R8e [f0..71] 0.046 [1.16] 0.018 [0.46] 0.070 [1.78] 0.010 (0.25) M C A B TOP VIEW BOTTOM VIEW 0.019 [0.48] 0.020 [0.51] Ref. Ref. 0.022 [0.56] Ref. 0.098 [2.49] 0.032 [0.80] 0.092 [2.34] 3 0.086 [2.18] 0.029 [0.72] 0.086 [2.18] 0.016 [0.41] 0.011 [0.28] 11× Seating Plane 0.006 [0.15] 0.004 [0.10] C C 0.306 [7.77] 0.000 [0.00] Ref. Detail A Seating plane to package bottom standoff SIDE VIEW END VIEW 0.067 [1.70] Land Pattern 0.217 [5.51] Dimensions Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 1 12 2. Dimensions noted are determined at the outermost 0.028 [0.71] extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but 2 11 including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 3 10 [0.18] per side. 0.321 [8.15] 3. Dimensions noted are inclusive of plating thickness. 4 9 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches [mm]. 8 6. Datums A and B to be determined at Datum H. 7. Exposed pad is nominally located at the centerline of 6 7 Datums A and B. “Max” dimensions noted include both size and positional tolerances. 0.429 [10.90] PI-5748a-100311 16 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 eDIP-12B (V Package) 0.004 [0.10] C A 2 (LaPsienr # M1a Ir.Dke.d) 01.302M5a [x8..26] 0.120 [3.05] 0.S0e1a0t [in0.g2 5P]l aRneef.C 00..001116 [[00..2481]] 11× 0.400 [10.16] A0.059 [1.50] 2X 1 2 3 4 6 Ref. 6 1 Ref, typ. 0.004 [0.10] C B 0.412 [10.46] 7 2 Ref. 0.400 [10.16] 0.350 [8.89] 0.225 [5.72] 0.306 [7.77] 8 Max. Ref. 0.436 [11.08] 0.059 [1.50] 10 0.406 [10.32] Ref, typ. B 12 11 10 9 8 7 7 12 3 4 Detail A 5 °±4° 00..002138 [[00..5486]] 11× TOP VIEW 0.104 [2.65] Ref. 0.010 [0.25] M C A B END VIEW BOTTOM VIEW 0.356 [9.04] 0.092 [2.34] Ref. 0.086 [2.18] 0.019 [0.48] 0.049 [1.23] Ref. 0.046 [1.16] 0.022 [0.56] Ref. 0.192 [4.87] H Ref. 0.031 [0.80] 0.020 [0.51] 0.028 [0.72] Ref. 0.070 [1.78] 0.028 [0.71] Ref. SIDE VIEW DETAIL A (Scale = 9X) Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outer- Mounting most extremes of the plastic body exclusive of 0.07 [1.78] 0.03 [0.76] Hole Pattern mold flash, tie bar burrs, gate burrs, and interlead Dimensions flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in inches [mm]. 6. Datums A and B to be determined at Datum H. 0.400 [10.16] 7. Measured with the leads constrained to be perpendicular to Datum C. 8. Measured with the leads unconstrained. 9. Lead numbering per JEDEC SPP-012. 10. Exposed pad is nominally located at the center- Drill Hole 0.03 [0.76] line of Datums A and B. “Max” dimensions Round Pad 0.05 [1.27] noted include both size and positional tolerances. Solder Mask 0.056 [1.42] PI-5556a-100311 17 www.powerint.com Rev. C 10/11

LNK454/456-458/460 Part Ordering Information • LinkSwitch Product Family • PL Series Number • Package Identifier D SO-8C K eSOP-12 V eDIP-12 • Package Material G GREEN: Halogen Free and RoHS Compliant • Tape & Reel and Other Options Blank Standard Configurations LNK 454 D G - TL TL Tape & Reel, 2.5 k pcs minimum for D package, 1 k pcs minimum for K package. 18 Rev. C 10/11 www.powerint.com

LNK454/456-458/460 19 www.powerint.com Rev. C 10/11

Revision Notes Date A Initial Release. 11/01/10 B Revised K and V Package Drawings. 06/11 C Added eDIP-12B and eSOP-12B packages. Removed eDIP-12 and eSOP-12 packages. 10/11 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2011, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters Germany Japan Taiwan 5245 Hellyer Avenue Rueckertstrasse 3 Kosei Dai-3 Bldg. 5F, No. 318, Nei Hu Rd., Sec. 1 San Jose, CA 95138, USA. D-80336, Munich 2-12-11, Shin-Yokomana, Nei Hu Dist. Main: +1-408-414-9200 Germany Kohoku-ku Taipei, Taiwan 114, R.O.C. Customer Service: Phone: +49-89-5527-3910 Yokohama-shi Kanagwan Phone: +886-2-2659-4570 Phone: +1-408-414-9665 Fax: +49-89-5527-3920 222-0033 Japan Fax: +886-2-2659-4550 Fax: +1-408-414-9765 e-mail: eurosales@powerint.com Phone: +81-45-471-1021 e-mail: taiwansales@powerint.com e-mail: usasales@powerint.com Fax: +81-45-471-3717 India e-mail: japansales@powerint.com Europe HQ China (Shanghai) #1, 14th Main Road 1st Floor, St. James’s House Rm 1601/1610, Tower 1, Vasanthanagar Korea East Street, Farnham Kerry Everbright City Bangalore-560052 India RM 602, 6FL Surrey GU9 7TJ No. 218 Tianmu Road West, Phone: +91-80-4113-8020 Korea City Air Terminal B/D, 159-6 United Kingdom Shanghai, P.R.C. 200070 Fax: +91-80-4113-8023 Samsung-Dong, Kangnam-Gu, Phone: +44 (0) 1252-730-141 Phone: +86-21-6354-6323 e-mail: indiasales@powerint.com Seoul, 135-728, Korea Fax: +44 (0) 1252-727-689 Fax: +86-21-6354-6325 Phone: +82-2-2016-6610 e-mail: eurosales@powerint.com e-mail: chinasales@powerint.com Italy Fax: +82-2-2016-6630 Via De Amicis 2 e-mail: koreasales@powerint.com Applications Hotline China (ShenZhen) 20091 Bresso MI World Wide +1-408-414-9660 3rd Floor, Block A, Italy Singapore Zhongtou International Business Phone: +39-028-928-6000 51 Newton Road Applications Fax Center, No. 1061, Xiang Mei Rd, Fax: +39-028-928-6009 #15-08/10 Goldhill Plaza World Wide +1-408-414-9760 FuTian District, ShenZhen, e-mail: eurosales@powerint.com Singapore, 308900 China, 518040 Phone: +65-6358-2160 Phone: +86-755-8379-3243 Fax: +65-6358-2015 Fax: +86-755-8379-5828 e-mail: singaporesales@powerint.com e-mail: chinasales@powerint.com

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: P ower Integrations: RDK-268 RDK-271 LNK454DG LNK454DG-TL LNK456DG LNK456DG-TL LNK457DG LNK457DG-TL LNK457VG LNK457KG LNK457KG-TL LNK458VG LNK458KG LNK458KG-TL LNK460VG LNK460KG LNK460KG-TL