LNBH24L Dual LNBS supply and control IC with step-up and I²C interface Features ■ Complete interface between LNBS and I²C bus ■ Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93%@0.5 A) ■ Selectable output current limit by external resistor ■ Compliant with main satellite receivers output voltage specification QFN32 5 x 5 mm (ePad) ■ Auxiliary modulation input (EXTM) facilitates DiSEqC™ 1.X encoding ■ Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allow low power losses ■ Overload and over-temperature internal protections with I²C diagnostic bits ■ Output voltage and output current level diagnostic feedback by I²C bits ■ LNB short circuit dynamic protection ■ +/- 4 kV ESD tolerant on output power pins Description Intended for analog and digital DUAL satellite receivers/Sat-TV, Sat-PC cards, the LNBH24L is a monolithic voltage regulator and interface IC, assembled in QFN 5x5 ePAD, specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signaling for two independent LNB down-converters in the antenna dishes and/or multi-switch box. In this application field, it offers a dual tuner STBs complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing. Table 1. Device summary Order code Package Packaging LNBH24LQTR QFN32 5 x 5 (Exposed pad) Tape and reel March 2010 Doc ID 16857 Rev 2 1/25 www.st.com 25

Contents LNBH24L Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Application information (valid for each section A/B) . . . . . . . . . . . . . . . . . . 5 2.2 DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 DISEQC™ 1.X implementation with VoTX and EXTM pin connection . . . . 5 2.5 PDC optional circuit for DISEQC™ 1.X applications using VoTX signal on to EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 7 2.10 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.11 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 15 7.3 Transmitted data (I²C bus write mode) for each sections A/B . . . . . . . . . 15 2/25 Doc ID 16857 Rev 2

LNBH24L Contents 7.4 Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 16 7.5 Power-ON I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Address pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 17 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 16857 Rev 2 3/25

Block diagram LNBH24L 1 Block diagram Figure 1. Block diagram TTTTXX--AA IISSEELL----AA AADDDDRR----AA SSDDAA SSCCLL AADDDDRR----BB VVcccc BByypp VVcccc----LL IISSEELL----BB TTTTXX----BB LLXX----AA PPrreerreegguullaattoorr LLXX----BB ++UU..VV..lloocckkoouutt RRsseennssee ControllerControllerPWMPWM EENN--AA ++PP..OONN rreesseett EENN--BB WMWMontrollerontroller RRRRsssseeeennnnsssseeee TTEENN----AA TTEENN--BBBB PPCC PP--GGNNDD----AA VVSSEELL--AA EENN----AA EENN----BB VVSSEELL--BB PP--GGNNDD----BB ee VVSSEELL----AA acac VVSSEELL----BB TTTTXX----AA erferf TTTTXX----BB VVuupp----AA IISSEELL--AA VVOOUUTT----AACCoonnttrrooll I²C intII²C intI VVOOUUTT----BBCCoonnttrrooll IISSEELL--BB VVuupp----BB LLiinneeaarr PPoosstt----rreegg LLiinneeaarr PPoosstt----rreegg VVooRRXX----AA ++PPrrootteeccttiioonnss ++PPrrootteeccttiioonnss VVooRRXX----BB TTTTXX--AA ++DDiiaaggnnoossttiiccss II²²²²CC DDiiaaggnnoossttiiccss ++DDiiaaggnnoossttiiccss TTTTXX--BB FFFFFFFFBBBBBBBB FFFFBBBB VVooTTXX----AA 2222 kkHHzz 2222 kkHHzz VVooTTXX----BB OOsscciillllaattoorr OOsscciillllaattoorr EEXXTTMM----AA EEXXTTMM----BB DDSSQQIINN----AA DDSSQQIINN----BB TTEENN--AA TTTTEEEENNNN----BBBB LLNNBBHH2244LL PPDDCC--AA PPuullll DDoowwnn PPuullll DDoowwnn PPDDCC----BB CCoonnttrroolllleerr CCoonnttrroolllleerr AA----GGNNDD 4/25 Doc ID 16857 Rev 2

LNBH24L Introduction 2 Introduction The LNBH24L includes two completely independent sections. Unless for the V and I²C CC inputs, each circuit can be separately controlled and have its independent external components. All the below specification must be considered equal for both sections (A/B). 2.1 Application information (valid for each section A/B) This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V, generates the voltages (V ) that let the linear post-regulator to work at a minimum UP dissipated power of 0.55 W typ. @ 500 mA load per channel (the linear post-regulator drop voltage is internally kept at V - V = 1.1 V typ.). An under voltage lockout circuit will UP OUT disable the whole circuit when the supplied V drops below a fixed threshold (6.7 V CC typically). Note: In this document the V is intended as the voltage present at the linear post-regulator OUT output (V pin). oRX 2.2 DiSEqC™ data encoding The new internal 22 kHz tone generator is factory trimmed in accordance to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin (DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) the TTX function must be disabled setting TTX to LOW. 2.3 DiSEqC™ 1.X implementation by EXTM pin In order to improve design flexibility and reduce the total application cost, an analogic modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the V DC output voltage. An appropriate DC blocking capacitor must be used to couple the oRX modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter can be removed (see Section5: Application circuits) saving the external components cost.The pin EXTM modulates the V voltage through the series decoupling capacitor, so oRX that: V =V ×G oRX(AC) EXTM(AC) EXTM Where V (AC) and V (AC) are, respectively, the peak to peak voltage on the V oRX EXTM oRX and EXTM pins while G is the voltage gain from EXTM to V . EXTM oRX 2.4 DISEQC™ 1.X implementation with V and EXTM pin oTX connection If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz tone generator signal available through the V pin to drive the EXTM pin. By this way the oTX Doc ID 16857 Rev 2 5/25

Introduction LNBH24L V 22 kHz signal will be superimposed to the V DC voltage to generate the LNB output oTX oRX 22 kHz tone (see Figure3: LNBH24L with internal tone for DiSEqC 1.X applications). The internal 22 kHz tone generator available through the V pin must be activated during the oTX 22 kHz transmission by DSQIN pin or by the TEN bit.The DSQIN internal circuit activates the 22 kHz tone on the V output with 0.5 cycles ± 25 µs delay from the TTL signal oTX presence on the DSQIN pin, and it stops with 1 cycles ± 25 µs delay after the TTL signal is expired. The V pin internal circuit must be preventively set ON by the TTX function. This oTX can be controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is expired, the V must be disabled by setting the TTX to LOW. The 13 / 18 V power oTX supply is always provided to the LNB from the V pin. oRX 2.5 PDC optional circuit for DISEQC™ 1.X applications using V signal on to EXTM pin oTX In some applications, at light output current (< 50 mA) and in case of heavy output capacitive load, the 22 kHz tone can be distorted. In this case it is possible to add the "Optional" external components shown in the typical application circuit (see Figure4: DiSEqC 1.x using external 22 kHz tone generator source through EXTM pin) connected between V and PDC pin. This optional circuit acts as an active pull-down discharging the oRX output capacitance only when the internal 22 kHz tone is activated. 2.6 I²C interface The main functions of the IC are controlled via I²C bus by writing 6 bits on the system register (SR 8 bits in write mode). On the same register there are 5 bits that can be read back (SR 8 bits in read mode) to provide the diagnostic flags of two internal monitoring functions (OTF, OLF) and three output voltage register status (EN, VSEL, LLC) received by the IC (see Section2.8: Diagnostic and protection functions). In read mode there are 3 test bits (TEST1-2-3) that must be disregarded from the MCU. While, in write mode, there 2 Test bits (TEST4-5) that must be always set LOW. Each section (A/B) has two selectable I²C addresses selectable respectively, by the ADDR-A and ADDR-B pins (see Table11: Address pins characteristics). 2.7 Output voltage selection When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by mean of the VSEL bit (voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH24L is provided with the LLC I²C bit that increase the selected voltage value to compensate possible voltage drop along the output line. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during the stand-by condition). 2.8 Diagnostic and protection functions The LNBH24L has two diagnostic internal functions provided via I²C bus by reading 2 bits on the system register (SR bits in read mode). The diagnostic bits are, in normal operation (no 6/25 Doc ID 16857 Rev 2

LNBH24L Introduction failure detected), set to LOW. The diagnostic bits are dedicated to the over-temperature and over-load protections status (OTF and OLF). 2.9 Over-current and short circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. It is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current protection circuit works dynamically: as soon as an overload is detected, the output is shut- down for a time T , typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the OFF system register is set to "1". After this time has elapsed, the output is resumed for a time T = 1/10 T = 90 ms (typ.). At the end of T , if the overload is still detected, the ON OFF ON protection circuit will cycle again through T and T . At the end of a full T in which no OFF ON ON overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW. Typical T + T time is 990 ms and an internal timer determines it. This dynamic ON OFF operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to "1" when the current clamp limit is reached and returns LOW when the overload condition is cleared. 2.10 Thermal protection and diagnostic The LNBH24L is also protected against overheating: when the junction temperature exceeds 150°C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135°C (typ.) 2.11 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to ISEL pin. The resistor value defines the output current limit by the equation: Equation 1 1100000000 II [[AA]] == MMAAXX RR SSEELL where R is the resistor connected between I and GND (see R2 in the typical SEL SEL application circuit). The highest selectable current limit threshold is 0.9 A typ. with R = 11 SEL kΩ. The above equation defines the typical threshold value for each output. However, it is suggestible to not exceed for a long period a total amount of current of 1 A from both sections (I + I < 1 A) in order to avoid the over temperature protection triggering. OUT_A OUT_B Note: External components are needed to comply to bidirectional DiSEqC™ bus hardware requirements. Full compliance of the whole application with DiSEqC™ specifications is not implied by the bare use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT. Doc ID 16857 Rev 2 7/25

Pin configuration LNBH24L 3 Pin configuration Figure 2. Pin connections (bottom view) Table 2. Pin description Pin n° Symbol Name Pin function (sec. A/B) 21 V Supply Input 8 to 15 V IC DC-DC power supply. CC 20 V L Supply Input 8 to 15 V analog power supply. CC– 5 / 2 LX-A / LX-B N-MOS Drain Integrated N-channel Power MOSFETs drain. Input of the linear post-regulators. The voltage on these pins is 16 / V -A / UP Step-Up Voltage monitored by the internal step-up controllers to keep a 25 V -B UP minimum dropout across the linear pass transistors. 18 / V -A / Outputs of the integrated low drop linear regulators. See oRX LDO Output Port 23 V -B Table7 for voltage selections and description. oRX 17 / V A / Output Port during oTX – Tone outputs to the LNB. See Table7 for selection. 24 V B 22KHz Tone TX oTX – 6 SDA Serial Data Bidirectional data from / to I²C bus. 7 SCL Serial Clock Clock from I²C bus. These pins will accept the DiSEqC code from the main 10 / DSQIN-A / microcontroller. The LNBH24L will uses this code to modulate DiSEqC Inputs 31 DSQIN-B the internally generated 22 kHz carrier. Set to ground if not used. These pins can be used, as well as the TTX I²C bits of the 12 / TTX-A / system register, to control the TTX function enable before to TTX Enable 29 TTX-B start the 22 kHz tone transmission. Set floating or to GND if not used. 11 / 30 Reserved Reserved To be connected to GND. To be connected to the external NPN transistors base to 9 / PDC – A / Pull Down Control reduce the 22 kHz tone distortion in case of heavy capacitive 32 PDC – B load at light output current. If not used they can be left floating. 8/25 Doc ID 16857 Rev 2

LNBH24L Pin configuration Table 2. Pin description (continued) Pin n° Symbol Name Pin function (sec. A/B) External modulation inputs act on V linear regulator oRX 13 / EXTM-A / External outputs to superimpose an external 22 kHz signal. Need DC 28 EXTM-B Modulation decoupling to the AC source. If not used they can be left floating. 4 / P-GND-A / Power Grounds DC-DC converters power grounds. 3 P-GND-B To be connected with power grounds and to the ground layer Epad Epad Exposed Pad through vias to dissipate the heat. 22 A-GND Analog Grounds Analog circuits grounds. Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any 19 BYP By-pass Capacitor connection of this pin to external current or voltage sources may cause permanent damage to the device. Two I²C addresses available for each section by setting the 8 / ADDR-A / Address Setting Address pins voltage level. See address pin characteristics 1 ADDR-B table. The resistors “R ” connected between I and GND define 15/ ISEL-A / SEL SEL Current selection the linear regulators current limit protection threshold by the 26 ISEL-B equation: I = 10000 / R . max(typ) SEL 14 / Reserved Reserved To be left floating. Do Not connect to GND. 27 Doc ID 16857 Rev 2 9/25

Maximum ratings LNBH24L 4 Maximum ratings Table 3. Absolute maximum ratings (valid for both sections A/B) Symbol Parameter Value Unit V , V DC power supply input voltage pins -0.3 to 16 V CC-L CC I Output current Internally limited mA OUT V DC output pin voltage -0.3 to 25 V oRX V Tone output pin voltage -0.3 to 25 V oTX LX LX input voltage -0.3 to 25 V V DC input voltage -0.3 to 24 V UP V Logic input voltage (TTX, SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V I V Logic high output voltage (PDC pin) -0.3 to 7 V OH V EXTM pin voltage -0.3 to 2 V EXTM V Internal reference pin voltage (1) -0.3 to 4.6 V BYP ISEL Current selection pin voltage -0.3 to 4.6 V T Storage temperature range -50 to 150 °C STG T Junction temperature range -25 to 150 °C J ESD rating with human body model (HBM) for all pins unless 4, 21, 22 2 kV ESD ESD rating with human body model (HBM) for pins 21, 22 4 ESD rating with human body model (HBM) for pin 4 0.6 1. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Table 4. O perating ratings Symbol Parameter Value Unit V , V DC power supply input voltage pins 8 to 15 V CC-L CC T Junction temperature range 0 to 125 °C J Table 5. T hermal data Symbol Parameter Value Unit R Thermal resistance junction-case 2 °C/W thJC Thermal resistance junction-ambient with device soldered R 35 °C/W thJA on 2s2p PC board 10/25 Doc ID 16857 Rev 2

LNBH24L Application circuits 5 Application circuits Figure 3. LNBH24L with internal tone for DiSEqC 1.X applications DDDDDD333333 VVVVuuuupppp VVooTTXX RRRRRR999999 CCCCCCCCCCCC333333333333 CCCCCC666666 22KKOOhhmm 222...222µµµFFF ttttoooo LLLLNNNNBBBB CCCC11115555 DDDDDD111111 LLNNBBHH2244LL EEEEXXXXTTTTMMMM 44447777 nnnnFFFF 555500000000mmmmAAAA mmmmaaaaxxxx ((sseeccttiioonnss AA//BB)) DDD444 LLLLXXXX LLLL1111 VVVVooooRRRRXXXX VVVVVVcccccccccccc C2C2C2C2C2C2222222111111000000000000nnnnnnFFFFFF DDDDDDDDD222222222 VVVViiiinnnn VVVVVVcccccccccccc------LLLLLL 11112222VVVV CCCC1111 CCCCCCCC88888888 PPPPDDDDCCCC 222222222222222200000000nnnnnnnnFFFFFFFF {{{ SSSDDDAAA III222CCC BBBuuusss SSSCCCLLL EEXXTTMM AAADDDDDDRRR TTTTTTXXX IISSEELL RR22 ((RRSSEELL)) TTTooonnneee EEEnnnaaabbbllleee cccooonnntttrrrooolll DDDSSSQQQIIINNN PPPPPP------GGGGGGNNNNNNDDDDDD AAAAAA------GGGGGGNNNNNNDDDDDD BByypp CC1111 1155kkOOhhmm TTTTTTLLL 222200nnFF Figure 4. DiSEqC 1.x using external 22 kHz tone generator source through EXTM pin DD33 VVuupp VVooTTXX CC33 CC66 22..22µµµµFF LLNNBBHH2244LL DD11 ttoo LLNNBB ((sseeccttiioonnss AA//BB)) 550000mmAA mmaaxx LLXX VVooRRXX LL11 DD22 VVcccc CC1100 222200nnFF VViinn VVcccc--LL 1122VV CC11 CCCC8888 222222220000nnnnFFFF II22CCCC BBBBuuuussss{{ SSDDAA PPDDCC SSCCLL DDSSQQIINN AADDDDRR IISSEELL TTTTXX RR22 ((RRSSEELL)) 2222 kkHHzz ssiiggnnaall ssoouurrccee EEXXTTMM PP----GGNNDD AA--------GGNNDD BByypp 1155kkOOhhmm CC1111 CC1155 222200nnFF 222200nnFF Doc ID 16857 Rev 2 11/25

Application circuits LNBH24L Figure 5. LNBH24L with PDC circuit for DiSEqC 1.X applications DDDDDD333333 VVVVooooTTTTXXXX VVVVuuuupppp RRRRRR999999 22KKOOhhmm CCCCCCCCCCCC333333333333 CCCCCC666666 CCCC11115555 222...222µµµFFF LLNNBBHH2244LL EEEEXXXXTTTTMMMM 44447777 nnnnFFFF ttttoooo LLLLNNNNBBBB 555500000000mmmmAAAA mmmmaaaaxxxx DDDDDD111111 ((sseeccttiioonnss AA//BB)) DDD444 LLLLXXXX VVVVooooRRRRXXXX CCCCCC111111000000 LLLL1111 222222222222000000nnnnnnFFFFFF DDDDDD222222 VVVVVVcccccccccccc ****RRRR8888 111155550000 OOOOhhhhmmmm VVVViiiinnnn VVVVVVcccccccccccc------LLLLLL DD88 11112222VVVV 11NN44114488 CCCC1111 CCCCCCCC88888888 PPPPDDDDCCCC ****TTTTRRRR1111 222222222222222200000000nnnnnnnnFFFFFFFF ****RRRR5555 {{{ SSSDDDAAA 2222....2222KKKK OOOOhhhhmmmm ****CCCC11114444 III222CCC BBBuuusss SSSCCCLLL 1111nnnnFFFF *2*2*2*2RRRR22227777 OOOOhhhhmmmm AAADDDDDDRRR 3333....3333VVVV TTTTTTXXX IIIIIISSSSSSEEEEEELLLLLL ((((((******))))))OOOOOOPPPPPPTTTTTTIIIIIIOOOOOONNNNNNAAAAAALLLLLL ccccccoooooommmmmmppppppoooooonnnnnneeeeeennnnnnttttttssssss...... TTTTTToooooo bbbbbbeeeeee uuuuuusssssseeeeeedddddd oooooonnnnnnllllllyyyyyy iiiiiinnnnnn ccccccaaaaaasssssseeeeee RRRRRRRR22222222 ((((((((RRRRRRRRSSSSSSSSEEEEEEEELLLLLLLL)))))))) ooooooffffff hhhhhheeeeeeaaaaaavvvvvvyyyyyy ccccccaaaaaappppppaaaaaacccccciiiiiittttttiiiiiivvvvvveeeeee llllllooooooaaaaaadddddd TTTooonnneee EEEnnnaaabbbllleee cccooonnntttrrrooolll DDDSSSQQQIIINNN PPPPPP------GGGGGGNNNNNNDDDDDD AAAAAA------GGGGGGNNNNNNDDDDDD BBBBBBBByyyyyyyypppppppp CCCCCCCCCC11111111111111111111 1111111155555555kkkkkkkkOOOOOOOOhhhhhhhhmmmmmmmm TTTTTTLLL 222222222222222222220000000000nnnnnnnnnnFFFFFFFFFF Table 6. B ill of material (valid for A and B sections unless for C1, C2, C7, C8 and C11) Component Notes R2, R9, R5 (1) 1/16 W resistors. Refer to the typical application circuit for the relative values R7 (1), R8 (1) 1/2 W resistors. Refer to the typical application circuit for the relative values C1 25 V electrolytic capacitor, 100 µF or higher is suitable C3 25 V, 220 µF electrolytic capacitor, ESR in the 100 mΩ to 350 mΩ range C6, C8, C10, C11, C15, C14 (1) 25 V ceramic capacitors. Refer to the typ. appl. circuit for the relative values STPS130A or similar schottky diode with V > 25 V and I (AV) higher than: D1 RRM F I > I x (V / V ) F(AV) OUT_MAX UP_MAX IN_MIN STPS130A, 1N5818 or similar schottky diode with VRRM>25V. To be placed as D2 close as possible to VoRX pin D3 1N4001-07 or any similar general purpose rectifier BAT54, STPS130A, BAT43, 1N5818, or similar schottky diode with VRRM>20V. D4 To be placed as close as possible to EXTM pin D8 1N4148 or similar TR1 (1) BC817 or similar NPN general-purpose transistor 22 µH inductor with I > I where I is the boost converter peak current: L1 sat peak peak (see Equation 2) 1. These components can be added to avoid any 22 kHz tone distortion due to heavy capacitive output loads. If not needed they can be removed leaving the PDC pin floating. Equation 2 12/25 Doc ID 16857 Rev 2

LNBH24L I²C bus interface 6 I²C bus interface Data transmission from main microprocessor to the LNBH24L and vice versa takes place through the 2 wires I²C bus interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 6.1 Data validity As shown in Figure6, the data on the SDA line must be stable during the high semi-period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 Start and stop condition As shown in Figure7 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 6.4 Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure8). The peripheral (LNBH24L) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH24L won't generate acknowledge if the V supply is below the under-voltage lockout threshold (6.7 V typ.). CC 6.5 Transmission without acknowledge Avoiding to detect the acknowledges of the LNBH24L, the microprocessor can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Doc ID 16857 Rev 2 13/25

I²C bus interface LNBH24L Figure 6. Data validity on the I²C bus Figure 7. Timing diagram of I²C bus Figure 8. Acknowledge on the I²C bus 14/25 Doc ID 16857 Rev 2

LNBH24L LNBH24 software description 7 LNBH24 software description The LNBH24L I²C interface controls both the IC sections A and B depending on the address sent before the DATA byte. All the below description is valid for both sections. 7.1 Interface protocol The interface protocol comprises: ● A start condition (S) ● A chip address byte [the LSB bit determines read (=1)/write (=0) transmission] ● A sequence of data (1 byte + acknowledge) ● A stop condition (P) Section address (A or B) Data MSB LSB MSB LSB S 0 0 0 1 0 X X R/W ACK ACK P ACK = Acknowledge S = Start P = Stop R/W = 1/0, Read/Write bit X = 0/1, two addresses for each section selectable by ADDR-A/B pins (see Table11) 7.2 System register (SR, 1 Byte for each section A and B) Mode MSB LSB Write PCL TTX TEN LLC VSEL EN TEST4 TEST5 Read TEST1 TEST2 TEST3 LLC VSEL EN OTF OLF Write = control bits functions in write mode Read = diagnostic bits in read mode. All bits reset to 0 at power on 7.3 Transmitted data (I²C bus write mode) for each sections A/B When the R/W bit in the section address is set to 0, the main microprocessor can write on the system register (SR) of the relative section (A or B, depending on the 7 bit address value) via I²C bus. All and 8 bits are available and can be written by the microprocessor to control the device functions as per the below truth table (Table7). Doc ID 16857 Rev 2 15/25

LNBH24 software description LNBH24L Table 7. T ruth table PCL TTX TEN LLC VSEL EN TEST4 TEST5 Function 0 0 0 1 0 0 V = 13.3 V, V =14.4 V, (V -V =1.1 V typ.) oRX UP UP oRX 0 0 1 1 0 0 V = 18.2 V, V =19.3 V, (V -V =1.1 V typ.) oRX UP UP oRX 0 1 0 1 0 0 V = 14.3 V, V =15.4 V, (V -V =1.1 V typ.) oRX UP UP oRX 0 1 1 1 0 0 V = 19.2 V, V =20.3 V, (V -V =1.1 V typ.) oRX UP UP oRX Internal 22 kHz controlled by DSQIN pin (only if 1 0 1 0 0 TTX=1) Internal 22 kHz tone output on V is always 1 1 1 0 0 oTX activated Internal 22 kHz generator disabled, EXTM 0 0 1 0 0 modulation enabled V output is ON, V Tone generator output is 0 1 0 0 oRX oTX OFF V output is ON, V Tone generator output is 1 1 0 0 oRX oTX ON 0 1 0 0 Pulsed (Dynamic) current limiting is selected 1 1 0 0 Static current limiting is selected X X X X X 0 X X Power block disabled X = don't care Values are typical unless otherwise specified Valid with TTX pin floating 7.4 Diagnostic received data (I²C read mode) for both sections A/B The LNBH24L can provide to the MCU master a copy of the diagnostic system register information via I²C bus in read mode. The read mode is master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH24L issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the master can: ● Acknowledge the reception, starting in this way the transmission of another byte from the LNBH24L ● No acknowledge, stopping the read mode communication Three bits of the register are read back as a copy of the corresponding write output voltage register status (LLC, VSEL, EN), two bits convey diagnostic information about the over- temperature (OTF), output over-load (OLF) and three bit are for internal usage (TEST1-2-3) and must be disregarded by the MCU software. In normal operation the diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to one. At start-up all the bits are reset to zero. 16/25 Doc ID 16857 Rev 2

LNBH24L LNBH24 software description Table 8. R egister TEST1 TEST2 TEST3 LLC VSEL EN OTF OLF Function 0 T < 135°C, normal operation J 1 T > 150°C, power blocks disabled These bits are read J exactly the same as 0 I < I , normal operation O OMAX they were left after 1 I > I , Overload Protection triggered last write operation O OMAX These bits status must be disregarded by the X X X MCU. X = don’t care Note: Values are typical unless otherwise specified. 7.5 Power-ON I²C interface reset The I²C interface built in the LNBH24L is automatically reset at power-on. As long as the V stays below the undervoltage lockout (UVL) threshold (6.7 V), the interface will not CC respond to any I²C command and the system registers (SR) are initialized to all zeroes, thus keeping the power blocks disabled. Once the V rises above 7.3 V typ. The I²C interface CC becomes operative and the SRs can be configured by the main microprocessor. This is due to 500 mV of hysteresis provided in the UVL threshold to avoid false re-triggering of the Power-ON reset circuit. 7.6 Address pins For each section of the LNBH24L it is possible to select two I²C interface addresses by means of the relevant ADDR pin. The ADDR pins are TTL compatible and can be set as per hereafter address pins characteristics see Table11. 7.7 DiSEqC™ implementation for each section A/B LNBH24L helps system designer to implement DiSEqC 1.x protocol by allowing an easy PWK modulation of the 22 kHz carrier through the EXTM and V pins. Full compliance of oTX the system to the specification is thus not implied by the bare use of the LNBH24L (see DiSEqC 1.x operation descriptions and typical application circuits). Doc ID 16857 Rev 2 17/25

Electrical characteristics LNBH24L 8 Electrical characteristics Refer to the typical application circuits, T from 0 to 85 °C, EN=1, J VSEL=LLC=TEN=PCL=TEST4=TEST5=TTX=0, R =15 kΩ, DSQIN=LOW, V = 12 V, SEL IN I = 50 mA, unless otherwise stated. Typical values are referred to T = 25°C. OUT J V = V pin voltage. See software description section for I²C access to the system OUT oRX register. Table 9. E lectrical characteristics of each sections A/B Symbol Parameter Test conditions Min. Typ. Max. Unit V Supply voltage I = 500 mA, VSEL = LLC = 1 8 12 15 V IN OUT Both sections A and B enabled 20 30 I = 0 OUT Both sections A and B enabled, I Supply current mA IN optional PDC circuit not connected. 50 70 EN = TEN = TTX = 1, I = 0 OUT EN = 0 6 VSEL = 1 LLC = 0 17.3 18.2 19 V Output voltage OUT IOUT = 500 mA LLC = 1 19.2 V VSEL = 0 LLC = 0 12.6 13.3 14 V Output voltage OUT IOUT = 500 mA LLC = 1 14.3 VSEL=0 5 40 V Line regulation V = 8 to 15 V OUT IN VSEL=1 5 60 mV V Load regulation VSEL=0 or 1, I from 50 to 500mA 200 OUT OUT RSEL= 15 kΩ 500 800 I Output current limiting mA MAX RSEL= 11 kΩ 750 1000 I Output short circuit current VSEL=0/1 800 mA SC Dynamic overload protection T PCL=0, Output Shorted 900 OFF OFF time ms Dynamic overload protection T / T PCL=0, Output Shorted OFF ON ON time 10 F Tone frequency DSQIN=HIGH or TEN=1, TTX=1 18 22 26 kHz TONE DSQIN=HIGH or TEN=1, TTX=1, Tone amplitude using internal DiSEqC 1.X configuration using A 0.4 0.650 0.9 V TONE tone generator internal generator, C from 0 to PP BUS 250 nF, I from 50 to 500 mA OUT DSQIN=HIGH or TEN=1, TTX=1, DiSEqC 1.X configuration using Tone amplitude using internal internal generator, I from 0 to 500 A OUT 0.4 0.650 0.9 V TONE tone generator mA, C from 0 to 750 nF, PDC PP OUT optional circuit connected to LNB bus(1) DSQIN=HIGH or TEN=1, TTX=1 D Internal tone duty cycle 40 50 60 % TONE (using internal generator) 18/25 Doc ID 16857 Rev 2

LNBH24L Electrical characteristics Table 9. Electrical characteristics of each sections A/B (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit DSQIN=HIGH or TEN=1, TTX=1 t, t Tone rise or Fall time 5 8 15 µs r f (using internal generator) V PDC pin logic LOW I = 2 mA 0.3 V PDC_OL PDC I PDC pin leakage current V = 5 V 1 µA PDC_OZ PDC ΔV / ΔV , freq. from 10 kHz to G External modulation Gain OUT EXTM 1.8 EXTM 50 kHz External modulation input V EXTM AC coupling (2) 400 mV EXTM voltage PP External modulation Z 2 kΩ EXTM impedance Eff DC-DC converter efficiency I = 500 mA 93 % DC-DC OUT DC-DC converter switching F 220 kHz SW frequency V DSQIN,TTX, pin logic low 0.8 V IL V DSQIN,TTX, pin logic high 2 V IH I DSQIN,TTX, pin input current V = 5 V 15 µA IH IH I Output backward current EN = 0, V = 21 V -6 -15 mA OBK OBK T Thermal shut-down threshold 150 °C SHDN ΔT Thermal shut-down 15 °C SHDN hysteresis 1. Guaranteed by design, but not tested in production 2. External signal maximum voltage for which the EXTM function is guaranteed T from 0 to 85 °C, V = 12 V. J I Table 10. I ² C electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V LOW Level input voltage SDA, SCL 0.8 V IL V HIGH Level input voltage SDA, SCL 2 V IH I Input current SDA, SCL, V = 0.4 to 4.5 V -10 10 µA IN I V Low level output voltage SDA (open drain), I = 6 mA 0.6 V OL OL F Maximum clock frequency SCL 400 kHz MAX Doc ID 16857 Rev 2 19/25

Electrical characteristics LNBH24L T from 0 to 85 °C, V = 12 V. J I Table 11. A ddress pins characteristics Symbol Parameter Test condition Min. Typ. Max. Unit SECTION “A” ADDRESS SELECTION “0001000(R/W)” Address pin R/W bit determines the transmission V 0 0.8 V ADDR-A1 voltage range for section A mode: read (R/W=1) write (R/W=0) “0001001(R/W)” Address pin R/W bit determines the transmission V 2 5 V ADDR-A2 voltage range for section A mode: read (R/W=1) write (R/W=0) SECTION “B” ADDRESS SELECTION “0001010(R/W)” Address pin R/W bit determines the transmission V 0 0.8 V ADDR-B1 voltage range for section B mode: read (R/W=1) write (R/W=0) “0001011(R/W)” Address pin R/W bit determines the transmission V 2 5 V ADDR-B2 voltage range for section B mode: read (R/W=1) write (R/W=0) 20/25 Doc ID 16857 Rev 2

LNBH24L Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 16857 Rev 2 21/25

Package mechanical data LNBH24L Table 12. Q FN32 (5 x 5 mm) mechanical data (mm.) Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 A3 0.20 b 0.18 0.25 0.30 D 4.85 5.00 5.15 D2 3.20 3.70 E 4.85 5.00 5.15 E2 3.20 3.70 e 0.50 L 0.30 0.40 0.50 ddd 0.08 Figure 9. QFN32 package dimensions 7376875/E 22/25 Doc ID 16857 Rev 2

LNBH24L Package mechanical data Tape & reel QFNxx/DFNxx (5x5 mm.) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 99 101 3.898 3.976 T 14.4 0.567 Ao 5.25 0.207 Bo 5.25 0.207 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 16857 Rev 2 23/25

Revision history LNBH24L 10 Revision history Table 13. Document revision history Date Revision Changes 03-Dec-2009 1 Initial release. 18-Mar-2010 2 Modified: Figure3 on page11 and Figure5 on page12. 24/25 Doc ID 16857 Rev 2

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