Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 LMV641 10-MHz, 12-V, Low-Power Amplifier 1 Features 3 Description • Specifiedfor2.7-V,and±5-VPerformance The LMV641 is a low-power, wide-bandwidth 1 operational amplifier with an extended power supply • LowPowerSupplyCurrent:138µA voltagerangeof2.7Vto12V. • HighUnityGainBandwidth:10MHz The device features 10 MHz of gain bandwidth • MaxInputOffsetVoltage:500 µV product with unity gain stability on a typical supply • CMRR:120dB current of 138 µA. Other key specifications are a • PSRR:105dB PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV, input referred voltage noise of 14 nV/√Hz, and a THD • InputReferredVoltageNoise:14nV/√Hz of 0.002%. This amplifier has a rail-to-rail output • 1/fCornerFrequency:4Hz stage and a common mode input voltage, which • OutputSwingWith2-kΩLoad40mVfromRail includesthenegativesupply. • TotalHarmonicDistortion:0.002%at1kHz,2kΩ The LMV641 device operates over a temperature • TemperatureRange −40°Cto125°C rangeof−40°Cto+125°Candisofferedintheboard- space-saving 5-Pin SC70, SOT-23, and 8-Pin SOIC 2 Applications packages. • PortableEquipment DeviceInformation(1) • Battery-PoweredSystems PARTNUMBER PACKAGE BODYSIZE(NOM) • SensorsandInstrumentation SOIC(8) 4.90mm×3.91mm LMV641 SOT-23(5) 2.90mm×1.60mm SC70(5) 2.00mm×1.25mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. OffsetVoltageDistribution OpenLoopGainandPhasevsFrequency 20 18 UNITS TESTED = 12,000 V+ = +5V 180 + 180 - V = +6V 16 V = -5V 150 V- = -6V 150 VCM = 0V )%( E 1124 TA = 25°C 120 PHASE RCLL == 1200 kp:F 120 G 90 90 ATNE 10 )Bd( N 60 GAIN 60 °) E(S CR 8 IA AH EP 6 G 30 30 P 4 0 0 2 -30 -30 0 -400-300-200-100 0 100 200 300 400 -60 -60 100 1k 10k 100k 1M 10M 100M OFFSET VOLTAGE (PV) FREQUENCY (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................15 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 17 3 Description............................................................. 1 8.1 ApplicationInformation............................................17 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................17 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 23 6 Specifications......................................................... 4 10 Layout................................................................... 23 6.1 AbsoluteMaximumRatings .....................................4 10.1 LayoutGuidelines.................................................23 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................23 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 24 6.4 ThermalInformation..................................................4 11.1 DeviceSupport ....................................................24 6.5 DCElectricalCharacteristics:2.7V .........................5 11.2 DocumentationSupport .......................................24 6.6 DCElectricalCharacteristics:10V...........................6 11.3 ReceivingNotificationofDocumentationUpdates24 6.7 TypicalCharacteristics..............................................8 11.4 CommunityResource............................................24 7 DetailedDescription............................................ 14 11.5 Trademarks...........................................................24 7.1 Overview.................................................................14 11.6 ElectrostaticDischargeCaution............................24 7.2 FunctionalBlockDiagram.......................................14 11.7 Glossary................................................................24 7.3 FeatureDescription.................................................14 12 Mechanical,Packaging,andOrderable Information........................................................... 25 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(February2013)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • MovedPackagethermalresistance(R )rowsfromRecommendedOperatingConditionstoThermalInformation...........4 θJA ChangesfromRevisionB(February2013)toRevisionC Page • ChangedlayoutofNationalSemiconductorDataSheettoTIFormat................................................................................... 1 2 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 5 Pin Configuration and Functions DBVandDCKPackages 5-PinSOT-23andSC70 DPackage TopView 8-PinSOIC TopView 1 8 N/C N/C V - 2 - 7 V+ IN 3 6 V + + V IN OUT 4 5 V- N/C PinFunctions PIN TYPE(1) DESCRIPTION NAME SOT-23 SC70 SOIC V + 3 3 3 I NoninvertingInput IN V - 4 4 2 I InvertingInput IN V 1 1 6 O Output OUT V+ 5 5 7 P Positivesupplyinput V– 2 2 4 P Supplynegativeinput (1) I=input;O=output;P=power Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT DifferentialinputV ±0.3 ±0.3 V ID Supplyvoltage(V =V+-V−) 13.2 V S Inputandoutputpinvoltage (V−−0.3) V++0.3 V Junctiontemperature (3) 150 °C Storagetemperature,T –65 150 °C stg (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobefunctional,butspecificperformanceisnotguaranteed.Forensuredspecificationsandthetest conditions,seetheElectricalCharacteristicsTables. (2) IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) ThemaximumpowerdissipationisafunctionofT ,R .Themaximumallowablepowerdissipationatanyambienttemperatureis J(MAX θJA P =(T -T )/R .AllnumbersapplyforpackagessoldereddirectlyontoaPCboard. D J(MAX) A θJA 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM), (1) ±2000 V Electrostaticdischarge V (ESD) Machinemodel(MM) ±200 (1) HumanBodyModel,applicablestd.MIL-STD-883,Method3015.7. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Temperature (1) –40 125 °C Supplyvoltage(V =V+–V−) 2.7 12 V S (1) ThemaximumpowerdissipationisafunctionofT ,R .Themaximumallowablepowerdissipationatanyambienttemperatureis J(MAX θJA P =(T -T )/R .AllnumbersapplyforpackagessoldereddirectlyontoaPCboard. D J(MAX) A θJA 6.4 Thermal Information LMV641 THERMALMETRIC(1) DBV(SOT-23) DCK(SC70) D(SOIC) UNIT 5PINS 5PINS 8PINS R (2) Junction-to-ambientthermalresistance 325 456 166 °C/W θJA R Junction-to-case(top)thermalresistance 178.1 121.8 93.6 °C/W θJC(top) R Junction-to-boardthermalresistance 60.8 68.9 90.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 57.7 5.3 38.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 60.2 68.1 90.4 °C/W JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ThemaximumpowerdissipationisafunctionofT ,R .Themaximumallowablepowerdissipationatanyambienttemperatureis J(MAX θJA P =(T -T )/R .AllnumbersapplyforpackagessoldereddirectlyontoaPCboard. D J(MAX) A θJA 4 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 6.5 DC Electrical Characteristics: 2.7 V Unlessotherwisespecified,alllimitsarespecifiedforT =25°C,V+=2.7V,V−=0V,V =V =V+/2,andR >1MΩ. A O CM L MIN TYP MAX PARAMETER TESTCONDITIONS (1) (2) (1) UNIT T =25°C 30 500 A V Inputoffsetvoltage µV OS Temperatureextremes 750 TCV Inputoffsetaveragedrift 0.1 µV/°C OS T =25°C (3) 75 95 A I Inputbiascurrent nA B Temperatureextremes 110 I Inputoffsetcurrent 0.9 5 nA OS Common-moderejection TA=25°C (3) 89 114 CMRR 0V≤V ≤1.7V dB ratio CM Temperatureextremes 84 2.7V≤V+≤10V,VCM= TA=25°C (3) 94.5 105 0.5 Temperatureextremes 92.5 PSRR Powersupplyrejectionratio dB 2.7V≤V+≤12V,VCM= TA=25°C (3) 94 100 0.5 Temperatureextremes 92 Inputcommon-mode CMRR≥80dB TA=25°C (3) 0 1.8 CMVR V voltagerange CMRR≥68dB Temperatureextremes 0 1.8 0.3V≤V ≤2.4V,R =2kΩtoV+/2 82 88 O L 0.4V≤V ≤2.3V,R =2kΩtoV+/2 78 O L AVOL Largesignalvoltagegain 01.03kVΩ≤toVVO+≤/22.4V,RL= TA=25°C (3) 86 98 dB 0.4V≤V ≤2.3V,R = 10kΩtoVO+/2 L Temperatureextremes 82 RL=2kΩtoV+/2,VIN= TA=25°C (3) 42 58 100mV Temperatureextremes 68 Outputswinghigh RL=10kΩtoV+/2,VIN= TA=25°C (3) 22 35 100mV Temperatureextremes 40 mVfrom V O RL=2kΩtoV+/2,VIN= TA=25°C (3) 38 48 rail 100mV Temperatureextremes 58 Outputswinglow R =10kΩtoV+/2,V = 18 30 L IN 100mV 35 Sourcingandsinkingoutput V =100mVtoV Sourcing 22 IOUT current =INV_+D/2IFF(4) O Sinking 25 mA T =25°C (3) 138 170 A I Supplycurrent µA S Temperatureextremes 220 Rising(10%to90%) 2.3 SR Slewrate A =1,V =1V V/µs V O PP Falling(90%to10%) 1.6 GBW Gainbandwidthproduct 10 MHz e Input-referredvoltagenoise f=1kHz 14 nV/√Hz n i Input-referredcurrentnoise f=1kHz 0.15 pA/√Hz n THD Totalharmonicdistortion f=1kHz,A =2,R =2kΩ 0.014% V L (1) Limitsare100%productiontestedat25°C.Limitsovertheoperatingtemperaturerangearespecifiedthroughcorrelationsusing StatisticalQualityControl(SQC)method. (2) Typicalvaluesrepresentthemostlikelyparametricnormasdeterminedatthetimeofcharacterization.Actualtypicalvaluesmayvary overtimeandalsodependontheapplicationandconfiguration.Thetypicalvaluesarenottestedandarenotspecifiedonshipped productionmaterial. (3) Positivecurrentcorrespondstocurrentflowingintothedevice. (4) Thepartisnotshort-circuitprotectedandisnotrecommendedforoperationwithlowresistiveloads.Typicalsourcingandsinkingoutput currentcurvesareprovidedinTypicalCharacteristicsandshouldbeconsultedbeforedesigningforheavyloads. Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com 6.6 DC Electrical Characteristics: 10 V Unlessotherwisespecified,alllimitsarespecifiedforT =25°C,V+=10V,V−=0V,V =V =V+/2,andR >1MΩ. A O CM L MIN TYP MAX PARAMETER TESTCONDITIONS (1) (2) (1) UNIT T =25°C (3) 5 500 A V Inputoffsetvoltage µV OS Temperatureextremes 750 TCV Inputoffsetaveragedrift 0.1 µV/°C OS T =25°C (3) 70 90 A IB Inputbiascurrent (3) Temperature nA 105 extremes I Inputoffsetcurrent 0.7 5 nA OS T =25°C (3) 94 120 A Common-moderejection CMRR ratio 0V≤VCM≤9V Temperature 90 dB extremes T =25°C (3) 94.5 105 2.7V≤V+≤10V,V =0.5 A CM V Temperature 92.5 Powersupplyrejection extremes PSRR dB ratio T =25°C (3) 94 100 2.7V≤V+≤12V,V =0.5 A CM V Temperature 92 extremes CMRR≥80dB T =25°C (3) 0 9.1 A Inputcommon-mode CMVR voltagerange CMRR≥76dB Temperature 0 9.1 V extremes 0.3V≤V ≤9.7V,R =2 T =25°C (3) 90 99 O L A kΩtoV+/2 0.4V≤VO≤9.6V,RL=2 Temperature 85 kΩtoV+/2 extremes A Largesignalvoltagegain dB VOL 0.3V≤V ≤9.7V,R =10 T =25°C (3) 97 104 O L A kΩtoV+/2 0.4V≤VO≤9.6V,RL=10 Temperature 92 kΩtoV+/2 extremes T =25°C (3) 68 95 R =2kΩtoV+/2,V =100 A L IN mV Temperature 125 extremes OutputSwingHigh T =25°C (3) 37 55 R =10kΩtoV+/2,V =100 A L IN mV Temperature 65 extremes mVfrom V O T =25°C (3) 65 90 rail R =2kΩtoV+/2,V =100 A L IN mV Temperature 110 extremes OutputSwingLow T =25°C (3) 32 42 R =10kΩtoV+/2,V =100 A L IN mV Temperature 52 extremes Sourcingandsinking V =100mV Sourcing 26 IOUT outputcurrent toINV_ODIF=FV+/2 (4) Sinking 112 mA T =25°C (3) 158 190 A I Supplycurrent µA S Temperatureextremes 240 Rising(10%to90%) 2.6 SR Slewrate A =1,V =2Vto8V V/µs V O PP Falling(90%to10%) 1.6 (1) Limitsare100%productiontestedat25°C.Limitsovertheoperatingtemperaturerangearespecifiedthroughcorrelationsusing StatisticalQualityControl(SQC)method. (2) Typicalvaluesrepresentthemostlikelyparametricnormasdeterminedatthetimeofcharacterization.Actualtypicalvaluesmayvary overtimeandalsodependontheapplicationandconfiguration.Thetypicalvaluesarenottestedandarenotspecifiedonshipped productionmaterial. (3) Positivecurrentcorrespondstocurrentflowingintothedevice. (4) Thepartisnotshort-circuitprotectedandisnotrecommendedforoperationwithlowresistiveloads.Typicalsourcingandsinkingoutput currentcurvesareprovidedinTypicalCharacteristicsandshouldbeconsultedbeforedesigningforheavyloads. 6 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 DC Electrical Characteristics: 10 V (continued) Unlessotherwisespecified,alllimitsarespecifiedforT =25°C,V+=10V,V−=0V,V =V =V+/2,andR >1MΩ. A O CM L MIN TYP MAX PARAMETER TESTCONDITIONS (1) (2) (1) UNIT GBW Gainbandwidthproduct 10 MHz Input-referredvoltage e f=1kHz 14 nV/√Hz n noise Input-referredcurrent i f=1kHz 0.15 pA/√Hz n noise THD Totalharmonicdistortion f=1kHz,A =2,R =2kΩ 0.002% V L Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com 6.7 Typical Characteristics Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 220 40 200 125°C 20 -40°C )A( TNERRP 111468000 25°C )V( EGATLP -200 25°C U O C Y 120 -40°C V T -40 125°C LP 100 ES PU FF -60 S 80 O 60 -80 40 -100 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure1.SupplyCurrentvsSupplyVoltage Figure2.OffsetVoltagevsSupplyVoltage 0 50 -40°C V+ = +5V -10 40 - V = 0V -20 30 )V( EP -30 )V( EP 20 -40°C GA -40 25°C GA 10 T T LOV -50 LOV 0 25°C T -60 T -10 E E SF -70 SF -20 FO 125°C FO -80 -30 + V = +2.7V -90 - -40 V = 0V 125°C -100 -50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 VCM (V) VCM (V) Figure3.OffsetVoltagevsV Figure4.OffsetVoltagevsV CM CM 50 50 40 VV+- == 0+V10V 40 VV+- == 0+V12V V) 30 -40°C V) 30 -40°C E (P 20 E (P 20 AG 10 AG 10 T T OL 0 25°C OL 0 V V 25°C T -10 T -10 E E FS -20 FS -20 F F O -30 O -30 -40 125°C -40 125°C -50 -50 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 VCM (V) VCM (V) Figure5.OffsetVoltagevsVCM Figure6.OffsetVoltagevsVCM 8 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 Typical Characteristics (continued) Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 20 20 18 UNITS TESTED = 12,000 V+ = +1.35V 18 UNITS TESTED = 12,000 V+ = +5V V- = -1.35V V- = -5V 16 16 VCM = 0V VCM = 0V )%( E 1124 TA = 25°C )%( E 1124 TA = 25°C G G A A T 10 T 10 N N E E C 8 C 8 R R EP 6 EP 6 4 4 2 2 0 0 -400-300-200-100 0 100 200 300 400 -400-300-200-100 0 100 200 300 400 OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) Figure7.OffsetVoltageDistribution Figure8.OffsetVoltageDistribution 160 130 + +PSRR V = 5V + 140 V- = 5V 110 V- = +5V 120 RL = 1 k: 80 V = -5V )Bd( RRMC 1680000 )Bd( RRSP 5700 -VVP+- S ==R -+R55VV -VP+S =R +R1.35V - 30 V = -1.35V 40 +PSRR 20 10 V+ = +1.35V - V = -1.35V 0 -10 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure9.CMRRvsFrequency Figure10.PSRRvsFrequency 1990050 125°C VV+- == 0+V2.7V 1990005 VV+- == 0+V10V 125°C 85 85 )An( ISAIB 778050 25°C I (nA)BIAS 787500 25°C 65 -40°C 65 60 60 -40°C 55 55 50 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 1 2 3 4 5 6 7 8 9 VCM (V) VCM (V) Figure11.InputBiasCurrentvsVCM Figure12.InputBiasCurrentvsVCM Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Typical Characteristics (continued) Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 180 180 180 180 150 150 150 150 PHASE PHASE 120 120 120 120 CL = 20 pF CL = 20 pF 90 90 90 90 )Bd( NIA 60 GAIN CL = C10L0 = p 5F0 pF 60 )(° ESAH )Bd( NIA 60 GAIN CL = C10L0 = p 5F0 pF 60 )(° ESAH G 30 30 P G 30 30 P -300 VV+- == -+11.3.355VV CL = 100 pF 0-30 -300 VV+- == -+55VV CL = 100 pF 0-30 RL = 2 k: CL = 50 pF RL = 2 k: CL = 50 pF -60 -60 -60 -60 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure13.Open-LoopGainandPhaseWithCapacitiveLoad Figure14.Open-LoopGainandPhaseWithCapacitiveLoad 180 180 180 180 150 150 150 150 + PHASE PHASE V = +5V 120 120 120 - 120 RL = 2 k: V = -5V 90 90 90 90 )Bd( NIAG 6300 GAIN RL = 10 k: 6300 °) E(SAHP )Bd( NIAG 6300 GAIN 6300 )(° ESAHP 0 + 0 0 0 -30 VVC-L === -+2660VV pF RL = 10 k:RL = 2 k: -30 -30 RCLL == 22 0k :pF VV+- == -+11.3.355VV -30 -60 -60 -60 -60 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure15.Open-LoopGainandPhaseWithResistiveLoad Figure16.Open-LoopGainandPhaseWithSupplyVoltage 1000 1000 + V = +5V - V = -5V Hz) 100 AV = +1 /V 100 n ( E :) 10 SION E NOISE VOLTAGE Z (OUT 1 GA 10 T L O V 0.1 1 0.01 0.10 1 10 100 1k 10k 100k 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure17.InputReferredNoiseVoltagevsFrequency Figure18.CloseLoopOutputImpedancevsFrequency 10 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 Typical Characteristics (continued) Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 0.1 0.1 + V = +5V - V = -5V VIN = 1 VPP RL = 2 k: 0.01 AV = +2 )% )% RL = 2 k: ( N+ 0.01 ( N+ DH RL = 10 k: DH T T V+- = +1.35V 0.001 RL = 10 k: V = -1.35V VIN = 1 VPP AV = +2 0.001 0.0001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure19.THD+NvsFrequency Figure20.THD+NvsFrequency 1 1 0.1 0.1 )% )% ( N+D RL = 100 k: ( N+D RL = 2 k: H H T 0.01 V+ = +1.35V RL = 2 k: T 0.01 V+ = +5V - - V = -1.35V V = -5V VIN = 1 kHz SINE WAVE VIN = 1 kHz SINE WAVE AV = +2 AV = +2 RL = 10 k: 0.001 0.001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 VOUT (V) VOUT (V) Figure21.THD+NvsV Figure22.THD+NvsV OUT OUT 35 120 VOUT = V+/2 VOUT = V+/2 30 100 25°C 25 )Am( IECRUOS 1250 125°C -40°C )Am( IKNIS 468000 -40°C 25°C 10 5 20 125°C 0 0 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure23.SourcingCurrentvsSupplyVoltage Figure24.SinkingCurrentvsSupplyVoltage Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Typical Characteristics (continued) Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 25 45 V+ = +1.35V V+ = +1.35V V- = -1.35V 25°C 40 V- = -1.35V 20 35 -40°C 30 )Am( ECR 15 -40°C (mA)NK 2205 25°C IUOS 10 125°C ISI 15 125°C 10 5 5 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 VOUT FROM RAIL (V) VOUT FROM RAIL (V) Figure25.SourcingCurrentvsV Figure26.SinkingCurrentvsV OUT OUT 35 1.5 + V = +5V 30 V- = -5V 25°C 1 25 0.5 )Am( EC 20 -40°C )Vm( T 0 VV+- == -+55VV RU 15 UO CL = 15 pF, AV = +1 IOS 125°C V -0.5 VIN = 2 VPP, 20 kHz 10 5 -1 0 -1.5 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 VOUT FROM RAIL (V) TIME (Ps) Figure27.SourcingCurrentvsV Figure28.Large-SignalTransient OUT 30 30 2205 VV+- == -+55VV CVILN = = 1 2205 mpFV,P APV, 2=0 +k1Hz 25 VV+- == -+55VV CVILN = = 1 250 p mFV, APVP ,= 2 0+ 1kHz 20 15 15 10 )Vm 5 )Vm 10 ( TU 0 ( TU 5 OV -5 VO 0 -10 -5 -15 -10 -20 -25 -15 -30 -20 0 20 40 60 70 80 0 20 40 60 80 100 TIME (Ps) TIME (Ps) Figure29.Small-SignalTransientResponse Figure30.Small-SignalTransientResponse 12 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 Typical Characteristics (continued) Unlessotherwisespecified,T =25°C,V+=10V,V−=0V,V =V /2. A CM S 100 100 RL = 2 k: RL = 2 k: 90 90 125°C )Vm 80 )Vm 80 ( L ( L 125°C IA 70 IA 70 R R M 25°C M 25°C OR 60 OR 60 F F T T -40°C UO 50 UO 50 V V -40°C 40 40 30 30 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure31.OutputSwingHighvsSupplyVoltage Figure32.OutputSwingLowvsSupplyvoltage 50 50 RL = 10 k: RL = 10 k: 45 45 125°C )Vm 40 25°C )Vm 40 ( L ( L 125°C IA 35 IA 35 R M R M 25°C OR 30 OR 30 -40°C F T -40°C F T UO 25 UO 25 V V 20 20 15 15 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure33.OutputSwingHighvsSupplyVoltage Figure34.OutputSwingLowandSupplyVoltage 3 RISING 2.5 )sP 2 /V ( E TAR 1.5 FALLING W EL 1 S 0.5 RL = 1 M: CL = 20 pF 0 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) Figure35.SlewRatevsSupplyVoltage Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com 7 Detailed Description 7.1 Overview The LMV641 is a wide-bandwidth, low-power operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. The device is unity-gain stable with a 10 MHz of gain bandwidth product. Operating on a typical supply current of 138 µA, it provides a PSRR of 105 dB, CMRR of 120 dB, V of 500 µV, input referred voltage OS noise of 14 nV/√Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode inputvoltagewhichincludesthenegativesupply. 7.2 Functional Block Diagram + V IN– – OUT IN+ + – V Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Low-VoltageandLow-PowerOperation The LMV641 has performance guaranteed at supply voltages of 2.7 V and 10 V. It is ensured to be operational at all supply voltages between 2.7 V and 12 V. The LMV641 draws a low supply current of 138 µA. The LMV641 providesthelow-voltageandlow-poweramplification,whichisessentialforportableapplications. 7.3.2 WideBandwidth Despite drawing the very low supply current of 138 µA, the LMV641 manages to provide a wide unity gain bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal forlowpowersignalprocessingapplicationssuchasportablemediaplayersandotheraccessories. 7.3.3 LowInputReferredNoise The LMV641 provides a flatband input referred voltage noise density of 14 nV/Hz, which is significantly better than the noise performance expected from a low-power op amp. This op amp also feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low-power applicationswhichrequiredecentnoiseperformance,suchasPDAsandportablesensors. 7.3.4 GroundSensingandRail-to-RailOutput The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing. The input common mode range of this part includesthenegativesupplyrailwhichallowsdirectsensingatgroundinasinglesupplyoperation. 7.3.5 SmallSize The small footprint of the packages for the LMV641 saves space on printed-circuit boards, and enables the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed closertothesignalsource,reducingnoisepickupandenhancingsignalintegrity. 14 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 7.4 Device Functional Modes 7.4.1 StabilityofOpAmpCircuits If the phase margin of the LMV641 is plotted with respect to the capacitive load (C ) at its output, and if C is L L increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher capacitive loads would have required either a drastic increase in supply current, or a large internal compensation capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher capacitiveloads,itwillhavetobeexternallycompensated. N AI G STABLE ROC – 20 dB/decade UNSTABLE ROC = 40 dB/decade 0 FREQUENCY (Hz) Figure36. GainvsFrequencyforanOpAmp An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (Figure 36). This increases the ROC to 40 dB/decade and causesinstability. In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which ensuresstability. 7.4.1.1 InTheLoopCompensation Figure 37 illustrates a compensation technique, known as in the loop compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, R , is used to isolate the amplifier output from the load capacitance, C , and a small capacitance, C , S L F isinsertedacrossthefeedbackresistortobypassC athigherfrequencies. L VIN + ROUT RS - CL RL CF RF RIN Figure37. IntheLoopCompensation Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Device Functional Modes (continued) ThevaluesforR andC aredecidedbyensuringthatthezeroattributedtoC liesatthesamefrequencyasthe S F F pole attributed to C . This ensures that the effect of the second pole on the transfer function is compensated for L bythepresenceofthezero,andthattheROCismaintainedat20dB/decade.ForthecircuitshowninFigure37 the values of R and C are given by Equation 1. Values of R and C required for maintaining stability for S F S F different values of C , as well as the phase margins obtained, are shown in Table 1. R and R are 10 kΩ, R is L F IN L 2kΩ,whileR is680Ω. OUT RS = ROUTRIN RF ¤§RF + 2RIN¤' CF = ¤' RF2 ¤§CLROUT (1) Table1.LoopCompensationStability C (nF) R (Ω) C (pF) PHASEMARGIN(°) L S F 0.5 680 10 17.4 1 680 20 12.4 1.5 680 30 10.1 The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any excessive ringing and help maintain the phase margin for stability. The values of the compensation network tabulatedaboveillustratethephasemargindegradationasafunctionofthecapacitiveload. Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth. TheclosedloopbandwidthofthecircuitisnowlimitedbyR andC . F F 7.4.1.2 CompensationbyExternalResistor In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in Figure 38. A resistor, R , is ISO placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The value of R to be used should be decided depending on the size of C and the level of performance desired. ISO L Values ranging from 5Ω to 50Ω are usually sufficient to ensure stability. A larger value of R will result in a ISO system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the circuit. RSO VOUT VIN CL Figure38. CompensationbyIsolationResistor 16 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The LMV641 is a low-power, low noise, wide-bandwidth operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. With 10 MHz of gain bandwidth, 14 nV/√Hz input referred noise, and supply current of 138 μA, the LMV641 is well suited for portable applications that require precision while amplifying at highgains. 8.2 Typical Applications 8.2.1 High-Gain,Low-PowerInvertingAmplifiers CF R1 R2 CC1 1 k: 100 k: + VIN - CC2 - + + V+ RB1 -VOUT RB2 R2 AV = - R1= -100 Copyright © 2016, Texas Instruments Incorporated Figure39. High-GainInvertingAmplifier 8.2.1.1 DesignRequirements The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while drivingloadsaslowas2kΩwithlessthan0.003%distortion. 8.2.1.2 DetailedDesignProcedure Figure 39 is an inverting amplifier, with a 100-kΩ feedback resistor, R , and a 1-kΩ input resistor, R , and 2 1 provides a gain of −100. With the LMV641, these circuits can provide gain of −100 with a −3-dB bandwidth of 120 kHz, for a quiescent current as low as 116 µA. Coupling capacitors C and C can be added to isolate the C1 C2 circuit from DC voltages, while R and R provide DC biasing. A feedback capacitor C can also be added to B1 B2 F improvecompensation. Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Typical Applications (continued) 8.2.1.3 ApplicationCurve e e d u plit m A al n g Si Vout (1V/div) Vin (10mV/div) 0 50 100 150 200 Time (us) C001 Figure40. HighGainInvertingAmplifierResults 8.2.2 AnisotropicMagnetoresistiveSensor BRIDGE TEMPCO COMPENSATION NETWORK RB R A STANDOFF DISTA NCE x + 58 0: + V 1% V+ RTH V x 24.5 k: 1% - U1 B - LMV641 LMV641 + U2 VOUT x + TO ADC or 24.5 k: METER 1% CIRCUITRY G = 23.2 x I(AC or DC) 568 1k%: BW-3 dB = 431 kHz HONEYWELL x FROM m As TO 20A HMC1051Z + 0.1 PF 9V or EQUIVALENT V ALKALINE BAT T E R Y CONDUCTOR TO BE xCURRENT MEASURED 20 k: 5 k: 20 k: OFFSET TRIM Copyright © 2016, Texas Instruments Incorporated Figure41. ABattery-OperatedSystemforContact-LessCurrentSensingUsinganAnisotropic MagnetoresistiveSensor 8.2.2.1 DesignRequirements The low operating current of the LMV641 makes it a good choice for battery-operated applications. Figure 41 shows two LMV641s in a portable application with a magnetic field sensor. The LMV641s condition the output from an anisotropic magnetoresistive (AMR) sensor. The sensor is arranged in the form of a Wheatstone bridge. This type of sensor can be used to accurately measure the current (either DC or AC) flowing in a wire by measuringthemagneticfluxdensity,B,emanatingfromthewire. 18 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 Typical Applications (continued) 8.2.2.2 DetailedDesignProcedure In this circuit, the use of a 9-V alkaline battery exploits the LMV641’s high voltage and low supply current for a low-power, portable-current-sensing application. The sensor converts an incident magnetic field (through the magnetic flux linkage) in the sensitive direction, to a balanced voltage output. The LMV641 can be used for moderate to high current sensing applications (from a few milliamps and up to 20 A) using a nearby external conductor providing the sensed magnetic field to the bridge. The circuit shows a Honeywell HMC1051Z used as a current sensor. Note that the circuit must be calibrated based on the final displacement of the sensed conductor relative to the measurement bridge. Typically, once the sensor has been oriented properly, with respect to the conductor to be measured, the conductor can be placed about one centimeter away from the bridgeandhavereasonablecapabilityofmeasuringfromtensofmilliamperestobeyond20amperes. In Figure 41, U1 is configured as a single differential input amplifier. Its input impedance is relatively low, however, and requires that the source impedance of the sensor be considered in the gain calculations. Also, the asymmetrical loading on the bridge will produce a small offset voltage that can be cancelled out with the offset trimcircuitshowninFigure41. Figure 42 shows a typical magnetoresistive Wheatstone bridge and the Thevenin equivalent of its resistive elements. As we shall see, the Thevenin equivalent model of the sensor is useful in calculating the gain needed inthedifferentialamplifier. VEXC R + ’R R - ’R SIG - SIG + R - ’R R + ’R (a) R/2 SIG + + - R/2 SIG - + WITH ’R << R, - THEN RTH |R/2 THUS, VEXC ± VSIG VTH± = 2 (b) Figure42. AnisotropicMagnetoresistiveWheatstoneBridgeSensor,(a), andTheveninEquivalentCircuit,(b) Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Typical Applications (continued) Using Thevenin’s Theorem, the bridge can be reduced to two voltage sources with series resistances. ΔR is normally very small in comparison to R, thus the Thevenin equivalent resistance, commonly called the source resistance, can be taken to be R. When a bias voltage is applied between V and ground, in the absence of a EXC magnetic field, all of the resistances are considered equal. The voltage at Sig+ and Sig− is half V , or 4.5 V, EXC and Sig+ - Sig− = 0. Bridges are designed such that, when immersed in a magnetic field, opposite resistances in the bridge change by ±ΔR with an amount proportional to the strength of the magnetic field. This causes the bridge's output differential voltage, to change from its half V value. Thus Sig+ - Sig− = Vsig ≠ 0. With four EXC activeelements,theoutputvoltageis: ’R V = V x SIG EXC R (2) Because ΔR is proportional to the field strength, B , the amount of output voltage from the sensor is a function of S sensorsensitivity,S.Thisexpressioncanrewrittenas,where V =V ·S·B SIG EXC S where • S=materialconstant(nominally1mV/V/gauss) • B =magneticfluxingauss (3) S A simplified schematic of a single op amp, differential amplifier is shown in Figure 43. The Thevenin equivalent circuitofthesensorcanbeusedtocalculatethegainofthisamplifier. R4 R2 SIG - - R4 VO = [(SIG + ) – (SIG -)] R2 SIG + + R1 R3 R1 = R2 = R3 = R4 Figure43. DifferentialInputAmplifier The Honeywell HMC1051Z AMR sensor has nominal 1-kΩ elements and a sensitivity of 1 mV/V/gauss and is being used with 9 V of excitation with a full scale magnetic field range of ±6 gauss. At full-scale, the resistors will haveΔR≈ 12Ω and108mVwillbeseenfromSig−toSig+(seeFigure44). 9V 1012: 988: SIG + = 4.554V 988: 1012: VSIG = 108 mV SIG - = 4.446V Figure44. SensorOutputwithNoLoad 20 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 Typical Applications (continued) Referring to the simplified diagram in Figure 43, and assuming that required full scale at the output of the amplifieris2.5V,againof23.2isneededforU1.ItisclearfromtheTheveninequivalentcircuitinFigure45 that a sensor Thevenin equivalent source resistance, R , of 500 Ω will be in series with both the inverting and THEV noninvertinginputsoftheLMV641.Therefore,therequiredgainis: R 4 A = = 23.2 VCL R + R THEV 2 (4) Choosing R = R = 24.5 kΩ, then R will be approximately 580 kΩ. The actual values chosen will depend on the 1 2 4 full-scale needs of the succeeding circuitry as well as bandwidth requirements. The values shown here provide a −3-dBbandwidthofapproximately431kHz,andarefoundasfollows. GAIN-BANDWIDTH PRODUCT 10 MHz BW-3 dB = = = 431 kHz AVCL 23.2 580 k: SENSOR 500: 24.5 k: 4.446V - LMV641 VO = 2.50V 4.554V + 500: 24.5 k: 580 k: Figure45. TheveninEquivalentShowingRequiredGain By choosing input resistor values for R and R that are four to ten times the bridge element resistance, the 1 2 bridge is minimally loaded and the offset errors induced by the op amp stages are minimized. These resistors shouldhave1%tolerance,orbetter,forthebestnoiserejectionandoffsetminimization. Referring once again to Figure 41, U2 is an additional gain stage with a thermistor element, R , in the feedback TH loop. It performs a temperature compensation function for the bridge so that it will have greater accuracy over a wide range of operational temperatures. With mangetoresistive sensors, temperature drift of the bridge sensitivity is negative and linear, and in the case of the sensor used here, is nominally −3000 PP/M. Thus the gain of U2 needs to increase proportionally with increasing temperature, suggesting a thermistor with a positive temperature coefficient. Selection of the temperature compensation resistor, R , depends on the additional gain required, on TH the thermistor chosen, and is dependent on the thermistor’s %/°C shift in resistance. For best op amp compatibility, the thermistor resistance should be greater than 1000 Ω. R should also be much less than R , TH A the feedback resistor. Because the temperature coefficient of the AMR bridge is largely linear, R also needs to TH behave in a linear fashion with temperature, thus R is placed in parallel with R , which acts to linearize the A TH thermistor. 8.2.2.2.1 GainErrorandBandwidthConsiderationifUsinganAnalogtoDigitalConverter The bandwidth available from Figure 41 is dependent on the system closed loop gain required and the maximum gain-errorallowedifdrivingananalogtodigitalconverter(ADC).Iftheoutputfromthesensorisintendedtodrive an ADC, the bandwidth will be considerably reduced from the closed-loop corner frequency. This is because the gain error of the pre-amplifier stage needs to be taken into account when calculating total error budget. Good practice dictates that the gain error of the amplifier be less than or equal to half LSB (preferably less in order to allow for other system errors that will eat up a portion of the available error budget) of the ADC. However, at the −3 dB corner frequency the gain error for any amplifier is 29.3%. In reality, the gain starts rolling off long before the −3dBcornerisreached.Forexample,iftheamplifierisdrivingan8-bitADC,theminimumgainerrorallowed for half LSB would be approximately 0.2%. To achieve this gain error with the op amp, the maximum frequency ofinterestcanbenohigherthan Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com Typical Applications (continued) 1 - 1 x f -3 dB § '2 1 ¤1 - ¤ ¤' 2n+1¤§ where • nisthebitresolutionoftheADC • f istheclosedloopcornerfrequency. (5) −3dB Given that the LMV641 has a GBW of 10 MHz, and is operating with a closed loop gain of 26.3, its closed loop bandwidthis380kHZ,therefore 1 MAX FREQ = - 1 = 0.062 x f-3 dB § '2 1 ¤1 - ¤ ¤' 2n+1 ¤§ = 0.062 x 380 kHz = 23.56 kHz (6) whichisthehighestfrequencythatcanbemeasuredwithrequiredaccuracy. 8.2.3 VoicebandFilter The majority of the energy of recognizable speech is within a band of frequencies between 200 Hz and 4 kHz. Therefore, it is beneficial to design circuits which transmit telephone signals that pass only certain frequencies and eliminate unwanted signals (noise) that could interfere with conversations and introduce error into control signals. The pass band of these circuits is defined as the ranges of frequencies that are passed. A telephone system voice frequency (VF) channel has a pass band of 0 Hz to 4 kHz. Specifically for human voices most of the energy content is found from 300 Hz to 3 kHz and any signal within this range is considered an in-band signal.Alternatively,anysignaloutsidethisrangebutwithintheVFchannelisconsideredanout-of-bandsignal. To properly recover a voice signal in applications such as cellular phones, cordless phones, and voice pagers, a low power bandpass filter that is matched to the human voice spectrum can be implemented using an LMV641 op amp. Figure 46 shows a multi-feedback, multi-pole filter (2nd order response) with a gain of −1. The lower 3 dB cutoff frequency which is set by the DC blocking capacitor C and resistor R is 60 Hz and the upper cutoff 1 1 frequencyis3.5kHz. Thetotalcurrentconsumptionisamere138µA.TheLV641isoperatingwithagainof −1,butthecircuitiseasily modified to add gain. The op amp is powered from a single supply, hence the need for offset (common-mode) adjustmentofitsoutput,whichissetto½ V viaitsnon-invertinginput. S Thisfilterisalsousefulinapplicationsforbatteryoperatedtalkingtoysandgames. R3 5.23 k: C3 2.2 nF VOICE IN C1 R1 R2 VS 0.5 PF 5.23 k: 12.1 k: - LMV641 VOUT C2 + 15 nF VS/2 Figure46. LowPowerVoiceIn-BandReceiveFilterforBattery-PoweredPortableUse 22 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 9 Power Supply Recommendations For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single supply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor between V+ andground,andonecapacitorbetweenV– andground. 10 Layout 10.1 Layout Guidelines To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8 µF or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1-µF ceramic capacitor should be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V− pins need to be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components withalow-inductivegroundconnection. 10.2 Layout Example Rf Cf V+ Cbyp GND OUTPUT GND INPUT Rin Figure47. LMV641LayoutExample Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LMV641

LMV641 SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 DevelopmentSupport Fordevelopmentsupportseethefollowing: • LMV641PSPICEModel • TINA-TISPICE-BasedAnalogSimulationProgram • DIPAdapterEvaluationModule • TIUniversalOperationalAmplifierEvaluationModule • TIFilterproSoftware 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • AbsoluteMaximumRatingsforSoldering(SNOA549) • AN-29ICOpAmpBeatsFETsonInputCurrent (SNOA624) • AN-31OpAmpCircuitCollection(SNLA140) • AN-71MicropowerCircuitsUsingtheLM4250ProgrammableOpAmp(SNOA652) • AN-127LM143MonolithicHighVoltageOperationalAmplifierApplications (SNVA516) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 24 SubmitDocumentationFeedback Copyright©2007–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMV641

LMV641 www.ti.com SNOSAW3D–SEPTEMBER2007–REVISEDAUGUST2016 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2007–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LMV641

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMV641MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LMV64 & no Sb/Br) 1MA LMV641MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LMV64 & no Sb/Br) 1MA LMV641MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LMV64 & no Sb/Br) 1MA LMV641MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS SN Level-1-260C-UNLIM AB9A & no Sb/Br) LMV641MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS SN Level-1-260C-UNLIM AB9A & no Sb/Br) LMV641MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS SN Level-1-260C-UNLIM AB9A & no Sb/Br) LMV641MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 A99 & no Sb/Br) LMV641MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 A99 & no Sb/Br) LMV641MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 A99 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LMV641MAE/NOPB SOIC D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LMV641MAE/NOPB SOIC D 8 250 210.0 185.0 35.0 LMV641MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV641MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV641MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMV641MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV641MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV641MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LMV641MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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