LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 LMK03000 Family Precision Clock Conditioner with Integrated VCO CheckforSamples:LMK03000,LMK03000C,LMK03000D,LMK03001,LMK03001C,LMK03001D,LMK03033,LMK03033C 1 FEATURES 12 • IntegratedVCOwithVeryLowPhaseNoise • PartiallyIntegratedLoopFilter Floor • DedicatedDividerandDelayBlocksonEach • IntegratedInteger-NPLLwithOutstanding ClockOutput NormalizedPhaseNoiseContributionof-224 • PinCompatibleFamilyofClockingDevices dBc/Hz • 3.15to3.45VOperation • VCODividerValuesof2to8(AllDivides) • Package:48PinWQFN(7.0x7.0x0.8mm) • ChannelDividerValuesof1,2to510(even • 200fsRMSClockGeneratorPerformance(10 divides) Hzto20MHz)withaCleanInputClock • LVDSandLVPECLClockOutputs 1.1 TARGET APPLICATIONS • DataConverterClocking VCO • Networking,SONET/SDH,DSLAM Device Outputs TuningRange RMSJitter (MHz) (fs) • WirelessInfrastructure LMK03000C 400 • Medical LMK03000 1185-1296 800 • TestandMeasurement LMK03000D 3LVDS 1200 • Military/Aerospace LMK03001C 5LVPECL 400 LMK03001 1470-1570 800 LMK03001D 1200 LMK03033C 4LVDS 500 1843-2160 LMK03033 4LVPECL 800 Recovered CLKout0 ‡GLUW\·(cid:3)FORFN(cid:3)RU(cid:3) Serializer/ clean clock LMK0300xx CLKout1 Deserializer OSCin Precision Clock CLKout4 Conditioner LMX2531 CLKout7 PLL+VCO FPGA Fout > 1 Gsps ADC DAC 0XOWLSOH(cid:3)‡FOHDQ·(cid:3)FORFNV(cid:3)DW(cid:3) different frequencies 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2006–2013,TexasInstrumentsIncorporated specifications per the terms of the Texas Instruments standard warranty. Production processingdoesnotnecessarilyincludetestingofallparameters.

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 1.2 DESCRIPTION The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integratedloopfilter,anduptoeightoutputsinvariousLVDSandLVPECLcombinations. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Dividertofeedthevariousclockdistributionblocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-relatedandphase-adjustedcopiesofthereferencetobedistributedtoeightsystemcomponents. The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devicesinthesamefamily. 1 FEATURES ............................................... 1 6.10 POWERONRESET ............................... 17 ........................... ........................... 1.1 TARGETAPPLICATIONS 1 6.11 DIGITALLOCKDETECT 18 1.2 DESCRIPTION ...................................... 2 7 GeneralProgrammingInformation ................ 19 2 DeviceInformation...................................... 3 7.1 RECOMMENDEDPROGRAMMINGSEQUENCE. 19 ........................... ............................... 2.1 FunctionalBlockDiagram 3 7.2 REGISTERR0toR7 22 ................................. ..................................... 2.2 ConnectionDiagram 4 7.3 REGISTERR8 24 3 ElectricalSpecifications ............................... 6 7.4 REGISTERR9...................................... 24 .......................... .................................... 3.1 AbsoluteMaximumRatings 6 7.5 REGISTERR11 24 ............... .................................... 3.2 RecommendedOperatingConditions 6 7.6 REGISTERR13 24 ....................... .................................... 3.3 PackageThermalResistance 6 7.7 REGISTERR14 25 ............................ .................................... 3.4 ElectricalCharacteristics 7 7.8 REGISTERR15 27 3.5 SerialDataTimingDiagram ........................ 11 8 ApplicationInformation .............................. 28 4 MeasurementDefinitions ............................ 12 8.1 SYSTEMLEVELDIAGRAM........................ 28 .... ........................................... 4.1 ChargePumpCurrentSpecificationDefinitions 12 8.2 BIASPIN 28 5 TypicalPerformanceCharacteristics ............. 13 8.3 LDOBYPASS ...................................... 28 6 FunctionalDescription ............................... 15 8.4 LOOPFILTER ...................................... 29 6.1 BIASPIN ........................................... 15 8.5 CURRENTCONSUMPTION/POWER ................... ...................................... DISSIPATIONCALCULATIONS 30 6.2 LDOBYPASS 15 ........................ .... 8.6 THERMALMANAGEMENT 31 6.3 OSCILLATORINPUTPORT(OSCin,OSCin*) 15 ......... 8.7 TERMINATIONANDUSEOFCLOCKOUTPUTS 6.4 LOWNOISE,FULLYINTEGRATEDVCO 15 ......................................... (DRIVERS) 32 ................................... 6.5 CLKoutDELAYS 15 ...................................... 8.8 OSCinINPUT 36 ......................... 6.6 LVDS/LVPECLOUTPUTS 16 8.9 MORETHANEIGHTOUTPUTSWITHAN 6.7 GLOBALCLOCKOUTPUTSYNCHRONIZATION 16 LMK03000FAMILYDEVICE ....................... 37 6.8 CLKoutOUTPUTSTATES ......................... 17 RevisionHistory ............................................ 38 6.9 GLOBALOUTPUTENABLEANDLOCKDETECT 17 2 Contents Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 2 Device Information 2.1 Functional Block Diagram ut o Partially P C Integrated Internal Loop Filter VCO OSCin R Divider OSCin* Phase Fout Detector N Divider VCO Distribution Divider Path CLKout0 CLKout4 Mux Divider Divider Mux CLKout0* CLKout4* Delay Delay CLKout1 CLKout5 Mux Divider Divider Mux CLKout1* CLKout5* Delay Delay CLKout2 CLKout6 Mux Divider Divider Mux CLKout2* CLKout6* Delay Delay CLKout3 CLKout7 Mux Divider Divider Mux CLKout3* CLKout7* Delay Delay Low Clock Buffers High Clock Buffers CLK GOE LD DATA PWire Control Device Port Registers SYNC* Control LE Copyright©2006–2013,TexasInstrumentsIncorporated DeviceInformation 3 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 2.2 Connection Diagram 7* 7 6* 6 5* 5 4* 4 CLKout CLKout Vcc14 CLKout CLKout Vcc13 CLKout CLKout Vcc12 CLKout CLKout Vcc11 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 Bias Fout 2 35 NC Vcc1 3 34 NC CLKuWire 4 33 Vcc10 DATAuWire 5 32 CPout LEuWire 6 Top Down View 31 Vcc9 NC 7 30 Vcc8 Vcc2 8 29 OSCin* LDObyp1 9 28 OSCin LDObyp2 10 27 SYNC* DAP GOE 11 26 Vcc7 LD 12 25 GND 13 14 15 16 17 18 19 20 21 22 23 24 Vcc3 CLKout0 CLKout0* Vcc4 CLKout1 CLKout1* Vcc5 CLKout2 CLKout2* Vcc6 CLKout3 CLKout3* Figure2-1. 48-PinWQFNPackage 4 DeviceInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 Table2-1.PINDESCRIPTIONS Pin# PinName I/O Description 1,25 GND - Ground 2 Fout O InternalVCOFrequencyOutput 3,8,13,16,19,22, Vcc1,Vcc2,Vcc3,Vcc4,Vcc5,Vcc6,Vcc7,Vcc8,Vcc9,Vcc10, 26,30,31,33,37, - PowerSupply Vcc11,Vcc12,Vcc13,Vcc14 40,43,46 4 CLKuWire I MICROWIREClockInput 5 DATAuWire I MICROWIREDataInput 6 LEuWire I MICROWIRELatchEnableInput 7,34,35 NC - NoConnectiontothesepins 9,10 LDObyp1,LDObyp2 - LDOBypass 11 GOE I GlobalOutputEnable 12 LD O LockDetectandTestOutput 14,15 CLKout0,CLKout0* O LVDSClockOutput0 17,18 CLKout1,CLKout1* O LVDSClockOutput1 20,21 CLKout2,CLKout2* O LVDSClockOutput2 ClockOutput3 23,24 CLKout3,CLKout3* O (LVDSforLMK03033C/LMK03033 LVPECLforallotherparts) 27 SYNC* I GlobalClockOutputSynchronization OscillatorClockInput;ShouldbeAC 28,29 OSCin,OSCin* I coupled 32 CPout O ChargePumpOutput 36 Bias I BiasBypass 38,39 CLKout4,CLKout4* O LVPECLClockOutput4 41,42 CLKout5,CLKout5* O LVPECLClockOutput5 44,45 CLKout6,CLKout6* O LVPECLClockOutput6 47,48 CLKout7,CLKout7* O LVPECLClockOutput7 DAP DAP - DieAttachPadisGround Copyright©2006–2013,TexasInstrumentsIncorporated DeviceInformation 5 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 3 Electrical Specifications 3.1 Absolute Maximum Ratings(1)(2)(3) Parameter Symbol Ratings Units PowerSupplyVoltage V -0.3to3.6 V CC InputVoltage V -0.3to(V +0.3) V IN CC StorageTemperatureRange T -65to150 °C STG LeadTemperature(solder4s) T +260 °C L JunctionTemperature T 125 °C J (1) "AbsoluteMaximumRatings"indicatelimitsbeyondwhichdamagetothedevicemayoccur,includinginoperabilityanddegradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximumRatingsor otherconditionsbeyondthoseindicatedintheRecommendedOperatingConditionsisnotimplied.TheRecommendedOperating Conditionsindicateconditionsatwhichthedeviceisfunctionalandthedeviceshouldnotbeoperatedbeyondsuchconditions. (2) ThisdeviceisahighperformanceintegratedcircuitwithESDhandlingprecautions.HandlingofthisdeviceshouldonlybedoneatESD protectedworkstations.ThedeviceisratedtoaHBM-ESDof>2kV,aMM-ESDof>200V,andaCDM-ESDof>1.2kV. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. 3.2 Recommended Operating Conditions Parameter Symbol Min Typ Max Units AmbientTemperature T -40 25 85 °C A PowerSupplyVoltage V 3.15 3.3 3.45 V CC 3.3 Package Thermal Resistance Package θ θ JA J-PAD(ThermalPad) 48-LeadWQFN (1) 27.4°C/W 5.8°C/W (1) Specificationassumes16thermalviasconnectthedieattachpadtotheembeddedcopperplaneonthe4-layerJEDECboard.These viasplayakeyroleinimprovingthethermalperformanceoftheWQFN.Itisrecommendedthatthemaximumnumberofviasbeusedin theboardlayout. 6 ElectricalSpecifications Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 3.4 Electrical Characteristics (1) (3.15V≤Vcc≤3.45V,-40°C≤T ≤85°C,DifferentialInputs/Outputs;Vboost=0;exceptasspecified.Typicalvalues A representmostlikelyparametricnormsatVcc=3.3V,T =25°C,andattheRecommendedOperationConditionsatthe A timeofproductcharacterizationandarenotensured). Symbol Parameter Conditions Min Typ Max Units CurrentConsumption Entiredevice;oneLVDSandone LVPECLclockenabled;nodivide;no 161.8 I PowerSupplyCurrent (2) delay. mA CC Entiredevice;AllOutputsOff(no 86 emitterresistorsplaced) I PD PowerDownCurrent POWERDOWN=1 1 mA CC ReferenceOscillator ReferenceOscillatorInputFrequency f square 1 200 MHz OSCin RangeforSquareWave ACcoupled;Differential(V ) OD SquareWaveInputVoltageforOSCin V square 0.2 1.6 Vpp OSCin andOSCin* PLL f PhaseDetectorFrequency 40 MHz PD V =Vcc/2,PLL_CP_GAIN=1x 100 CPout V =Vcc/2,PLL_CP_GAIN=4x 400 CPout I CPout ChargePumpSourceCurrent µA SRCE V =Vcc/2,PLL_CP_GAIN=16x 1600 CPout V =Vcc/2,PLL_CP_GAIN=32x 3200 CPout V =Vcc/2,PLL_CP_GAIN=1x -100 CPout V =Vcc/2,PLL_CP_GAIN=4x -400 CPout I CPout ChargePumpSinkCurrent µA SINK V =Vcc/2,PLL_CP_GAIN=16x -1600 CPout V =Vcc/2,PLL_CP_GAIN=32x -3200 CPout I TRI ChargePumpTRI-STATECurrent 0.5V<V <Vcc-0.5V 2 10 nA CPout CPout MagnitudeofChargePump V =Vcc/2 I %MIS CPout 3 % CPout Sinkvs.SourceCurrentMismatch T =25°C A MagnitudeofChargePump 0.5V<V <Vcc-0.5V I VTUNE Currentvs.ChargePumpVoltage CPout 4 % CPout T =25°C Variation A MagnitudeofChargePumpCurrentvs. I TEMP 4 % CPout TemperatureVariation PLL1/fNoiseat10kHzOffset (3) PLL_CP_GAIN=1x -117 PN10kHz dBc/Hz Normalizedto1GHzOutputFrequency PLL_CP_GAIN=32x -122 NormalizedPhaseNoiseContribution PLL_CP_GAIN=1x -219 PN1Hz (4) dBc/Hz PLL_CP_GAIN=32x -224 (1) TheElectricalCharacteristicstablelistsensuredspecificationsunderthelistedRecommendedOperatingConditionsexceptas otherwisemodifiedorspecifiedbytheElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) SeeSection8.5formorecurrentconsumption/powerdissipationcalculationinformation. (3) AspecificationinmodelingPLLin-bandphasenoiseisthe1/fflickernoise,L (f),whichisdominantclosetothecarrier.Flicker PLL_flicker noisehasa10dB/decadeslope.PN10kHzisnormalizedtoa10kHzoffsetanda1GHzcarrierfrequency.PN10kHz=L (10 PLL_flicker kHz)-20log(Fout/1GHz),whereL (f)isthesinglesidebandphasenoiseofonlytheflickernoise'scontributiontototalnoise, PLL_flicker L(f).TomeasureL (f)itisimportanttobeonthe10dB/decadeslopeclosetothecarrier.Ahighcomparefrequencyandaclean PLL_flicker crystalareimportanttoisolatingthisnoisesourcefromthetotalphasenoise,L(f).L (f)canbemaskedbythereference PLL_flicker oscillatorperformanceifalowpowerornoisysourceisused.ThetotalPLLinbandphasenoiseperformanceisthesumofL (f) PLL_flicker andL (f). PLL_flat (4) AspecificationinmodelingPLLin-bandphasenoiseistheNormalizedPhaseNoiseContribution,L (f),ofthePLLandisdefined PLL_flat asPN1Hz=L (f)–20log(N)–10log(f ).L (f)isthesinglesidebandphasenoisemeasuredatanoffsetfrequency,f,ina PLL_flat COMP PLL_flat 1HzBandwidthandf isthephasedetectorfrequencyofthesynthesizer.L (f)contributestothetotalnoise,L(f).Tomeasure COMP PLL_flat L (f)theoffsetfrequency,f,mustbechosensufficientlysmallerthentheloopbandwidthofthePLL,andyetlargeenoughtoavoid PLL_flat asubstantialnoisecontributionfromthereferenceandflickernoise.L (f)canbemaskedbythereferenceoscillatorperformanceif PLL_flat alowpowerornoisysourceisused. Copyright©2006–2013,TexasInstrumentsIncorporated ElectricalSpecifications 7 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com ElectricalCharacteristics(1)(continued) (3.15V≤Vcc≤3.45V,-40°C≤T ≤85°C,DifferentialInputs/Outputs;Vboost=0;exceptasspecified.Typicalvalues A representmostlikelyparametricnormsatVcc=3.3V,T =25°C,andattheRecommendedOperationConditionsatthe A timeofproductcharacterizationandarenotensured). Symbol Parameter Conditions Min Typ Max Units VCO LMK03000C/LMK03000/LMK03000D 1185 1296 f VCOTuningRange LMK03001C/LMK03001/LMK03001D 1470 1570 MHz Fout LMK03033C/LMK03033 1843 2160 AfterprogrammingR15forlock,no AllowableTemperatureDriftfor changestooutputconfigurationare |ΔT | 125 °C CL ContinuousLock permittedtoensurecontinuouslock. (1) LMK03000C/LMK03000/LMK03000D; 3.3 T =25°C A OutputPowertoa50Ωloaddrivenby pFout Fout (2) LMK03001C/LMK03001/LMK03001D; 2.7 dBm T =25°C A LMK03033C/LMK03033;T =25°C -5to0 A LMK03000C/LMK03000/LMK03000D 7to9 K FineTuningSensitivity (3) LMK03001C/LMK03001/LMK03001D 9to11 MHz/V VCO 14to LMK03033C/LMK03033 26 LMK03000C/LMK03001C 400 LMK03000/LMK03001 800 FoutRMSPeriodJitter J Fout LMK03000D/LMK03001D 1200 fs RMS (12kHzto20MHzbandwidth) LMK03033C 500 LMK03033 800 (1) AllowableTemperatureDriftforContinuousLockishowfarthetemperaturecandriftineitherdirectionandstayinlockfromtheambient temperatureandprogrammedstateatwhichthedevicewaswhenregisterR15wasprogrammed.TheactionofprogrammingtheR15 register,eventothesamevalue,activatesafrequencycalibrationroutine.Thisimpliesthatthedevicewillworkovertheentire frequencyrange,butifthetemperaturedriftsmorethanthemaximumallowabledriftforcontinuouslock,thenitwillbenecessaryto reprogramtheR15registertoensurethatthedevicestaysinlock.Regardlessofwhattemperaturethedevicewasinitiallyprogrammed at,theambienttemperaturecanneverdriftoutsidetherangeof-40°C≤T ≤85°Cwithoutviolatingspecifications.Forthis A specificationtobevalid,theprogrammedstateofthedevicemustnotchangeafterR15isprogrammed. (2) Outputpowervariesasafunctionoffrequency.Whenarangeisshown,thehigheroutputpowerappliestothelowerfrequencyandthe loweroutputpowerappliestothehigherfrequency. (3) Thelowersensitivityindicatesthetypicalsensitivityatthelowerendofthetuningrange,thehighersensitivityatthehigherendofthe tuningrange 8 ElectricalSpecifications Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 ElectricalCharacteristics(1)(continued) (3.15V≤Vcc≤3.45V,-40°C≤T ≤85°C,DifferentialInputs/Outputs;Vboost=0;exceptasspecified.Typicalvalues A representmostlikelyparametricnormsatVcc=3.3V,T =25°C,andattheRecommendedOperationConditionsatthe A timeofproductcharacterizationandarenotensured). Symbol Parameter Conditions Min Typ Max Units VCO(Continued) 10kHzOffset -91.4 LMK03000C 100kHzOffset -116.8 fFout=1296MHz (1) 1MHzOffset -137.8 10MHzOffset -156.9 10kHzOffset -93.5 LMK03000C 100kHzOffset -118.5 fFout=1185MHz (1) 1MHzOffset -139.4 10MHzOffset -158.4 10kHzOffset -89.6 LMK03001C 100kHzOffset -115.2 fFout=1570MHz (1) 1MHzOffset -136.5 10MHzOffset -156.0 L(f) FoutSingleSideBandPhaseNoise dBc/Hz Fout 10kHzOffset -91.6 LMK03001C 100kHzOffset -116.0 fFout=1470MHz (1) 1MHzOffset -137.9 10MHzOffset -156.2 10kHzOffset -83 LMK03033C 100kHzOffset -109 fFout=2160MHz (1) 1MHzOffset -131 10MHzOffset -152 10kHzOffset -86 LMK03033C 100kHzOffset -111 fFout=1843MHz (1) 1MHzOffset -134 10MHzOffset -153 (1) VCOphasenoiseismeasuredassumingtheVCOisthedominantnoisesourceduetoa75Hzloopbandwidth.Overfrequency,the phasenoisetypicallyvariesby1to2dB,withtheworstcaseperformancetypicallyoccurringatthehighestfrequency.Over temperature,thephasenoisetypicallyvariesby1to2dB,assumingthedeviceisnotreprogrammed.ReprogrammingR15willrunthe frequencycalibrationroutineforoptimumphasenoise. Copyright©2006–2013,TexasInstrumentsIncorporated ElectricalSpecifications 9 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com ElectricalCharacteristics(1)(continued) (3.15V≤Vcc≤3.45V,-40°C≤T ≤85°C,DifferentialInputs/Outputs;Vboost=0;exceptasspecified.Typicalvalues A representmostlikelyparametricnormsatVcc=3.3V,T =25°C,andattheRecommendedOperationConditionsatthe A timeofproductcharacterizationandarenotensured). Symbol Parameter Conditions Min Typ Max Units ClockDistributionSection (1) (2)-LVDSClockOutputs CLKoutX_MUX =Bypass(no 20 RL=100Ω divideordelay) DistributionPath= Jitter AdditiveRMSJitter (1) 765MHz CLKoutX_MUX fs ADD Bandwidth= =Divided(no 12kHzto20MHz delay) 75 CLKoutX_DIV =4 Equalloadingandidenticalclock t CLKoutXtoCLKoutY (3) configuration -30 ±4 30 ps SKEW R =100Ω L V DifferentialOutputVoltage R =100Ω 250 350 450 mV OD L ChangeinmagnitudeofV for ΔV OD R =100Ω -50 50 mV OD complementaryoutputstates L V OutputOffsetVoltage R =100Ω 1.070 1.25 1.370 V OS L ChangeinmagnitudeofV for ΔV OS R =100Ω -35 35 mV OS complementaryoutputstates L I ClockOutputShortCircuitCurrent SA Single-endedoutputsshortedtoGND -24 24 mA I single-ended SB ClockOutputShortCircuitCurrent I Complementaryoutputstiedtogether -12 12 mA SAB differential ClockDistributionSection (1) (2)-LVPECLClockOutputs CLKoutX_MUX =Bypass(no 20 RL=100Ω divideordelay) DistributionPath= Jitter AdditiveRMSJitter (1) 765MHz CLKoutX_MUX fs ADD Bandwidth= =Divided(no 12kHzto20MHz delay) 75 CLKoutX_DIV =4 Equalloadingandidenticalclock t CLKoutXtoCLKoutY (3) configuration -30 ±3 30 ps SKEW Termination=50ΩtoVcc-2V Vcc- V OutputHighVoltage V OH 0.98 Termination=50ΩtoVcc-2V Vcc- V OutputLowVoltage V OL 1.8 V DifferentialOutputVoltage R =100Ω 660 810 965 mV OD L DigitalLVTTLInterfaces (4) V High-LevelInputVoltage 2.0 Vcc V IH V Low-LevelInputVoltage 0.8 V IL I High-LevelInputCurrent V =Vcc -5.0 5.0 µA IH IH I Low-LevelInputCurrent V =0 -40.0 5.0 µA IL IL Vcc- V High-LevelOutputVoltage I =+500µA V OH OH 0.4 V Low-LevelOutputVoltage I =-500µA 0.4 V OL OL (1) TheClockDistributionSectionincludesallpartsofthedeviceexceptthePLLandVCOsections.TypicalAdditiveJitterspecifications applytotheclockdistributionsectiononlyandthisaddsinanRMSfashiontotheshapedjitterofthePLLandtheVCO. (2) ForCLKoutfrequenciesabove1GHz,thedelayshouldbelimitedtoonehalfofaperiod.For1GHzandbelow,themaximumdelaycan beused. (3) Specificationisensuredbycharacterizationandisnottestedinproduction. (4) AppliestoGOE,LD,andSYNC*. 10 ElectricalSpecifications Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 ElectricalCharacteristics(1)(continued) (3.15V≤Vcc≤3.45V,-40°C≤T ≤85°C,DifferentialInputs/Outputs;Vboost=0;exceptasspecified.Typicalvalues A representmostlikelyparametricnormsatVcc=3.3V,T =25°C,andattheRecommendedOperationConditionsatthe A timeofproductcharacterizationandarenotensured). Symbol Parameter Conditions Min Typ Max Units DigitalMICROWIREInterfaces (1) V High-LevelInputVoltage 1.6 Vcc V IH V Low-LevelInputVoltage 0.4 V IL I High-LevelInputCurrent V =Vcc -5.0 5.0 µA IH IH I Low-LevelInputCurrent V =0 -5.0 5.0 µA IL IL MICROWIRETiming t DatatoClockSetUpTime SeeDataInputTiming 25 ns CS t DatatoClockHoldTime SeeDataInputTiming 8 ns CH t ClockPulseWidthHigh SeeDataInputTiming 25 ns CWH t ClockPulseWidthLow SeeDataInputTiming 25 ns CWL t ClocktoEnableSetUpTime SeeDataInputTiming 25 ns ES t EnabletoClockSetUpTime SeeDataInputTiming 25 ns CES t EnablePulseWidthHigh SeeDataInputTiming 25 ns EWH (1) AppliestoCLKuWire,DATAuWire,andLEuWire. 3.5 Serial Data Timing Diagram MSB LSB DATAuWire D27 D26 D25 D24 D23 D0 A3 A2 A1 A0 CLKuWire tCES tCS tCH tCWH tCWL tES LEuWire tEWH Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. It is recommended that the slew rate ofCLKuWire,DATAuWire,andLEuWireshouldbeatleast30V/µs. Copyright©2006–2013,TexasInstrumentsIncorporated ElectricalSpecifications 11 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 4 Measurement Definitions 4.1 Charge Pump Current Specification Definitions I1=ChargePumpSinkCurrentatV =Vcc-ΔV CPout I2=ChargePumpSinkCurrentatV =Vcc/2 CPout I3=ChargePumpSinkCurrentatV =ΔV CPout I4=ChargePumpSourceCurrentatV =Vcc-ΔV CPout I5=ChargePumpSourceCurrentatV =Vcc/2 CPout I6=ChargePumpSourceCurrentatV =ΔV CPout ΔV=Voltageoffsetfromthepositiveandnegativesupplyrails.Definedtobe0.5Vforthisdevice. 4.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage 4.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch 4.1.3 Charge Pump Output Current Magnitude Variation vs. Temperature 12 MeasurementDefinitions Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 5 Typical Performance Characteristics NOTE Theseplots show performance at frequenciesbeyondwhat thepart is ensured to operate at to give the user an idea of the capabilities of the part, but they do not imply any sort of ensured specification. 1000 1000 900 900 Vboost = 1 800 800 700 700 Vboost = 0 V) 600 V) 600 m Vboost = 1 m (D 500 (D 500 O O V 400 V 400 300 300 Vboost = 0 200 200 100 100 0 0 0 200 400 600 800 100012001400160018002000 0 200 400 600 800 100012001400160018002000 FREQUENCY (MHz) FREQUENCY (MHz) Figure5-1.LVDSDifferentialOutputVoltage(V ) Figure5-2.LVPECLDifferentialOutputVoltage(V ) OD OD -146 -146 -148 -148 Vboost = 0 Vboost = 0 z) -150 z) -150 H H c/ c/ B B d -152 d -152 or ( or ( o o Fl -154 Fl -154 e e s s oi oi N -156 N -156 Vboost = 1 -158 -158 Vboost = 1 -160 -160 0 200 400 600 800 100012001400160018002000 0 200 400 600 800 100012001400160018002000 FREQUENCY (MHz) FREQUENCY (MHz) Toestimatethisnoise,onlytheoutputfrequencyisrequired.Divide Toestimatethisnoise,onlytheoutputfrequencyisrequired.Divide valueandinputfrequencyarenotintegral. valueandinputfrequencyarenotintegral. Figure5-3.LVDSOutputBufferNoiseFloor Figure5-4.LVPECLOutputBufferNoiseFloor Copyright©2006–2013,TexasInstrumentsIncorporated TypicalPerformanceCharacteristics 13 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com -135 Delay = 2250 ps Delay=1800 ps -140 Delay = 900 ps z) H -145 c/ B d R ( -150 O O L -155 F E S Delay = 450 ps OI -160 N Delay = 0 ps -165 -170 10 100 1000 FREQUENCY (MHz) Toestimatethisnoise,onlytheoutputfrequencyisrequired.Dividevalueandinputfrequencyarenotintegral. Thenoiseofthedelayblockisindependentofoutputtypeandonlyappliesifthedelayisenabled.Thenoisefloorduetothedistribution sectionaccountingforthedelaynisecanbecalculatedas:TotalOutputNoise=10×log(10OutputBufferNoise/10+10DelayNoiseFloor/10). Figure5-5.DelayNoiseFloor(AddstoOutputNoiseFloor) 14 TypicalPerformanceCharacteristics Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 6 Functional Description The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integratedloopfilter,threeLVDS,andfiveLVPECLclockoutputdistributionblocks. The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop filterbandwidths. The LMK03000 family has multiple options for VCO frequencies. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through an VCO Divider to feed the various clock distributionblocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-relatedandphase-adjustedcopiesofthereferencetobedistributedtoeightsystemcomponents. The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devicesinthesamefamily. 6.1 BIAS PIN Toproperlyusethedevice,bypassBias(pin36)withalowleakage1µFcapacitorconnectedtoVcc.This isimportantforlownoiseperformance. 6.2 LDO BYPASS To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1µFcapacitor. 6.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) ThepurposeofOSCinistoprovidethePLLwithareferencesignal.DuetoaninternalDCbiastheOSCin port should be AC coupled, refer to the Section 8.1 in the Section 8 section. The OSCin port may be drivensingle-endedlybyACgroundingOSCin*witha0.1µFcapacitor. 6.4 LOW NOISE, FULLY INTEGRATED VCO The LMK03000 family of devices contain a fully integrated VCO. In order for proper operation the VCO uses a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the R15 register is programmed. Once R15 is programmed the temperature may not drift more than the maximumallowabledriftforcontinuouslock,ΔT ,orelsetheVCOisnotensuredtostayinlock. CL For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 isprogrammed. 6.5 CLKout DELAYS Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) supporta150psstepsizeandrangefrom0to2250psoftotaldelay. Copyright©2006–2013,TexasInstrumentsIncorporated FunctionalDescription 15 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 6.6 LVDS/LVPECL OUTPUTS Bydefaultalltheclockoutputsaredisableduntilprogrammed. Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to0. ThedutycycleoftheLVDSandLVPECLclockoutputsareshowninthetablebelow. VCO_DIV CLKoutX_MUX DutyCycle Any Divided,orDividedandDelayed 50% 2,4,6,8 Any 50% 3 Bypassed,orDelayed 33% 5 Bypassed,orDelayed 40% 7 Bypassed,orDelayed 43% 6.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. The bypassed outputs will continue to operate normally. Shortly after the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a high state simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the bypassedstatearenotaffectedbySYNC*andarealwayssynchronizedwiththedividedoutputs. The SYNC* pin must be held low for greater than one clock cycle of the output of the VCO Divider, also knownasthedistributionpath.Oncethisloweventhasbeenregistered,theoutputswillnotreflectthelow state for four more cycles. This means that the outputs will be low on the fifth rising edge of the distribution path. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution path clock cycles have passed, which is the fifth rising edge of the distribution path. See the timing diagram in Figure 6-1 for further detail. The clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4. To synchronize the outputs, after the low SYNC* event has been registered, it is notrequiredtowaitfortheoutputstogolowbeforeSYNC*issethigh. Distribution Path SYNC* CLKout0 CLKout1 CLKout2 Figure6-1.SYNC*TimingDiagram The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used,clockoutputsynchronizationisnotensured. 16 FunctionalDescription Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 6.8 CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Globalissetto0. CLKoutX_ENbit EN_CLKout_Globalbit GOEpin CLKoutXOutputState 1 1 Low Low Don'tcare 0 Don'tcare Off 0 Don'tcare Don'tcare Off 1 1 High/NoConnect Enabled When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an LVPECLoutputisintheOffstate,theoutputsareatavoltageofapproximately1volt. 6.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pin provides an internal pull-up resistor as shown on the functional block diagram. If it is not terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN)andtheEN_CLKout_Globalbit. By programming the PLL_MUX register to Digital Lock Detect Active High, the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not locked. 6.10 POWER ON RESET When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets all registers to their default values, see the Section 7 section for more information on default register values.VoltageshouldbeappliedtoallVccpinssimultaneously. Copyright©2006–2013,TexasInstrumentsIncorporated FunctionalDescription 17 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 6.11 DIGITAL LOCK DETECT The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ. To indicate an out of lock state, the phase error must become greater δ. The values of ε and δ are shown inthetablebelow: ε δ 10ns 20ns To utilize the digital lock detect feature, PLL_MUX must be programmed for "Digital Lock Detect (Active High)" or "Digital Lock Detect (Active Low)." When one of these modes is programmed the state of the LD pinwillbesethighorlowasdeterminedbythedescriptionaboveasshowninFigure6-2. When the device is in power down mode and the LD pin is programmed for a digital lock detect function, LD will show a "no lock detected" condition which is low or high given active high or active low circuitry respectively. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to dividethecomparisonfrequencypresentedtothelockdetectcircuitby4. NO NO YES YES Lock Detected = START Phase Error <g Phase Error <g False NO NO NO YES YES YES YES Lock Detected = Phase Error <g Phase Error <g Phase Error <g Phase Error >* True NO Figure6-2.DigitalLockDetectFlowchart 18 FunctionalDescription Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 7 General Programming Information The LMK03000 family of devices are programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] formtheaddressfield.Theremaining28bitsformthedatafieldDATA[27:0]. During programming, LEuWire is low and serial data is clocked in on the rising edge of CLKuWire (MSB first). When LE goes high, data is transferred to the register bank selected by the address field. Only registersR0toR7,R11,andR13toR15needtobeprogrammedforproperdeviceoperation. For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed. Any changes to the PLL R divider or OSCin require R15 to be programmed again to activatethefrequencycalibrationroutine. 7.1 RECOMMENDED PROGRAMMING SEQUENCE TherecommendedprogrammingsequenceinvolvesprogrammingR0withtheresetbitset(RESET=1)to ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed again, the reset bit is programmed clear (RESET = 0). Registers are programmed in order with R15 being thelastregisterprogrammed.Anexampleprogrammingsequenceisshownbelow. • Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the resetbitissetinR0,theotherR0bitsareignored. – IfR0isprogrammedagain,theresetbitisprogrammedclear(RESET=0). • Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings. • ProgramR8foroptimumphasenoiseperformance. • ProgramR9withVboostsettingifnecessary.Optional,onlyneededtosetVboost=1. • ProgramR11withDIV4settingifnecessary. • ProgramR13withoscillatorinputfrequencyandinternalloopfiltervalues • Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and PLLRdivider. • Program R15 with PLL charge pump gain, VCO divider, and PLL N divider. Also starts frequency calibrationroutine. Copyright©2006–2013,TexasInstrumentsIncorporated GeneralProgrammingInformation 19 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com Table7-1.REGISTERMAP er gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e R Data[27:0] A3 A2 A1 A0 N E CLKout0 _ 0 CLKout0_DIV CLKout0_DLY R0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 0 0 0 L C N E CLKout1 _ 1 CLKout1_DIV CLKout1_DLY R1 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 0 0 1 L C N E CLKout2 _ 2 CLKout2_DIV CLKout2_DLY R2 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 0 1 0 L C N E CLKout3 _ 3 CLKout3_DIV CLKout3_DLY R3 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 0 1 1 L C N E CLKout4 _ 4 CLKout4_DIV CLKout4_DLY R4 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 1 0 0 L C N E CLKout5 _ 5 CLKout5_DIV CLKout5_DLY R5 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 1 0 1 L C N E CLKout6 _ 6 CLKout6_DIV CLKout6_DLY R6 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 1 1 0 L C N E CLKout7 _ 7 CLKout7_DIV CLKout7_DLY R7 0 0 0 0 0 0 0 0 0 0 0 0 0 _[M1:U0]X Kout [7:0] [3:0] 0 1 1 1 L C R8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 20 GeneralProgrammingInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 Table7-1.REGISTERMAP(continued) er gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e R st R9 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 oo 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 b V R11 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 DIV4 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 VCO_ VCO_ VCO_ OSCin_FREQ R13 0 0 0 0 0 0 1 0 1 0 R4_LF R3_LF C3_C4_LF 1 1 0 1 [7:0] [2:0] [2:0] [3:0] al b N R14 0 0 0 N_Fout Kout_Glo ERDOW 0 0 PLL[3_:M0]UX P[1L1L:_0R] 0 0 0 0 1 1 1 0 E N_CL POW E PLL_ CP_ VCO_DIV PLL_N R15 0 0 0 0 1 1 1 1 GAIN [3:0] [17:0] [1:0] Copyright©2006–2013,TexasInstrumentsIncorporated GeneralProgrammingInformation 21 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 7.2 REGISTER R0 to R7 Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_ENdenotetheactualclockoutputwhichmaybefrom0to7. Table7-2.DefaultRegisterSettingsafterPoweronReset Default Bit BitName BitState BitDescription Register BitValue Location RESET 0 Noreset,normaloperation Resettopowerondefaults R0 31 CLKoutX_MUX 0 Bypassed CLKoutXmuxmode 18:17 CLKoutX_EN 0 Disabled CLKoutXenable 16 R0toR7 CLKoutX_DIV 1 Divideby2 CLKoutXclockdivide 15:8 CLKoutX_DLY 0 0ps CLKoutXclockdelay 7:4 Vboost 0 NormalMode OutputPowerControl R9 16 DIV4 0 PDF≤20MHz PhaseDetectorFrequency R11 15 OSCin_FREQ 10 10MHzOSCin OSCinFrequencyinMHz 21:14 VCO_R4_LF 0 Low(~200Ω) R4internalloopfiltervalues 13:11 R13 VCO_R3_LF 0 Low(~600Ω) R3internalloopfiltervalues 10:8 VCO_C3_C4_LF 0 C3=0pF,C4=10pF C3andC4internalloopfiltervalues 7:4 EN_Fout 0 Foutdisabled Foutenable 28 EN_CLKout_Global 1 Normal-CLKoutsnormal Globalclockoutputenable 27 POWERDOWN 0 Normal-Deviceactive Devicepowerdown R14 26 PLL_MUX 0 Disabled MultiplexercontrolforLDpin 23:20 PLL_R 10 Rdivider=10 PLLRdividevalue 19:8 PLL_CP_GAIN 0 100µA Chargepumpcurrent 31:30 VCO_DIV 2 Divideby2 VCOdividevalue R15 29:26 PLL_N 760 Ndivider=760 PLLNdividevalue 25:8 7.2.1 RESET bit -- R0 only This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its propervaluesandRESET=0. 7.2.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. ThedifferentMUXmodesandassociateddelaysarelistedbelow. CLKoutX_MUX[1:0] Mode AddedDelayRelativetoBypassMode 0 Bypassed(default) 0ps 1 Divided 100ps 400ps 2 Delayed (Inadditiontotheprogrammeddelay) 500ps 3 DividedandDelayed (Inadditiontotheprogrammeddelay) 22 GeneralProgrammingInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 7.2.3 CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUXbitmustbesettoeither"Divided"or"DividedandDelayed"mode.Afterallthedividersare programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned. The ClockOutputDividersfollowtheVCODividersothefinalclockdivideforanoutputisVCODivider× Clock Output Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. TheactualClockOutputDividevalueistwicethebinaryvalueprogrammedaslistedinthetablebelow. CLKoutX_DIV[7:0] ClockOutputDividervalue 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2(default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 . . . . . . . . ... 1 1 1 1 1 1 1 1 510 7.2.4 CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX (See Section 7.2.2) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurredinadditiontothedelayshowninthetablebelow. CLKoutX_DLY[3:0] Delay(ps) 0 0(default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250 7.2.5 CLKoutX_EN bit -- Clock Output Enables These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See Section 7.7.4) is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clockoutputswillbedisabled. CLKoutX_ENbit Conditions CLKoutXState 0 EN_CLKout_Globalbit=1 Disabled(default) GOEpin=High/NoConnect 1 Enabled Copyright©2006–2013,TexasInstrumentsIncorporated GeneralProgrammingInformation 23 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 7.3 REGISTER R8 TheprogrammingofregisterR8providesoptimumphasenoiseperformance. 7.4 REGISTER R9 The programming of register R9 is optional. If it is not programmed the bit Vboost will be defaulted to 0, whichisthetestconditionforallelectricalcharacteristics. 7.4.1 Vboost -- Voltage Boost By enabling this bit, the voltage output levels for all clock outputs is increased. Also, the noise floor is improved Vboost TypicalLVDSVoltageOutput(mV) TypicalLVPECLVoltageOutput(mV) 0 350 810 1 390 865 7.5 REGISTER R11 This register only has one bit and only needs to be programmed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to thecorrectvalues. 7.5.1 DIV4 -- High Phase Detector Frequencies and Lock Detect This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable output from the digital lock detect output in the case of a phase detector frequency frequency greaterthan20MHz. DIV4 DigitalLockDetectCircuitryMode Notdivided 0 PhaseDetectorFrequency≤20MHz(default) Dividedby4 1 PhaseDetectorFrequency>20MHz 7.6 REGISTER R13 7.6.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4 ThesebitscontrolthecapacitorvaluesforC3andC4intheinternalloopfilter. LoopFilterCapacitors VCO_C3_C4_LF[3:0] C3(pF) C4(pF) 0 0(default) 10(default) 1 0 60 2 50 10 3 0 110 4 50 110 5 100 110 6 0 160 7 50 160 8 100 10 9 100 60 10 150 110 11 150 60 12to15 Invalid 24 GeneralProgrammingInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 7.6.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0]=0foroptimumphasenoiseandjitter. VCO_R3_LF[2:0] R3Value(kΩ) 0 Low(~600Ω)(default) 1 10 2 20 3 30 4 40 5to7 Invalid 7.6.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2:0]=0foroptimumphasenoiseandjitter. VCO_R4_LF[2:0] R4Value(kΩ) 0 Low(~200Ω)(default) 1 10 2 20 3 30 4 40 5to7 Invalid 7.6.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multipleof1MHz,thenroundtotheclosestvalue. OSCin_FREQ[7:0] OSCinFrequency 1 1MHz 2 2MHz ... ... 10 10MHz(default) ... ... 200 200MHz 201to255 Invalid 7.7 REGISTER R14 7.7.1 PLL_R[11:0] -- R Divider Value These bits program the PLL R Divider and are programmed in binary fashion. Any changes to PLL_R requireR15tobeprogrammedagaintoactivethefrequencycalibrationroutine. PLL_R[11:0] PLLRDivideValue 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 . . . . . . . . . . . . ... 0 0 0 0 0 0 0 0 1 0 1 0 10(default) . . . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 1 1 4095 Copyright©2006–2013,TexasInstrumentsIncorporated GeneralProgrammingInformation 25 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 7.7.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin ThesebitssettheoutputmodeoftheLDpin.Thetablebelowlistsseveraldifferentmodes. PLL_MUX[3:0] OutputType LDPinFunction 0 Hi-Z Disabled(default) 1 Push-Pull LogicHigh 2 Push-Pull LogicLow 3 Push-Pull DigitalLockDetect(ActiveHigh) 4 Push-Pull DigitalLockDetect(ActiveLow) 5 Push-Pull AnalogLockDetect OpenDrain 6 AnalogLockDetect NMOS OpenDrain 7 AnalogLockDetect PMOS 8 Invalid 9 Push-Pull NDividerOutput/2(50%DutyCycle) 10 Invalid 11 Push-Pull RDividerOutput/2(50%DutyCycle) 12to15 Invalid 7.7.3 POWERDOWN bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardlessofthestateofanyoftheotherbitsorpins. POWERDOWNbit Mode 0 NormalOperation(default) 1 EntireDevicePoweredDown 7.7.4 EN_CLKout_Global bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits. When this bit is set to 0, all clock outputs are disabled, regardlessofthestateofanyoftheotherbitsorpins. EN_CLKout_Globalbit ClockOutputs 0 AllOff 1 NormalOperation(default) 7.7.5 EN_Fout bit -- Fout port enable ThisbitenablestheFoutpin. EN_Foutbit FoutPinStatus 0 Disabled(default) 1 Enabled 26 GeneralProgrammingInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 7.8 REGISTER R15 ProgrammingR15alsoactivatesthefrequencycalibrationroutine. 7.8.1 PLL_N[17:0] -- PLL N Divider ThesebitsprogramthedividevalueforthePLLNDivider.ThePLLNDividerfollowstheVCODividerand precedesthePLLphasedetector.SincetheVCODividerisalsointhefeedbackpathfromtheVCOtothe PLL Phase Detector, the total N divide value, N , is also influenced by the VCO Divider value. N = Total Total PLL N Divider × VCO Divider. The VCO frequency is calculated as, f = f × PLL N Divider × VCO VCO OSCin Divider / PLL R Divider. Since the PLL N divider is a pure binary counter there are no illegal divide values forPLL_N[17:0]exceptfor0. PLL_N[17:0] PLLNDividerValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . . . . ... 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 760(default) . . . . . . . . . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262143 7.8.2 VCO_DIV[3:0] -- VCO Divider These bits program the divide value for the VCO Divider. The VCO Divider follows the VCO output and precedes the clock distribution blocks. Since the VCO Divider is in the feedback path from the VCO to the PLL phase detector the VCO Divider contributes to the total N divide value, N . N = PLL N Divider × Total Total VCO Divider. The VCO Divider can not be bypassed. See Section 7.8.1 for more information on setting theVCOfrequency. VCO_DIV[3:0] VCODividerValue 0 0 0 0 Invalid 0 0 0 1 Invalid 0 0 1 0 2(default) 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 Invalid . . . . ... 1 1 1 1 Invalid 7.8.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain ThesebitssetthechargepumpgainofthePLL. PLL_CP_GAIN[1:0] ChargePumpGain 0 1x(default) 1 4x 2 16x 3 32x Copyright©2006–2013,TexasInstrumentsIncorporated GeneralProgrammingInformation 27 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 8 Application Information 8.1 SYSTEM LEVEL DIAGRAM Vcc 1 PF ut CPo Bias 0.1 PF OSCin CLKout0 CLKout0* 100(cid:214) CLKout1 OSCin* CLKout1* 0.1 PF CLKout2 CLKout2* LEuWire CLKuWire CLKout3 DATAuWire CLKout3* CLKout4 To System To Host SYNC* CLKout4* LMK0300xx CLKout5 LD CLKout5* (optional) GOE CLKout6 CLKout6* LDObyp1 CLKout7 LDObyp2 CLKout7* 10 PF 0.1 PF Figure8-1.TypicalApplication Figure 8-1 shows an LMK03000 family device used in a typical application. In this setup the clock may be multiplied, reconditioned, and redistributed. Both the OSCin/OSCin* and CLKoutX/CLKoutX* pins can be used in a single-ended or a differential fashion, which is discussed later in this datasheet. The GOE pin needstobehighfortheoutputstooperate.OnetechniquesometimesusedistotaketheoutputoftheLD (Lock Detect) pin and use this as an input to the GOE pin. If this is done, then the outputs will turn off if lockdetectcircuitdetectsthatthePLLisoutoflock.Theloopfilteractuallyconsistsofsevencomponents, but four of these components that for the third and fourth poles of the loop filter are integrated in the chip. Thefirstandsecondpoleoftheloopfilterareexternal. 8.2 BIAS PIN SeeSection6.1forbiaspininformation. 8.3 LDO BYPASS SeeSection6.2forLDObypassinformation. 28 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 8.4 LOOP FILTER LMK0300xx R3 R4 Phase Detector C3 C4 Internal Loop Filter C2 C1 External Loop Filter R2 Figure8-2.LoopFilter The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in Figure 8-2. When the loop filter is designed, it must be stable over the entire frequency band, meaning that the changes in K from the Vtune low to high band specification will not make the loop filter unstable. The design of the loop filter is application specific and can be rather involved, but is discussed in depth in the Clock Conditioner Owner's Manual provided by Texas Instruments. When designing with the integrated loop filter of the LMK03000 family, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4. Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict how wide the loop bandwidth the PLL can have. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In some situations where spurs requirements are very stringent and there is margin on phase noise, it might make sense to design for a loop filter with integrated resistor values that arelargerthantheirminimumvalue. Copyright©2006–2013,TexasInstrumentsIncorporated ApplicationInformation 29 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 8.5 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3 V,T =25°C. A Table8-1.BlockCurrentConsumption Power Current Power Dissipatedin Block Condition Consumptionat Dissipatedin LVPECLemitter 3.3V(mA) device(mW) resistors(mW) Entiredevice, Alloutputsoff;NoLVPECLemitterresistorsconnected 86.0 283.8 - corecurrent Lowclockbuffer ThelowclockbufferisenabledanytimeoneofCLKout0 9 29.7 - (internal) throughCLKout3areenabled Highclockbuffer Thehighclockbufferisenabledanytimeoneofthe 9 29.7 - (internal) CLKout4throughCLKout7areenabled Foutbuffer,EN_Fout=1 14.5 47.8 - LVDSoutput,Bypassedmode 17.8 58.7 - LVPECLoutput,Bypassedmode(includes120Ωemitter 40 72 60 resistors) Outputbuffers LVPECLoutput,disabledmode(includes120Ωemitter 17.4 38.3 19.1 resistors) LVPECLoutput,disabledmode.Noemitterresistors 0 0 - placed;openoutputs Dividecircuitry Divideenabled,divide=2 5.3 17.5 - peroutput Divideenabled,divide>2 8.5 28.0 - Delaycircuitryper Delayenabled,delay<8 5.8 19.1 - output Delayenabled,delay>7 9.9 32.7 - Entiredevice CLKout0&CLKout4enabledinBypassedmode 161.8 474 60 From Table 8-1 the current consumption can be calculated in any configuration. For example, the current for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output in Bypassed mode can be calculated by adding up the following blocks: core current, low clock buffer, high clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switchedin,thentheadditionalcurrentforthesestagesneedstobeaddedaswell. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the caseof1LVDS(CLKout0)&1LVPECL(CLKout4)operatingat3.3volts,wecalculate3.3V ×(86+9+9 +17.8+40)mA=3.3V×161.8mA=533.9mW.BecausetheLVPECLoutput(CLKout4)hastheemitter resistors hooked up and the power dissipated by these resistors is 60 mW, the total device power dissipationis533.9mW-60mW=473.9mW. When the LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL Voh & Vol typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30 mW. When the LVPECL output is disabled, the emitter resistor voltageis~1.07V.Thereforethepowerdissipatedineachemitterresistorisapproximately(1.07V)2/120 Ω=9.5mW. 30 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 8.6 THERMAL MANAGEMENT Power consumption of the LMK03000 family of devices can be high enough to require attention to thermal management.Forreliabilityandperformancereasonsthedietemperatureshouldbelimitedtoamaximum of 125 °C. That is, as an estimate, T (ambient temperature) plus device power consumption times θ A JA shouldnotexceed125°C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the packageathermallandpatternincludingmultipleviastoagroundplanemustbeincorporatedonthePCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 8-3. More informationonsolderingWQFNpackagescanbeobtainedatwww.ti.com. 5.0 mm, min 0.33 mm, typ 1.2 mm, typ Figure8-3.RecommendedLandandViaPattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 8-3 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to whereitcanbemoreeffectivelydissipated. Copyright©2006–2013,TexasInstrumentsIncorporated ApplicationInformation 31 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 8.7 TERMINATION AND USE OF CLOCK OUTPUTS (DRIVERS) When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: • Transmissionlinetheoryshouldbefollowedforgoodimpedancematchingtopreventreflections. • Clockdriversshouldbepresentedwiththeproperloads.Forexample: – LVDSdriversarecurrentdriversandrequireaclosedcurrentloop. – LVPECLdriversareopenemitterandrequireaDCpathtoground. • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the propervoltagelevel.Inthiscase,thesignalshouldnormallybeACcoupled. It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK03000 family, OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level, see Figure 8-1. This is only slightly different from the AC coupled cases described in 3.7.2 because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same, which is the receiver (OSCin/OSCin*) set the input to the optimum DC bias voltage (commonmodevoltage),notthedriver. 8.7.1 Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 8-4. To ensure proper LVDS operation when DC coupling it is recommend to use LVDS receivers without fail-safe or internal input bias such as DS90LV110T. The LVDS driver will provide the DC bias level for the LVDS receiver. For operation with LMK03000 family LVDS drivers it is recommend to use AC coupling with LVDS receivers that have an internal DC bias voltage. Some fail-safe circuitry will present a DC bias (common mode voltage) which will prevent the LVDS driver from working correctly.ThisprecautiondoesnotapplytotheLVPECLdrivers. CLKoutX LVDS 100:(cid:3)Trace :0 LVDS Driver (Differential) 10 Receiver CLKoutX* Figure8-4.DifferentialLVDSOperation,DCCoupling 32 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 8-5. Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as showninFigure8-6forVcc=3.3V. Vcc - 2 V : 0 5 CLKoutX LVPECL 100:(cid:3)Trace LVPECL Driver (Differential) Receiver CLKoutX* : 0 5 Vcc - 2 V Figure8-5.DifferentialLVPECLOperation,DCCoupling Vcc :120 :82 CLKoutX LVPECL 100:(cid:3)Trace LVPECL Driver (Differential) Receiver CLKoutX* :120 :82 Vcc Figure8-6.DifferentialLVPECLOperation,DCCoupling,TheveninEquivalent Copyright©2006–2013,TexasInstrumentsIncorporated ApplicationInformation 33 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 8.7.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is importanttoensurethereceiverisbiasedtoitsidealDClevel. When driving LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. If the receiver does notautomaticallybiasitsinput,onewaytodothisiswiththeterminationcircuitryinFigure8-7. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. Figure 8-7 employs 0.1 µF capacitors. This value may need to be adjusted to meetthestartuprequirementsforaparticularapplication. CLKoutX 0.1 PF 100:(cid:3)Trace (Differential) : 0 5 LVDS Vbias LVDS Driver Receiver : 0 CLKoutX* 5 0.1 PF Figure8-7.DifferentialLVDSOperation,ACCoupling LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 8-8. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to Vcc and a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is a valid termination as shown in Figure8-8forVcc=3.3V.NotethisThevenincircuitisdifferentfromtheDCcoupledexampleinFigure8- 6. Vcc 20: 82: 120: CLKoutX 1 LVPECL 0.1 PF 100:(cid:3)Trace LVPECL Driver 0.1 PF (Differential) Reciever CLKoutX* 120: 82: 120: Vcc Figure8-8.DifferentialLVPECLOperation,ACCoupling,TheveninEquivalent 34 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 8.7.3 Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into anunbalanced,single-endedsignal. ItispossibletouseanLVPECLdriverasoneortwoseparate800mVp-psignals.WhenDCcouplingone of the LMK03000 family clock LVPECL drivers, the termination should still be 50 ohms to Vcc - 2 V as shown in Figure 8-9. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistorconnectedtogroundwiththedriverconnectedtothejunctionofthe120Ω and82Ωresistors)isa validterminationasshowninFigure8-10forVcc=3.3V. Vcc - 2V : 0 5 CLKoutX 50:(cid:3)Trace LVPECL Driver Vcc - 2V Load CLKoutX* 50: Figure8-9.Single-EndedLVPECLOperation,DCCoupling Vcc : 0 2 CLKoutX 1 LVDPrivEeCrL Vcc:0 50:(cid:3)Trace :82 2 1 CLKoutX* : Load 2 8 Figure8-10.Single-EndedLVPECLOperation,DCCoupling,TheveninEquivalent When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensurea50ohmterminationwiththeproperDCbiaslevelforthereceiver.ThetypicalDCbiasvoltagefor LVPECL receivers is 2 V (See Section 8.7.2). If the other driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias (0 V DC) is expected for safe and proper operation. The internal 50 ohm termination the test equipment provides correctly terminates the LVPECL driver being measured as shown Figure 8-11. When using only one LVPECL driver of a CLKoutX/CLKoutX*pair,besuretoproperlyterminatetheunuseddriver. : 0 2 CLKoutX 1 LVPECL 0.1 PF 50:(cid:3)Trace : 0 Driver 0.1 PF 5 CLKoutX* : : 120 50 Load Figure8-11.Single-EndedLVPECLOperation,ACCoupling Copyright©2006–2013,TexasInstrumentsIncorporated ApplicationInformation 35 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com 8.7.4 Conversion to LVCMOS Outputs To drive an LVCMOS input with an LMK03000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS converter such as TI's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best noiseperformance,LVPECLprovidesahighervoltageswingintoinputoftheconverter. 8.8 OSCin INPUT InadditiontoLVDSandLVPECLinputs,OSCincanalsobedrivenwithasinewave.TheOSCininputcan be driven single-ended or differentially with sine waves. The configurations for these are shown in Figure8-12andFigure8-13.Figure8-14showstherecommendedpowerlevelforsinewaveoperationfor both differential and single-ended sources over frequency. The part will operate at power levels below the recommended power level, but as power decreases the PLL noise performance will degrade. The VCO noise performance will remain constant. At the recommended power level the PLL phase noise degradationfromfullpoweroperation(8dBm)islessthan2dB. 0.1 PF 50:(cid:3)Trace 0: LMK Clock Source 5 Input 0.1 PF Figure8-12.Single-EndedSineWaveInput 100:(cid:3)Trace 0: 0.1 PF LMK (Differential) 10 0.1 PF Input Clock Source Figure8-13.DifferentialSineWaveInput 10 5 Minimum Recommended Power for Single-Ended Operation 0 m) B d R ( -5 E Minimum Recommended W Power for Differential O P Operation -10 -15 -20 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) Figure8-14.RecommendedOSCinPowerforOperationwithaSineWaveInput 36 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O–NOVEMBER2006–REVISEDMARCH2013 8.9 MORE THAN EIGHT OUTPUTS WITH AN LMK03000 FAMILY DEVICE The LMK03000 family devices include eight or less outputs. When more than 8 outputs are required the footprint compatible LMK01000 family may be used for clock distribution. By using an LMK03000 device with eight LMK01000 family devices up to 64 clocks may be distributed in many different LVDS / LVPECL combinations. It's possible to distribute more than 64 clocks by adding more LMK01000 family devices. RefertoAN-1864(literaturenumberSNAA060)formoredetailsonhowtodothis. Copyright©2006–2013,TexasInstrumentsIncorporated ApplicationInformation 37 SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O–NOVEMBER2006–REVISEDMARCH2013 www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionN(March2013)toRevisionO Page • ChangedlayoutofNationalDataSheettoTIformat .......................................................................... 37 38 ApplicationInformation Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:LMK03000 LMK03000C LMK03000D LMK03001LMK03001C LMK03001D LMK03033 LMK03033C

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMK03000CISQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000CI & no Sb/Br) LMK03000CISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000CI & no Sb/Br) LMK03000DISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000DI & no Sb/Br) LMK03000DISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000DI & no Sb/Br) LMK03000DISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000DI & no Sb/Br) LMK03000ISQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03000 I & no Sb/Br) LMK03001CISQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001CI & no Sb/Br) LMK03001CISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001CI & no Sb/Br) LMK03001DISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001DI & no Sb/Br) LMK03001DISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001DI & no Sb/Br) LMK03001DISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001DI & no Sb/Br) LMK03001ISQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03001 I & no Sb/Br) LMK03033CISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033CI & no Sb/Br) LMK03033CISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033CI & no Sb/Br) LMK03033CISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033CI & no Sb/Br) LMK03033ISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033 I & no Sb/Br) LMK03033ISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033 I & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMK03033ISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 K03033 I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LMK03000CISQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000CISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000DISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000DISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000DISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000ISQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001CISQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001CISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001DISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001DISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001DISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03001ISQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033CISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033CISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033CISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033ISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033ISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033ISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LMK03000CISQ/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03000CISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03000DISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK03000DISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03000DISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03000ISQ/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03001CISQ/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03001CISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03001DISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK03001DISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03001DISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03001ISQ/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03033CISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK03033CISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03033CISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03033ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK03033ISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK03033ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE RHS0048A WQFN - 0.8 mm max height SCALE 1.800 PLASTIC QUAD FLATPACK - NO LEAD A 7.15 B 6.85 PIN 1 INDEX AREA 0.5 0.3 7.15 6.85 0.30 0.18 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 0.7 C DIM A SEATING PLANE OPT 1 OPT 2 0.05 0.08 C (0.1) (0.2) 0.00 2X 5.5 (0.2) 5.1 0.1 (A) TYP 44X 0.5 13 24 12 25 EXPOSED THERMAL PAD 2X 49 SYMM 5.5 SEE TERMINAL DETAIL 1 36 0.30 48X 48 37 0.18 PIN 1 ID SYMM 0.5 0.1 C A B (OPTIONAL) 48X 0.3 0.05 4214990/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 5.1) SYMM 48 37 48X (0.6) 1 36 48X (0.25) (1.05) TYP 44X (0.5) (1.25) TYP 49 SYMM (6.8) (R0.05) TYP ( 0.2) TYP VIA 12 25 13 24 (1.25) (1.05) TYP TYP (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL EDGE OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214990/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.625) TYP (1.25) TYP 48 37 48X (0.6) 1 49 36 48X (0.25) 44X (0.5) (1.25) TYP (0.625) TYP SYMM (6.8) (R0.05) TYP METAL TYP 12 25 13 24 16X SYMM ( 1.05) (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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