LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 LMC6062 Precision CMOS Dual Micropower Operational Amplifier CheckforSamples:LMC6062 FEATURES DESCRIPTION 1 • (TypicalUnlessOtherwiseNoted) The LMC6062 is a precision dual low offset voltage, 2 micropower operational amplifier, capable of • LowOffsetVoltage 100μV precision single supply operation. Performance • UltraLowSupplycurrent 16μA/Amplifier characteristics include ultra low input bias current, • Operatesfrom4.5Vto15VSingleSupply high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes • UltraLowInputBiasCurrent 10fA ground. These features, plus its low power • OutputSwingwithin10mVofSupplyRail,100k consumption, make the LMC6062 ideally suited for Load batterypoweredapplications. • InputCommon-ModeRangeIncludesV− Other applications using the LMC6062 include • HighVoltageGain 140dB precision full-wave rectifiers, integrators, references, • ImprovedLatchupImmunity sample-and-hold circuits, and true instrumentation amplifiers. APPLICATIONS This device is built with TI's advanced double-Poly Silicon-GateCMOSprocess. • InstrumentationAmplifier • PhotodiodeandInfraredDetectorPreamplifier For designs that require higher speed, see the LMC6082precisiondualoperationalamplifier. • TransducerAmplifiers • Hand-HeldAnalyticInstruments PATENTPENDING • MedicalInstrumentation • D/AConverter • ChargeAmplifierforPiezoelectricTransducers Connection Diagram Figure1. 8-PinPDIP/SOIC TopView 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1994–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. Absolute Maximum Ratings (1)(2) DifferentialInputVoltage ±SupplyVoltage VoltageatInput/OutputPin (V+)+0.3V, (V−)−0.3V SupplyVoltage(V+−V−) 16V OutputShortCircuittoV+ See (3) OutputShortCircuittoV− See (4) LeadTemperature(Soldering,10sec.) 260°C StorageTemp.Range −65°Cto+150°C JunctionTemperature 150°C ESDTolerance (5) 2kV CurrentatInputPin ±10mA CurrentatOutputPin ±30mA CurrentatPowerSupplyPin 40mA PowerDissipation See (6) (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobefunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtest conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications (3) DonotconnectoutputtoV+,whenV+isgreaterthan13Vorreliabilitywitllbeadverselyaffected. (4) Appliestobothsingle-supplyandsplit-supplyoperation.Continuosshortcircuitoperationatelevatedambienttemperaturecanresultin exceedingthemaximumallowedjunctiontemperatureof150°C.Outputcurrentsinexcessof±30mAoverlongtermmayadversely affectreliability. (5) Humanbodymodel,1.5kΩinserieswith100pF. (6) ThemaximumpowerdissipationisafunctionofT ,θ ,andT .Themaximumallowablepowerdissipationatanyambient J(Max) JA A temperatureisP =(T −T )/θ . D J(Max) A JA Operating Ratings (1) TemperatureRange LMC6062AM −55°C≤T ≤+125°C J LMC6062AI,LMC6082I −40°C≤T ≤+85°C J SupplyVoltage 4.5V≤V+≤15.5V ThermalResistance(θ ) (2) 8-PinPDIP 115°C/W JA 8-PinSOIC 193°C/W PowerDissipation See (3) (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobefunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtest conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted. (2) AllnumbersapplyforpackagessoldereddirectlyintoaPCboard. (3) Foroperatingatelevatedtemperaturesthedevicemustbederatedbasedonthethermalresistanceθ withP =(T–T )/θ . JA D J A JA DC Electrical Characteristics(1) Unlessotherwisespecified,alllimitsensuredforT =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V,V−= J 0V,V =1.5V,V =2.5VandR >1Munlessotherwisespecified. CM O L LMC6062AM LMC6062AI LMC6062I Symbol Parameter Conditions Typ(2) Units Limit(3) Limit(3) Limit(3) V InputOffsetVoltage 100 350 350 800 μV OS 1200 900 1300 Max (1) ForensuredMilitaryTemperatureRangeparameters,seeRETSMC6062X. (2) Typicalvaluesrepresentthemostlikelyparametricnorm. (3) Alllimitsareensuredbytestingorstatisticalanalysis. 2 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 DC Electrical Characteristics(1) (continued) Unlessotherwisespecified,alllimitsensuredforT =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V,V−= J 0V,V =1.5V,V =2.5VandR >1Munlessotherwisespecified. CM O L LMC6062AM LMC6062AI LMC6062I Symbol Parameter Conditions Typ(2) Units Limit(3) Limit(3) Limit(3) TCV InputOffsetVoltage 1.0 μV/°C OS AverageDrift I InputBiasCurrent 0.010 pA B 100 4 4 Max I InputOffsetCurrent 0.005 pA OS 100 2 2 Max R InputResistance >10 TeraΩ IN CMRR CommonMode 0V≤V ≤12.0V 85 75 75 66 dB CM RejectionRatio V+=15V 70 72 63 Min +PSRR PositivePowerSupply 5V≤V+≤15V 85 75 75 66 dB RejectionRatio V =2.5V 70 72 63 Min O −PSRR NegativePowerSupply 0V≤V−≤−10V 100 84 84 74 dB RejectionRatio 70 81 71 Min V InputCommon-Mode V+=5Vand15V −0.4 −0.1 −0.1 −0.1 V CM VoltageRange forCMRR≥60dB 0 0 0 Max V+−1.9 V+−2.3 V+−2.3 V+−2.3 V V+−2.6 V+−2.5 V+−2.5 Min A LargeSignal R =100kΩ(4) Sourcing 4000 400 400 300 V/mV V L VoltageGain 200 300 200 Min Sinking 3000 180 180 90 V/mV 70 100 60 Min R =25kΩ (4) Sourcing 3000 400 400 200 V/mV L 150 150 80 Min Sinking 2000 100 100 70 V/mV 35 50 35 Min V OutputSwing V+=5V 4.995 4.990 4.990 4.950 V O R =100kΩto2.5V 4.970 4.980 4.925 Min L 0.005 0.010 0.010 0.050 V 0.030 0.020 0.075 Max V+=5V 4.990 4.975 4.975 4.950 V R =25kΩto2.5V 4.955 4.965 4.850 Min L 0.010 0.020 0.020 0.050 V 0.045 0.035 0.150 Max V+=15V 14.990 14.975 14.975 14.950 V R =100kΩto7.5V 14.955 14.965 14.925 Min L 0.010 0.025 0.025 0.050 V 0.050 0.035 0.075 Max V+=15V 14.965 14.900 14.900 14.850 V R =25kΩto7.5V 14.800 14.850 14.800 Min L 0.025 0.050 0.050 0.100 V 0.200 0.150 0.200 Max (4) V+=15V,V =7.5VandR connectedto7.5V.ForSourcingtests,7.5V≤V ≤11.5V.ForSinkingtests,2.5V≤V ≤7.5V. CM L O O Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com DC Electrical Characteristics(1) (continued) Unlessotherwisespecified,alllimitsensuredforT =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V,V−= J 0V,V =1.5V,V =2.5VandR >1Munlessotherwisespecified. CM O L LMC6062AM LMC6062AI LMC6062I Symbol Parameter Conditions Typ(2) Units Limit(3) Limit(3) Limit(3) I OutputCurrent Sourcing,V =0V 22 16 16 13 mA O O V+=5V 8 10 8 Min Sinking,V =5V 21 16 16 16 mA O 7 8 8 Min I OutputCurrent Sourcing,V =0V 25 15 15 15 mA O O V+=15V 9 10 10 Min Sinking,V =13V (5) 35 20 20 20 mA O 7 8 8 Min I SupplyCurrent BothAmplifiers 32 38 38 46 μA S V+=+5V,V =1.5V 60 46 56 Max O BothAmplifiers 40 47 47 57 μA V+=+15V,V =7.5V 70 55 66 Max O (5) DonotconnectoutputtoV+,whenV+isgreaterthan13Vorreliabilitywillbeadverselyaffected. AC Electrical Characteristics(1) Unlessotherwisespecified,alllimitsensuredforT =25°C,Boldfacelimitsapplyatthetemperatureextremes.V+=5V,V−= J 0V,V =1.5V,V =2.5VandR >1Munlessotherwisespecified. CM O L LMC6062AM LMC6062AI LMC6062I Symbol Parameter Conditions Typ(2) Units Limit(3) Limit(3) Limit(3) SR SlewRate See (4) 35 20 20 15 V/ms 8 10 7 Min GBW Gain-BandwidthProduct 100 kHz θ PhaseMargin 50 Deg m Amp-to-AmpIsolation See (5) 155 dB e Input-ReferredVoltageNoise F=1kHz 83 nV/√Hz n i Input-ReferredCurrentNoise F=1kHz 0.0002 pA/√Hz n T.H.D. TotalHarmonicDistortion F=1kHz,A =−5 V R =100kΩ,V =2V 0.01 % L O PP ±5VSupply (1) ForensuredMilitaryTemperatureRangeparameters,seeRETSMC6062X. (2) Typicalvaluesrepresentthemostlikelyparametricnorm. (3) Alllimitsareensuredbytestingorstatisticalanalysis. (4) V+=15V.ConnectedasVoltageFollowerwith10Vstepinput.Numberspecifiedistheslowerofthepositiveandnegativeslewrates. (5) InputreferredV+=15VandR =100kΩconnectedto7.5V.Eachampexcitedinturnwith100HztoproduceV =12V . L O PP 4 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 Typical Performance Characteristics V =±7.5V,T =25°C,Unlessotherwisespecified S A DistributionofLMC6062InputOffsetVoltage DistributionofLMC6062InputOffsetVoltage (T =+25°C) (T =−55°C) A A Figure2. Figure3. InputBiasCurrent DistributionofLMC6062InputOffsetVoltage vs. (T =+125°C) Temperature A Figure4. Figure5. SupplyCurrent InputVoltage vs. vs. SupplyVoltage OutputVoltage Figure6. Figure7. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (continued) V =±7.5V,T =25°C,Unlessotherwisespecified S A CommonModeRejectionRatio PowerSupplyRejectionRatio vs. vs. Frequency Frequency Figure8. Figure9. InputVoltageNoise vs. Frequency OutputCharacteristicsSourcingCurrent Figure10. Figure11. GainandPhaseResponse vs. Temperature OutputCharacteristicsSinkingCurrent (−55°Cto+125°C) Figure12. Figure13. 6 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 Typical Performance Characteristics (continued) V =±7.5V,T =25°C,Unlessotherwisespecified S A GainandPhaseResponse GainandPhaseResponse vs. vs. CapacitiveLoad CapacitiveLoad withR =20kΩ withR =500kΩ L L Figure14. Figure15. OpenLoopFrequencyResponse InvertingSmallSignalPulseResponse Figure16. Figure17. InvertingLargeSignalPulseResponse Non-InvertingSmallSignalPulseResponse Figure18. Figure19. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (continued) V =±7.5V,T =25°C,Unlessotherwisespecified S A CrosstalkRejection vs. Non-InvertingLargeSignalPulseResponse Frequency Figure20. Figure21. Stability Stability vs vs. CapacitiveLoad,R =20kΩ CapacitiveLoadR =1MΩ L L Figure22. Figure23. 8 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6062 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op amps. These features make the LMC6062 both easier to designwith,andprovidehigherspeedthanproductstypicallyfoundinthisultralowpowerclass. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6062. Although the LMC6062 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phasemargins. When high input impedances are demanded, guarding of the LMC6062 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT FORHIGH-IMPEDANCEWORK). The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, C, around the f feedbackresistor(asinFigure24)suchthat: (1) or R C ≤R C (2) 1 IN 2 f Since it is often difficult to know the exact value of C , C can be experimentally adjusted so that the desired IN f pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensatingforinputcapacitance. Figure24. CancelingtheEffectofInputCapacitance CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominate pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistiveloadinparallelwiththecapacitiveload(seetypicalcurves). Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created bythecombinationoftheop-amp'soutputimpedanceandthecapacitiveload.Thispoleinducesphaselagatthe unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. Withafewexternalcomponents,opampscaneasilyindirectlydrivecapacitiveloads,asshowninFigure25. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com Figure25. LMC6062NoninvertingGainof10Amplifier,CompensatedtoHandleCapacitiveLoads In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overallfeedbackloop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 26). Typically a pull up resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure26. CompensatingforLargeCapacitiveLoads withaPullUpResistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6062, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,thesurfaceleakagewillbeappreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6062's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's inputs, as in Figure 27. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6062's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 28 for typical connections of guard ringsforstandardop-ampconfigurations. 10 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 Figure27. ExampleofGuardRinginP.C.BoardLayout (a)InvertingAmplifier (b)Non-InvertingAmplifier (c)Follower Figure28.TypicalConnectionsofGuardRings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.SeeFigure29. Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6062 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pinswillalsoinhibitlatchupsusceptibility. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com (InputpinsareliftedoutofPCboardandsoldereddirectlytocomponents.AllotherpinsconnectedtoPCboard). Figure29. AirWiring Typical Single-Supply Applications (V+=5.0V ) DC The extremely high input impedance, and low power consumption, of the LMC6062 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Figure 30 shows an instrumentation amplifier that features high differential and common mode input resistance (>1014Ω), 0.01% gain accuracy at A = 100, excellent CMRR with 1 kΩ imbalance in bridge source resistance. V Input current is less than 100 fA and offset drift is less than 2.5 μV/°C. R provides a simple means of adjusting 2 gain over a wide range without degrading CMRR. R is an initial trim used to maximize CMRR without using 7 superprecisionmatchedresistors.ForgoodCMRRovertemperature,lowdriftresistorsshouldbeused. IfR =R ,R =R ,andR =R ;then 1 5 3 6 4 7 ∴A ≈100forcircuitshown(R =9.822k). V 2 Figure30. InstrumentationAmplifier 12 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

LMC6062 www.ti.com SNOS631D–NOVEMBER1994–REVISEDMARCH2013 Figure31. Low-LeakageSampleandHold Figure32. 1HzSquareWaveOscillator Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6062

LMC6062 SNOS631D–NOVEMBER1994–REVISEDMARCH2013 www.ti.com REVISION HISTORY ChangesfromRevisionC(March2013)toRevisionD Page • ChangedlayoutofNationalDataSheettoTIformat.......................................................................................................... 13 14 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6062

PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMC6062AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 62AIM LMC6062AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 62AIM LMC6062AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 62AIM LMC6062I MDC ACTIVE DIESALE Y 0 288 Green (RoHS Call TI Level-1-NA-UNLIM -40 to 85 & no Sb/Br) LMC6062IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 62IM LMC6062IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 62IM LMC6062IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 62IM LMC6062IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS CU SN Level-1-NA-UNLIM -40 to 85 LMC6062 & no Sb/Br) IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LMC6062AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6062IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LMC6062AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6062IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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