LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 LMC6041 CMOS Single Micropower Operational Amplifier CheckforSamples:LMC6041 FEATURES DESCRIPTION 1 • LowSupplyCurrent: 14μA(Typ) Ultra-low power consumption and low input-leakage 2 current are the hallmarks of the LMC6041. Providing • Operatesfrom4.5Vto15.5VSingleSupply input currents of only 2 fA typical, the LMC6041 can • UltraLowInputCurrent: 2fA(Typ) operate from a single supply, has output swing • Rail-to-RailOutputSwing extending to each supply rail, and an input voltage rangethatincludesground. • InputCommon-ModeRangeIncludesGround The LMC6041 is ideal for use in systems requiring APPLICATIONS ultra-low power consumption. In addition, the insensitivity to latch-up, high output drive, and output • BatteryMonitoringandPowerConditioning swing to ground without requiring external pull-down • PhotodiodeandInfraredDetectorPreamplifier resistors make it ideal for single-supply battery- • SiliconBasedTransducerSystems poweredsystems. • Hand-HeldAnalyticInstruments Other applications for the LMC6041 include bar code reader amplifiers, magnetic and electric field • pHProbeBufferAmplifier detectors,andhand-heldelectrometers. • FireandSmokeDetectionSystems This device is built with TI's advanced Double-Poly • ChargeAmplifierforPiezoelectricTransducers Silicon-GateCMOSprocess. See the LMC6042 for a dual, and the LMC6044 for a quadamplifierwiththesefeatures. Connection Diagrams TopView Figure1. 8-PinSOICorPDIPPackage SeePackageNumberD0008AorP0008E Figure2. Low-LeakageSampleandHold 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1994–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Absolute Maximum Ratings(1)(2) DifferentialInputVoltage ±SupplyVoltage SupplyVoltage(V+−V−) 16V OutputShortCircuittoV− See(3) OutputShortCircuittoV+ See(4) LeadTemperature (Soldering,10sec.) 260°C StorageTemperatureRange −65°Cto+150°C JunctionTemperature 110°C ESDTolerance(5) 500V CurrentatInputPin ±5mA CurrentatOutputPin ±18mA CurrentatPowerSupplyPin 35mA VoltageatInput/OutputPin (V+)+0.3V,(V−)−0.3V PowerDissipation See(6) (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.Operatingconditionsindicateconditionsfor whichthedeviceisintendedtobefunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtest conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications. (3) Appliestobothsingle-supplyandsplit-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperaturecanresultin exceedingthemaximumallowedjunctiontemperatureof110°C.Outputcurrentsinexcessof±30mAoverlongtermmayadversely affectreliability. (4) DonotconnectoutputtoV+whenV+isgreaterthan13Vorreliabilitymaybeadverselyaffected. (5) Humanbodymodel,1.5kΩinserieswith100pF. (6) ThemaximumpowerdissipationisafunctionofT ,θ ,andT .Themaximumallowablepowerdissipationatanyambient J(max) JA A temperatureisP =(T −T )/θ . D J(max) A JA Operating Ratings TemperatureRange LMC6041AI,LMC6041I −40°C≤T ≤+85°C J SupplyVoltage 4.5V≤V+≤15.5V PowerDissipation See(1) ThermalResistance(θ )(2) 8-PinPDIPpackage 101°C/W JA 8-PinSOICpackage 165°C/W (1) Foroperatingatelevatedtemperaturesthedevicemustbederatedbasedonthethermalresistanceθ withP =(T −T )/θ . JA D J A JA (2) AllnumbersapplyforpackagessoldereddirectlyintoaPCboard. 2 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Electrical Characteristics Unlessotherwisespecified,alllimitsensuredforT =T =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V, A J V−=0V,V =1.5V,V =V+/2,andR >1Munlessotherwisespecified. CM O L Parameter TestConditions Typical(1) LMLCim60it4(21)AI LMLiCm6it0(42)1I (ULinmitist) V InputOffsetVoltage 1 3 6 mV OS 3.3 6.3 max TCV InputOffsetVoltage OS 1.3 μV/°C AverageDrift I InputBiasCurrent 0.002 pA B 4 4 max I InputOffsetCurrent 0.001 pA OS 2 2 max R InputResistance >10 TeraΩ IN CMRR CommonModeRejection 0V≤V ≤12.0V 75 68 62 dB CM Ratio V+=15V 66 60 min +PSRR PositivePowerSupply 5V≤V+≤15V 75 68 62 dB RejectionRatio V =2.5V O 66 60 min −PSRR NegativePowerSupply 0V≤V−≤−10V 94 84 74 dB RejectionRatio V =2.5V O 83 73 min CMR InputCommon-Mode V+=5Vand15V −0.4 −0.1 −0.1 V VoltageRange forCMRR≥50dB 0 0 max V+−1.9V V+−2.3V V+−2.3V V V+−2.5V V+−2.4V min A LargeSignalVoltageGain R =100kΩ(3) Sourcing 1000 400 300 V/mV V L 300 200 min Sinking 500 180 90 V/mV 120 70 min R =25kΩ(3) Sourcing 1000 200 100 V/mV L 160 80 min Sinking 250 100 50 V/mV 60 40 min V OutputSwing V+=5V 4.987 4.970 4.940 V O R =100kΩtoV+/2 L 4.950 4.910 min 0.004 0.030 0.060 V 0.050 0.090 max V+=5V 4.980 4.920 4.870 V R =25kΩtoV+/2 L 4.870 4.820 min 0.010 0.080 0.130 V 0.130 0.180 max V+=15V 14.970 14.920 14.880 V R =100kΩtoV+/2 L 14.880 14.820 min 0.007 0.030 0.060 V 0.050 0.090 max V+=15V 14.950 14.900 14.850 V R =25kΩtoV+/2 L 14.850 14.800 min 0.022 0.100 0.150 V 0.150 0.200 max (1) TypicalValuesrepresentthemostlikelyparametricnorm. (2) Alllimitsareensuredatroomtemperature(standardtypeface)oratoperatingtemperatureextremes(boldfacetype). (3) V+=15V,V =7.5VandR connectedto7.5V.ForSourcingtests,7.5V≤V ≤11.5V.ForSinkingtests,2.5V≤V ≤7.5V. CM L O O Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com Electrical Characteristics (continued) Unlessotherwisespecified,alllimitsensuredforT =T =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V, A J V−=0V,V =1.5V,V =V+/2,andR >1Munlessotherwisespecified. CM O L Parameter TestConditions Typical(1) LMLCim60it4(21)AI LMLiCm6it0(42)1I (ULinmitist) I OutputCurrent Sourcing,V =0V 22 16 13 mA SC O V+=5V 10 8 min Sinking,V =5V 21 16 13 mA O 8 8 min I OutputCurrent Sourcing,V =0V 40 15 15 mA SC O V+=15V 10 10 min Sinking,V =13V(4) 39 24 21 mA O 8 8 min I SupplyCurrent V =1.5V 14 20 26 μA S O 24 30 max V+=15V 18 26 34 μA 31 39 max (4) DonotconnectoutputtoV+whenV+isgreaterthan13Vorreliabilitymaybeadverselyaffected. AC Electrical Characteristics Unlessotherwisespecified,alllimitsensuredforT =T =25°C.Boldfacelimitsapplyatthetemperatureextremes.V+=5V, A J V−=0V,V =1.5V,V =V+/2,andR >1Munlessotherwisespecified. CM O L Parameter TestConditions Typ(1) LMC6041AI LMC6041I Units Limit(2) Limit(2) (Limit) SR SlewRate See(3) 0.02 0.015 0.010 V/μs 0.010 0.007 min GBW Gain-BandwidthProduct 75 kHz φ PhaseMargin 60 Deg m e Input-ReferredVoltageNoise F=1kHz 83 nV/√Hz n i Input-ReferredCurrentNoise F=1kHz 0.0002 pA/√Hz n THD TotalHarmonicDistortion F=1kHz,A =−5 0.01 % V R =100kΩ,V =2V L O pp ±5VSupply (1) TypicalValuesrepresentthemostlikelyparametricnorm. (2) Alllimitsareensuredatroomtemperature(standardtypeface)oratoperatingtemperatureextremes(boldfacetype). (3) V+=15V.ConnectedasVoltageFollowerwith10Vstepinput.Numberspecifiedintheslowerofthepositiveandnegativeslewrates. 4 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Typical Performance Characteristics V =±7.5V,T =25°Cunlessotherwisespecified S A SupplyCurrent OffsetVoltage vs vs SupplyVoltage TemperatureofFiveRepresentativeUnits Figure3. Figure4. InputBiasCurrent InputBiasCurrent vs vs Temperature InputCommon-ModeVoltage Figure5. Figure6. InputCommon-ModeVoltageRange vs OutputCharacteristics Temperature CurrentSinking Figure7. Figure8. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (continued) V =±7.5V,T =25°Cunlessotherwisespecified S A InputVoltageNoise OutputCharacteristics vs CurrentSourcing Frequency Figure9. Figure10. PowerSupplyRejectionRatio CMRR vs vs Frequency Frequency Figure11. Figure12. CMRR Open-LoopVoltageGain vs vs Temperature Temperature Figure13. Figure14. 6 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Typical Performance Characteristics (continued) V =±7.5V,T =25°Cunlessotherwisespecified S A GainandPhaseResponses Open-Loop vs FrequencyResponse LoadCapacitance Figure15. Figure16. GainandPhaseResponses GainError(V OS vs vs Temperature V ) OUT Figure17. Figure18. Common-ModeError Non-InvertingSlewRate vs vs Common-ModeVoltageofThreeRepresentativeUnits Temperature Figure19. Figure20. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (continued) V =±7.5V,T =25°Cunlessotherwisespecified S A InvertingSlewRate Non-InvertingLarge vs SignalPulseResponse Temperature (A =+1) V Figure21. Figure22. Non-InvertingSmall InvertingLarge-Signal SignalPulseResponse PulseResponse Figure23. Figure24. Stability InvertingSmallSignal vs PulseResponse CapacitiveLoad(A =+1) V Figure25. Figure26. 8 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Typical Performance Characteristics (continued) V =±7.5V,T =25°Cunlessotherwisespecified S A Stability vs CapacitiveLoad(A =±10) V Figure27. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6041 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6041 both easier to designwith,andprovidehigherspeedthanproductstypicallyfoundinthisultra-lowpowerclass. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the LMC6041. Although the LMC6041 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce phasemargins. When high input impedance are demanded, guarding of the LMC6041 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High ImpedanceWork.) Figure28. CancellingtheEffectofInputCapacitance The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, C, around f thefeedbackresistor(asinFigure28)suchthat: (1) or R C ≤R C (2) 1 IN 2 f Since it is often difficult to know the exact value of C , C can be experimentally adjusted so that the desired IN f pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensatingforinputcapacitance. CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created bythecombinationoftheop-amp'soutputimpedanceandthecapacitiveload.Thispoleinducesphaselagatthe unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. Withafewexternalcomponents,opampscaneasilyindirectlydrivecapacitiveloads,asshowninFigure29. 10 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Figure29. LMC6041NoninvertingGainof10Amplifier,CompensatedtoHandleCapacitiveLoads In the circuit of Figure 29, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overallfeedbackloop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 30 ). Typically a pull up resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure30. CompensatingforLarge CapacitiveLoadswithaPullUpResistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6041, typically less than 2fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,thesurfaceleakagewillbeappreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6041's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's inputs, as in Figure 31. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6041's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 34 for typical connections of guard ringsforstandardop-ampconfigurations. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com Figure31. ExampleofGuardRing inP.C.BoardLayout Figure32. InvertingAmplifier Figure33. Follower Non-InvertingAmplifier Figure34. TypicalConnectionsofGuardRings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.SeeFigure35. 12 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 (InputpinsareliftedoutofPCboardandsoldereddirectlytocomponents.AllotherpinsconnectedtoPCboard.) Figure35. AirWiring Typical Single-Supply Applications (V+=5.0V ) DC The extremely high input impedance, and low power consumption, of the LMC6041 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Figure36. TwoOp-AmpInstrumentationAmplifier The circuit in Figure 36 is recommended for applications where the common-mode input range is relatively low and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an independentadjustmentofthegainandcommon-moderejectiontrim,andatotalquiescentsupplycurrentofless than 28 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board layout an important part of the overall system design (see Printed-Circuit-Board Layout for High Impedance Work). Referring to Figure 36, the input voltages are represented as a common-mode input V plus a CM differentialinputV . D Rejection of the common-mode component of the input is accomplished by making the ratio of R1/R2 equal to R3/R4.Sothatwhere, (3) A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the gainequationcanbesimplified: (4) Due to the “zero-in, zero-out” performance of the LMC6041, and output swing rail-rail, the dynamic range is only limited to the input common-mode range of 0V to V –2.3V, worst case at room temperature. This feature of the S LMC6041makesitanidealchoiceforlow-powerinstrumentationsystems. Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 37. Provisions have been madeforlowsensitivitytrimmingofCMRRandgain. Figure37. Low-PowerTwo-Op-AmpInstrumentationAmplifier Figure38. Low-LeakageSampleandHold Figure39. InstrumentationAmplifier Figure40. 1HzSquare-WaveOscillator 14 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

LMC6041 www.ti.com SNOS610E–DECEMBER1994–REVISEDMARCH2013 Figure41. ACCoupledPowerAmplifier Copyright©1994–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC6041

LMC6041 SNOS610E–DECEMBER1994–REVISEDMARCH2013 www.ti.com REVISION HISTORY ChangesfromRevisionD(March2013)toRevisionE Page • ChangedlayoutofNationalDataSheettoTIformat.......................................................................................................... 15 16 SubmitDocumentationFeedback Copyright©1994–2013,TexasInstrumentsIncorporated ProductFolderLinks:LMC6041

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMC6041AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 41AIM LMC6041AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 41AIM LMC6041AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 41AIM LMC6041IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 41IM LMC6041IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC60 & no Sb/Br) 41IM LMC6041IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS SN Level-1-NA-UNLIM -40 to 85 LMC60 & no Sb/Br) 41IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LMC6041AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6041IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LMC6041AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6041IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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