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  • 型号: LMC555CTP/NOPB
  • 制造商: Texas Instruments
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ICGOO电子元器件商城为您提供LMC555CTP/NOPB由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 LMC555CTP/NOPB价格参考¥3.79-¥9.41。Texas InstrumentsLMC555CTP/NOPB封装/规格:时钟/计时 - 可编程计时器和振荡器, 555 Type, Timer/Oscillator (Single) IC 3MHz 8-µSMD (1.41x1.44)。您可以下载LMC555CTP/NOPB参考资料、Datasheet数据手册功能说明书,资料中有LMC555CTP/NOPB 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC OSC SINGLE TIMER 3MHZ 8-USMD计时器和支持产品 CMOS Timer 8-DSBGA -40 to 85

产品分类

时钟/计时 - 可编程计时器和振荡器

品牌

Texas Instruments

产品手册

http://www.ti.com/lit/gpn/lmc555

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

时钟和计时器IC,计时器和支持产品,Texas Instruments LMC555CTP/NOPB-

数据手册

点击此处下载产品Datasheet

产品型号

LMC555CTP/NOPB

PCN组件/产地

点击此处下载产品Datasheet

产品种类

计时器和支持产品

传播延迟—最大值

100 ns (Typ)

供应商器件封装

8-uSMD

其它名称

LMC555CTP/NOPBCT

内部定时器数量

1

包装

剪切带 (CT)

商标

Texas Instruments

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

8-UFBGA

封装/箱体

DSBGA-8

工作温度

-40°C ~ 85°C

工厂包装数量

250

最大功率耗散

568 mW

最大工作温度

+ 85 C

最小工作温度

- 40 C

标准包装

1

电压-电源

1.5 V ~ 15 V

电流-电源

150µA

电源电压-最大

15 V

电源电压-最小

1.5 V

电源电流

50 uA

类型

Standard

系列

LMC555

计数

-

频率

3MHz

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PDF Datasheet 数据手册内容提取

Product Order Technical Tools & Support & Folder Now Documents Software Community LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 LMC555 CMOS Timer 1 Features 3 Description • Industry'sFastestAstableFrequencyof3MHz The LMC555 device is a CMOS version of the 1 industry standard 555 series general-purpose timers. • AvailableinIndustry'sSmallest8-BumpDSBGA In addition to the standard package (SOIC, VSSSOP, Package(1.43mm× 1.41mm) and PDIP) the LMC555 is also available in a chip- • LessThan1mWTypicalPowerDissipationat5V sized package (8-bump DSBGA) using TI's DSBGA Supply package technology. The LMC555 offers the same capability of generating accurate time delays and • 1.5VSupplyOperatingVoltageEnsured frequencies as the LM555 but with much lower power • OutputFullyCompatibleWithTTLandCMOS dissipation and supply current spikes. When operated Logicat5VSupply as a one-shot, the time delay is precisely controlled • Testedto −10mA,50mAOutputCurrentLevels by a single external resistor and capacitor. In the astable mode the oscillation frequency and duty cycle • ReducedSupplyCurrentSpikesDuringOutput are accurately set by two external resistors and one Transitions capacitor. The use of TI's LMCMOS process extends • ExtremelyLowReset,Trigger,andThreshold both the frequency range and the low supply Currents capability. • ExcellentTemperatureStability DeviceInformation(1) • Pin-for-PinCompatibleWith555SeriesofTimers PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications SOIC(8) 4.90mm×3.91mm • PrecisionTiming VSSOP(8) 3.00mm×3.00mm LMC555 PDIP(8) 9.81mm×6.35mm • PulseGeneration DSBGA(8) 1.43mm×1.41mm • SequentialTiming (1) For all available packages, see the orderable addendum at • TimeDelayGeneration theendofthedatasheet. • PulseWidthModulation • PulsePositionModulation • LinearRampGenerators PulseWidthModulator PulseWidthModulatorWaveform: TopWaveform-Modulation BottomWaveform-OutputVoltage 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 9.1 ApplicationInformation............................................12 2 Applications........................................................... 1 9.2 TypicalApplication .................................................12 3 Description............................................................. 1 9.3 FrequencyDivider...................................................14 9.4 PulseWidthModulator............................................14 4 RevisionHistory..................................................... 2 9.5 PulsePositionModulator........................................15 5 PinConfigurationandFunctions......................... 3 9.6 50%DutyCycleOscillator......................................16 6 Specifications......................................................... 4 10 PowerSupplyRecommendations..................... 17 6.1 AbsoluteMaximumRatings......................................4 11 Layout................................................................... 17 6.2 ESDRatings..............................................................4 11.1 LayoutGuidelines.................................................17 6.3 RecommendedOperatingConditions.......................4 11.2 LayoutExample....................................................17 6.4 ThermalInformation .................................................4 12 DeviceandDocumentationSupport................. 18 6.5 ElectricalCharacteristics...........................................5 12.1 ReceivingNotificationofDocumentationUpdates18 7 ParameterMeasurementInformation..................6 12.2 CommunityResources..........................................18 8 DetailedDescription.............................................. 7 12.3 Trademarks...........................................................18 8.1 Overview...................................................................7 12.4 ElectrostaticDischargeCaution............................18 8.2 FunctionalBlockDiagram.........................................7 12.5 Glossary................................................................18 8.3 FeatureDescription...................................................7 13 Mechanical,Packaging,andOrderable 8.4 DeviceFunctionalModes..........................................8 Information........................................................... 18 9 ApplicationandImplementation........................ 12 4 Revision History ChangesfromRevisionL(February2016)toRevisionM Page • ChangedorderofFeatureslist. ............................................................................................................................................. 1 • Changedstabletoastable-typo........................................................................................................................................... 1 • Changedstabletoastable-typo........................................................................................................................................... 7 • Changedbeingstobeginstypo.............................................................................................................................................. 8 • ChangedtypoLM555toLMC555. ...................................................................................................................................... 12 • ChangedtypoLM555toLMC555. ...................................................................................................................................... 12 • Addedadditionalapplications. ............................................................................................................................................. 14 ChangesfromRevisionK(January2015)toRevisionL Page • Changedtypo-temprangefrom185to85 .......................................................................................................................... 4 ChangesfromRevisionJ(March2013)toRevisionK Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 ChangesfromRevisionI(March2013)toRevisionJ Page • ChangedlayoutofNationalSemiconductorDataSheettoTIformat ................................................................................. 17 2 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 5 Pin Configuration and Functions D,DGK,andPPackages 8-PinSOIC,VSSOP,andPDIP YPBPackage (TopView) 8-PinDSBGA (TopView) PinFunctions PIN SOIC,VSSOP,and DSBGANO. NAME I/O DESCRIPTION PDIPNO. 1 A3 GND O Groundreferencevoltage 2 B3 Trigger I Responsiblefortransitionoftheflip-flopfromsettoreset.Theoutputofthe timerdependsontheamplitudeoftheexternaltriggerpulseappliedtothispin 3 C3 Output O Outputdrivenwaveform 4 C2 Reset I Negativepulseappliedtothispintodisableorresetthetimer.Whennotused forresetpurposes,itshouldbeconnectedtoVCCtoavoidfalsetriggering 5 C1 Control I Controlvoltagecontrolsthethresholdandtriggerlevels.Itdeterminesthepulse Voltage widthoftheoutputwaveform.Anexternalvoltageappliedtothispincanalso beusedtomodulatetheoutputwaveform 6 B1 Threshold I Comparesthevoltageappliedtotheterminalwithareferencevoltageof2/3 Vcc.Theamplitudeofvoltageappliedtothisterminalisresponsiblefortheset stateoftheflip-flop. 7 A1 Discharge I Opencollectoroutputwhichdischargesacapacitorbetweenintervals(inphase withoutput).Ittogglestheoutputfromhightolowwhenvoltagereaches2/3of thesupplyvoltage 8 A2 V+ I SupplyvoltagewithrespecttoGND Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Overoperatingfree-airtemperaturerange,unlessotherwisenoted.(1)(2)(3) MIN MAX UNIT Supply 15 V Voltage Input –0.3 (V+)+0.3 V Output 15 V Curent Output 100 mA Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) SeeAN-1112(SNVA009)forDSBGAconsiderations. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1500 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT LMC555IM −40 125 °C TemperatureRange LMC555CM/MM/N/TP −40 85 °C PDIP-8 1126 mW MaximumAllowablePowerDissipation SOIC-8 740 mW at25°C VSSOP-8 555 mW 8-bumpDSBGA 568 mW 6.4 Thermal Information LMC555 THERMALMETRIC(1) SOIC VSSOP PDIP 8-BUMPDSBGA UNIT 8PINS 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 169 225 111 220 °C/W θJA (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 4 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 6.5 Electrical Characteristics TestCircuit,T=25°C,allswitchesopen,RESETtoV unlessotherwisenoted(1) S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I SupplyCurrent V =1.5V 50 150 S S V =5V 100 250 µA S V =12V 150 400 S V ControlVoltage V =1.5V 0.8 1.0 1.2 CTRL S V =5V 2.9 3.3 3.8 V S V =12V 7.4 8.0 8.6 S V DischargeSaturationVoltage V =1.5V,I =1mA 75 150 DIS S DIS mV V =5V,I =10mA 150 300 S DIS V OutputVoltage(Low) V =1.5V,I =1mA 0.2 0.4 OL S O V =5V,I =8mA 0.3 0.6 V S O V =12V,I =50mA 1.0 2.0 S O V OutputVoltage V =1.5V,I =−0.25mA 1.0 1.25 OH S O (High) V =5V,I =−2mA 4.4 4.7 V S O V =12V,I =−10mA 10.5 11.3 S O V TriggerVoltage V =1.5V 0.4 0.5 0.6 TRIG S V V =12V 3.7 4.0 4.3 S I TriggerCurrent V =5V 10 pA TRIG S V ResetVoltage V =1.5V (2) 0.4 0.7 1.0 RES S V V =12V 0.4 0.75 1.1 S I ResetCurrent V =5V 10 pA RES S I ThresholdCurrent V =5V 10 pA THRESH S I DischargeLeakage V =12V 1.0 100 nA DIS S t TimingAccuracy SW2,4Closed V =1.5V 0.9 1.1 1.25 S ms V =5V 1.0 1.1 1.20 S V =12V 1.0 1.1 1.25 S Δt/ΔV TimingShiftwithSupply V =5V±1V 0.3% V S S Δt/ΔT TimingShiftwithTemperature V =5V 75 ppm/°C S f AstableFrequency SW1,3Closed,V =12V 4.0 4.8 5.6 kHz A S f MaximumFrequency Max.Freq.TestCircuit,V =5V 3.0 MHz MAX S t ,t OutputRiseand Max.Freq.TestCircuit 15 ns R F FallTimes V =5V,C =10pF S L t TriggerPropagationDelay V =5V,MeasureDelay PD S 100 ns fromTriggertoOutput (1) Allvoltagesaremeasuredwithrespecttothegroundpin,unlessotherwisespecified. (2) IftheRESETpinistobeusedattemperaturesof−20°CandbelowV isrequiredtobe2.0Vorgreater. S Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 7 Parameter Measurement Information Fordevicepinout,seePinConfigurationandFunctions. Fordevicepinout,seePinConfigurationandFunctions. Figure1.TestCircuit Figure2.MaximumFrequencyTestCircuit 6 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 8 Detailed Description 8.1 Overview The LMC555 is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard package (SOIC, VSSSOP, and PDIP) the LMC555 is also available in a chip-sized package (8-bump DSBGA) using TI’s DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. Whenoperatedasaone-shot,thetimedelayispreciselycontrolledbyasingleexternalresistorandcapacitor.In the astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI’s LMCMOS process extends both the frequency range and the low supply capability. TheLMC555isavailableinan8-pinPDIP,SOIC,VSSOP,and8-bumpDSBGApackage. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-PowerDissipation The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages withtheLMC555. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com Feature Description (continued) 8.3.2 VariousPackagesandCompatibility There are various packages available for use of the LMC555. In addition to the standard package (8-pin SOIC, VSSOP, and PDIP, the LMC555 is also available in a chip-sized package (8-bump DSBGA). The PDIP, SOIC, and VSSOP packages for the LMC555 are pin-for-pin compatible with the 555 series of timers (NE555/SE555/LM555) allowing flexibility in design and unnecessary modifications to PCB schematics and layouts. 8.3.3 OperatesinBothAstableandMonostableMode TheLMC555canoperateinbothastableandmonostablemodedependingontheapplicationrequirements. • Monostable mode: The LMC555 timer acts as a “one-shot” pulse generator. The pulse begins when the LMC555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shorteneddependingontheapplicationbyadjustingtheRandCvalues. • Astable (free-running) mode: The LMC555 timer can operate as an oscillator and puts out a continuous streamofrectangularpulseshavingaspecifiedfrequency.Thefrequencyofthepulsestreamdependsonthe valuesofRA,RB,andC. 8.4 Device Functional Modes 8.4.1 MonostableOperation In this mode of operation, the timer functions as a one-shot (Figure 3). The external capacitor is initially held discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 V to the Trigger S terminal,theflip-flopissetwhichbothreleasestheshortcircuitacrossthecapacitoranddrivestheoutputhigh. Figure3. Monostable(One-Shot) The voltage across the capacitor then increases exponentially for a period of t = 1.1 R C, which is also the time H A that the output stays high, at the end of which time the voltage equals 2/3 V . The comparator then resets the S flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 4 shows the waveforms generated in this mode of operation. Because the charge and the threshold level of the comparator arebothdirectlyproportionaltosupplyvoltage,thetiminginternalisindependentofsupply. 8 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 Device Functional Modes (continued) V =5V TopTrace:Input5V/Div. CC TIME=0.1ms/Div. MiddleTrace:Output5V/Div. R =9.1kΩ BottomTrace:CapacitorVoltage2V/Div. A C=0.01µF Figure4. MonostableWaveforms Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the desired t . The minimum pulse width for the Trigger is 20 ns, and it is 400 ns for the Reset. During the timing H cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal. The output will then remain in the low stateuntilatriggerpulseisagainapplied. When the reset function is not use, it is recommended that it be connected to V to avoid any possibility of false + triggering.Figure5isanomographforeasydeterminationofRCvaluesforvarioustimedelays. NOTE Inmonstableoperation,thetriggershouldbedrivenhighbeforetheendoftimingcycle. Figure5. TimeDelay Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com Device Functional Modes (continued) 8.4.2 AstableOperation If the circuit is connected as shown in Figure 6 (Trigger and Threshold terminals connected together) it will trigger itself and free run as a multivibrator. The external capacitor charges through R + R and discharges A B throughR .Thusthedutycyclemaybepreciselysetbytheratioofthesetworesistors. B Figure6. Astable(VariableDutyCycleOscillator) In this mode of operation, the capacitor charges and discharges between 1/3 V and 2/3 V . As in the triggered S S mode,thechargeanddischargetimes,andthereforethefrequencyareindependentofthesupplyvoltage. Figure7 showsthewaveformgeneratedinthismodeofoperation. V =5V TopTrace:Output5V/Div. CC TIME=20µs/Div. BottomTrace:CapacitorVoltage1V/Div. R =3.9kΩ A R =9kΩ B C=0.01µF Figure7. AstableWaveforms Thechargetime(outputhigh)isgivenby t =0.693(R +R )C (1) 1 A B Andthedischargetime(outputlow)by: t =0.693(R )C (2) 2 B Thusthetotalperiodis: T=t +t =0.693(R +2R )C (3) 1 2 A B Thefrequencyofoscillationis: (4) Figure 8 may be used for quick determination of these RC Values. The duty cycle, as a fraction of total period thattheoutputislow,is: R B D = RA + 2RB (5) 10 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 Device Functional Modes (continued) Figure8. Free-RunningFrequency Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The LMC555 timer can be used a various configurations, but the most commonly used configuration is in monostable mode. A typical application for the LMC555 timer in monostable mode is to turn on an LED for a specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low. Thissimpleapplicationcanbemodifiedtofitanyapplicationrequirement. 9.2 Typical Application Figure9 showstheschematicoftheLM555thatflashesanLEDinmonostablemode. Figure9. SchematicofMonostableModetoFlashanLED 9.2.1 DesignRequirements The main design requirement for this application requires calculating the duration of time for which the output stayshigh.ThedurationoftimeisdependentontheRandCvalues(asshowninmonostablefigure)andcanbe calculatedby:t=1.1*R*Cseconds. t=1.1×R×C (6) 12 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 Typical Application (continued) 9.2.2 DetailedDesignProcedure To allow the LED to flash on for a noticeable amount of time, a 5-second time delay was chosen for this application.Byusingtheequation: t=1.1×R×Cseconds where • RCequals4.545 (7) If R is chosen as 100 kΩ, C = 45.4 µF. The values of R = 100 kΩ and C = 47 µF was chosen based on standard valuesofresistorsandcapacitors. A momentary push button switch connected to ground is connected to the trigger input with a 10-kΩ current limiting resistor pull up to the supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to the output pin with a current limiting resistor in series from the output of the LMC555 to GND.Theresetpinisnotusedandwasconnectedtothesupplyvoltage. 9.2.3 ApplicationCurve The data shown in Figure 10 was collected with the circuit used in the typical applications section. The LM555 wasconfiguredinthemonostablemodewithatimedelayof5.17s.Thewaveformscorrespondto: • TopWaveform(Blue)– Capacitorvoltage • MiddleWaveform(Purple)– Trigger • BottomWaveform(Green)– Output Asthetriggerpinpulseslow,thecapacitorvoltagestartschargingandtheoutputgoeshigh.Theoutputgoeslow as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C value.Forthisexample,thetimedelayis5.17seconds. Figure10.Trigger,CapacitorVoltage,andOutputWaveformsinMonostableMode Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 9.3 Frequency Divider The monostable circuit of Figure 11 can be used as a frequency divider by adjusting the length of the timing cycle.Figure12showsthewaveformsgeneratedinadividebythreecircuit. Figure11. Monostable(One-Shot) 9.3.1 DesignRequirements Designafrequencydividerbyadjustingthelengthofthetimingcycle. 9.3.2 ApplicationCurve Figure12. FrequencyDividerWaveforms 9.4 Pulse Width Modulator When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulsewidthcanbemodulatedbyasignalappliedtothecontrolvoltageterminal.Figure13showsthecircuit,and inFigure14aresomewaveformexamples. Figure13. PulseWidthModulator 9.4.1 DesignRequirements Modulatortheoutputpulsewidthbythesignalappliedtothecontrolvoltageterminal. 14 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 Pulse Width Modulator (continued) 9.4.2 ApplicationCurve Figure14. PulseWidthModulatorWaveforms 9.5 Pulse Position Modulator This application uses the timer connected for astable operation, as in Figure 15, with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 16 shows the waveforms generated for a triangle wave modulationsignal. Figure15. PulsePositionModulator 9.5.1 DesignRequirements Usingastableoperationvarythepulsepositionwithamodulatingsignalappliedtothecontrolvoltageterminal. 9.5.2 ApplicationCurve Figure16. PulsePositionModulatorWaveforms Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 9.6 50% Duty Cycle Oscillator Thefrequencyofoscillationis: f=1/(1.4R C) (8) C Figure17. 50%DutyCycleOscillator 9.6.1 DesignRequirements Anoscillatorwitha50%dutycycleoutput. 16 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

LMC555 www.ti.com SNAS558M–FEBRUARY2000–REVISEDJULY2016 10 Power Supply Recommendations The LM555 requires a voltage supply within 1.5 V to 15 V. Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1 μF in parallel with 1-μF electrolytic. Place the bypass capacitorsascloseaspossibletotheLM555andminimizethetracelength. 11 Layout 11.1 Layout Guidelines Standard PCB rules apply to routing the LMC555. The 0.1 µF in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LMC555. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity. 11.2 Layout Example Thefigurebelowisthebasiclayoutforvariousapplications. • C1– basedontimedelaycalculations • C2– 0.01 µFbypasscapacitorforcontrolvoltagepin • C3– 0.1 µFbypassceramiccapacitor • C4– 1-µFelectrolyticbypasscapacitor • R1– basedontimedelaycalculations • U1– LMC555 Figure18. PCBLayout Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMC555

LMC555 SNAS558M–FEBRUARY2000–REVISEDJULY2016 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 18 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:LMC555

PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LMC555CM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC 555CM LMC555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC & no Sb/Br) 555CM LMC555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 ZC5 LMC555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 ZC5 & no Sb/Br) LMC555CMMX NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 85 ZC5 LMC555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 ZC5 & no Sb/Br) LMC555CMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC 555CM LMC555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 LMC & no Sb/Br) 555CM LMC555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS Call TI | SN Level-1-NA-UNLIM -40 to 85 LMC & no Sb/Br) 555CN LMC555CTP/NOPB ACTIVE DSBGA YPB 8 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 F & no Sb/Br) 02 LMC555CTPX/NOPB ACTIVE DSBGA YPB 8 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 F & no Sb/Br) 02 LMC555IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LMC & no Sb/Br) 555IM LMC555IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LMC & no Sb/Br) 555IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2020 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LMC555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC555CMMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC555CTP/NOPB DSBGA YPB 8 250 178.0 8.4 1.5 1.5 0.66 4.0 8.0 Q1 LMC555CTPX/NOPB DSBGA YPB 8 3000 178.0 8.4 1.5 1.5 0.66 4.0 8.0 Q1 LMC555IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LMC555CMM VSSOP DGK 8 1000 210.0 185.0 35.0 LMC555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMC555CMMX VSSOP DGK 8 3500 367.0 367.0 35.0 LMC555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC555CMX SOIC D 8 2500 367.0 367.0 35.0 LMC555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC555CTP/NOPB DSBGA YPB 8 250 210.0 185.0 35.0 LMC555CTPX/NOPB DSBGA YPB 8 3000 210.0 185.0 35.0 LMC555IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE YPB0008 DSBGA - 0.575 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.575 MAX C SEATING PLANE 0.15 BALL TYP 0.11 0.05 C 1 TYP C 1 SYMM TYP B D: Max = 1.464 mm, Min =1 .403 mm 0.5 TYP E: Max = 1.438 mm, Min =1 .377 mm A 8X 0.18 1 2 3 0.16 0.015 C A B 0.5 TYP SYMM 4215100/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YPB0008 DSBGA - 0.575 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.16) 1 2 3 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.16) 0.05 MAX METAL UNDER 0.05 MIN METAL SOLDER MASK SOLDER MASK ( 0.16) OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS NOT TO SCALE 4215100/B 07/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YPB0008 DSBGA - 0.575 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP (R0.05) TYP 8X ( 0.3) 1 2 3 A (0.5) TYP SYMM B METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.125mm THICK STENCIL SCALE:50X 4215100/B 07/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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