LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization CheckforSamples:LM5642,LM5642X FEATURES DESCRIPTION 1 • TwoSynchronousBuckRegulators The LM5642 series consists of two current mode 2 synchronous buck regulator controllers operating • 180°OutofPhaseOperation 180° out of phase with each other at a normal • 200kHzFixedNominalFrequency:LM5642 switching frequency of 200kHz for the LM5642 and at • 375kHzFixedNominalFrequency:LM5642X 375kHzfortheLM5642X. • SynchronizableSwitchingFrequencyfrom150 Out of phase operation reduces the input RMS ripple kHzto250kHzfortheLM5642and200kHzto current, thereby significantly reducing the required 500kHzfortheLM5642X input capacitance. The switching frequency can be synchronized to an external clock between 150 kHz • 4.5Vto36VInputRange and 250 kHz for the LM5642 and between 200 kHz • 50µAShutdownCurrent and 500 kHz for the LM5642X. The two switching • AdjustableOutputfrom1.3Vto90%ofVin regulator outputs can also be paralleled to operate as adual-phase,singleoutputregulator. • 0.04%(Typical)LineandLoadRegulation Accuracy The output of each channel can be independently • CurrentModeControlwithorwithoutaSense adjusted from 1.3V to 90% of Vin. An internal 5V rail is also available externally for driving bootstrap Resistor circuitry. • IndependentEnable/Soft-startPinsAllow SimpleSequentialStartupConfiguration. Current-mode feedback control assures excellent line and load regulation and wide loop bandwidth for • ConfigurableforSingleOutputParallel excellent response to fast load transients. Current is Operation.(SeeFigure4) sensed across either the Vds of the top FET or • AdjustableCycle-by-cycleCurrentLimit across an external current-sense resistor connected • InputUnder-voltageLockout inserieswiththedrainofthetopFET. • OutputOver-voltageLatchProtection The LM5642 features analog soft-start circuitry that is • OutputUnder-voltageProtectionwithDelay independent of the output load and output capacitance making the soft-start behavior more • ThermalShutdown predictable and controllable than traditional soft-start • SelfDischargeofOutputCapacitorswhenthe circuits. RegulatorisOFF Over-voltage protection is available for both outputs. • TSSOPandHTSSOP(ExposedPAD)Packages AUV-Delaypinisalsoavailabletoallowdelayedshut off time for the IC during an output under-voltage APPLICATIONS event. • EmbeddedComputerSystems Typical Application Circuit • NavigationSystems • TelecomSystems VIN • Set-TopBoxes 4.5V - 36V • WebPAD UV_Delay Vout1 1.3V-0.9VIN • PointOfLoadPowerArchitectures SYNC LM5642/LM5642X SS/ON1 SS/ON2 Vout2 1.3V-0.9VIN 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com Connection Diagram KS1 1 28 RSNS1 KS1 1 28 RSNS1 ILIM1 2 27 SW1 ILIM1 2 27 SW1 COMP1 3 26 HDRV1 COMP1 3 26 HDRV1 FB1 4 25 CBOOT1 FB1 4 25 CBOOT1 SYNC 5 24 VDD1 SYNC 5 24 VDD1 UVDELAY 6 23 LDRV1 UVDELAY 6 23 LDRV1 VLIN5 7 22 VIN VLIN5 7 22 VIN DAP SGND 8 21 PGND SGND 8 21 PGND ON/SS1 9 20 LDRV2 ON/SS1 9 20 LDRV2 ON/SS2 10 19 VDD2 ON/SS2 10 19 VDD2 FB2 11 18 CBOOT2 FB2 11 18 CBOOT2 COMP2 12 17 HDRV2 COMP2 12 17 HDRV2 ILIM2 13 16 SW2 ILIM2 13 16 SW2 KS2 14 15 RSNS2 KS2 14 15 RSNS2 Figure1.TopView Figure2.TopView PINDESCRIPTIONS KS1(Pin1) Thepositive(+)KelvinsensefortheinternalcurrentsenseamplifierofChannel1.Useaseparatetraceto connectthispintothecurrent-sensepoint.ItshouldbeconnectedtoVINascloseaspossibletothecurrent- senseresistor.Whennocurrent-senseresistorisused,connectascloseaspossibletothedrainnodeofthe upperMOSFET. ILIM1(Pin2) CurrentlimitthresholdsettingforChannel1.Itsinksaconstantcurrentof9.9µA,whichisconvertedtoavoltage acrossaresistorconnectedfromthispintoVIN.ThevoltageacrosstheresistoriscomparedwitheithertheV DS ofthetopMOSFETorthevoltageacrosstheexternalcurrentsenseresistortodetermineifanover-current conditionhasoccurredinChannel1. COMP1(Pin3) CompensationpinforChannel1.Thisistheoutputoftheinternaltransconductanceerroramplifier.Theloop compensationnetworkshouldbeconnectedbetweenthispinandthesignalground,SGND(Pin8). FB1(Pin4) Feedbackinputforchannel1.ConnecttoVOUTthroughavoltagedividertosettheChannel1outputvoltage. SYNC(Pin5) TheswitchingfrequencyoftheLM5642canbesynchronizedtoanexternalclock. SYNC = LOW: Free running at 200 kHz for LM5642, and at 375kHz for LM5642X. Channels are 180° out of phase. SYNC=HIGH:Waitingforexternalclock SYNC=FallingEdge:Channel1HDRVpingoeshigh.Channel2HDRVpingoeshighafter2.5µsdelay.The maximumSYNCpulsewidthmustbegreaterthan100ns. ForSYNC=Lowoperation,connectthispintosignalgroundthrougha220kΩresistor. UV_DELAY(Pin6) AcapacitorfromthispintogroundsetsthedelaytimeforUVP.Thecapacitorischargedfroma5µAcurrent source.WhenUV_DELAYchargesto2.3V(typical),thesystemimmediatelylatchesoff.Connectingthispinto groundwilldisabletheoutputunder-voltageprotection. VLIN5(Pin7) Theoutputofaninternal5VLDOregulatorderivedfromVIN.Itsuppliestheinternalbiasforthechipandpowers thebootstrapcircuitryforgatedrive.Bypassthispintosignalgroundwithaminimumof4.7µFceramiccapacitor. SGND(Pin8) Thegroundconnectionforthesignal-levelcircuitry.Itshouldbeconnectedtothegroundrailofthesystem. ON/SS1(Pin9) Channel1enablepin.ThispinisinternallypulleduptoonediodedropaboveVLIN5.Pullingthispinbelow1.2V (open-collectortype)turnsoffChannel1.IfbothON/SS1andON/SS2pinsarepulledbelow1.2V,thewholechip goesintoshutdownmode.Addingacapacitortothispinprovidesasoft-startfeaturethatminimizesinrush currentandoutputvoltageovershoot. ON/SS2(Pin10) Channel2enablepin.SeethedescriptionforPin9,ON/SS1.MaybeconnectedtoON/SS1forsimultaneous startuporforparalleloperation. FB2(Pin11) Feedbackinputforchannel2.ConnecttoVOUTthroughavoltagedividertosettheChannel2outputvoltage. 2 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 PINDESCRIPTIONS(continued) COMP2(Pin12) CompensationpinforChannel2.Thisistheoutputoftheinternaltransconductanceerroramplifier.Theloop compensationnetworkshouldbeconnectedbetweenthispinandthesignalgroundSGND(Pin8). ILIM2(Pin13) CurrentlimitthresholdsettingforChannel2.SeeILIM1(Pin2). KS2(Pin14) Thepositive(+)KelvinsensefortheinternalcurrentsenseamplifierofChannel2.SeeKS1(Pin1). RSNS2(Pin15) Thenegative(-)KelvinsensefortheinternalcurrentsenseamplifierofChannel2.Connectthispintothelowside ofthecurrentsenseresistorthatisplacedbetweenVINandthedrainofthetopMOSFET.WhentheRdsofthe topMOSFETisusedforcurrentsensing,connectthispintothesourceofthetopMOSFET.Alwaysusea separatetracetoformaKelvinconnectiontothispin. SW2(Pin16) Switch-nodeconnectionforChannel2,whichisconnectedtothesourceofthetopMOSFETofChannel2.It servesasthenegativesupplyrailforthetop-sidegatedriver,HDRV2. HDRV2(Pin17) Top-sidegate-driveoutputforChannel2.HDRVisafloatingdriveoutputthatridesonthecorresponding switching-nodevoltage. CBOOT2(Pin18) Bootstrapcapacitorconnection.ItservesasthepositivesupplyrailfortheChannel2top-sidegatedrive.Connect thispintoVDD2(Pin19)throughadiode,andconnectthelowsideofthebootstrapcapacitortoSW2(Pin16). VDD2(Pin19) ThesupplyrailfortheChannel2low-sidegatedrive.ConnectedtoVLIN5(Pin7)througha4.7Ωresistorand bypassedtopowergroundwithaceramiccapacitorofatleast1µF.TiethispintoVDD1(Pin24). LDRV2(Pin20) Low-sidegate-driveoutputforChannel2. PGND(Pin21) Thepowergroundconnectionforbothchannels.Connecttothegroundrailofthesystem. VIN(Pin22) Thepowerinputpinforthechip.Connecttothepositive(+)inputrailofthesystem.Thispinmustbeconnected tothesamevoltagerailasthetopFETdrain(orthecurrentsenseresistorwhenused). LDRV1(Pin23) Low-sidegate-driveoutputforChannel1. VDD1(Pin24) ThesupplyrailforChannel1low-sidegatedrive.TiethispintoVDD2(Pin19). CBOOT1(Pin25) Bootstrapcapacitorconnection.ThispinservesasthepositivesupplyrailfortheChannel1top-sidegatedrive. SeeCBOOT2(Pin18). HDRV1(Pin26) Top-sidegate-driveoutputforChannel1.SeeHDRV2(Pin17). SW1(Pin27) Switch-nodeconnectionforChannel1.SeeSW2(Pin16). RSNS1(Pin28) Thenegative(-)KelvinsensefortheinternalcurrentsenseamplifierofChannel1.SeeRSNS2(Pin15). PGND(DAP) Thepowergroundconnectionforbothchannels.Connecttothegroundrailofthesystem.Useofmultipleviasto internalgroundplaneorGNDlayerhelpstodissipateheatgeneratedbyoutputpower. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ABSOLUTE MAXIMUM RATINGS(1)(2) VoltagesfromtheindicatedpinstoSGND/PGND: VIN,ILIM1,ILIM2,KS1,KS2 −0.3Vto38V SW1,SW2,RSNS1,RSNS2 −0.3to(V +0.3)V IN FB1,FB2,VDD1,VDD2 −0.3Vto6V SYNC,COMP1,COMP2,UVDelay −0.3Vto(VLIN5+0.3)V ON/SS1,ON/SS2 (3) −0.3Vto(VLIN5+0.6)V CBOOT1,CBOOT2 43V CBOOT1toSW1,CBOOT2toSW2 −0.3Vto7V LDRV1,LDRV2 −0.3Vto(VDD+0.3)V HDRV1toSW1,HDRV2toSW2 −0.3V HDRV1toCBOOT1,HDRV2toCBOOT2 +0.3V PowerDissipation(T =25°C)(4) A TSSOP 1.1W HTSSOP 3.4W AmbientStorageTemp.Range −65°Cto+150°C SolderingDwellTime,Temp.(5) Wave 4sec,260°C Infrared 10sec,240°C VaporPhase 75sec,219°C ESDRating (6) 2kV (1) Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRangeindicatesconditionsfor whichthedeviceisintendedtobefunctional,butdoesnotensurespecificperformancelimits.Forensuredspecificationsandtest conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditions.Someperformance characteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) ON/SS1andON/SS2areinternallypulleduptoonediodedropaboveVLIN5.Donotapplyanexternalpull-upvoltagetothesepins.It maycausedamagetotheIC. (4) ThemaximumallowablepowerdissipationiscalculatedbyusingP =(T -T )/θ ,whereT isthemaximumjunction DMAX JMAX A JA JMAX temperature,T istheambienttemperatureandθ isthejunction-to-ambientthermalresistanceofthespecifiedpackage.Thepower A JA dissipationratingsresultsfromusing125°C,25°C,and90.6°C/WforT ,T ,andθ respectively.Aθ of90.6°C/Wrepresentsthe JMAX A JA JA worst-caseconditionofnoheatsinkingofthe28-pinTSSOP.TheHTSSOPpackagehasaθ of29°C/W.TheHTSSOPpackage JA thermalratingsresultsfromtheICbeingmountedona4layerJEDECstandardboardusingthesametemperatureconditionsasthe TSSOPpackageabove.Athermalshutdownwilloccurifthetemperatureexceedsthemaximumjunctiontemperatureofthedevice. (5) Seehttp://www.ti.comforothermethodsofsolderingplasticsmall-outlinepackages. (6) Fortestingpurposes,ESDwasappliedusingthehuman-bodymodel,a100pFcapacitordischargedthrougha1.5kΩresistor. OPERATING RATINGS (1) VIN(VLIN5tiedtoVIN) 4.5Vto5.5V VIN(VINandVLIN5separate) 5.5Vto36V JunctionTemperature −40°Cto+125°C (1) Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRangeindicatesconditionsfor whichthedeviceisintendedtobefunctional,butdoesnotensurespecificperformancelimits.Forensuredspecificationsandtest conditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditions.Someperformance characteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions. 4 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,V =28V,GND=PGND=0V,VLIN5=VDD1=VDD2.Limitsappearinginboldfacetypeapply IN overthespecifiedoperatingjunctiontemperaturerange,(-40°Cto+125°C,ifnototherwisespecified).Specifications appearinginplaintypearemeasuredusinglowdutycyclepulsetestingwithT =25°C (1), (2).Min/Maxlimitsarespecifiedby A design,test,orstatisticalanalysis. Symbol Parameter Conditions Min Typ Max Units System ΔV /V LoadRegulation VIN=28V,V =0.5Vto1.5V 0.04 % OUT OUT compx LineRegulation 5.5V≤VIN≤36V,V =1.25V 0.04 % compx V FeedbackVoltage 5.5V≤VIN≤36V 1.2154 1.2364 1.2574 FB1_FB2 V -20°Cto85°C 1.2179 1.2364 1.2549 I InputSupplyCurrent V >2V VIN ON_SSx 1.1 2.0 mA 5.5V≤VIN≤36V Shutdown (3) 50 110 µA V =V =0V ON_SS1 ON_SS2 VLIN5 VLIN5OutputVoltage IVLIN5=0to25mA, 4.70 5 5.30 V 5.5V≤VIN≤36V V CurrentLimitComparator V =6V CLos IN ±2 ±7.0 mV Offset(VILIMX−VRSNSX) I CurrentLimitSinkCurrent 8.4 9.9 11.4 µA CL I , Soft-StartSourceCurrent V =V =1.5V(on) ss_SC1 ON_ss1 ON_ss2 0.5 2.4 5.0 µA I ss_SC2 I , Soft-StartSinkCurrent V =V =1.5V ss_SK1 ON_ss1 ON_ss2 2 5.5 10 µA I ss_SK2 V , Soft-StartOnThreshold ON_SS1 0.7 1.12 1.4 V V ON_SS2 V Soft-StartTimeout (4) SSTO 3.4 V Threshold I UV_DELAYSourceCurrent UV-DELAY=2V 2 5 9 µA sc_uvdelay I UV_DELAYSinkCurrent UV-DELAY=0.4V 0.2 0.48 1.2 mA sk_uvdelay V UV_DELAYThreshold UVDelay 2.3 V Voltage V FB1,FB2,UnderVoltage Asapercentageofnominaloutputvoltage UVP 75 80.7 86 % ProtectionLatchThreshold (fallingedge) Hysteresis 3.7 % V V Overvoltage AsapercentagemeasuredatV ,V OVP OUT FB1 FB2 107 114 122 % ShutdownLatchThreshold S SW1,SW2ON-Resistance V =V =0.4V 420 487 560 Ω wx_R SW1 SW2 (1) AtypicalisthecenterofcharacterizationdatameasuredwithlowdutycyclepulsetstingatT =25°C.Typicalsarenotensured. A (2) Alllimitsarespecified.Allelectricalcharacteristicshavingroom-temperaturelimitsaretestedduringproductionwithT =T =25°C.All A J hotandcoldlimitsarespecifiedbycorrelatingtheelectricalcharacteristicstoprocessandtemperaturevariationsandapplyingstatistical processcontrol. (3) Bothswitchingcontrollersareoff.ThelinearregulatorVLIN5remainson. (4) WhenSS1andSS2pinsarechargedabovethisvoltageandeitheroftheoutputvoltagesatVout1orVout2isstillbelowtheregulation limit,theundervoltageprotectionfeatureisinitialized. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unlessotherwisespecified,V =28V,GND=PGND=0V,VLIN5=VDD1=VDD2.Limitsappearinginboldfacetypeapply IN overthespecifiedoperatingjunctiontemperaturerange,(-40°Cto+125°C,ifnototherwisespecified).Specifications appearinginplaintypearemeasuredusinglowdutycyclepulsetestingwithT =25°C(1),(2).Min/Maxlimitsarespecifiedby A design,test,orstatisticalanalysis. Symbol Parameter Conditions Min Typ Max Units GateDrive I CBOOTxLeakageCurrent V =V =7V 10 nA CBOOT CBOOT1 CBOOT2 I HDRVxandLDRVxSource V =V =5V,VSWx=0V, SC_DRV CBOOT1 CBOOT2 0.5 A Current HDRVx=LDRVx=2.5V I HDRVxSinkCurrent V =VDDx=5V,V =0V,HDRVX sk_HDRV CBOOTx SWx 0.8 A =2.5V I LDRVxSinkCurrent V =VDDx=5V,V =0V,LDRVX sk_LDRV CBOOTx SWx 1.1 A =2.5V R HDRV1&2SourceOn- V =V =5V, HDRV CBOOT1 CBOOT2 3.1 Ω Resistance V =V =0V SW1 SW2 HDRV1&2SinkOn- 1.5 Ω Resistance R LDRV1&2SourceOn- V =V =5V, LDRV CBOOT1 CBOOT2 3.1 Ω Resistance V =V =0V SW1 SW2 V =V =5V LDRV1&2SinkOn- DD1 DD1 1.1 Ω Resistance OscillatorandSyncControls 5.5≤V ≤36V,LM5642 166 200 226 IN F OscillatorFrequency kHz osc 5.5≤V ≤36V,LM5642X 311 375 424 IN Don_max MaximumOn-DutyCycle V =V =1V,Measuredatpins FB1 FB2 96 98.9 % HDRV1andHDRV2 T MinimumOn-Time 166 ns on_min SS HDRV1andHDRV2Delta ON/SS1=ON/SS2=2V OT_delta 20 250 ns OnTime V SYNCPinMinHighInput 2 1.52 V HS V SYNCPinMaxLowInput 1.44 0.8 V LS ErrorAmplifier I ,I FeedbackInputBias V =1.5V,V =1.5V FB1 FB2 FB1_FIX FB2_FIX 80 ±200 nA Current I , COMPOutputSource V =V =1V, comp1_SC FB1_FIX FB2_FIX 6 127 Icomp2_SC Current VCOMP1=VCOMP2=1V µA -20°Cto85°C 18 I , COMPOutputSinkCurrent V =V =1.5Vand comp1_SK FB1_FIX FB2_FIX 6 118 Icomp2_SK VCOMP1=VCOMP2=0.5V µA -20°Cto85°C 18 gm1,gm2 Transconductance 720 µmho GI , CurrentSenseAmplifier V =1.25V SNS1 COMPx 4.2 5.2 7.5 GI (1&2)Gain SNS2 VoltageReferencesandLinearVoltageRegulators UVLO VLIN5Under-voltage ON/SS1,ON/SS2transition Lockout fromlowtohigh 3.6 4.0 4.4 V ThresholdRising 6 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 C2 10 nF C3 100 pF VIN Vin = 24V+10% 22 2 R1 R2 100: VIN ILIM1 IC1 1 12 k: C6 C1 1 PF LM5642 KS1 28 C4 100 pF 1R07 m: 1500 PVF RSNS1 R6 2.8Arms 6 UV_DELAY HDRV1 26 100: Q1 Si4850EY D3A BAS40-06 C34 100 nF CBOOT1 2257 C7 100 nF VDD L1 Vo1 = 1.8V, 7A SYNC SW1 5 SYNC 4.2 PH(cid:3)(cid:3) R28 23 Q2 7 m:(cid:3) R10 + 3C390 PF 220 k: S1 C11 10 n9F ON/SS1 LPDGRNVD1 21 Si4840DY R11 2k:.26 61.03 Vm:(cid:3) 4 4.99 k: FB1 10 C13 10 nF C14100 pF VIN ON/SS2 S2 C12 10 nF 13 R13 R14 100: 24 ILIM2 VDD VDD1 14 6.8 k: C16 R27 197 VDD2 RSNKSS22 15 C16 100 pFR16 1R01 m5: 15200.8 VPAFrms VLIN5 4.7 : 3 17 100: Q4 COMP1 HDRV2 Si4850EY 12 18 D3B BAS40-06 C27 C26 C19 8.2 nF COMP2 CBOOT2 16 C25 100 nF VDD L2 Vo2 = 3.3V, 4A 1 PF 4.7 PF C20 15 nF SW2 8R.k42:53 R24 1k:3.7 LDRV2 20 Q5 1120 mP+:(cid:3)(cid:3)(cid:3) 8R.1295 + 3C3203 PF 8 SGND FB2 11 Si4840DY R20 k: 6.3V 10 m:(cid:3) 4.99 k: Figure3. Typical2ChannelApplicationCircuit Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com C210 nF C3 100 pF VIN Vin = 30Vr10% R1 R2 100: 22 2 VIN ILIM1 C1 1 PF LMIC56142 KS1 128 C146.190 k0: pF 1R07 m: 1C06 PF RSNS1 R6 50V 2.8Arms 6 26 100: Q1 UV_DELAY HDRV1 Si4850EY C34 100 25 D3A BAS40-06 SYNC nF CBOOT1 27 C7 100 nF VDD L1 Vo = 1.8V, 20A 5 SW1 R28 SYNC 23 Q2 Q3 42..57 mPH:(cid:3)(cid:3)(cid:3) R10 +100C09 PF C10 220 k: 9 ON/SS1 LDRV1 R11 2k.2:6 16V 1 PF C11 21 22 m:(cid:3) S1 PGND 22 nF 4 Si4470DY x 2 4.99 k: FB1 10 ON/SS2 FB2 11 C13 10 nF C14100 pF VIN 24 R13 R14 100: VDD VDD1 ILIM2 13 19 VDD2 KS2 14 16.9 k: C16 R27 7 VLIN5 15 C16 100 pF 1R01 m5: 1500 PVF 4.7: RSNS2 R16 2.8Arms 3 COMP1 17 100: Q4 C27 C26 C19 12 COMP2 HDRV2 D3B BAS40-06 Si4850EY 1 PF 4.7 PF R23 27 nF CBOSOWT22 1186 C25 100 nF VDD L2 11.5 k: 8 SGND LDRV2 20 Q5 Q6 42..57 mPH:(cid:3)(cid:3)(cid:3) + 100C02 P3F C24 16V 1 PF Si4470DY x 2 22 m:(cid:3) Figure4. TypicalSingleChannelApplicationCircuit 8 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 BLOCK DIAGRAM VIN Input Power Supply Voltage SD Disable BG BG gCenuaernrredantotr GenBeiarastor +- reference Current Vref +- 5V LDO IREF bias (Allways ON) VLIN5 From another Ch. 10 PA COMPx Ch1 and Ch2 are identical CoImLIpM ILIMx + - KSx CHx + output - RSNSx ISENSE amp FBx error- amp ONNormal: +-PWM comp anSdh ilfatetcrh CBOOTx + PWM logic R Q control HDRVx BG OSSN: Corrective S Q SWx COHutxput 2 PA ON/OanFdF ramp - Shoot through + S/S + protection ON/SSx control S/S level 0.50V +- CSykciple sequencer VDDx comp LDRVx 7 PA PGNDx FAULT fault TSD UVLO Active discharge Rdson = 5 PA UVP 500: R Q UV_DELAY S Q UV RS QQ coUmOUVpVVPaPPrGa1tor FaCnrHoom.ther 0 2d.e5l aPysTo Ch2 Reset by OSC POR or SD 200 kHz LM5642 or 375 kHz LM5642X SYNC OVP SGND Figure5. BlockDiagram Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS SoftstartWaveforms(No-LoadBothChannels) UVPStartupWaveform(VIN=24V) ON/SS1, 2V/div Vo2, 2V/div Vo1, Vo1, 2V/div 1V/div ON/SS1 and 2, Vo2, 2V/div 5V/div, VIN = 36V Io1, 5A/div Vo1, 2V/div ON/SS1 and 2, 5V/div, VIN = 24V UV DELAY, 2V/div 4 ms/DIV 20ms/DIV Figure6. Figure7. Over-CurrentandUVPShutdown(VIN=24V,Io2=0A) ShutdownWaveforms(VIN=24V,No-Load) Io1, 5A/div Vo2, 1V/div Vo1, 1V/div Vo2, 1V/div Vo1, 1V/div UV DELAY, 1V/div ON/SS1 and 2, 5V/div 20ms/DIV 100ms/DIV Figure8. Figure9. Ch.1LoadTransientResponse(VIN=24V,Vo1=1.8V) Ch.2LoadTransientResponse(VIN=24V,Vo2=3.3V) Io2, 2A/DIV Io1, 2A/DIV Vo2, 100mV/DIV Vo1, 100mV/DIV 100Ps/DIV 100Ps/DIV Figure10. Figure11. 10 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Ch.2LoadTransientResponse(VIN=36V,Vo2=3.3V) Ch.1LoadTransientResponse(VIN=36V,Vo1=1.8V) Io2, 2A/DIV Io1, 2A/DIV Vo2, 100mV/DIV Vo1, 100mV/DIV 100Ps/DIV 100Ps/DIV Figure12. Figure13. InputSupplyCurrentvsTemperature InputSupplyCurrentvsV IN (ShutdownModeV =28V) ShutdownMode(25°C) IN 55 53.5 53 50 52.5 52 45 )A A) ( IPQ 40 I (PQ 51.5 51 50.5 35 50 30 49.5 -40 -20 0 25 50 75 100 125 5.5 8 12 16 20 24 28 32 36 TEMPERATURE (oC) VIN Figure14. Figure15. VLIN5vsTemperature VLIN5vsV (25°C) IN 5.1 5.095 5.08 5.09 VIN = 36V 5.06 5.085 N5 (V) 5.04 VIN = 5.5V N5 (V) 5.08 VLI 5.02 VLI 5.075 5 5.07 4.98 4.96 5.065 -40 -20 0 25 50 75 100 125 5.5 8 12 16 20 24 28 32 36 TEMPERATURE (oC) VIN (V) Figure16. Figure17. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) OperatingFrequencyvsTemperature FBReferenceVoltagevsTemperature (VIN=28V) 1.237 204 1.2365 202 1.236 200 1.2355 )z 198 H k 1.235 ( Y 196 )V C ( VFER 11.2.233445 NEUQ 119924 E 1.2335 R 190 F 1.233 188 1.2325 186 1.232 184 -40 -20 0 25 50 75 100 125 -40 -20 0 25 50 75 100 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure18. Figure19. ErrorAmplifierTranconductanceGain vs EfficiencyvsLoadCurrentUsingResistorSense Temperature Ch.1=1.8V,Ch.2=Off 750 100 VIN = 24V 700 90 650 80 VIN = 36V o) %) mh 600 Y ( 70 P C A gm ( 550 FFICIEN 60 E E 500 50 450 40 400 30 -40 -20 0 25 50 75 100 125 0 1 2 3 4 5 6 7 TEMPERATURE (oC) LOAD CURRENT (A) Figure20. Figure21. 12 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) EfficiencyvsLoadCurrent EfficiencyvsLoadCurrentUsingVdsSense Ch.2=3.3V,Ch.1=Off Ch.2=1.8V,Ch.2=Off 100 100 VIN = 24V 90 VIN = 24V 90 VIN = 36V 80 VIN = 36V Y (%) 80 Y (%) 70 C C N N E E CI CI 60 FI 70 FI F F E E 50 60 40 50 30 0 1 2 3 4 5 0 1 2 3 4 5 6 7 LOAD CURRENT (A) LOAD CURRENT (A) Figure22. Figure23. EfficiencyvsLoadCurrentUsingVdsSense Ch.2=3.3V,Ch.1=Off 100 VIN = 24V 90 VIN = 36V Y (%) 80 C N E CI FI 70 F E 60 50 0 1 2 3 4 5 LOAD CURRENT (A) Figure24. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com OPERATING DESCRIPTIONS SOFT START The ON/SS1 pin has dual functionality as both channel enable and soft start control. Referring to the soft start block diagram is shown in Figure 25, the LM5642 will remain in shutdown mode while both soft start pins are grounded. In a normal application (with a soft start capacitor connected between the ON/SS1 pin and SGND) soft start functions as follows: As the input voltage rises (note, Iss starts to flow when VIN ≥ 2.2V), the internal 5V LDO starts up, and an internal 2.4 µA current charges the soft start capacitor. During soft start, the error amplifier output voltage at the COMPx pin is clamped at 0.55V and the duty cycle is controlled only by the soft start voltage. As the SSx pin voltage ramps up, the duty cycle increases proportional to the soft start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft start capacitor. The higher the capacitance, the slower the output voltage ramps up. When the corresponding output voltage exceeds 98% (typical) of the set target voltage, the regulator switches from soft start to normal operating mode. At this time, the 0.55V clamp at the output of the error amplifier releases and peak current feedback control takes over. Once in peak current feedback control mode, the output voltage of the error amplifierwilltravelwithina0.5Vand2VwindowtoachievePWMcontrol.SeeFigure26. Theamountofcapacitanceneededforadesiredsoft-starttimecanbeapproximatedinthefollowingequation: I x t ss ss C = ss V ss where • I =2.4µAforonechanneland4.8µAifthechannelsareparalleled ss • t isthedesiredsoft-starttime (1) ss Finally, §V • o Vss = 1.5'V + 1„ in (2) Duringsoftstart,over-voltageprotectionandcurrentlimitremainineffect.Theundervoltageprotectionfeatureis activated when the ON/SS pin exceeds the timeout threshold (3.4V typical). If the ON/SSx capacitor is too small, thedutycyclemayincreasetoorapidly,causingthedevicetolatchoffduetooutputvoltageovershootabovethe OVP threshold. This becomes more likely in applications with low output voltage, high input voltage and light load.Acapacitanceof10nFisrecommendedateachsoftstartpintoprovideasmoothmonotonicoutputramp. + R Q - S>R 2PA disable S Q fault ONx ON/SSx + - 1.2V/ ON/OFF ON: 2.4PA source 1.05V comparator 7PA Fault: 5.5PA sink + S/S level - S/S buffer Figure25. Soft-StartandON/OFF 14 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 low clamp + - 0.45V COMPx + - SS:0.55V high clamp OP:2V Figure26. VoltageClampatCOMPxPin FBx shutdown from other CH. latch OVP HDRV: off OVP OVPx LDRV:on OVP 1/2 1.13BG - S Q + R Q 5u UVP A UV_DELAY in: 0.84BG - UVPx out:0.80BG + ONx SS Timeout from other CH. S Q SD R Q power on reset shutdown latch UVP HDRV: off fault LDRV:off TSD UVLO Figure27. OVPandUVP OVER VOLTAGE PROTECTION (OVP) If the output voltage on either channel rises above 113% of nominal, over voltage protection activates. Both channels will latch off. When the OVP latch is set, the high side FET driver, HDRVx, is immediately turned off andthelowsideFETdriver,LDRVx,isturnedontodischargetheoutputcapacitorthroughtheinductor.Toreset the OVP latch, either the input voltage must be cycled, or both channels must be switched off (both ON/SS pins pulledlow). UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY If the output voltage on either channel falls below 80% of nominal, under voltage protection activates. As shown in Figure 27, an under-voltage event will shut off the UV_DELAY MOSFET, which will allow the UV_DELAY capacitor to charge with 5µA (typical). If the UV_DELAY pin voltage reaches the 2.3V threshold both channels will latch off. UV_DELAY will then be disabled and the UV_DELAY pin will return to 0V. During UVP, both the highsideandlowsideFETdriverswillbeturnedoff.IfnocapacitorisconnectedtotheUV_DELAYpin,theUVP latch will be activated immediately. To reset the UVP latch, either the input voltage must be cycled, or both ON/SSpinsmustbepulledlow.TheUVPfunctioncanbedisabledbyconnectingtheUV_DELAYpintoground. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com THERMAL SHUTDOWN The LM5642 IC will enter thermal shutdown if the die temperature exceeds 160°C. The top and bottom FETs of both channels will be turned off immediately. In addition, both soft start capacitors will begin to discharge through separate 5.5 µA current sinks. The voltage on both capacitors will settle to approximately 1.1V, where it will remain until the thermal shutdown condition has cleared. The IC will return to normal operating mode when the die temperature has fallen to below 146°C. At this point the two soft start capacitors will begin to charge with their normal 2.4 µA current sources. This allows a controlled return to normal operation, similar to the soft start during turn-on. If the thermal shutdown condition clears before the voltage on the soft start capacitors has fallen to1.1V,thecapacitorswillfirstbedischargedto1.1V,andthenimmediatelybeginchargingbackup. OUTPUT CAPACITOR DISCHARGE Each channel has an embedded 480Ω MOSFET with the drain connected to the SWx pin. This MOSFET will discharge the output capacitor of its channel if its channel is off, or the IC enters a fault state caused by one of thefollowingconditions: 1. UVP 2. UVLO If an output over voltage event occurs, the HDRVx will be turned off and LDRVx will be turned on immediately to dischargetheoutputcapacitorsofbothchannelsthroughtheinductors. BOOTSTRAP DIODE SELECTION The bootstrap diode and capacitor form a supply that floats above the switch node voltage. VLIN5 powers this supply, creating approximately 5V (minus the diode drop) which is used to power the high side FET drivers and driver logic. When selecting a bootstrap diode, Schottky diodes are preferred due to their low forward voltage drop, but care must be taken for circuits that operate at high ambient temperature. The reverse leakage of some Schottky diodes can increase by more than 1000x at high temperature, and this leakage path can deplete the charge on the bootstrap capacitor, starving the driver and logic. Standard PN junction diodes and fast rectifier diodes can also be used, and these types maintain tighter control over reverse leakage current across temperature. SWITCHING NOISE REDUCTION Power MOSFETs are very fast switching devices. In synchronous rectifier converters, the rapid increase of drain current in the top FET coupled with parasitic inductance will generate unwanted Ldi/dt noise spikes at the source node of the FET (SWx node) and also at the VIN node. The magnitude of this noise will increase as the output current increases. This parasitic spike noise may produce excessive electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, it must be suppressed using one of the following methods. When using resistor based current sensing, it is strongly recommended to add R-C filters to the current sense amplifier inputs as shown in Figure 29. This will reduce the susceptibility to switching noise, especially during heavy load transients and short on time conditions. The filter components should be connected as close as possibletotheIC. AsshowninFigure28,addingaresistorinserieswiththeHDRVxpinwillslowdownthegatedrive,thusslowing theriseandfalltimeofthetopFET,yieldingalongerdraincurrenttransitiontime. Usually a 3.3Ω to 4.7Ω resistor is sufficient to suppress the noise. Top FET switching losses will increase with higherresistancevalues. Small resistors (1-5 ohms) can also be placed in series with the CBOOTx pin to effectively reduce switch node ringing. A CBOOT resistor will slow the rise time of the FET, whereas a resistor at HDRV will increase both rise andfalltimes. 16 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 CBOOTx HDRVx Rsw 4R7 SWx 0.1 PF Figure28. HDRVSeriesResistor CURRENT SENSING AND LIMITING As shown in Figure 29, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET. The advantages of sensing current across the top FET are reducedpartscount,costandpowerloss. The R of the top FET is not as stable over temperature and voltage as a sense resistor, hence great care DS-ON must be used in layout for V sensing circuits. At input voltages above 30V, the maximum recommended output DS currentis5Aperchannel. Keeping the differential current-sense voltage below 200mV ensures linear operation of the current sense amplifier. Therefore, the R of the top FET or the current sense resistor must be small enough so that the DS-ON current sense voltage does not exceed 200 mV when the top FET is on. There is a leading edge blanking circuit that forces the top FET on for at least 166ns. Beyond this minimum on time, the output of the PWM comparator is used to turn off the top FET. Additionally, a minimum voltage of at least 50 mV across Rsns is recommended toensureahighSNRatthecurrentsenseamplifier. Assumingamaximumof200mVacrossRsns,thecurrentsenseresistorcanbecalculatedasfollows: where • Imaxisthemaximumexpectedloadcurrent,includingoverloadmultiplier(ie:120%) • Iripistheinductorripplecurrent(seeEquation17) (3) The above equation gives the maximum allowable value for Rsns. Conduction losses will increase with larger Rsns,thusloweringefficiency. The peak current limit is set by an external resistor connected between the ILIMx pin and the KSx pin. An internal 10 µA current sink on the ILIMx pin produces a voltage across the resistor to set the current limit threshold which is then compared to the current sense voltage. A 10 nF capacitor across this resistor is required tofilterunwantednoisethatcouldimproperlytripthecurrentlimitcomparator. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com 10 PA LIMx comp LIMx 13k + POWER - SUPPLY KSx 10 nF 100 + - ISEN SE RSNSx 100 20m amp 100 pF 100 pF Figure29. CurrentSenseandCurrentLimit Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately. The comparator is disabled when the top FET is turned off and during the leading edge blanking time. The equation forcurrentlimitresistor,R ,isasfollows: lim where • Ilimistheloadcurrentatwhichthecurrentlimitcomparatorwillbetripped (4) When sensing current across the top FET, replace Rsns with the R of the FET. This calculated Rlim value DS-ON specifiesthattheminimumcurrentlimitwillnotbelessthanImax.Itisrecommendedthata1%toleranceresistor beused. When sensing across the top FET (V sensing), R will show more variation than a current-sense resistor, DS DS-ON largely due to temperature variation. R will increase proportional to temperature according to a specific DS-ON temperature coefficient. Refer to the FET manufacturer's datasheet to determine the range of R values over DS-ON operating temperature or see the Component Selection section (Equation 27) for a calculation of maximum R DS- . This will prevent R variations from prematurely tripping the current limit comparator as the operating ON DS-ON temperatureincreases. ToensureaccuratecurrentsensingusingV sensing,specialattentioninboardlayoutisrequired.TheKSxand DS RSNSx pins require separate traces to form a Kelvin connection at the corresponding current sense nodes. In addition,thefiltercomponentsR14,R16,C14,C15shouldberemoved. INPUT UNDER VOLTAGE LOCKOUT (UVLO) The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical). Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480Ω MOSFETs will be turned on to discharge the output capacitors through the SWx pins. When the input voltage is below the UVLO threshold, the ON/SS pins will sink 5mA to discharge the soft start capacitors and turn off both channels. As the inputvoltageincreasesagainabove4.0V,UVLOwillbede-activated,andthedevicewillrestartthroughanormal soft start phase. If the voltage at VLIN5 remains below 4.5V, but above the 4.0V UVLO threshold, the device cannotbeensuredtooperatewithinspecification. If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately 200 mVbelowtheinputvoltage. 18 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 DUAL-PHASE PARALLEL OPERATION In applications with high output current demand, the two switching channels can be configured to operate as a two phase converter to provide a single output voltage with current sharing between the two switching channels. This approach greatly reduces the stress and heat on the output stage components while lowering input ripple current. The inductor ripple currents also cancel to a varying degree which results in lowered output ripple voltage. Figure 4 shows an example of a typical two-phase circuit. Because precision current sense is the primary design criteria to ensure accurate current sharing between the two channels, both channels must use external sense resistors for current sensing. To minimize the error between the error amplifiers of the two channels, tie the feedback pins FB1 and FB2 together and connect to a single voltage divider for output voltage sensing. Also, tie the COMP1 and COMP2 together and connect to the compensation network. ON/SS1 and ON/SS2mustbetiedtogethertoenableanddisablebothchannelssimultaneously. EXTERNAL FREQUENCY SYNC TheLM5642serieshastheabilitytosynchronizetoexternalsourcesinordertosettheswitchingfrequency.This allows the LM5642 to use frequencies from 150 kHz to 250 kHz and the LM5642X to use frequencies from 200 kHz to 500 kHz. Lowering the switching frequency allows a smaller minimum duty cycle, DMIN, and hence a greater range between input and output voltage. Increasing switching frequency allows the use of smaller output inductors and output capacitors (see Component Selection). In general, synchronizing all the switching frequenciesinmulti-convertersystemsmakesfilteringoftheswitchingnoiseeasier. The sync input can be from a system clock, from another switching converter in the system, or from any other periodic signal with a logic low-level less than 1.4V and a logic high level greater than 2V. Both CMOS and TTL levelinputsareacceptable. The LM5642 series uses a fixed delay between Channel 1 and Channel 2. The nominal switching frequency of 200kHz for the LM5642 corresponds to a switching period of 5µs. Channel 2 always turns its high-side switch on 2.5µs after Channel 1 Figure 30 (a). When the converter is synchronized to a frequency other than 200kHz, the switching period is reduced or increased, while the fixed delay between Channel 1 and Channel 2 remains constant.Thephasedifferencebetweenchannelsisthereforenolonger180°.Attheextremesofthesyncrange, the phase difference drops to 135° Figure 30 (b) and Figure 30 (c). The result of this lower phase difference is a reduction in the maximum duty cycle of one channel that will not overlap the duty cycle of the other. As shown in Input Capacitor Selection section, when the duty cycle D1 for Channel 1 overlaps the duty cycle D2 for Channel 2, the input rms current increases, requiring more input capacitors or input capacitors with higher ripple current ratings. The new, reduced maximum duty cycle can be calculated by multiplying the sync frequency (in Hz) by 2.5x10-6 (the fixed delay in seconds). The same logic applies to the LM5642X. However the LM5642X has a nominal switching frequency of 375kHz which corresponds to a period of 2.67µs. Therefore channel 2 of the LM5642Xalwaysbeginsit'speriodafter1.33µs. D =FSYNC*2.5x10-6 (5) MAX At a sync frequency of 150 kHz, for example, the maximum duty cycle for Channel 1 that will not overlap Channel2wouldbe37.5%.At250kHz,itisthedutycycleforChannel2thatisreducedtoaD of37.5%. MAX Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com F = 200 kHz SW 5 Ps D1 5 Ps D2 2.5 Ps (a) F = 150 kHz SW 6.67 Ps D1 6.67 Ps D2 2.5 Ps (b) F = 250 kHz SW 4 Ps D1 4 Ps D2 2.5 Ps (c) Figure30. PeriodFixedDelayExample Component Selection OUTPUTVOLTAGESETTING The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 31. The resistor valuescanbedeterminedbythefollowingequation: where • Vfb=1.238V (6) AlthoughincreasingthevalueofR1andR2willincreaseefficiency,thiswillalsodecreaseaccuracy.Therefore,a maximum value is recommended for R2 in order to keep the output within .3% of Vnom. This maximum R2 value shouldbecalculatedfirstwiththefollowingequation: where • 200nAisthemaximumcurrentdrawnbyFBxpin (7) 20 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 Vout R2 FBx GND R1 Figure31. OutputVoltageSetting Example:Vnom=5V,Vfb=1.2364V,Ifbmax=200nA. (8) Choose60K (9) The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum output voltage is determined by the Cycle Skip Comparator. This circuitry skips the high side FET ON pulse when the COMP pin voltage is below 0.5V at the beginning of a cycle. The converter will continue to skip every other pulse until the duty cycle (and COMP pin voltage) rise above 0.5V, effectively halving the switching frequency. Maximum output voltage is determined by the Dropout circuitry, which skips the low side FET ON pulse whenever the COMP pin voltage exceeds the ramp voltage derived from the current sense. Up to three low side pulsesmaybeskippedinarowbeforeaminimumon-timepulsemustbeappliedtothelowsideFET. Figure 32 shows the range of ouput voltage (for Io = 3A) with respect to input voltage that will keep the converter fromenteringeitherSkipCycleorDropoutmode. For input voltages below 5.5V, VLIN5 must be connected to Vin through a small resistor (approximately 4.7 ohm).ThiswillensurethatVLIN5doesnotfallbelowtheUVLOthreshold. 35 30 25 T 20 U O V 15 Operating Region 10 5 0 4 8 12 16 20 24 28 32 36 VIN Figure32. OutputVoltageRange Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com Output Capacitor Selection In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worst- case load transients, special consideration should be given to output capacitor selection. The total combined ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple voltagemustbelow,startingfromtherequiredoutputvoltageripplewilloftenresultinfewerdesigniterations. ALLOWEDTRANSIENTVOLTAGEEXCURSION Theallowedoutputvoltageexcursionduringaloadtransient(ΔVc_s)is: where • ±δ%istheoutputvoltageregulationwindow • ±ε%istheoutputvoltageinitialaccuracy (10) Example:Vnom=5V,δ%=7%,ε%=3.4%,Vrip=40mVpeaktopeak. (11) MAXIMUMESRCALCULATION Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the total combined ESR (Re) is too high, the load transient requirement will not be met, no matter how large the capacitance. ThemaximumallowedtotalcombinedESRis: (12) Since the ripple voltage is included in the calculation of ΔVc_s, the inductor ripple current should not be included intheworst-caseloadcurrentexcursion.Simplyusetheworst-caseloadcurrentexcursionforΔIc_s. Example:ΔVc_s=160mV,ΔIc_s=3A.ThenRe_max=53.3mΩ. Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more capacitorsthanthenumberdeterminedbythiscriterionshouldbeusedinparallel. MINIMUMCAPACITANCECALCULATION In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that happens when the input voltage is the highest and when the current switching cycle has just finished. The correspondingminimumcapacitanceiscalculatedasfollows: (13) Notice it is already assumed the total ESR, Re, is no greater than Re_max, otherwise the term under the square root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L value should be calculated before C and after Re (see Inductor Selection below). Example: Re = 20 mΩ, min Vnom=5V,ΔVc_s=160mV,ΔIc_s=3A,L=8 µH (14) Generallyspeaking,C decreaseswithdecreasingRe,ΔIc_s,andL,butwithincreasingVnomand ΔVc_s. min 22 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 Inductor Selection The size of the output inductor can be determined from the desired output ripple voltage, Vrip, and the impedance of the output capacitors at the switching frequency. The equation to determine the minimum inductancevalueisasfollows: (15) In the above equation, Re is used in place of the impedance of the output capacitors. This is because in most cases, the impedance of the output capacitors at the switching frequency is very close to Re. In the case of ceramiccapacitors,replaceRewiththetrueimpedanceattheswitchingfrequency. Example:Vin=36V,Vo=3.3V,V =60mV,Re=20mΩ,F=200kHz. RIP 36 - 3.3 3.3 x 0.02 L = x = 5PH min 200kHz x 36 .060 (16) The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output voltages and load transient requirements should be considered. If an inductance value larger than Lmin is selected,makesurethattheCminrequirementisnotviolated. Priority should be given to parameters that are not flexible or more costly. For example, if there are very few types of capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of 3.2capacitorscanbereducedto3capacitors. Since inductor ripple current is often the criterion for selecting an output inductor, it is a good idea to double- checkthisvalue.Theequationis: (17) Also important is the ripple content, which is defined by Irip /Inom. Generally speaking, a ripple content of less than50%isok.Largerripplecontentwillcausetoomuchpowerlossintheinductor. Example:Vin=36V,Vo=3.3V,F=200kHz,L=5µH,3AmaxI OUT 36 - 3.3 3.3 I = x = 3A rip 200kHz x 5x10-6 36 (18) 3Ais100%ripplewhichistoohigh. Inthiscase,theinductorshouldbereselectedonthebasisofripplecurrent. Example:40%ripple,40%•3A=1.2A 36 - 3.3 3.3 1.2A = x L x 200kHz 36 (19) 36 - 3.3 3.3 L = x = 12.5PH 200kHz x 1.2A 36 (20) When choosing the inductor, the saturation current should be higher than the maximum peak inductor current andtheRMScurrentratingshouldbehigherthanthemaximumloadcurrent. Input Capacitor Selection The fact that the two switching channels of the LM5642 are 180° out of phase will reduce the RMS value of the ripple current seen by the input capacitors. This will help extend input capacitor life span and result in a more efficient system. Input capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the maximum input voltage. In applications in which output voltages are less than half of the input voltage, the corresponding duty cycles will be less than 50%. This means there will be nooverlapbetweenthetwochannels'inputcurrentpulses. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com TheequationforcalculatingthemaximumtotalinputrippleRMScurrentfordutycyclesunder50%is: where • I1ismaximumloadcurrentofChannel1 • I2isthemaximumloadcurrentofChannel2 • D1isthedutycycleofChannel1 • D2isthedutycycleofChannel2 (21) Example:Imax_1=3.6A,Imax_2=3.6A,D1=0.42,andD2=0.275 (22) Choose input capacitors that can handle 1.66A ripple RMS current at highest ambient temperature. In applications where output voltages are greater than half the input voltage, the corresponding duty cycles will be greater than 50%, and there will be overlapping input current pulses. Input ripple current will be highest under thesecircumstances.TheinputRMScurrentinthiscaseisgivenby: (23) Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles. Thisequationshouldbeusedwhenbothdutycyclesareexpectedtobehigherthan50%. If the LM5642 is being used with an external clock frequency other than 200kHz, or 375 kHz for the LM5642X, the preceding equations for input rms current can still be used. The selection of the first equation or the second changes because overlap can now occur at duty cycles that are less than 50%. From the EXTERNAL FREQUENCY SYNC section, the maximum duty cycle that ensures no overlap between duty cycles (and hence inputcurrentpulses)is: D =F *2.5x10-6 (24) MAX SYNC There are now three distinct possibilities which must be considered when selecting the equation for input rms current.ThefollowingappliesfortheLM5642,andalsotheLM5642Xbyreplacing200kHzwith375kHz: 1. BothdutycyclesD andD arelessthanD .Inthiscase,thefirst,simpleequationcanalwaysbeused. 1 2 MAX 2. One duty cycle is greater than D and the other duty cycle is less than D . In this case, the system MAX MAX designer can take advantage of the fact that the sync feature reduces D for one channel, but lengthens it MAX for the other channel. For F < 200kHz, D is reduced to D while D actually increases to (1-D ). SYNC 1 MAX 2 MAX For F > 200kHz, D is reduced to D while D increases to (1-D ). By using the channel reduced to SYNC 2 MAX 1 MAX D for the lower duty cycle, and the channel that has been increased for the higher duty cycle, the first, MAX simplermsinputcurrentequationcanbeused. 3. Both duty cycles are greater than D . This case is identical to a system at 200 kHz where either duty cycle MAX is 50% or greater. Some overlap of duty cycles is specified, and hence the second, more complicated rms inputcurrentequationmustbeused. Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the capacitor should then be selected based on hold up time requirements. Bench testing for individual applications is still the best way to determine a reliable input capacitor value. Input capacitors should always be placed as close as possible to the current sense resistor or the drain of the top FET. When high ESR capacitors such as tantalum are used, a 1µF ceramic capacitor should be added as closely as possible to the high-side FET drain andlow-sideFETsource. 24 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 MOSFET Selection BOTTOMFETSELECTION During normal operation, the bottom FET is switching on and off at almost zero voltage. Therefore, only conduction losses are present in the bottom FET. The most important parameter when selecting the bottom FET is the on-resistance (R ). The lower the on-resistance, the lower the power loss. The bottom FET power loss DS-ON peaks at maximum input voltage and load current. The equation for the maximum allowed on-resistance at room temperatureforagivenFETpackage,is: where • Tj_maxisthemaximumallowedjunctiontemperatureintheFET • Ta_maxisthemaximumambienttemperature • R isthejunction-to-ambientthermalresistanceoftheFET θja • TCisthetemperaturecoefficientoftheon-resistancewhichistypicallyintherangeof4000ppm/°C (25) If the calculated R is smaller than the lowest value available, multiple FETs can be used in parallel. DS-ON (MAX) This effectively reduces the I term in the above equation, thus reducing R . When using two FETs in max DS-ON parallel, multiply the calculated R by 4 to obtain the R for each FET. In the case of three DS-ON (MAX) DS-ON (MAX) FETs,multiplyby9. (26) If the selected FET has an Rds value higher than 35.3Ω, then two FETs with an R less than 141 mΩ (4 x DS-ON 35.3 mΩ) can be used in parallel. In this case, the temperature rise on each FET will not go to Tj_max because eachFETisnowdissipatingonlyhalfofthetotalpower. TOPFETSELECTION The top FET has two types of losses: switching loss and conduction loss. The switching losses mainly consist of crossover loss and losses related to the low-side FET body diode reverse recovery. Since it is rather difficult to estimate the switching loss, a general starting point is to allot 60% of the top FET thermal capacity to switching losses. The best way to precisely determine switching losses is through bench testing. The equation for calculatingtheonresistanceofthetopFETisthus: (27) Example:Tj_max=100°C,Ta_max=60°C,Rqja=60°C/W,Vin_min=5.5V,Vnom=5V,andIload_max=3.6A. Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com (28) WhenusingFETsinparallel,thesameguidelinesapplytothetopFETasapplytothebottomFET. Loop Compensation The general purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked to determine small-signal performance. Loop gain is equal to the product of control-output transfer function and the feedback transfer function (the compensation network transfer function). Generally speaking it is desirable to have a loop gain slope that is roughly -20dB /decade from a very low frequency to well beyond the crossover frequency. The crossover frequency should not exceed one-fifth of the switching frequency. The higher the bandwidth, the faster the load transient response speed will be. However, if the duty cycle saturates during a load transient, further increasing the small signal bandwidthwillnothelp.Sincethecontrol-outputtransferfunctionusuallyhasverylimitedlowfrequencygain,itis a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain will be relatively large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or linevariations).Therestofthecompensationschemedependshighlyontheshapeofthecontrol-outputplot. 20 0 Asymptoti c 0 -45 NIAG)Bd(-20 -90 )°( ESA Phas H P e -40 -135 Gain -60 -180 1 10 100 10 100 1M k k k FREQUENCY (Hz) Figure33. Control-OutputTransferFunction As shown in Figure 33, the control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the switching frequency). The following can be done to create a -20dB /decade roll-off of the loop gain: Place the first pole at 0Hz, the first zero at fp, the second pole at fz, and the second zero at fn. The resultingfeedbacktransferfunctionisshowninFigure34. B) -20dB/dec (fp1 is at zero frequency) d GAIN ( -20dB/dec B fz1 fp2 fz2 FREQUENCY Figure34. FeedbackTransferFunction 26 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determinedapproximatelybythefollowingequations: (29) 1 1 - D - .5 fP =2SRO CO+ 2SfLCO (30) Since fp is determined by the output network, it will shift with loading (Ro). It is best to use a minimum Iout value ofapproximately100mAwhendeterminingthemaximumRovalue. Example:Re=20mΩ,Co=100uF,Romax=5V/100mA=50Ω: (31) (32) First determine the minimum frequency (fpmin) of the pole across the expected load range, then place the first compensationzeroatorbelowthatvalue.Oncefpminisdetermined,Rc1shouldbecalculatedusing: where • BisthedesiredgaininV/Vatfp(fz1) • gmisthetransconductanceoftheerroramplifier • R1andR2arethefeedbackresistors (33) Againvaluearound10dB(3.3v/v)isgenerallyagoodstartingpoint. Example:B=3.3v/v,gm=650m,R1=20kKΩ,R2=60.4kΩ: (34) BandwidthwillvaryproportionaltothevalueofRc1.Next,Cc1canbedeterminedwiththefollowingequation: (35) Example:fpmin=995Hz,Rc1=20kΩ: (36) Thecompensationnetwork(Figure35)willalsointroducealowfrequencypolewhichwillbecloseto0Hz. A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted Rc2(seeFigure35).Theminimumvalueforthiscapacitorcanbecalculatedby: (37) Cc2 may not be necessary, however it does create a more stable control loop. This is especially important with highloadcurrentsandincurrentsharingmode. Example:fz=80kHz,Rc1=20kΩ: (38) Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com A second zero can also be added with a resistor in series with Cc2. If used, this zero should be placed at fn, where the control to output gain rolls off at -40dB/dec. Generally, fn will be well below the 0dB level and thus will havelittleeffectonstability.Rc2canbecalculatedwiththefollowingequation: (39) V o V c g m R CC1 CC2 2 RC1 RC2 compensation R1 network Figure35. CompensationNetwork PCB Layout Considerations To produce an optimal power solution with the LM5642 series, good layout and design of the PCB are as importantasthecomponentselection.Thefollowingareseveralguidelinestoaidincreatingagoodlayout. KELVINTRACESFORSENSELINES When using the current sense resistor to sense the load current connect the KS pin using a separate trace to VIN, as close as possible to the current-sense resistor. The RSNS pin should be connected using a separate trace to the low-side of the current sense resistor. The traces should be run parallel to each other to give common mode rejection. Although it can be difficult in a compact design, these traces should stay away from the output inductor and switch node if possible, to avoid coupling stray flux fields. When a current-sense resistor is not used the KS pin should be connected as close as possible to the drain node of the upper MOSFET and the RSNS pin should be connected as close as possible to the source of the upper MOSFET using Kelvin traces. To furtherhelpminimizenoisepickuponthesenselinesistouseRCfilteringontheKSandRSNSpins. SEPARATEPGNDANDSGND Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components like the compensation and feedback resistors should be connected to a section of this internal SGND plane. The SGND section of the plane should be connected to the power ground at only one point. The best place to connecttheSGNDandPGNDisrightatthePGNDpin.. MINIMIZETHESWITCHNODE The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use just enough copper to give low impedance to the switching currents, preferably in the form of a wide, but short, tracerun. LOWIMPEDANCEPOWERPATH The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the same layer. Vias add resistance and inductance to the power path, and have relatively high impedance connections to the internal planes. If high switching currents must be routed through vias and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. The power components should be kept closetogether.Thelongerthepathsthatconnectthem,themoretheyactasantennas,radiatingunwantedEMI. PleaseseeAN-1229(literaturenumberSNVA054)forfurtherPCBlayoutconsiderations. 28 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 Table1.BillOfMaterialsforFigure324Vto1.8,3.3VLM5642 ID PartNumber Type Size Parameters Qty Vendor U1 LM5642 Dual TSSOP-28 1 TI Synchronous Controller Q1,Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2,Q5 Si4840DY N-MOSFET SO-8 40V 2 Vishay D3 BAS40-06 SchottkyDiode SOT-23 40V 1 Vishay L1 RLF12560T-4R2N100 Inductor 12.5x12.5x6mm 4.2µH,7mΩ10A 1 TDK L2 RLF12545T-100M5R1 Inductor 12.5x12.5x4.5mm 10µH,12mΩ5.1A 1 TDK C1 C3216X7R1H105K Capacitor 1206 1µF,50V 1 TDK C3,C4,C14, VJ1206Y101KXXAT Capacitor 1206 100pF,25V 3 Vishay C15 C27 C2012X5R1C105K Capacitor 0805 1µF,16V 1 TDK C6,C16 C5750X5R1H106M Capacitor 2220 10µF50V,2.8A 2 TDK C9,C23 6TPD330M Capacitor 7.3x4.3x3.8mm 330µF,6.3V,10mΩ 2 Sanyo C2,C11,C12, VJ1206Y103KXXAT Capacitor 1206 10nF,25V 4 Vishay C13 C7,C25,C34 VJ1206Y104KXXAT Capacitor 1206 100nF,25V 3 Vishay C19 VJ1206Y822KXXAT Capacitor 1206 8.2nF10% 1 Vishay C20 VJ1206Y153KXXAT Capacitor 1206 15nF10% 1 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7µF25V 1 TDK R1 CRCW1206123J Resistor 1206 12kΩ5% 1 Vishay R2,R6,R14, CRCW1206100J Resistor 1206 100Ω5% 1 Vishay R16 R13 CRCW1206682J Resistor 1206 6.8kΩ12% 1 Vishay R7,R15 WSL-2512.0101% Resistor 2512 10mΩ1W 2 Vishay R8,R9,R12, CRCW1206000Z Resistor 1206 0Ω 8 Vishay R17,R18,R21, R31,R32 R10 CRCW12062261F Resistor 1206 2.26kΩ1% 1 Vishay R23 CRCW12068451F Resistor 1206 8.45kΩ1% 1 Vishay R24 CRCW12061372F Resistor 1206 13.7kΩ1% 1 Vishay R11,R20 CRCW12064991F Resistor 1206 4.99kΩ1% 2 Vishay R19 CRCW12068251F Resistor 1206 8.25kΩ1% 1 Vishay R27 CRCW12064R7J Resistor 1206 4.7Ω5% 1 Vishay R28 CRCW1206224J Resistor 1206 220kΩ5% 1 Vishay Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com Table2.BillofMaterialsforFigure430Vto1.8V,20ALM5642 ID PartNumber Type Size Parameters Qty Vendor U1 LM5642 Dual TSSOP-28 1 TI Synchronou sController Q1,Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2,Q3,Q5,Q6 Si4470DY N-MOSFET SO-8 60V 4 Vishay D3 BAS40-06 Schottky SOT-23 40V 1 Vishay Diode L1,L2 RLF12560T-2R7N110 Inductor 12.5x12.5x6mm 2.7µH,4.5mΩ11.5A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1µF,50V 1 TDK C10,C24,C27 C2012X5R1C105K Capacitor 0805 1µF,16V 3 TDK C6,C16,C28, C5750X5R1H106M Capacitor 2220 10µF50V,2.8A 4 TDK C30 C9,C23 16MV1000WX Capacitor 10mmD20mmH 1000µF,16V,22mΩ 2 Sanyo C2,C13 VJ1206Y103KXXAT Capacitor 1206 10nF,25V 2 Vishay C11 VJ1206Y223KXXAT Capacitor 1206 22nF,25V 1 Vishay C7,C25,C34 VJ1206Y104KXXAT Capacitor 1206 100nF,25V 3 Vishay C19 VJ1206Y273KXXAT Capacitor 1206 27nF10% 1 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7µF25V 1 TDK R1,R13 CRCW1206123J Resistor 1206 16.9kΩ1% 1 Vishay R2,R6,R14, CRCW1206100J Resistor 1206 100Ω5% 1 Vishay R16 R7,R15 WSL-2512.0101% Resistor 2512 10mΩ1W 2 Vishay R8,R9,R12, CRCW1206000Z Resistor 1206 0Ω 8 Vishay R17,R18,R21, R31,R32 R10 CRCW12062261F Resistor 1206 2.26kΩ1% 1 Vishay R11 CRCW12064991F Resistor 1206 4.99kΩ1% 1 Vishay R23 CRCW12061152F Resistor 1206 11.5kΩ1% 1 Vishay R27 CRCW12064R7J Resistor 1206 4.7Ω5% 1 Vishay R28 CRCW1206224J Resistor 1206 220kΩ5% 1 Vishay 30 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 Table3.BillOfMaterialsBasedonFigure3V =9-16V,V =1.5V,1.8V,5ALM5642X in O1,2 ID PartNumber Type Size Parameters Qty Vendor U1 LM5642X Dual TSSOP-28 1 TI Synchronous Controller Q1,Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2,Q5 Si4840DY N-MOSFET SO-8 40V 2 Vishay D3 BA54A SchottkyDiode SOT-23 30V 1 Vishay L1,L2 RLF12545T-4R2N100 Inductor 12.5x12.5x4.5mm 4.2µH,7mΩ6.5A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1µF,50V 1 TDK C3,C4,C14, VJ1206Y101KXXAT Capacitor 1206 100pF,25V 4 Vishay C15 C27 C2012X5R1C105K Capacitor 0805 1µF,16V 1 TDK C6,C28 C5750X7R1H106M Capacitor 2220 10µF50V,2.8A 2 TDK C9,C23 C4532X7R0J107M Capacitor 1812 100µF,6.3V,1mΩ 2 TDK C2,C11,C12, VJ1206Y103KXXAT Capacitor 1206 10nF,25V 4 Vishay C13 C7,C25,C34 VJ1206Y104KXXAT Capacitor 1206 100nF,25V 3 Vishay C18,C20 VJ1206Y473KXXAT Capacitor 1206 47nF10% 2 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7µF25V 1 TDK R1,R13 CRCW12061912F Resistor 1206 19.1kΩ1% 2 Vishay R2,R6,R14, CRCW1206100J Resistor 1206 100Ω5% 1 Vishay R16 R7,R15 WSL-1206.0201% Resistor 1206 20mΩ1W 2 Vishay R8,R9,R12, CRCW1206000Z Resistor 1206 0Ω 8 Vishay R17,R18,R21, R31,R32 R10,R19 CRCW12061001F Resistor 1206 1kΩ1% 2 Vishay R11 CRCW12062611F Resistor 1206 2.61kΩ1% 1 Vishay R20 CRCW12062321F Resistor 1206 2.32kΩ1% 1 Vishay R22,R24 CRCW12063011F Resistor 1206 3.01kΩ1% 2 Vishay R27 CRCW12064R7J Resistor 1206 4.7Ω5% 1 Vishay R28 CRCW1206224J Resistor 1206 220kΩ5% 1 Vishay Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X SNVS219K–JUNE2003–REVISEDAPRIL2013 www.ti.com Table4.BillOfMaterialsBasedonFigure3V =9-16V,V =3.3V,5V,5ALM5642X in O1,2 ID PartNumber Type Size Parameters Qty Vendor U1 LM5642X Dual TSSOP-28 1 TI Synchronous Controller Q1,Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2,Q5 Si4840DY N-MOSFET SO-8 40V 2 Vishay D3 BA54A SchottkyDiode SOT-23 30V 1 Vishay L1,L2 RLF12545T-5R6N6R1 Inductor 12.5x12.5x4.5mm 5.6µH,9mΩ6.1A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1µF,50V 1 TDK C3,C4,C14, VJ1206Y101KXXAT Capacitor 1206 100pF,25V 4 Vishay C15 C27 C2012X5R1C105K Capacitor 0805 1µF,16V 1 TDK C6,C28 C5750X7R1H106M Capacitor 2220 10µF50V,2.8A 2 TDK C9,C23 C4532X7R0J107M Capacitor 1812 100µF,6.3V,1mΩ 2 TDK C2,C11,C12, VJ1206Y103KXXAT Capacitor 1206 10nF,25V 4 Vishay C13 C7,C25,C34 VJ1206Y104KXXAT Capacitor 1206 100nF,25V 3 Vishay C18,C20 VJ1206Y393KXXAT Capacitor 1206 39nF10% 2 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7µF25V 1 TDK R1,R13 CRCW12061912F Resistor 1206 19.1kΩ1% 2 Vishay R2,R6,R14, CRCW1206100J Resistor 1206 100Ω5% 1 Vishay R16 R7,R15 WSL-1206.0201% Resistor 1206 20mΩ1W 2 Vishay R8,R9,R12, CRCW1206000Z Resistor 1206 0Ω 8 Vishay R17,R18,R21, R31,R32 R10,R19 CRCW12061002F Resistor 1206 10kΩ1% 2 Vishay R11 CRCW12066191F Resistor 1206 6.19kΩ1% 1 Vishay R20 CRCW12063321F Resistor 1206 3.32kΩ1% 1 Vishay R22,R24 CRCW12063831F Resistor 1206 3.83kΩ1% 2 Vishay R27 CRCW12064R7J Resistor 1206 4.7Ω5% 1 Vishay R28 CRCW1206224J Resistor 1206 220kΩ5% 1 Vishay 32 SubmitDocumentationFeedback Copyright©2003–2013,TexasInstrumentsIncorporated ProductFolderLinks:LM5642 LM5642X

LM5642, LM5642X www.ti.com SNVS219K–JUNE2003–REVISEDAPRIL2013 REVISION HISTORY ChangesfromRevisionJ(April2013)toRevisionK Page • ChangedlayoutofNationalDataSheettoTIformat.......................................................................................................... 32 Copyright©2003–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM5642 LM5642X

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LM5642MH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS SN Level-1-260C-UNLIM LM5642 & no Sb/Br) MH LM5642MHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS SN Level-1-260C-UNLIM LM5642 & no Sb/Br) MH LM5642MTC NRND TSSOP PW 28 48 TBD Call TI Call TI -40 to 125 LM5642 MTC LM5642MTC/NOPB ACTIVE TSSOP PW 28 48 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LM5642 & no Sb/Br) MTC LM5642MTCX NRND TSSOP PW 28 2500 TBD Call TI Call TI -40 to 125 LM5642 MTC LM5642MTCX/NOPB ACTIVE TSSOP PW 28 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LM5642 & no Sb/Br) MTC LM5642XMH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LM5642 & no Sb/Br) XMH LM5642XMHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LM5642 & no Sb/Br) XMH LM5642XMT/NOPB ACTIVE TSSOP PW 28 48 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LM5642 & no Sb/Br) XMT LM5642XMTX/NOPB ACTIVE TSSOP PW 28 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LM5642 & no Sb/Br) XMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LM5642MHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642MTCX TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642MTCX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642XMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642XMTX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LM5642MHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642MTCX TSSOP PW 28 2500 367.0 367.0 38.0 LM5642MTCX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0 LM5642XMHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642XMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE PWP0028A PowerPAD T M - 1.1 mm max height SCALE 1.800 PLASTIC SMALL OUTLINE C 6.6 6.2 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 26X 0.65 28 1 9.8 2X 9.6 NOTE 3 8.45 14 15 0.30 28X 0.19 1.1 MAX 4.5 B 4.3 0.1 C A B NOTE 4 0.20 TYP 0.09 SEE DETAIL A 3.15 2.75 0.25 GAGE PLANE 5.65 5.25 0.10 THERMAL 0 - 8 0.02 PAD 0.7 0.5 DETAIL A (1) TYPICAL 4214870/A 10/2014 NOTES: PowerPAD is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-153, variation AET. www.ti.com

EXAMPLE BOARD LAYOUT PWP0028A PowerPAD T M - 1.1 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 (3) SOLDER 28X (1.5) MASK SOLDER MASK OPENING DEFINED PAD 28X (1.3) 28X (0.45) 28X (0.45) 1 28 26X (0.65) SYMM (5.5) (9.7) SOLDER MASK OPENING (1.3) TYP 14 15 SEE DETAILS (1.3) ( 0.2) TYP (0.9) TYP VIA SYMM (6.1) METAL COVERED (0.65) TYP BY SOLDER MASK HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE (5.8) OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214870/A 10/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN PWP0028A PowerPAD T M - 1.1 mm max height PLASTIC SMALL OUTLINE (3) BASED ON 0.127 THICK METAL COVERED 28X (1.5) STENCIL BY SOLDER MASK 28X (1.3) 28X (0.45) 1 28 26X (0.65) 28X (0.45) SYMM (5.5) BASED ON 0.127 THICK STENCIL 14 15 SEE TABLE FOR SYMM DIFFERENT OPENINGS FOR OTHER STENCIL (6.1) THICKNESSES (5.8) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE IPC-7351 NOMINAL OTHER DIMENSIONS IDENTICAL TO IPC-7351 0.65 CLEARANCE CREEPAGE SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE AREA SCALE:6X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 3.55 X 6.37 0.127 3.0 X 5.5 (SHOWN) 0.152 2.88 X 5.16 0.178 2.66 X 4.77 4214870/A 10/2014 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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