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L M 5 5 January 2013 5 — S i n g LM555 le T i Single Timer m e r Features Description • High-Current Drive Capability: 200 mA The LM555 is a highly stable controller capable of pro- • Adjustable Duty Cycle ducing accurate timing pulses. With a monostable opera- tion, the delay is controlled by one external resistor and • Temperature Stability of 0.005%/°C one capacitor. With astable operation, the frequency and • Timing From μs to Hours duty cycle are accurately controlled by two external • Turn off Time Less Than 2 μs resistors and one capacitor. Applications 8-DIP • Precision Timing • Pulse Generation 1 • Delay Generation 8-SOIC • Sequential Timing 1 Ordering Information Part Number Operating Temperature Range Top Mark Package Packing Method LM555CN LM555CN DIP 8L Rail LM555CM 0 ~ +70°C LM555CM SOIC 8L Rail LM555CMX LM555CM SOIC 8L Tape & Reel © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 1

L M Block Diagram 5 5 5 — R R R S GGNNDD 1 8 VVcCcC in g l e T i Comp. DiDscishcahrgairnggi nTgra Tnsri.stor m TTrriiggggeerr 2 7 DDiisscchhaarrggee e r OOuuttppuutt 3 OutPut F/F 6 TThhrreesshhoolldd Stage Comp. CTCohonrnettrsroohllold RReesseett 4 5 VVrReEfF VVoollttaaggee Figure 1. Block Diagram Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at T = 25°C unless otherwise noted. A Symbol Parameter Value Unit V Supply Voltage 16 V CC T Lead Temperature (Soldering 10s) 300 °C LEAD P Power Dissipation 600 mW D T Operating Temperature Range 0 ~ +70 °C OPR T Storage Temperature Range -65 ~ +150 °C STG © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 2

L M Electrical Characteristics 5 5 5 Values are at T = 25°C, V = 5 ~ 15 V unless otherwise specified. A CC — Parameter Symbol Conditions Min. Typ. Max. Unit S Supply Voltage VCC 4.5 16.0 V in g Supply Current (Low Stable) (1) I VCC = 5 V, RL = ∞ 3 6 mA le CC V = 15 V, R = ∞ 7.5 15.0 mA T CC L i m Timing Error (Monostable) Initial Accuracy (2) ACCUR R = 1 kΩ to100 kΩ 1.0 3.0 % er A Drift with Temperature (3) Δt / ΔT C = 0.1 μF 50 ppm / °C Drift with Supply Voltage (3) Δt / ΔV 0.1 0.5 % / V CC Timing Error (Astable) ACCUR 2.25 % InItial Accuracy (2) R = 1 kΩ to 100kΩ A Drift with Temperature (3) Δt / ΔT C = 0.1 μF 150 ppm / °C Drift with Supply Voltage (3) Δt / ΔV 0.3 % / V CC V = 15 V 9.0 10.0 11.0 V CC Control Voltage V C V = 5 V 2.60 3.33 4.00 V CC V = 15 V 10.0 V CC Threshold Voltage V TH V = 5V 3.33 V CC Threshold Current (4) I 0.10 0.25 μA TH V = 5 V 1.10 1.67 2.20 V CC Trigger Voltage V TR V = 15 V 4.5 5.0 5.6 V CC Trigger Current I V = 0 V 0.01 2.00 μA TR TR Reset Voltage V 0.4 0.7 1.0 V RST Reset Current I 0.1 0.4 mA RST I = 10 mA 0.06 0.25 V SINK V = 15 V CC Low Output Voltage V I = 50 mA 0.30 0.75 V OL SINK V = 5 V, I = 5 mA 0.05 0.35 V CC SINK I = 200 mA 12.5 V SOURCE V = 15 V CC High Output Voltage V I = 100 mA 12.75 13.30 V OH SOURCE V = 5 V, I = 100 mA 2.75 3.30 V CC SOURCE Rise Time of Output(3) t 100 ns R Fall Time of Output(3) t 100 ns F Discharge Leakage Current I 20 100 nA LKG Notes: 1. When the output is high, the supply current is typically 1 mA less than at V = 5 V. CC 2. Tested at V = 5.0 V and V = 15 V. CC CC 3. These parameters, although guaranteed, are not 100% tested in production. 4. This determines the maximum value of RA + RB for 15 V operation, the maximum total R = 20 MΩ, and for 5 V operation, the maximum total R = 6.7 MΩ. © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 3

L M Application Information 5 5 5 Table 1 below is the basic operating table of 555 timer. — Table 1. Basic Operating Table S i n Discharging g Reset V V Output l TR TH Transistor e (PIN 4) (PIN 2) (PIN 6) (PIN 3) T (PIN 7) i m Low X X Low ON e r High < 1/3 V X High OFF CC High > 1/3 V > 2/3 V Low ON CC CC High > 1/3 V < 2/3 V Previous State CC CC When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold volt- age or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes accord- ing to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis- charge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt- age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output again at high. 1. Monostable Operation +Vcc 102 RE4SET V8cc RA 101 R=A1kΩ 10kΩ 100kΩ 1MΩ 10MΩ Trigger DISCH 7 uF) 100 2 TRIG nce( THRES 6 acita 10-1 p a C 3 OUT C1 10-2 CONT 5 GND RL 1 C2 10-3 10-5 10-4 10-3 10-2 10-1 100 101 102 Time Delay(s) Figure2. Monostable Circuit Figure 3. Resistance and Capacitance vs. Time Delay (t ) D Figure 4. Waveforms of Monostable Operation © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 4

L M 1. Monostable Operation 5 5 Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage 5 falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low, — the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging S the external capacitor C1 and setting the flip-flop output at the same time. i n The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and g reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant le R C, the longer it takes for the V to reach 2 V /3. In other words, the time constant R C controls the output pulse T A C1 CC A i width. m When the applied voltage to the capacitor C1 reaches 2 V /3, the comparator on the trigger terminal resets the flip- e CC r flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela- tionship based on R and C. Figure 4 shows the general waveforms during the monostable operation. A It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of V /3 before CC the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below V /3. Figure 5 shows such a timer output abnormality. CC Figure 5. Waveforms of Monostable Operation (abnormal) 2. Astable Operation +Vcc 100 RA (RA+2RB) 4 8 10 RESET Vcc 1kΩ 2 TRIG DISCH 7 RB nce(uF) 1 100kΩ10kΩ THRES 6 acita 0.1 1MΩ Cap 10MΩ 3 OUT C1 CONT 5 0.01 GND RL 1 C2 1E-3 100m 1 10 100 1k 10k 100k Frequency(Hz) Figure 6. A Stable Circuit Figure 7. Capacitance and Resistance vs. Frequency © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 5

L M 5 5 5 — S i n g l e T i m e r Figure 8. Waveforms of Astable Operation An astable timer operation is achieved by adding resistor R to Figure 2 and configuring as shown on Figure 6. In the B astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operat- ing as a multi-vibrator. When the timer output is high, its internal discharging transistor. turns off and the V increases C1 by exponential function with the time constant (R +R )*C. A B When the V , or the threshold voltage, reaches 2 V /3; the comparator output on the trigger terminal becomes C1 CC high, resetting the F/F and causing the timer output to become low. This turns on the discharging transistor and the C1 discharges through the discharging channel formed by R and the discharging transistor. When the V falls below B C1 V /3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The dis- CC charging transistor turns off and the V rises again. C1 In the above process, the section where the timer output is high is the time it takes for the V to rise from V /3 to 2 C1 CC V /3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2 V /3 to V /3. CC CC CC When timer output is high, the equivalent circuit for charging capacitor C1 is as follows: R R A B Vcc C1 Vc1(0-)=Vcc/3 dv V –V(0-) C --------c---1--=-----c---c----------------------- (1) 1 dt R +R A B V (0+) = V ⁄3 (2) C1 CC  -–------------------t-------------------   (R +R )C1 V (t) = V 1–2---e A B  (3) C1 CC 3      Since the duration of the timer output high state (t ) is the amount of time it takes for the V (t) to reach 2 V /3, L C1 CC   tH  V (t) = 2---V =V 1–2---e-–(---R-----A-----+-----R-----B----)--C-----1--- (4) C1 3 CC CC 3      t = C (R +R )In2=0.693(R +R )C (5) H 1 A B A B 1 © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 6

L M The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows: 5 5 5 — R B S i n g l C1 V (0-)=2Vcc/3 R e C1 D T i m e r dv C --------C----1---+-----------1------------V =0 (6) 1 dt R +R C1 A B t -------------------------------------- (R +R )C1 V (t)=2---V A D (7) C1 3 e CC Since the duration of the timer output low state (t ) is the amount of time it takes for the VC1(t) to reach V /3, L CC t -------------------L------------------- 1---V = 2---V (RA+RD)C1 (8) 3 CC 3 e CC t = C (R +R )In2=0.693(R +R )C (9) L 1 B D B D 1 Since R is normally R >>R although related to the size of discharging transistor, D B D t = 0.693R C (10) L B 1 Consquently, if the timer operates in astable, the period is the same with 't = t +t = 0.693(RA+R )C +0.693R C = 0.693(R +2R )C ' H L B 1 B 1 A B 1 because the period is the sum of the charge time and discharge time. Since frequency is the reciprocal of the period, the following applies: frequency, f = 1--- = ---------------1---.--4---4----------------- (11) t (R +2R )C A B 1 © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 7

L M 3. Frequency Divider 5 5 5 By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. — Figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. S i n g l e T i m e r Figure 9. Waveforms of Frequency Divider Operation 4. Pulse Width Modulation The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and chang- ing the reference of the timer's internal comparators. Figure 10 illustrates the pulse width modulation circuit. When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated accord- ing to the signal applied to the control terminal. Sine wave, as well as other waveforms, may be applied as a signal to the control terminal. Figure 11 shows the example of pulse width modulation waveform. +Vcc R A 4 8 RESET Vcc 7 Trigger DISCH 2 TRIG 6 THRES Output 3 OUT Input GND CONT 5 C 1 Figure 10. Circuit for Pulse Width Modulation Figure 11. Waveforms of Pulse Width Modulation © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 8

L M 5. Pulse Position Modulation 5 5 5 If the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in — Figure 12, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates the S i timer output according to the modulation signal applied to the control terminal. n g Figure 13 illustrates a sine wave for modulation signal and the resulting output pulse position modulation; however, any l e wave shape be used. T i m e r +Vcc R A 4 8 RESET Vcc 7 DISCH 2 TRIG R B 6 THRES Output 3 OUT Modulation CONT 5 C GND 1 Figure 12. Circuit for Pulse Position Modluation Figure 13. Wafeforms of pulse position modulation 6. Linear Ramp When the pull-up resistor RA in the monostable circuit shown in Figure 2 is replaced with constant current source, the V increases linearly, generating a linear ramp. Figure 14 shows the linear ramp generating circuit and Figure 15 illus- C1 trates the generated linear ramp waveforms. +Vcc R R1 E 4 8 RESET Vcc 7 DISCH Q1 2 TRIG THRES 6 R2 Output 3 OUT C1 CONT 5 GND 1 C2 Figure 14. Circuit for Linear Ramp Figure 15. Waveforms of Linear Ramp © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 9

L M In Figure 14, current source is created by PNP transistor Q1 and resistor R1, R2, and RE. 5 5 5 V –V — I = -----C----C---------------E--- (12) C R S E i n Here, V g E is l e R T V = V +------------2----------V (13) im E BE R +R CC 1 2 e For example, if V = 15 V, R = 20 kΩ, R1 = 5 kΩ, R2 = 10 kΩ, and V = 0.7 V, r CC E BE V =0.7 V+10 V=10.7 V, and E I =(15-10.7) / 20 k=0.215 mA. C When the trigger starts in a timer configured as shown in Figure 14, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the V is a linear ramp function as shown in Figure 15. The gradient S of the linear ramp function is defined as C follows: V S = -----p-----–----p-- (14) t Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumulated in the capacitor is divided by the capacitance, the V comes out as follows: C V = Q/C (15) The above equation divided on both sides by t gives: V---- = Q-------§-----t- (16) t C and may be simplified into the following equation: S = I/C (17) In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215 mA and the capacitance is 0.02 μF, the gradient of the ramp function at both ends of the capacitor is S = 0.215 m / 0.022 μ = 9.77 V/ms. © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 10

L M Physical Dimensions 5 5 5 8-DIP — S i n g l A ..430703 [190.4.165] e T .036 [0.9 TYP] im e (.092) [Ø2.337] r PIN #1 (.032) [R0.813] .250±.005 [6.35±0.13] PIN #1 B TOP VIEW TOP VIEW OPTION 1 OPTION 2 ..007405 [11..7184] .310±.010 [7.87±0.25] .130±.005 [3.3±0.13] 7° TYP .210 MAX [5.33] 7° TYP C .015 MIN ..002115 [00..5337] ..114205[ 0[.333..851]57] [.73.0602] .001[.025] C .100 .430 MAX [2.54] [10.92] NOTES: .060 MAX [1.52] A . VCAORNIFAOTIROMNSS TBOA JEDEC REGISTRATION MS-001, .010+-..000005 [0.254+-00..010207] B. CONTROLING DIMENSIONS ARE IN INCHES REFERENCE DIMENSIONS ARE IN MILLIMETERS C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. D. DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. E. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N08EREVG Figure 16. 8-Lead, DIP, JEDEC MS-001, 300" WIDE Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf. © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 11

L M Physical Dimensions (continued) 5 5 5 8-SOIC — S i n g l e T i m e r Figure 17. 8-Lead, SOIC,JEDEC MS-012, 150" NARROW BODY Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com LM555 Rev. 1.1.0 12

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