Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 LM5037 Dual-Mode PWM Controller With Alternating Outputs 1 Features 3 Description • High-Voltage(100-V)Start-upRegulator The LM5037 PWM controller contains all the features 1 necessary to implement balanced double-ended • AlternatingOutputsforDouble-EndedTopologies power converter topologies, such as push-pull, half- • Current-modeorFeed-forwardVoltage-mode bridge and full-bridge. These double-ended Control topologies allow for higher efficiencies and greater • ProgrammableMaximumDutyCycleLimit power densities compared to common single-ended topologies such as the flyback and forward. The • 2%FeedbackReferenceAccuracy device can be configured for either voltage mode or • HighGain-bandwidthErrorAmplifier current mode control with minimum external • ProgrammableLineUndervoltageLockout(UVLO) components. Two alternating gate drive outputs are withAdjustableHysteresis provided, each capable of 1.2-A peak output current. The device can be configured to operate directly from • VersatileDualModeOvercurrentProtectionwith the input voltage rail over a wide range of 13 V to HiccupDelayTimer 100V. • ProgrammableSoft-startTime Additional features include programmable maximum • Precision5-VReferenceOutput duty cycle limit, line undervoltage lockout, cycle-by- • CurrentSenseLeadingEdgeBlanking cycle current limit and a hiccup mode fault protection • ResistorProgrammed2-MHzCapableOscillator with adjustable timeout delay, soft-start and a 2 MHz capable oscillator with synchronization capability, • OscillatorSynchronizationCapabilitywithLow- precisionreferenceandthermalshutdown. FrequencyLockoutProtection DeviceInformation(1) 2 Applications PARTNUMBER PACKAGE BODYSIZE(NOM) • TelecomPowerConverters LM5037 TSSOP(16) 5.00mm×4.4mm • IndustrialPowerConverters (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedApplication VIN VOUT LM5037 VIN VCC UVLO OUTA REF OUTB RT1/SYNC RAMP RT2 CS RES COMP Isolated SS FB Feedback PGND AGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................12 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................17 3 Description............................................................. 1 8 ApplicationandImplementation........................ 21 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................21 8.2 TypicalApplication .................................................26 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 32 6 Specifications......................................................... 4 10 Layout................................................................... 33 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................33 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................33 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 34 6.5 ElectricalCharacteristics...........................................5 11.1 CommunityResources..........................................34 6.6 TypicalCharacteristics..............................................8 11.2 Trademarks...........................................................34 7 DetailedDescription............................................ 10 11.3 ElectrostaticDischargeCaution............................34 7.1 Overview.................................................................10 11.4 Glossary................................................................34 7.2 FunctionalBlockDiagram.......................................11 12 Mechanical,Packaging,andOrderable Information........................................................... 34 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(March2013)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 ChangesfromRevisionB(March2013)toRevisionC Page • ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 26 2 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 5 Pin Configuration and Functions PWPACKAGE 16PINTSSOP (TOPVIEW) RAMP 1 16 VIN UVLO 2 15 REF COMP 3 14 VCC FB 4 13 OUTA RT2 5 12 OUTB AGND 6 11 PGND RT1/SYNC 7 10 SS CS 8 9 RES PinFunctions PIN I/O(1) DESCRIPTION NAME NO. AGND 6 — Analogground.Connectdirectlytopowerground COMP 3 I/O Inputtothepulsewidthmodulator.OutputoftheerroramplifierandinputtothePWMcomparator. Currentsenseinput.IftheCSpinexceeds250mVtheoutputpulseterminates,enteringcycle-by- CS 8 I cyclecurrentlimit.AninternalswitchholdstheCSpinlowforaperiodof65nsaftereitheroutput switcheshightoblankleadingedgetransients. Feedback.Connectedtoinvertinginputoftheerroramplifier.Aninternal1.25-Vreferenceis FB 4 I connectedtothenon-invertinginputoftheerroramplifier.Inisolatedapplicationsusinganexternal erroramplifier,thispinshouldbeconnectedtotheanaloggroundpin(AGND). OUTA 13 Outputdriver.Alternatinggate-driveoutputofthepulsewidthmodulator.Thesepinsarecapableof O OUTB 12 1.2-Apeaksourceandsinkcurrent. PGND 11 — Powerground.Connectdirectlytotheanaloggroundpin(AGND). Pulsewidthmodulatorramp.ModulationrampforthePWMcomparator.Thisrampcanbea RAMP 1 I representativeoftheprimarycurrent(currentmode)orproportionaltoinputvoltage(feed-forward voltagemode).ThispinisresettogroundattheconclusionofeverycyclebyaninternalFET. Outputofa5Vreference.Locallydecouplewithacapacitorwithavalueof0.1-µForgreater. REF 15 O Maximumoutputcurrentis10mA(typ). Restarttimer.Ifcycle-by-cyclecurrentlimitisreachedduringanycycle,thedevicesources18µAof currenttotheexternalRESpincapacitor.IftheREScapacitorvoltagereaches2.0V,thesoft-start RES 9 I capacitorisdischargedandthenreleasedwithapull-upcurrentof1µA.Afterthefirstoutputpulse (whenSS=1V),theSSpinchargingcurrentincreasestothenormallevelof100µA. Oscillatordead-timecontrol.Theresistanceconnectedbetweenthispin(RT1/SYNC)andtheAGND RT1/SYNC 7 I pinsetstheoscillatormaximumon-time.Thesumofthismaximumon-timeandtheforceddead-time (setbytheRT2pin)setstheoscillatorperiod. Oscillatordead-timecontrol.Theresistanceconnectedbetweenthispin(RT2)andtheAGNDpin RT2 5 I setstheforceddead-timebetweenswitchingperiodsofthealternatingoutputs. Soft-start.Anexternalcapacitorandaninternal100-µAcurrentsourcesetthesoft-startramp.The SS 10 I SScurrentsourceisreducedto1µAfollowingarestartevent(RESpinhigh). Lineundervoltagelockout.Anexternalvoltagedividerfromthepowersourcesetstheshutdownand standbycomparatorthresholdlevels.WhentheUVLOpinexceedsthe0.45-Vshutdownthreshold, UVLO 2 I theVCCpinandREFpinregulatorsareenabled.WhentheUVLOpinexceedsthe1.25-Vstandby threshold,theSSpinisreleasedandthedeviceenterstheactivemode. Outputofthehighvoltagestart-upregulator.TheVCCpinvoltageisregulatedto7.7V.Ifanauxiliary windingraisesthevoltageonthispinabovetheregulationsetpoint,theinternalstart-upregulator VCC 14 I/O shutsdownthusreducingthepowerdissipationofthedevice.LocallydecoupletheVCCpinwitha capacitorwithavalueof0.47µForgreater. Inputvoltagesource.InputtotheVCCstart-upregulator.Operatinginputrangeis13Vto100V.For VIN 16 I powersourcesoutsideofthisrange,theLM5037devicecanbebiaseddirectlyattheVCCpinbyan externalregulator. (1) I=Input,O=Output,G=Ground Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT VIN –0.3 105 VCC,OUTA,OUTB –0.3 16 Inputvoltage(2) V CS –0.3 1.0 UVLO,FB,RT2,RT1/SYNC,RAMP,SS,REF –0.3 7 Outputvoltage –0.3 7 V Storagetemperature,T −65 50 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allinputvoltageratingsapplyw/r/tGND. 6.2 ESD Ratings VALUE UNIT Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V (ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT VIN Supplyinputvoltagerange 13 100 V VCC ExternalvoltageappliedtoVCC 8 15 V T Operatingjunctiontemperature –40 125 °C J 6.4 Thermal Information LM5037 THERMALMETRIC(1) PW(TSSOP) UNIT 16PINS R Junction-to-ambientthermalresistance 99.9 °C/W θJA R Junction-to-case(top)thermalresistance 32.7 °C/W θJC(top) R Junction-to-boardthermalresistance 45.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 2.0 °C/W JT ψ Junction-to-boardcharacterizationparameter 45.1 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 4 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange,V =48V,V =10V,R =30.1kΩ,R =30.1kΩ,V =3V(unless VIN VCC RT1/SYNC RT2 UVLO otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT STARTUPREGULATOR(VCCPIN) I =10mA 7.4 8 VCC V VCCvoltage V VCC I =10mA,T =25°C 7.7 VCC A V =7V 45 VCC I VCCcurrentlimit mA VCC(lim) V =7V,T =25°C 60 VCC A VCCReg- V =V VIN VCC 0.2 VCCundervoltagethreshold V VCCReg- V VCC(UV) V =V ,T =25°C VIN VCC A 0.1 Hysteresis 1.5 V =100V,V =0V 430 VIN UVLO V =100V,V =0V, VIN UVLO 350 IVIN Startupregulatorcurrent TA=25°C µA V =48V,V =0V 370 VIN UVLO V =48V,V =0V,T =25°C 325 VIN UVLO A OutputpinsandCOMP=Open 5.5 SupplycurrentintoVCCfrom IVCC externalsource OutputpinsandCOMP=Open, 3 mA T =25°C A VOLTAGEREFERENCEREGULATOR(REFPIN) I =0mA 4.75 5.15 REF REFpinvoltage V I =0mA,T =25°C 5 REF A V REF 0A≤I ≤2.5mA 25 REF REFvoltageregulation mV 0A≤I ≤2.5mA,T =25°C 7 REF A V =4.5V 5 REF I REFcurrentlimit mA REF(lim) V =4.5V,T =25°C 10 REF A 3.7 4.3 V undervoltagethreshold V REF T =25°C 4 A V Hysteresis 0.35 V REF(UV) UNDERVOLTAGELOCKOUTANDSHUTDOWN(UVLOPIN) 1.20 1.295 T =25°C 1.25 A V Undervoltagelockoutthreshold V UVLO UVLOvoltagerising 0.37 0.47 UVLOvoltagerising,T =25°C 0.42 A Hysteresisvoltage 0.1 V UVLOpinsinking 18 25 I Hysteresiscurrent µA UVLO UVLOpinsinking,T =25°C 22 A CURRENTSENSEINPUT(CSPIN) 0.22 0.29 V Currentlimitthreshold V CS T =25°C 0.25 A t CSdelaytooutput(1) V risingfromzeroto1V.Noload. 27 ns DLY(CS) CS t LeadingedgeblankingtimeatCS 66 ns BLK(CS) 45 R CSsinkimpedance(clocked)(2) Ω CS(sink) T =25°C 21 A (1) TimeforOUTApinandOUTBpintofallto90%ofVCC. (2) InternalFETsinkimpedance. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange,V =48V,V =10V,R =30.1kΩ,R =30.1kΩ,V =3V(unless VIN VCC RT1/SYNC RT2 UVLO otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMITRESTART(RESPIN) 1.9 2.2 V RESvoltagethreshold V RES T =25°C 2 A V =1.5V 14 22 RES I Chargesourcecurrent µA CHG(src) V =1.5V,T =25°C 18 RES A V =1V 5 11 RES I Dischargesinkcurrent µA DSCHG(snk) V =1V,T =25°C 8 RES A SOFT-START(SSPIN) V =0,Normaloperation 70 130 SS V =0,Normaloperation,T = SS A 100 25°C I Chargingcurrent µA SS V =0,Hiccupmoderestart 0.6 1.5 SS V =0,Hiccupmoderestart,T = SS A 1 25°C V =2.0V 70 130 SS I Soft-stopcurrentsink µA SS(sink) V =2.0V,T =25°C 100 SS A OSCILLATOR(RT1/SYNCANDRT2PINS) R =15kΩ 40 105 RT2 t Deadtime R =15kΩ,T =25°C 75 ns DEAD RT2 A R =75kΩ 250 RT2 R =30.1kΩ,R =30.1 RT1/SYNC RT2 176 223 kΩ fSW1 Switchingfrequency1(3) RRT1/SYNC=30.1kΩ,RRT2=30.1 kHz kΩ, 200 T =25°C A R =11kΩ,R =30.1kΩ 441 571 RT1/SYNC RT2 fSW2 Switchingfrequency2(3) RRT1/SYNC=11kΩ,RRT2=30.1kΩ, 508 kHz T =25°C A DCvoltagelevel 2 V Inputsynchronizationthreshold 2.5 3.4 V voltage T =25°C 3 A PWMCONTROLLER(COMPPIN) t Delay-to-outputtime 65 ns DLY(pwm) 0.7 1.2 V SStoRAMPoffsetvoltage V PWM-OS T =25°C 1 A D Mimumumdutycycle V =0V 0% MIN SS V =0V 4.5 5 FB COMPopencircuitvoltage V V =0V,T =25°C 4.75 FB A V =0V,V =0V 0.5 1.5 FB COMP COMPshortcircuitcurrent mA V =0V,V =0V,T =25°C 1 FB COMP A VOLTAGEFEED-FORWARD(RAMPPIN) 20 R RAMPsinkimpedance(clocked) Ω RAMP(sink) T =25°C 5 A (3) MeasuredatOUTA,halfoscillatorfrequency 6 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Electrical Characteristics (continued) overoperatingfree-airtemperaturerange,V =48V,V =10V,R =30.1kΩ,R =30.1kΩ,V =3V(unless VIN VCC RT1/SYNC RT2 UVLO otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ERRORAMPLIFIER GBW Gainbandwidth 4 MHz DCgain V =V 1.22 1.27 FB COMP Inputvoltage V V =V ,T =25°C 1.245 FB COMP A COMPpinsinkcapability V =1.5V,V =1V 5 13 mA FB COMP FBpinbiascurrent 10 nA MAINOUTPUTDRIVERS(OUTAANDOUTBPINS) I =50mA,(Source) V –0.5 OUT VCC V High-leveloutputvoltage V OH I =50mA,(Source),T =25°C V –0.25 OUT A VCC I =100mA(Sink) 0.5 OUT V Low-leveloutputvoltage V OL I =100mA(Sink),T =25°C 0.2 OUT A t Risetime C =1nF 15 ns RISE LOAD t Falltime C =1nF 13 ns FALL LOAD I Peaksourcecurrent V =10V 1.2 A PEAK(src) VCC I Peaksourcecurrent V =10V 1.2 A PEAK(snk) VCC THERMALSHUTDOWN T Thermalshutdownthreshold 165 °C SD Thermalshutdownhysteresis 25 °C Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 6.6 Typical Characteristics V =0V UVLO Figure1.ReferenceVoltagevs.InputVoltage Figure2.Start-UpRegulatorCurrentvsInputVoltage Figure3.InputVoltagevsInputCurrent Figure4.ReferenceVoltagevs.ReferenceCurrent 60 180 50 150 40 120 30 90 20 60 )Bd( N 100 030 o)( ESA IA -10 -30 H G P -20 -60 -30 -90 -40 -120 -50 -150 -60 -180 10k 100k 1M 10M FREQUENCY Figure5.FeedbackAmplifierBodePlot Figure6.OscillatorFrequencyvs TimingResistance(R ) RT1/SYNC 8 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Typical Characteristics (continued) Figure7.DeadTimevs.TimingResistance(RRT2) Figure8.FeedbackVoltagevs.Temperature Figure9.OscillatorFrequencyvs.Temperature Figure10.Dead-Timevs.Temperature Figure11.Soft-StartandRestartCurrentvs.Temperature Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 7 Detailed Description 7.1 Overview The LM5037 PWM controller contains all the features necessary to implement double-ended power converter topologies such as push-pull, half-bridge and full-bridge. The unique architecture allows the modulator to be configured for either voltage-mode or current-mode control. The device provides two alternating gate driver outputs to drive the primary-side power MOSFETs with programmable forced dead-time. The device can be configuredtooperatewithbiasvoltagesrangingfrom13Vto100V.Additionalfeaturesincludelineundervoltage lockout, cycle-by-cycle current limit, voltage feed-forward compensation, hiccup mode fault protection with adjustable delays, soft-start, a 2-MHz capable oscillator with synchronization capability, precision reference and thermal shutdown. These features simplify the design of double ended topologies. The Functional Block Diagram sectionshowsthefunctionalblockdiagram. 10 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 7.2 Functional Block Diagram 7.7V Series Regulator VIN VCC UVLO 0.45V SHUTDOWN REF 5V 1.25V STANDBY Reference MODE VCC/REF CONTROL UVLO LOGIC THERMAL LIMIT UVLO HYSTERESIS (20PA) (165°C) VCC RT1/SYNC CLK JSETQ DRIVER OUTA OSCILLATOR RT2 KCLRQ S Q VCC R RAMP OUTB DRIVER 1.25V ERROR AMP FB +5V PGND 5k PWM COMP AGND 1V PWM LOGIC SS SS Buffer 2.0V +5V CS Restart 18PA 0.25V Current CLK + LEB Hiccup CLK Source Logic RES +5V +5V SS SOFT-START RESTART DELAY 8PA 100PA 1PA SS Shutdown 100PA Standby SOFT-STOP Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 7.3 Feature Description 7.3.1 High-VoltageStart-UpRegulator The LM5037 device contains an internal high voltage, start-up regulator that allows the input pin (VIN) to be connected directly to the supply voltage over a range of 13V to a maximum of 100 V. The regulator input can withstand transients up to 105 V. The regulator output at VCC (7.7 V) is internally current limited with a minimum of 45 mA. When the UVLO pin potential is greater than 0.45 V, the VCC regulator is enabled to charge an external capacitor connected to the VCC pin. The VCC regulator provides power to the voltage reference (REF) and the gate drivers (OUTA and OUTB). When the voltage on the VCC pin exceeds its undervoltage (VCC UV) threshold, the internal voltage reference (REF) reaches its regulation set point of 5 V and the UVLO voltage is greaterthan1.25V,thecontrolleroutputsareenabled.ThevalueselectedfortheVCCcapacitordependsonthe total system design, and its start-up characteristics. The recommended range of values for the VCC capacitor between0.47µFand10µF. Powering VCC from an external supply can reduce the internal power dissipation of the device. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8.1 V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller’s power dissipation. The VCC UV circuit function remains in this mode, requiring that VCC never falls below its nominal threshold during the start-up sequence. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biasedinnormaloperation.ThereforetheauxiliaryVCCvoltageshouldneverexceedtheVINvoltage. An external DC bias voltage can be used instead of the internal regulator by connecting the external bias voltage to both the VCC and the VIN pins. In this particular case, the external bias must be greater than maximum VCC pinregulationof8VandlessthantheVCCmaximumoperatingvoltagerating(15V). 7.3.2 Reference The REF pin is the output of a 5-V linear regulator that can be used to bias an opto-coupler transistor and externalhousekeepingcircuits.Theregulatoroutputisinternallycurrentlimitedto10mA(typical). 7.3.3 ErrorAmplifier AninternalhighgainerroramplifierisprovidedwithintheLM5037.Thenon-invertingamplifierreferenceistiedto a 1.25 V reference. In non-isolated applications the power converter output is connected to the FB pin via the voltage setting resistors and loop compensation is connected between the COMP and FB pins. A typical gain/phaseplotisshownintheTypicalCharacteristicssection. For most isolated applications the error amplifier function is implemented on the secondary side. Since the internal error amplifier is configured as an open drain output, it can be disabled by connecting FB to ground. The internal, 5-kΩ pull-up resistor connected between the COMP pin and the 5-V reference can be used as the pull- upforanopto-couplerorotherisolationdevice. 7.3.4 Cycle-By-CycleCurrentLimit TheCSpinistobedrivenbyasignalrepresentativeofthetransformerprimarycurrent.Thecurrentsensesignal can be generated by using a sense resistor or a current sense transformer. If the voltage sensed at the CS pin exceeds 0.25 V, the current sense comparator terminates the output driver pulse. If the high current condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the current sense comparator instead of the PWM comparator. Cycle-by-cycle current limiting may eventually trigger the hiccup mode restart cycle; depending on the configuration of the RES pin (see Overload Protection Timer section). To suppress noise, a small R-C filter connected to the CS pin and located near the controller is recommended. An internal, 21-Ω MOSFET discharges the external current sense filter capacitor at the conclusion of every cycle. The discharge MOSFET remains on for an additional 65 ns after either OUTA or OUTB driver switches high to blank leading edge transients in the current sensing circuit. Discharging the CS pin filter each cycle and blanking leading edge spikes reduces the filtering requirements and improves the current sense response time. The current sense comparator is very fast and may respond to short duration noise pulses. Layoutconsiderationsarecriticalforthecurrentsensefilterandsenseresistor.Thecapacitorassociatedwiththe 12 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Feature Description (continued) CS filter must be placed very close to the device and connected directly to the CS and AGND pins. If a sense resistor located in the source of the main MOSFET switch is used for current sensing, a low inductance type of resistor is required. When designing with a current sense resistor, all the noise sensitive, low power ground connections should be connected together near the AGND pin, and a single connection should be made to the powerground(senseresistorgroundpoint). 7.3.5 Soft-StartSequence Thesoft-startcircuitallowstheregulatortograduallyreachasteadystateoperatingpoint,therebyreducingstart- up stresses and current surges. When bias is supplied to the LM5037, the SS pin capacitor is discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 100 µA current source. The PWM comparator control voltage at the COMP pin is clamped to the SS pin voltage by an internal amplifier. When the PWM comparator input reaches 1 V, output pulses commence with slowly increasing duty cycle. The voltage at the SS pin eventually increases to 5 V, while the voltage at the PWM comparator increases to the value required for regulation as determined by the voltage feedbackloop. One method to disable the regulator is to ground the SS pin. This forces the internal PWM control signal to ground, reducing the output duty cycle quickly to zero. Releasing the SS pin initiates a soft-start sequence and normaloperationresumes.AsecondshutdownmethodisdiscussedintheThermalProtectionsection. 7.3.6 PWMComparator The pulse width modulation (PWM) comparator compares the voltage ramp signal at the RAMP pin to the loop error signal. The loop error signal is derived from the internal error amplifier (COMP pin). The resulting control voltage passes through a 1-V level shift before being applied to the PWM comparator. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The common mode input voltage rangeofthePWMcomparatorisfrom0Vto4.3V. 7.3.7 ModulationRamp The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator compares the modulation ramp signal at the RAMP pin to the loop error signal to control the output duty cycle. The modulation ramp can be implemented either as a ramp proportional to input voltage, known as feed-forward voltage mode control, or as a ramp proportional to the primary current, known as current mode control. The RAMP pin is reset by an internal FET with an R of 5 Ω (typical) at the end of every cycle. The ability to DS(on) configure the RAMP pin for either voltage mode or current mode allows the controller to be implemented for the optimum control method for the selected power stage topology. Configuring RAMP pin is explained below and the differences between voltage mode control and current mode control in various double-ended topologies is explainedinApplicationInformationsection. 7.3.8 Feed-ForwardVoltageMode An external resistor (R ) and capacitor (C ) connected to VIN, AGND, and the RAMP pins is required to create FF FF the PWM ramp signal as shown in Figure 12. It can be seen that the slope of the signal at RAMP varies in proportion to the input line voltage. This varying slope provides line feed-forward information necessary to improve line transient response with voltage mode control. The RAMP signal is compared to the error signal by the pulse width modulator comparator to control the duty cycle of the outputs. With a constant error signal, the on-time (t ) varies inversely with the input voltage (VIN) to stabilize the Volt-Second product of the transformer ON primary.Attheendofclockperiod,aninternalFETengagestoresettheC capacitor.TheformulaeforR and FF FF C and component selection criteria are explained in Application and Implementation section. The amplitude of FF the signal driving RAMP pin must not exceed the common mode input voltage range of the PWM comparator (3.3V)whileinnormaloperation. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Feature Description (continued) SLOPE PROPORTIONAL Vin TO Vin VIN RFF COMP 1V Gate Drive RAMP CLK CFF LM5037 Figure12. Feed-ForwardVoltageModeConfiguration 7.3.9 CurrentMode The LM5037 device can be configured for current mode control by injecting a signal representative of primary current into the RAMP pin. One way to achieve this is shown in Figure 13. Filter components R and C are filter filter used to filter leading edge noise spikes. The signal at the CS pin is thus a ramp on a pedestal. The pedestal corresponds to the continuous conduction current in the transformer at the beginning of an OUTA or OUTB conduction cycle. The R-C circuit (R and C ), shown in Figure 13, tied to V adds an additional ramp to Slope Slope REF the current sense signal. This additional ramp signal, known as slope compensation, is required to avoid instabilities at duty cycles above 50% (25% per phase). The compensated RAMP signal consists of two parts, the primary current signal and the slope compensation. The compensated RAMP signal is compared to the error signal by the PWM comparator to control the duty cycle of the outputs. The RAMP capacitor and CS capacitor are reset through internal discharge FETs. The on-resistance (R ) of RAMP discharge FET is 5 Ω (typical); DS(on) this ensures fast discharge of the RAMP reset capacitor. Any dc voltage source can be used in place of V to REF generatetheslopecompensationramp. The timing diagram shown in Figure 14 depicts the current mode waveforms and relative timing. When OUTA or OUTB is enabled, the signal at the RAMP pin consists of the CS pin signal (current ramp on a pedestal) plus the slope compensation ramp (dotted lines). When OUTA or OUTB is turned off, the primary current component is absent but the voltage at the RAMP pin continues to rise due to slope compensation component until the end of theclockperiod,afterwhichitisresetbytheRAMPdischargeFET.Acomponentselectionexampleisexplained indetailintheApplicationandImplementationsection. 14 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Feature Description (continued) VREF (5V) Rslope RAMP CLK Cslope LM5037 Current Sense Rfilter cs CLK + LEB RCS Cfilter Figure13. CurrentModeConfigurationwithSlopeCompensation CLK CS OUTA OUTB COMP RAMP Slope Compensation OUTPUT OUTA OUTB Figure14. TimingDiagramforCurrentModeConfiguration 7.3.10 Oscillator TheLM5037deviceoscillatorfrequencyandthemaximumdutycyclearesetbytwoexternalresistorsconnected between the RT1/SYNC and RT2 pins to AGND. The minimum dead-time between OUTA and OUTB pulses is proportional to the RT2 resistor value and the overall oscillator frequency is inversely proportional to R RT1/SYNC and R resistor values. Each output switches at half the oscillator frequency. Use Equation 1 to calculate a RT2 value of R that supports a required dead-time. Use Equation 2 to calculate a value of R that supports a RT2 RT2 maximumdutycycle(D ). MAX Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Feature Description (continued) æ t ö RRT2 =çè5´D1E0A-D12 ÷ø (1) 50 ns £ t £ 250 ns DEAD (2) ææ(1-DMAX)öö çç ÷÷ ç f ÷ RRT2 =çççè 5´O1S0C-12 ø÷÷÷ ç ÷ è ø (3) The recommended dead-time range is between 50 ns and 250 ns. Beyond 250 ns, the R resistance becomes RT2 excessively large, and is prone to noise pickup. Fixed internal delays limit the dead-time to greater than 50 ns. After the dead-time has been programmed by RT2, the overall oscillator frequency can be set by selecting the resistorR usingEquation4. RT1/SYNC ææ 1 ö ö ççf ÷-tDEAD ÷ çè OSC ø ÷ R = RT1/SYNC ç 0.162´10-9 ÷ ç ÷ ç ÷ è ø (4) For example, if the desired oscillator frequency is 400 kHz (OUTA and OUTB each switching at 200 kHz) and desired dead-time is 100 ns, the maximum duty cycle for each output is 96%. The value of R is 15 kΩ RT1/SYNC andR is20kΩ. RT2 CLK tON(max) OUTA OUTB tOSC tDEAD tDEAD Time Figure15. TimingDiagramofOUTA,OUTBandDead-TimeSetbyRT2 As shown in Figure 15, the internal clock pulse width is the same as the dead-time set by the RT2 pin. This dead-time pulse is used to limit the maximum duty cycle for each of the outputs. Also, the discharge FET connected to the RAMP pin is enabled during the dead-time every clock period. The voltages at both the RT1/SYNC and RT2 pins are internally regulated to a nominal 2 V. Both the R and R resistors should RT1/SYNC RT2 be located as close as possible to the device, and connected directly to the pins. Consider the tolerance of the external resistors and the frequency tolerance indicated in the Electrical Characteristics table when determining theworstcasefrequencyrange. 7.3.11 SynchronizationCapability The LM5037 device can be synchronized to an external clock by applying a narrow ac pulse to the RT1/SYNC pin. The external clock must be at least 10% higher than the free-running oscillator frequency set by the R and R resistors. If the external clock frequency is less than the programmed frequency, the device RT1/SYNC RT2 ignores the synchronizing pulses. The synchronization pulse width at the RT1/SYNC pin must be a minimum of 15 ns wide. The synchronization signal should be coupled into the RT1/SYNC pin through a 100 pF capacitor or 16 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Feature Description (continued) another value small enough to ensure the sync pulse width at RT1/SYNC is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions from low-to-high (rising edge), the voltage at the RT1/SYNC pin must be driven to exceed 3.0 V from its nominal 2.0 Vdc level. During the synchronization clock signal low time, the voltage at the RT1/SYNC pin clamps at 2 V by an internal regulator. The R and R RT1/SYNC RT2 resistorsarealwaysrequired,whethertheoscillatorisfreerunningorexternallysynchronized. 7.3.12 GateDriverOutputs(OUTAandOUTBPins) The LM5037 device provides two alternating gate driver outputs, OUTA and OUTB. The internal gate drivers can each source and sink 1.2-A peak each. The maximum duty cycle is inherently limited to less than 50% and is based on the value of R resistor. As an example, if the COMP pin is in a high state, R = 15 kΩ and RT2 RT1/SYNC R =20kΩ thentheoutputsoperateatamaximumdutycycleof96%. RT2 7.3.13 ThermalProtection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby state with the output drivers (OUTA and OUTB) and the bias regulators (VCC and REF) disabled. This helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature fallstotheoperatinglevel(140°C). 7.4 Device Functional Modes 7.4.1 OverloadProtectionTimer The LM5037 device provides a current limit restart timer to disable the outputs and force a delayed restart (hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required to trigger the restart is programmed by the external capacitor at the RES pin. During each PWM cycle, the device either sources to or sinks current from the RES pin capacitor. If no current limit is detected during a cycle, a 8-µA discharge current sink is enabled to pull the RES pin towards ground. If a current limit is detected, the 8-µA sink current is disabled and a 18-µA current source causes the voltage at the RES pin to gradually increase. The device protects the converter with cycle-by-cycle current limiting while the voltage at RES pin increases. If the RES voltage reaches the 2.0 V threshold, the following restart sequence occurs (also see Figure16): • TheREScapacitorandSScapacitorsarefullydischarged. • Thesoft-startcurrentsourceisreducedfrom100µAto1 µA. • The SS capacitor voltage slowly increases. When the SS voltage reaches approximately 1 V, the PWM comparator produces the first narrow output pulse. After the first pulse occurs, the SS source current reverts to the normal 100 µA level. The SS voltage increases at its normal rate, gradually increasing the duty cycle of theoutputdrivers. • If the overload condition persists after restart, cycle-by-cycle current limiting begins to increase the voltage on theREScapacitoragain,repeatingthehiccupmodesequence. • Iftheoverloadconditionnolongerexistsafterrestart,theRESpinremainsatgroundbythe8-µAcurrentsink andnormaloperationresumes. 7.4.1.1 OverloadTimerFunction Thissectionliststhemodesofprotectionavailablebyconfiguringtheoverloadtimerfunction. 7.4.1.1.1 Cycle-by-cycleOnly The hiccup mode can be completely disabled by connecting a zero to 50 kΩ resistor from the RES pin to AGND. In this configuration, the cycle-by-cycle protection limits the output current indefinitely and no hiccup sequences occurs. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Device Functional Modes (continued) 7.4.1.1.2 HiccupOnly The timer can be configured for immediate activation of a hiccup sequence upon detection of an overload by leaving the RES pin open circuit. In this configuration, the first detection of current limit condition by the CS pin comparatorinitiatesahiccupcyclewithSScapacitorfullydischargedandadelayedrestart. 7.4.1.1.3 DelayedHiccup Connecting a capacitor to the RES pin provides a programmed interval of cycle-by-cycle limiting before initiating a hiccup mode restart, as previously described. The dual advantages of this configuration are that a short term overload does not cause a hiccup mode restart but during extended overload conditions, the average dissipation ofthepowerconverterremainsverylow. 7.4.1.2 ExternallyControlledHiccup The RES pin can also be used as an input. The RES pin forces the device into a delayed restart sequence when the pin rises to a level greater than the 2.0 V hiccup threshold. For example, an external trigger for a delayed restartsequencemaycomefromanover-temperatureprotectioncircuitoranoutputover-voltagesensor. Current CS CLuirmreintt 5V Sense Circuit 0.25V CLK CRuersrteanrtt 18PA RES Source Logic 8PA CRES SS Voltage COMP PWM DTroiv Oerustput 2.0V Feedback S Restart Comparator R Q Drivers Off Restart Latch +5V +5V 100PA SS 1PA SS CSS 100mV Logic Drivers Off Soft-start LM5037 Figure16. CurrentLimitRestartCircuit Current Limit Detected Current Limit Persists at CS 2.0V RES 0V 5V 100PA #(cid:3)1V SS 1(cid:3)PA OUTA OUTB t1 t2 t3 Figure17. CurrentLimitRestartTiming 18 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Device Functional Modes (continued) 7.4.2 TopologyandControlAlgorithmChoice The LM5037 device has all the features required to implement double-ended power converter topologies such as push-pull, half-bridge and full-bridge with minimum external components. One key feature is the flexibility in control algorithm selection. For example, the device can be used to implement either voltage mode control or current mode control. Designers familiar with these topologies recognize that conventionally, current mode control is used for push-pull and full-bridge topologies while voltage mode control is required for the half-bridge topology. In limited applications, voltage mode control can be used for push-pull and full-bridge topologies as well, with special care to maintain flux balance, such as using a dc-blocking capacitor in the primary (full-bridge). The goal of this section is to illustrate implementation of both current mode control and voltage mode control usingtheLM5037deviceandaidthedesignerinthedesignprocess. 7.4.3 VoltageModeControl An external resistor (R ) and capacitor (C ) connected to VIN, AGND, and the RAMP pins is required to create FF FF a saw-tooth modulation ramp signal shown in Figure 18. The slope of the signal at RAMP varies in proportion to the input line voltage. The varying slope provides line feed-forward information necessary to improve line transient response with voltage mode control. With a constant error signal, the on-time (t ) varies inversely with ON theinputvoltage(VIN)tostabilizetheVolt •Secondproductofthetransformerprimary.Usingalinefeed-forward ramp for PWM control requires very little change in the voltage regulation loop to compensate for changes in inputvoltage,ascomparedtoafixedslopeoscillatorramp.Furthermore,voltagemodecontrolislesssusceptible to noise and does not require leading edge filtering, and is therefore a good choice for wide input range power converters. Voltage mode control requires a more complicated compensation network, due to the complex- conjugatepolesoftheL-Coutputfilter. Inpush-pullandfull-bridgetopologies,anyasymmetryinthevolt-secondproductappliedtoprimaryinonephase may not be cancelled by subsequent phase, possibly resulting in a dc current build-up in the transformer, which pushes the transformer core towards saturation. Special care in the transformer design, such as gapping the core, or adding ballasting resistance in the primary is required to rectify this imbalance when using voltage mode control with these topologies. Current mode control naturally corrects for any volt-second asymmetry in the primary. The recommended capacitor value range for C is 100 pF to 1500 pF. Referring to Figure 18, it can be seen FF that value C must be small enough such that the capacitor can be discharged within the clock (CLK) pulse FF width each cycle. The CLK pulse width is same as the dead-time set by RT2. The minimum possible dead-time forthedeviceis50nsandtheinternaldischargeFETR is5Ω (typical), DS(on) ThevalueofR requiredcanbecalculatedfrom FF -1 RFF = æ V ö fOSC´CFF´lnçç1- VRAMP ÷÷ IN(min) è ø (5) For example, assuming a V of 1 V at V (a good compromise of signal range and noise immunity), RAMP IN(min) oscillatorfrequency,f of250kHz,V of24V,andC =270pFresultsinavalueforR of348kΩ. OSC IN(min) FF FF Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Device Functional Modes (continued) SLOPE PROPORTIONAL Vin TO Vin VIN RFF COMP 1V Gate Drive RAMP CLK CFF LM5037 Figure18. Feed-ForwardVoltageModeConfiguration 7.4.4 CurrentModeControl The LM5037 device can be configured in current mode control by applying the primary current signal into the RAMP pin. One way to achieve this is shown in Figure 19, which depicts a simplified push-pull converter. The primary current is sensed using a sense resistor and the current information is then filtered and applied to the RAMP pin through capacitor C , for use as the modulation ramp. It can be seen that the signal applied to the slope RAMP pin consists of the primary current information from the CS pin plus an additional ramp for slope compensation,addedbyR andC . slope slope VREF Rslope RAMP Vin + Q1 Q2 CLK - Cslope LM5037 Rfilter CS CLK + LEB Current Sense RCS Cfilter Figure19. CurrentModeConfiguration Current mode control inherently provides line voltage feed-forward, cycle-by-cycle current limiting and ease of loop compensation as it removes the additional pole due to output inductor. Also, in push-pull and full-bridge converters, current mode control inherently balances volt-second product in both the phases by varying the duty cycle as needed to terminate the cycle at the same peak current for each output phase. For duty cycles greater than 50% (25% for each phase), peak current mode controlled circuits are subject to sub-harmonic oscillation. 20 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Device Functional Modes (continued) Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles at the controller output. Adding an artificial ramp (slope compensation) to the current sense signal eliminates this potential oscillation. Current mode control is also susceptible to noise and layout considerations. It is recommended that C and C be placed as close to the IC as possible to avoid any noise pickup and trace Filter slope inductance. When the converter is operating at low duty cycles and light load, the primary current amplitude is small and is susceptible to noise. The artificial ramp, added to avoid sub-harmonic oscillations, provides additionalbenefitsbyimprovingthenoiseimmunityoftheconverter. 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information 8.1.1 InputSupplyVoltage(VINandVCCpins) The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power transformer’s primary (V ), can vary from 8 V to 100 V. The current into the VIN pin depends primarily on the PWR gate charge provided by the output drivers, the switching frequency, and any external loads on the VCC and REF pins. This design uses the filter shown in Figure 20 to suppress transients that may occur at the input supply. A filter is particularly important when VIN is operated close to the maximum operating rating of the LM5037. When power is applied to VIN and the UVLO pin voltage is greater than 0.45 V, the VCC regulator is enabled and supplies current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches the regulation point of 7.7 V, the voltage reference (REF) enables. The reference regulation set point is 5 V. The outputs (OUTA and OUTB) enable when the two bias regulators reach their set point and the UVLO pin potential is greater than 1.25 V. In typical applications, an auxiliary transformer winding connects through a diode to the VCC pin. In order to shut off the internal start-up regulator, this winding must raise the VCC voltage above 8.1V. After the outputs are enabled and the external VCC supply voltage has begun supplying power to the device, the current into the VIN pin drops below 1 mA. VIN should remain at a voltage equal to or above the VCC voltage to avoidreversecurrentthroughprotectiondiodes. VPWR 50 VIN LM5037 0.1PF Figure20. InputTransientProtection 8.1.2 100-V(orHigher)InputVoltageApplications Forapplicationswherethesysteminputvoltageexceeds100Vorthedevicepowerdissipationisofconcern,the LM5037 device can be powered from an external start-up regulator as shown in Figure 21. This configuration showstheVINandtheVCCpinsconnectedtogether.ThevoltageattheVCCandVINpinsmustbegreaterthan 8.1 V (> VCC reference voltage) and not exceed 15 V. Use an auxiliary winding to reduce the power MAX dissipation in the external regulator after the power converter activates. The N-P-N base-emitter reverses breakdown voltage, which can be as low as 5 V for some transistors. Consider this breakdown voltage when selectingthetransistor. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Application Information (continued) 8.1V to 15V VPWR VIN VCC from aux winding LM5037 9V Figure21. Start-upRegulatorforV >100V PWR 8.1.3 CurrentSense TheCSpinreceivesaninputsignalrepresentativeofthetransformerprimarycurrent,eitherfromacurrentsense transformer or from a resistor in series with the source of the OUTA and OUTB MOSFET switches. In both cases,thesensedcurrentcreatesavoltagerampacrossR1,andtheR C filtersuppressesnoiseandtransients F F as shown in Figure 22 and Figure 23. Locate components R1, R and C as close to the device as possible. Use F F a dedicated track from the current sense transformer (R1) to the ground connection (AGND pin). Ensure that the currentsensecomponentsprovidegreaterthan220mVattheCSpinwhenanover-currentconditionexists. VPWR Current Sense Power Transformer VIN Q1 CS RF LM5037 CF R1 AGND Level OUTA Shift Q2 OUTB Figure22. CurrentSenseUsingTransformer 22 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Application Information (continued) Power Transformer VPWR Vin OUTA Q1 Q2 OUTB RF CS LM5037 CF R1 Figure23. CurrentSenseUsingCurrentSenseResistor(R1) Configuration and component selection for current mode control is recommended as follows: The current sense resistor is selected such that during over current condition, the voltage across the current sense resistor is above the minimum CS threshold of 220 mV. It is recommended to set the impedances of R and C as seen from Filter Filter C at relatively low values, so that the slope compensation is primarily dictated by R and C slope slope slope components. For example, if the filtering time (R and C ) for leading edge noise is selected for 50 ns and if Filter Filter thevalueselectedforR =25Ω,then Filter 50 x 10-9 C = Filter 3 x 25: (6) Equation 6 results in a value of C = 680 pF (approximated to a standard value). In general, the amount of Filter slope compensation required to avoid sub-harmonic oscillation is equal to at least one-half the down-slope of the output inductor current, transformed to the primary. To mitigate sub-harmonic oscillation after one switching period, the slope compensation has to be equal to one times the down slope of the filter inductor current transformed to primary. This is known as deadbeat control. For circuits where primary current is sensed using a resistor,theamountofslopecompensationfordead-beatcontrolrequiredcanbecalculatedfrom: Turns-Ratio x Vout x R Slope-Comp = CS F x L OSC filter where • turns-ratioisreferredwithrespecttotheprimary (7) For example, for a 5-V output converter with a turns ratio between secondary and primary of 1:2, an oscillator frequency(f )of250kHz,afilterinductanceof4µH(L )andacurrentsenseresistor(R )of32mΩ,slope OSC Filter CS compensation of 80 mV suffices. The slope compensation "volts" that results from the above expression is the maximum voltage of the artificial ramp added linearly to the RAMP pin till the end of maximum switching period. For circuits where a current sense transformer is used for primary current sensing, the turns-ratio of the current sensetransformerhastobetakenintoaccount. C should be selected such that it can be fully discharged by the internal RAMP discharge FET. Capacitor slope values ranging from 100 pF to 1500 pF are recommended. The value must be small enough such that the capacitorcanbedischargedwithintheclock(CLK)pulsewidtheachcycle. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Application Information (continued) R canbeselectedfromthefollowingformula: slope -1 Rslope = - Rfilter Slope-Comp F x C x In 1 - OSC slope V REF (8) For example, with a C of 1500 pF, F of 250 kHz, reference voltage of 5V (V ), slope compensation of slope OSC REF 80mVandR =25Ω resultsinR valueof165kΩ. filter slope 8.1.4 UVLODividerSelection A dedicated comparator connected to the UVLO pin detects an input under-voltage condition. When the UVLO pin voltage is below 0.45 V, the LM5037 controller is in a low current shutdown mode. For a UVLO pin voltage greater than 0.45 V but less than 1.25 V, the controller is in standby mode with VCC and REF regulators active but no switching. Once the UVLO pin voltage is greater than 1.25 V, the controller is fully enabled. When the UVLO pin voltage rises above the 1.25-V threshold, an internal 22-µA current source as shown in Figure 24, is activated thus providing threshold hysteresis. The 22-µA current source is deactivated when the voltage at the UVLOpinfallsbelow1.25V.UseEquation9tocalculateresistancevaluesforR1andR2. 20 x 10-3 x V R = V - PWR 1 HYS 1.25 22 PA 1.25 x R 1 R = 2 V - 1.25 PWR where • V isthedesiredturn-onvoltage PWR • V isthedesiredUVLOhysteresisatV (9) HYS PWR LM5037 5.0V VIN 22 PA R1 1.25V UVLO STANDBY R2 0.45V SHUTDOWN Figure24. BasicUVLOConfiguration For example, if the device is to be enabled when V reaches 33 V, and disabled when V decreases to 30 PWR PWR V,R1is113kΩ,andR2is4.42kΩ. CAUTION DonotallowthevoltageattheUVLOpintoexceed7Vatanytime. 24 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Application Information (continued) Ensure that both the power and voltage ratings are (0603 resistors can be rated as low as 50 V) for the selected R1resistor.MaintaintheUVLOthresholdaccuracy,byusingaresistortoleranceof1%orbetter. Remote control of the LM5037 operational modes can be accomplished with open drain device(s) connected to theUVLOpinasshowninFigure25. 5.0V LM5037 VIN 22 PA R1 1.25V UVLO STANDBY R2 0.45V STANDBY OFF SHUTDOWN Figure25. RemoteStandbyandDisableControl 8.1.5 HiccupModeCurrentLimitRestart(RESPin) The basic operation of the hiccup mode current limit is described in the functional description. The delay time to the initiation of a hiccup cycle is programmed by the selection of the RES pin capacitor C as illustrated in RES Figure26. Current Limit Detected Current Limit Persists at CS 2.0V RES 0V 5V 100PA #(cid:3)1V SS 1(cid:3)PA OUTA OUTB t1 t2 t3 Figure26. HiccupOver-LoadRestartTiming In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for C to reach RES the2.0Vhiccupmodethresholdis: C x 2.0V RES t1 = = 111K x C 18 PA RES (10) Forexample,ifC =0.01 µFthetimet1isapproximately2.0ms.Thecooldowntime,t2issetbythesoft-start RES capacitor(C )andtheinternal1µASScurrentsource,andisequalto: SS C x 1V t2 = S1S PA = 1M x CSS (11) Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com Application Information (continued) IfC =0.01 µF,t2is ≊10ms. SS Thesoft-starttimet3issetbytheinternal100 µAcurrentsource,andisequalto: C x 4V t3 = 1S0S0 PA = 40K x CSS (12) IfC =0.01 µF,t3is ≊400 µs. SS The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or short circuit. This off time results in lower average input current and lower power dissipation within the power components. It is recommended that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this feature. If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup mode(t1=0),theRESpincanbeleftopen(noexternalcapacitor).Todisablethehiccupmodeentirely,connect theRESpintoground(AGND). 8.2 Typical Application Figure 27 shows an example of an LM5037-controlled 50-W half-bridge converter. The converter provides a single regulated 5-V output at 10 A, from a standard Telecoms 36-V to 72-V input. The converter is configured for feed-forward voltage-mode control. An auxiliary winding on the power transformer is used to supply the VCC voltageexternally,toreducethepowerdissipationinthedevice. 26 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 Figure27. TypicalApplicationSchematic,LM5037 Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 8.2.1 DesignRequirements • Operatinginputvoltagerange:36Vto72V • Outputvoltage:5V • Outputcurrent:10A • UVLOOnLevel:34VOn(rising) • UVLOOffLevel:30VOff(falling) • Outputripplevoltage,V :<2%(960mV ) RIPPLE(OUT) P-P • Oscillatorfrequency(2× f perphase):300kHz SW • Switchingfrequency(f perphase):150kHz SW 8.2.2 DetailedDesignProcedure 8.2.2.1 OscillatorFrequencyandMaximumDutyCycle TheLM5037oscillatorfrequencyistwicetheswitchingfrequencyofeachswitchinthehalf-bridgepowerstage. f =2×f (13) OSC SW Calculate the dead-time resistor value for R . The recommended of dead-time range is between 50 ns and 250 RT2 ns. A value of 175 ns is chosen, which sets a maximum duty cycle of approximately 95%. Equation 14 calculates theR resistorvalue,(R9inFigure27). RT2 æ t ö 175´10-9 RRT2 =çè5´D1E0A-D12 ÷ø= 5´10-12 =35kW (14) UsetheneareststandardE96valueof34.8kΩ. Use the resistor value on the RT2 pin to calculate the required resistor value for the RT1 pin (R8 in Figure 27) usingEquation15. ææ 1 ö ö ææ 1 ö ö çççèfOSC ÷ø-tDEAD ÷÷ çççè300´103 ÷ø-175´10-9 ÷÷ R = = =19.5kW RT1 ç 0.162´10-9 ÷ ç 0.162´10-9 ÷ ç ÷ ç ÷ ç ÷ ç ÷ è ø è ø (15) UsethenearestE96valueof20kΩ. 8.2.2.2 PowerStageDesign AsshownintheschematicinFigure27,theprimarycomponentsofthehalf-bridgepowerstageare: • Half-bridgesplittercapacitors(C1,C2,C3,C4,C5andC6) • PowerMOSFETs(Q1andQ2) • Powertransformer(T1) • Outputrectifier(D3) • Outputfilter(L2andC18,C19,andC20) The half-bridge stage DC input voltage divides evenly across the splitter capacitors, so that one end of the primary-side of the power transformer connects to a DC level of approximately V /2. The other end of the IN transformer primary is alternately connected by Q1 to the VIN pin, and then by Q2 to GND, with appropriate dead-time in between. The device modulates the dead-time or duty cycle in order to regulate the output voltage to the required level. Thus the primary winding is subjected to a bi-polar voltage swing of ±V /2. This voltage is IN then scaled by the secondary to primary turns ratio (N /N ). The secondary winding is center-tapped, so that the S P double-diode,D3canthenfull-waverectifythebi-polarsecondarywaveform.Auni-polarpulsetrainoccursatthe full f frequency of 300 kHz at the cathode of D3. Output filter inductor L2 and output capacitors C18, C19, OSC C20thenfilterthispulsetraintoaDCoutputvoltageplusACrippleatthef frequency. OSC The PWM controller adjusts the duty cycle with input line voltage in order to regulate the output voltage. The maximum duty cycle occurs at minimum operating input voltage, which is approximately 30 V (UVLO turn-off point). 28 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 æ2´V ´N ö æ2´5´2ö D=ç OUT P ÷=ç ÷=67% è VIN´NS ø è 30´1 ø (16) Equation 16 shows that there is sufficient tolerance to the oscillator 95% D setting (set by the RT2 resistor MAX value). Use Equation 17 to estimate the peak-to-peak ripple current (I ) in continuous conduction mode (CCM) P-P oncethedutycycle(D),f frequencyandturnsratio,andoutputinductance(L )arecalculatedorchosen. OSC OUT æççèæçèV2IN ´NNPS ÷øö-VOUTö÷÷ø D æççèVOUT -æççè2´VVIONUT2 ´NNPS ö÷÷øö÷÷ø DI = ´ = =1.24 A P_P L f L ´f P_P OUT OSC OUT OSC (17) 8.2.2.3 Half-BridgeMOSFETDriver Because this application uses half-bridge power stage MOSFETs connected in series between the VIN pin and GND, the Q1 device is high-side or floating. No high-side floating driver or bootstrap circuit which are necessary todriveQ1existsinthisdevice.Bothoftheoutputs(OUTAandOUTB)arelow-sideorgroundreferenced. This design uses an external high-side and low-side half-bridge driver device (U2, LM5100) to interface between the gate drive outputs and the actual gates of Q1 and Q2. The design requires a bootstrap capacitor (C16) to generatethenecessaryhigh-sideorfloatingbiassupplyforthehigh-sidedriversectionoftheLM5100. 8.2.2.4 UVLOSetting To ensure start-up at the required minimum system input voltage of 34 V, with the 4 V of hysteresis to the desiredturn-offlevel,calculatetheUVLOdividerresistorsR5andR6usingEquation18andEquation19. æççVHYS -çæç20´110.2-35´VIN÷ö÷÷ö÷ æçç4-æçç20´110.2-53´34ö÷÷÷ö÷ R5=ç è ø÷=ç è ø÷=157.1kW ç 22mA ÷ ç 22mA ÷ ç ÷ ç ÷ ç ÷ ç ÷ è ø è ø (18) Roundthiscalculatedvaluetothemoreconvenientvalueof150kΩ. æ1.25´R ö 1.25´150kW R6=ç R5 ÷= =5.73kW è VIN-1.25 ø 34-1.25 (19) UsetheneareststandardE96valueof5.76kΩ. 8.2.2.5 VIN,VCC,Start-Up To reduce the power dissipation in the internal start-up regulator on the VIN pin, use a separate external VCC supply. Usually, it is the auxiliary winding on the transformer that derives this external VCC supply. The auxiliary to secondary turns ratio is 2:1, so when the output voltage regulates at 5 V, the auxiliary VCC voltage approximately10V.ThisissufficientlygreaterthanthemaximuminternalVCCregulatorlevelof8Vtoback-bias theinternalregulatorafterstart-up. 8.2.2.6 Voltage-ModeRampInput Because this design uses voltage-mode control, connect an R-C network from the system input voltage to the RAMP pin, R4 and C9 as shown in Figure 27. Use Equation 5 to calculate the required R-C values. Using a value of 1 nF for C9, and targeting a ramp amplitude of 850 mV at V (a good compromise between signal IN(min) rangeandnoiseimmunity),Equation20calculatestherequiredvalueR4. æ ö ç ÷ æ ö ç ÷ ç ÷ -1 -1 R4=ç ÷=ç ÷=139.5kW çççfOSC´C9´lnæçç1- VVRAMP ö÷÷÷÷÷ ççè300kW´1nF´lnæçè1-03.865ö÷ø÷÷ø IN(min) è è øø (20) Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com UsethenearestE96valueof140kΩ. 8.2.2.7 Soft-StartDelay UseEquation21tocalculatethetimeperiodfromsoft-startdelaytocommencementoffirstPWMswitching. æ1.0 V´C12ö æ1.0 V´0.1mFö tSS(dly)=çè 100mA ÷ø=çè 100mA ÷ø=1.0ms (21) After the soft-start delay period, the soft-start ramp time depends on the power stage design and the operating conditions(inputvoltageandoutputload). 8.2.2.8 OverloadTimer With a timing capacitance of 10 nF on the RES pin (C13), calculate hiccup-mode timing and duty cycle for a sustained over-current condition using Equation 22 and Equation 23. Time period t1 describes the hiccup-mode current-limitpersisttimeandtimeperiodt2describeshiccup-modecool-downoff-time. æ2.0 V´C13ö æ2.0 V´10nFö t1=ç ÷=ç ÷=1.11ms è 18mA ø è 18mA ø (22) æ1.0 V´C12ö æ1.0 V´´100nFö t2=ç ÷=ç ÷=100ms è 1mA ø è 1mA ø (23) Calculatethehiccup-modedutycycleusingEquation24. t1 1.11 D = = =1.09% HICCUP t1+t2+t 1.11+100+1 SS (24) 8.2.2.9 CurrentSense In order to improve the efficiency, a current sense transformer (T2) is used. This transformer uses a 1:100 step- downratio.Thisratioreducesthepowerdissipationinthecurrent-senseresistor,R11. Setthecurrent-limitpointaftercalculatingthe • outputinductorpeak-to-peakripplecurrentwhenthedeviceoperatesinCCM • theturnsratiosofthemaintransformer(N /N ) S P • theturnsratiosofthecurrent-sensetransformer(CSR) Using the full load output current of 10 A, and the current limit target of 150%, or 15 A, calculate the required valueforR11.TheR11resistancemustgenerateavoltageattheCSpintoequaltheinternalcycle-by-cyclelimit ofnominally0.25Vatthecurrentlimitlevelattheoutput. 0.25 V 0.25 V R11= = =3.2W æ DIö N 1 æ 1.24ö 1 1 çèIILIM+ 2 ÷ø´NPS ´CSR çè15+ 2 ÷ø´2´100 (25) Round the calculated R11 resistance to a standard 3 Ω. If the power stage operates heavily in CCM, the output inductorripplecomponentcanbeignoredtoyieldagoodfirst-orderapproximationtotherequiredvalue. 8.2.2.10 OutputVoltageFeedback Because the output of the DC-DC converter is isolated from the input, this design uses a secondary-side reference (U5) and error amplifier (U3). The output of the error amplifier, U3 represents the required demand level to maintain regulation as a function of output load and input line. The design couples the demand signal acrosstheisolationbarriertotheprimarythroughopto-coupler,U6. Because the error amplifier and reference reside on the secondary side, this design disregards the internal reference and error amplifier features of the LM5037 device. The FB pin of the LM5037 device is connected to GND, which forces the COMP pin to pull up to approximately 5 V through the internal 5-kΩ pull-up resistance. The opto-coupler, U6 then externally pulls down on the COMP pin to set the required level to achieve the requireddutycycleatanygivenloadorlinelevel. 30 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 8.2.3 ApplicationCurves V =48Vdc 1V/div V =48Vdc V/div=1V IN IN I =10A Time=1ms/div Time=1µs/div OUT Figure28.OutputVoltageDuringSoft-StartPeriod Figure29.OutputVoltageDuringSoft-StopPeriod VIN=36Vdc V/div=10V VIN=72Vdc V/div=20V IOUT=10A Time=2µs/div IOUT=10A Time=2µs/div Figure30.DrainWaveformofQ2 Figure31.DrainWaveformofQ2 Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com VIN=48Vdc VOUT(P-P),50mV/div VIN=48Vdc TopTrace:IOUTStep,5Ato10A IOUT=10A Time=5µs/div IOUTStep,5Ato10A BottomTrace:VOUT,100mV/div BandwidthLimit=20MHz Time=200µs/div BandwidthLimit=20MHz Figure32.OutputRipple Figure33.TransientResponse f =250kHz SW Figure34.Efficiencyvs.LoadCurrent 9 Power Supply Recommendations The VCC pin requires a local decoupling capacitor that is connected to GND. This capacitor ensures stability of the internal regulator from the VIN pin. The decoupling capacitor also provides the current pulses to drive the gates of the external MOSFETs through the driver output pins. Place the decoupling capacitor close to the VCC andPGNDpinsandtrackitdirectlytothosepins. Thetwogroundpins(PGNDandAGND)mustbeconnectedtogetherwithashort,directPCBconnection. 32 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

LM5037 www.ti.com SNVS578D–NOVEMBER2008–REVISEDMAY2015 10 Layout 10.1 Layout Guidelines The LM5037 device current sense and PWM comparators are very fast, and respond to short duration noise pulses. Place components for the CS, COMP, SS, UVLO, RT2 and the RT1/SYNC pins as physically close as possibletothedevice.ThisplacementminimizesnoisepickuponthePCboardtraceinductances. Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the device pins. The ground side of the transformer should be connected via a dedicated PC board trace to the AGND pin, rather than throughthegroundplane. If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors should be used. In this case, all the noise sensitive, low-current ground trace should be connected in common nearthedevice,andthenasingleconnectionmadetothepowerground(senseresistorgroundpoint). While employing current mode control, RAMP pin capacitor and CS pin capacitor must be placed close to the device.Also,ashortdirecttraceshouldbeemployedtoconnectRAMPcapacitortotheCSpin. The gate drive outputs of the device should have short, direct paths to the power MOSFETs in order to minimize inductance in the PC board The two ground pins (AGND, PGND) must be connected together with a short, direct connection,toavoidjitterduetorelativegroundbounce. If the internal dissipation of the device produces high junction temperatures during normal operation, the use of multiple vias under the device to a ground plane can help conduct heat away from the device. Judicious positioning of the PC board within the end product, along with use of any available air flow (forced or natural convection) helps reduce the junction temperatures. If using forced air cooling, avoid placing the device in the airflowshadowoftallcomponents,suchasinputcapacitors. 10.2 Layout Example From VIN RAMP VIN UVLO REF COMP VCC From FB FB OUTA To GDA LM5037 RT2 OUTB To GDB AGND PGND RT1 SS From CS CS RES Figure35. LM5037BoardLayout Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM5037

LM5037 SNVS578D–NOVEMBER2008–REVISEDMAY2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.2 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 34 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM5037

PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LM5037MT/NOPB LIFEBUY TSSOP PW 16 92 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM5037 & no Sb/Br) MT LM5037MTX/NOPB LIFEBUY TSSOP PW 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM5037 & no Sb/Br) MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2017 Addendum-Page 2

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