Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 LM5005 75-V, 2.5-A Step-Down Switching Regulator With Wide Input Voltage Range 1 Features 3 Description • High-EfficiencyDC-DCBuckConverter The LM5005 high-voltage buck converter features all 1 of the functions necessary to implement an efficient – WideInputVoltageRangeFrom7Vto75V high-voltage switching regulator with a minimum – AdjustableOutputVoltageasLowas1.225V number of external components. This easy-to-use – OutputCurrentasHighas2.5A converter operates over an input voltage range from 7 V to 75 V and delivers a maximum output current of – JunctionTemperatureRange –40°Cto125°C 2.5 A. The control loop architecture is based upon • Integrated75-V,160-mΩ BuckMOSFET current-mode control using an emulated current ramp • MeetsEN55022andCISPR22EMIStandards for high noise immunity. Current-mode control provides inherent line feed-forward, cycle-by-cycle • ±1.5%FeedbackVoltageAccuracy overcurrent protection and straightforward loop • EmulatedPeakCurrent-ModeControl compensation. The use of an emulated control ramp – Ultra-FastLineandLoadTransientResponse reduces noise sensitivity of the PWM circuit, allowing • SwitchingFrequencyFrom50kHzto500kHz reliable control of small duty cycles necessary in high inputvoltageapplications. • MasterorSlaveFrequencySynchronizationInput The switching frequency is resistor-programmable • 80-nsMinimumPWMONTimeForLowV OUT from 50 kHz to 500 kHz. To reduce EMI, an oscillator • MonotonicStart-upintoPrebiasedOutput synchronization pin allows multiple LM5005 • InternalHigh-VoltageVCCBiasSupplyRegulator regulators to self-synchronize or be synchronized to • AuxiliaryBiasSupplyOptiontoVCC an external clock signal. Additional protection features include configurable soft start, external • ConfigurableSoftStartWithTracking power supply tracking, thermal shutdown with • PrecisionStandbyandShutdownInput automaticrecovery,andremoteshutdowncapability. – ProgrammableInputUVLOWithHysteresis The LM5005 is available in an 20-pin HTSSOP • RemoteShutdownandStandbyControl package with an exposed pad that is soldered to the • Cycle-by-CycleOvercurrentProtection PCB to achieve a low junction-to-board thermal impedance. To create a custom regulator design, use • VCCandGateDriveUVLOProtection theLM5005withWEBENCH®PowerDesigner. • ThermalShutdownProtectionWithHysteresis • Thermally-Enhanced20-PinHTSSOPPackage DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications LM5005 HTSSOP(20) 6.50mm×4.40mm • High-EfficiencyPoint-of-LoadRegulators (1) For all available packages, see the orderable addendum at • TelecommunicationsInfrastructure theendofthedatasheet. • FactoryAutomationandControl SPACER TypicalApplicationCircuit TypicalEfficiency,V =5V OUT V 100 IN 3,4 VIN BST 20 C CBST 90 IN 2 SD 17,18 LF VOUT SW 80 optional LM5005 18 VCC PRE 19 DF COUT (cid:8)y () 70 CVCC RT RT IS 15,16 cienc 60 OUT 12 RFB1 Effi 50 VIN = 12 V SYNC 5 SYNC FB 7 VIN = 24 V optional 9 RAMP 6 CC1 RC1 40 VVIINN == 3468 VV 11 SS COMP RFB2 30 VIN = 60 V CRAMP CSS PGND AGND VIN = 75 V 13,14 10 CC2 20 0 0.5 1 1.5 2 2.5 Copyright ' 2016, Texas Instruments Incorporated Output Current (A) D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 15 2 Applications........................................................... 1 8.1 ApplicationInformation............................................15 3 Description............................................................. 1 8.2 TypicalApplication..................................................17 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 26 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 26 6 Specifications......................................................... 5 10.1 LayoutGuidelines.................................................26 6.1 AbsoluteMaximumRatings......................................5 10.2 LayoutExample....................................................29 6.2 ESDRatings..............................................................5 11 DeviceandDocumentationSupport................. 31 6.3 RecommendedOperatingConditions.......................5 11.1 Third-PartyProductsDisclaimer...........................31 6.4 ThermalInformation..................................................5 11.2 DeviceSupport ....................................................31 6.5 ElectricalCharacteristics...........................................6 11.3 DocumentationSupport........................................31 6.6 SwitchingCharacteristics..........................................7 11.4 ReceivingNotificationofDocumentationUpdates31 6.7 TypicalCharacteristics..............................................7 11.5 CommunityResources..........................................32 7 DetailedDescription.............................................. 9 11.6 Trademarks...........................................................32 7.1 Overview...................................................................9 11.7 ElectrostaticDischargeCaution............................32 7.2 FunctionalBlockDiagram.........................................9 11.8 Glossary................................................................32 7.3 FeatureDescription...................................................9 12 Mechanical,Packaging,andOrderable Information........................................................... 32 7.4 DeviceFunctionalModes.......................................14 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(March2013)toRevisionE Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedSimplifiedApplicationSchematicimage................................................................................................................... 1 • AddedTypicalApplicationCircuitimage................................................................................................................................ 1 • ChangedJunctiontoAmbient,R ,valueintheThermalInformationtableFrom:40To:35.2........................................... 5 θJA • ChangedJunctiontoCase,R ,valueintheThermalInformationtableFrom:4To:1.2............................................... 5 θJC(bot) • ChangedEfficiencyvsI andV graph.............................................................................................................................. 7 OUT IN • DeletedR toV forV >7.5Vfigure........................................................................................................................ 13 RAMP CC OUT • AddedConnectionofExternalRampResistortoVCCwhenVOUT>7.5Vfigure............................................................. 13 ChangesfromRevisionC(March2013)toRevisionD Page • ChangedlayoutofNationalSemiconductorDataSheettoTIformat.................................................................................... 1 2 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 5 Pin Configuration and Functions PWPPackage 20-PinHTSSOP TopView VCC 1 20 BST SD 2 19 PRE VIN 3 18 SW VIN 4 17 SW SYNC 5 16 IS Exposed Pad COMP 6 15 IS FB 7 14 PGND RT 8 13 PGND RAMP 9 12 OUT AGND 10 11 SS Not to scale PinFunctions PIN TYPE(1) DESCRIPTION NO. NAME Outputofthebiasregulator.VCCtracksVINupto9V.Beyond9V,VCCisregulatedto7V.A0.1-µFto 1 VCC I 1-µFceramicdecouplingcapacitorisrequired.Anexternalvoltage(7.5Vto14V)canbeappliedtothis pintoreduceinternalpowerdissipation. ShutdownorUVLOinput.IftheSDpinvoltageisbelow0.7V,theregulatorisinalowpowerstate.Ifthe SDpinvoltageisbetween0.7Vand1.225V,theregulatorisinstandbymode.IftheSDpinvoltageis 2 SD I above1.225V,theregulatorisoperational.Useanexternalvoltagedividertosetalineundervoltage shutdownthreshold.IftheSDpinisleftopencircuit,a5-µApullupcurrentsourceconfigurestheregulator asfullyoperational. 3,4 VIN P Inputsupplyvoltage,nominaloperatingrange:7Vto75V. Oscillatorsynchronizationinputoroutput.Theinternaloscillatorcanbesynchronizedtoanexternalclock 5 SYNC I/O withanexternalpulldowndevice.MultipleLM5005regulatorscanbesynchronizedtogetherbyconnection oftheirSYNCpins. Outputoftheinternalerroramplifier,theloopcompensationnetworkmustbeconnectedbetweenthispin 6 COMP O andtheFBpin. Feedbacksignalfromtheregulatedoutput.Thispinisconnectedtotheinvertinginputoftheinternalerror 7 FB I amplifier.Theregulationthresholdis1.225V. Internaloscillatorfrequencysetinput.Theinternaloscillatorissetwithasingleresistorconnectedbetween 8 RT I RTandAGNDpins.Therecommendedswitchingfrequencyrangeis50kHzto500kHz. Rampcontrolsignal.AnexternalcapacitorconnectedbetweenRAMPandAGNDpinssetstherampslope 9 RAMP I usedforemulatedpeakcurrent-modecontrol.Recommendedcapacitancerangeis50pFto2nF. 10 AGND G Analogground.Internalreferencefortheregulatorcontrolfunctions. Soft-start.Anexternalcapacitorandaninternal10-µAcurrentsourcesettherampratefortheriseofthe 11 SS I erroramplifier'sreference.TheSSpinisheldlowduringstandby,VCCUVLOandthermalshutdown. 12 OUT I Outputvoltageconnection.Connectdirectlytotheregulatedoutputvoltage. 13,14 PGND G Powerground.Low-sidereferencefortheintegratedPREswitchandtheIScurrentsenseresistor. Currentsense.CurrentmeasurementconnectionforthefreewheelingSchottkydiode.Aninternalsense 15,16 IS P resistorandasample-and-holdcircuitsensethediodecurrentneartheconclusionoftheoff-time.This currentmeasurementprovidestheDCleveloftheemulatedcurrentramp. Switchingnode.Thesourceterminaloftheinternalbuckswitch.ConnecttheSWpintotheexternal 17,18 SW P Schottkydiodeandtothebuckinductor. (1) G=Ground,I=Input,O=Output,P=Power Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com PinFunctions(continued) PIN TYPE(1) DESCRIPTION NO. NAME Prechargeassistforthebootstrapcapacitor.Connectthisopen-drainoutputtotheSWpinstoaidcharging thebootstrapcapacitorduringlight-loadconditionsorinapplicationswheretheoutputmaybeprecharged 19 PRE P beforetheLM5005isenabled.AninternalprechargeMOSFETisturnedonfor250nseachcyclejustprior totheon-timeintervalofthebuckswitch. Boostinputforbootstrapcapacitor.ConnectanexternalcapacitorbetweentheBSTandSWpins.A22-nF 20 BST P ceramiccapacitorisrecommended.ThecapacitorischargedfromVCCthroughaninternalbootstrap diodeduringtheoff-timeofthebuckswitchwhentheSW-nodevoltageislow. Exposedpad.Exposedmetalpadontheundersideofthedevice.ConnectthispadtothePCBground — EP P planetoassistwithheatspreading. 4 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 6 Specifications 6.1 Absolute Maximum Ratings Overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT VINtoGND 76 V BSTtoGND 90 V PREtoGND 76 V SWtoGND(steadystate) –1.5 76 V BSTtoVCC 76 V VCCtoGND 14 V BSTtoSW 14 V OUTtoGND LimitedtoV V VIN SD,SYNC,SS,FBtoGND 7 V Junctiontemperature,T –40 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. 6.2 ESD Ratings VALUE UNIT Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V (ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±750 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions Overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Inputvoltage 7 75 V IN I Outputcurrent 0 2.5 A OUT T Operatingjunctiontemperature –40 125 °C J (1) RecommendedOperatingConditionsareconditionsunderwhichoperationofthedeviceisintendedtobefunctional.Forensured specificationsandtestconditions,seetheElectricalCharacteristics. 6.4 Thermal Information LM5005 THERMALMETRIC(1) PWP(HTSSOP) UNIT 20PINS R Junction-to-ambientthermalresistance 35.2 °C/W θJA R Junction-to-case(top)thermalresistance 17.8 °C/W θJC(top) R Junction-to-boardthermalresistance 15.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 15.3 °C/W JB R Junction-to-case(bottom)thermalresistance 1.2 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com 6.5 Electrical Characteristics TypicalvaluescorrespondtoT =25°C.Minimumandmaximumlimitsapplyoverthe–40°Cto125°Cjunctiontemperature J range.V =48VandR =32.4kΩ(unlessotherwisenoted).(1) IN T PARAMETER TESTCONDITIONS MIN(2) TYP MAX(2) UNIT START-UPREGULATOR V VCCregulatoroutput 6.85 7.15 7.45 V VCC-REG V VCCLDOmodeturnoff 9 V VCC-EXT I VCCcurrentlimit V =0V 20 mA VCC-CL VCC VCCSUPPLY V VCCUVLOthreshold V increasing 5.95 6.35 6.75 V VCC-UV VCC V VCCundervoltagehysteresis 1 V VCC-HYS I Biascurrent,I V =1.3V 5 mA VCC IN FB I Shutdowncurrent,I V =0V 60 100 µA SD IN SD SHUTDOWNTHRESHOLDS V Shutdownthreshold 0.5 0.7 0.9 V SD-TH V Shutdownhysteresis 0.1 V SD-HYS V Standbythreshold 1.18 1.225 1.27 V SBY-TH V Standbyhysteresis 0.1 V SBY-HYS I SDpullupcurrentsource 5 µA SD BUCKSWITCH R Buckswitch,R 160 320 mΩ DS-ON DS(on) V BOOSTUVLO 3.8 V BST-UV V BOOSTUVLOhysteresis 0.56 V BST-UV-HYS R Prechargeswitch,R 75 Ω PRE DS(on) CURRENTLIMIT I Cycle-by-cyclecurrentlimit RAMP=0V 3 3.5 4.25 A CL T Cycle-by-cyclecurrentlimitdelay RAMP=2.5V 100 ns CL-DLY SOFT-START I SScurrentsource 7 10 13 µA SS OSCILLATOR F Switchingfrequency1 180 200 220 kHz SW1 F Switchingfrequency2 R =11kΩ 425 485 525 kHz SW2 T R SYNCsourceimpedance 10 kΩ SYNC-SRC R SYNCsinkimpedance 160 Ω SYNC-SINK V SYNCthreshold(falling) 1.4 V SYNC-FALL F SYNCfrequency 550 kHz SYNC-MAX T SYNCpulsewidthminimum 15 ns SYNC-MIN RAMPGENERATOR I Rampcurrent1 V =60V,V =10V 234 275 316 µA RAMP1 IN OUT I Rampcurrent2 V =10V,V =10V 20 25 30 µA RAMP2 IN OUT PWMCOMPARATOR V COMPtoPWMcomparatoroffset 0.7 V COMP-OFS (1) Thejunctiontemperature(T in°C)iscalculatedfromtheambienttemperature(T in°C)andpowerdissipation(P inWatts)asfollows: J A D T =T +(P ×R )whereR (in°C/W)isthepackagethermalimpedanceprovidedinThermalInformation. J A D θJA θJA (2) Minimumandmaximumlimitsare100%productiontestedat25°C.Limitsovertheoperatingtemperaturerangeareensuredthrough correlationusingStatisticalQualityControl(SQC)methods.LimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL). 6 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Electrical Characteristics (continued) TypicalvaluescorrespondtoT =25°C.Minimumandmaximumlimitsapplyoverthe–40°Cto125°Cjunctiontemperature J range.V =48VandR =32.4kΩ(unlessotherwisenoted).(1) IN T PARAMETER TESTCONDITIONS MIN(2) TYP MAX(2) UNIT ERRORAMPLIFIER V Feedbackvoltage V =V 1.207 1.225 1.243 V FB FB COMP I FBbiascurrent 10 nA FB-BIAS A DCgain 70 dB OL I COMPsinkandsourcecurrent 3 mA COMP F Unitygainbandwidth 3 MHz BW THERMALSHUTDOWN T Thermalshutdownthreshold 165 °C SD T Thermalshutdownhysteresis 25 °C SD-HYS 6.6 Switching Characteristics Overoperatingfree-airtemperaturerange(unlessotherwisenoted). PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T MinimumcontrollablePWMon-time 80 ns ON-MIN T ForcedPWMoff-time 500 ns OFF-MIN T Prechargeswitchon-time 275 ns PRE 6.7 Typical Characteristics Unlessotherwisespecified,V =48VandV =5V(seeTypicalApplicationforcircuitdesigns). IN OUT 1000 1.010 Y C Hz) UEN UENCY (k OR FREQ 1.005 REQ 100 LLAT 1.000 F CI R S O O T D A E 0.995 L Z CIL ALI S M O R NO 0.990 10 -50 -25 0 25 50 75 100 125 1 10 100 1000 RT (k:) TEMPERATURE (oC) F =200kHz OSC Figure1.OscillatorFrequencyvsR Figure2.OscillatorFrequency T vsTemperature Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) Unlessotherwisespecified,V =48VandV =5V(seeTypicalApplicationforcircuitdesigns). IN OUT 8 1.10 T N E R R U 1.05 6 C T R A OFTST 1.00 )V( CC 4 S V D E Z LI 0.95 2 A M R O N 0.90 0 -50 -25 0 25 50 75 100 125 0 4 8 12 16 20 24 TEMPERATURE (oC) ICC (mA) V =12V IN Figure3.Soft-StartCurrentvsTemperature Figure4.VCCvsICC 10 50 225 40 180 8 30 135 V (V)CC 46 Ramp Down GAIN (dB) 12000 PHASE 04950 PHASE (°) GAIN -10 -45 2 Ramp Up -20 -90 0 -30 -135 0 2 4 6 8 10 10k 100k 1M 10M 100M VIN (V) FREQUENCY (Hz) R =7kΩ A =101 L VCL Figure5.V vsV Figure6.ErrorAmplifierGainandPhase CC IN 100 90 80 (cid:8)) 70 y ( nc 60 e ci Effi 50 VIN = 12 V VIN = 24 V 40 VIN = 36 V VIN = 48 V 30 VIN = 60 V VIN = 75 V 20 0 0.5 1 1.5 2 2.5 Output Current (A) D001 Figure7.LM5005EvaluationBoardEfficiencyvsI andV OUT IN 8 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 7 Detailed Description 7.1 Overview The LM5005 high-voltage switching regulator features all of the functions necessary to implement an efficient high-voltage buck regulator using a minimum of external components. This easy-to-use regulator integrates a 75-V N-channel buck switch with an output current capability of 2.5 A. The regulator control method is based on current mode control using an emulated current ramp. Peak current mode control provides inherent line feed- forward, cycle-by-cycle current limiting and simple loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of small duty cycles necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to 500 kHz. An oscillator synchronization pin allows multiple LM5005 regulators to self-synchronize or be synchronized to an external clock. The output voltage can be set at or above 1.225 V. Fault protection features include cycle-by-cycle current limiting, thermal shutdown and remote shutdown capability. The device is available inthe20-pinHTSSOPpackagefeaturinganexposedpadtoaidthermaldissipation. The LM5005's functional block diagram and typical application are shown in the following section. The LM5005 canbeappliedinnumerousapplicationstoefficientlystepdownfromanunregulatedinputvoltage.Thedeviceis wellsuitedfortelecom,industrial,andautomotivepowerbusvoltageranges. 7.2 Functional Block Diagram V = 7V to 75V LM5005 IN 3, 4 VIN 7V VCC 1 REGULATOR 5 PA 2C.2INP1F C2.I2N2PF RNU/AV1 2 SD 1.225V STANDBY UVLO STHHUETRDMOAWLN C0.V4C7CPF BST 20 SHUTDOWN DIS VIN SD UVLO CBST 0.7V 22nF CLK DRIVER LF CNU/AV RNU/AV2 11 SS 10 PA 1.225V RS QQ LSEHVIFETL SW 17, 18 33 PH VOUT = 5V C10SnSF 0.7V PWM PRE 19 C33S0pF C15O0UPT1F C22OPUFT2 C_LIMIT CLK D1 7 FB CSHD6-100C RS 10: CC2 C10Cn1F ERARMOPR 1.75V 0.5V/A STARMAPCLKE IS 15, 16 open RC1 and 49.9k:6 COMP CLK Ir + VIN HOLD PGND 13, 14 RAMP GENERATOR OSCILLATOR IRAMP = 5 PA u (VIN – VOUT) AGND 10 RFB1 + 25 PA CLK 5.11k: SYNC RT RAMP OUT 5 8 9 12 RFB2 SYNC 1.65k: R20T.5k: C33R0AMpPF Copyright ' 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 High-VoltageStart-UpRegulator The LM5005 contains a dual-mode internal high-voltage start-up regulator that provides the VCC bias supply for the PWM controller and bootstrap MOSFET gate driver. The VIN pins can be connected directly to the input voltage,ashighas75V.Forinputvoltagesbelow9V,alowdropoutswitchconnectsVCCdirectlytoVIN.Inthis supply range, VCC is approximately equal to VIN. For input voltages greater than 9 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating range of 7Vto75Visachievedthroughtheuseofthisdual-moderegulator. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) The output of the VCC regulator is current limited to 20 mA. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 6.3 V and the SD pin is greater than 1.225 V, a soft-start sequence begins. Switching continues until VCC falls below5.3VortheSDpinfallsbelow1.125V. An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary voltage is greater than 7.3 V, the internal regulator essentially shuts off, reducing the IC power dissipation. The VCC regulator series pass transistor includes a diode between VCC and VIN that must not be forward biased in normaloperation.ThereforetheauxiliaryVCCvoltagemustneverexceedtheVINvoltage. Take extra care in high-voltage applications to ensure the VIN and PRE pin voltages do not exceed their absolute maximum voltage ratings of 76 V. During line or load transients, voltage ringing on the input bus that exceeds the Absolute Maximum Ratings can damage the IC. Careful PC board layout and the use of quality input bypass capacitors placed close to the VIN and PGND pins are essential. See Layout Guidelines for more detail. VIN 9V VCC 7V 6.3V Internal Enable Signal Figure8. VINandVCCSequencing 7.3.2 ShutdownandStandby The LM5005 contains a dual-level shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the regulator is in a low-current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225 V, the regulator is in standby mode. In standby mode the VCC regulator is active but MOSFET switching is disabled. When the SD pin voltage exceeds 1.225 V, switching is enabled and normal operation begins. An internal 5-µA pullupcurrentsourceconfigurestheregulatortobefullyoperationaliftheSDpinisleftopen. An external voltage divider from VIN to GND can be used to set the operational input range of the regulator. The divider must be designed such that the voltage at the SD pin is greater than 1.225 V when VIN is in the desired operatingrange.Theinternal5-µApullupcurrentsourcemustbeincludedincalculationsoftheexternalset-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The voltage at the SD pin must never exceed 7 V. When using an external divider, it may be necessary to clamp the SD pin to limit its voltageathighinputvoltageconditions. 7.3.3 OscillatorandSynchronizationCapability The LM5005 oscillator frequency is set by a single external resistor designated R connected between the RT T and AGND pins. Place the R resistor close to the LM5005's RT and AGND pins. Calculate the resistance of R T T fromEquation1tosetadesiredswitchingfrequency,F . SW 7407 R “‹k:”… (cid:16)4.3 T FSW “‹kHz”… (1) 10 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Feature Description (continued) The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock signal must be of higher frequency than the free-running frequency of the LM5005 set by the R resistor. A clock circuit T with an open-drain output as shown in Figure 9 is the recommended interface to the SYNC pin. The clock pulse durationmustbegreaterthan15ns. LM5005 LM5005 SYNC SW SYNC SYNC AGND CLK LM5005 SW SYNC 500 ns Copyright ' 2016, Texas Instruments Incorporated Up to Five Total Devices Copyright © 2016, Texas Instruments Incorporated Figure9.ExternalClockSynchronization Figure10.Self-SynchronizationofMultiple LM5005Regulators Multiple LM5005 devices can be synchronized together simply by connecting the SYNC pins together. In this configuration all of the devices are synchronized to the highest frequency device. The diagram in Figure 11 illustrates the SYNC input/output features of the LM5005. The internal oscillator circuit drives the SYNC pin with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low either by the internal oscillator or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the SYNC pins of several LM5005 IC's are connected together, the IC with the highest internal clock frequency pulls the connected SYNC pins low first and terminates the oscillator ramp cycles of the other IC’s. The LM5005 with the highest programmed clock frequency serves as the master and controls the switching frequency of all the deviceswithloweroscillatorfrequency. 5V 10k SYNC I = f (R ) T 2.5V Q S Q R DEADTIME ONE-SHOT Figure11. SimplifiedOscillatorBlockDiagramandSYNCI/OCircuit Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com 7.3.4 ErrorAmplifierandPWMComparator The internal high-gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference of 1.225 V. The output of the error amplifier is at the COMP pin, allowing the user to connect loop compensation components, generally a type-II network, from COMP to FB as illustrated in the Functional Block Diagram. This network creates a pole at unity frequency, a zero, and a noise-attenuating high-frequency pole. The PWM comparator compares the emulated current sense signalfromtheRAMPgeneratortotheerroramplifier'soutputvoltageattheCOMPpin. 7.3.5 RAMPGenerator The ramp signal used in the pulse width modulator for current-mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading-edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimum achievable pulse-width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse-widths and duty cycles is necessary for regulation. The LM5005 uses a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the current signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading-edge spikes and measurement or filtering delays. The currentreconstructioniscomprisedoftwoelements:asample-and-holdDClevelandanemulatedcurrentramp. RAMP (5P x (VIN – VOUT) + 25P) x tON CRAMP Sample and Hold DC Level 0.5V/A TON Figure12. EmulatedCurrent-SenseRampWaveform Thesample-and-holdDClevelillustratedinFigure12isderivedfromameasurementofthecurrentflowinginthe freewheeling Schottky diode. Connect the freewheeling diode's anode terminal to the LM5005's IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample-and-hold provide the DC level for the reconstructed current signal. The positive slope inductor current ramp is emulated by an internal voltage-controlled current source and an external capacitor connected between the RAMP and AGND pins. The ramp current source that emulates the inductor currentisafunctionoftheinputandoutputvoltagesgivenbyEquation2. I 5(cid:29)$(cid:152)(cid:11)9 (cid:16)9 (cid:12)(cid:14)(cid:21)(cid:24)(cid:29)$ RAMP IN OUT (2) Proper selection of the RAMP capacitor depends upon the selected output inductance. Select the capacitance of C usingEquation3. RAMP C L (cid:152)10(cid:16)5 RAMP F where • L istheoutputinductanceinHenrys (3) F 12 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Withthisvalue,thescalefactoroftheemulatedcurrentrampisapproximatelyequaltothescalefactoroftheDC levelsample-and-hold(0.5V/A).PlacetheC capacitorclosetotheLM5005'sRAMPandAGNDpins. RAMP For duty cycles greater than 50%, peak current-mode control circuits are subject to subharmonic oscillation. Subharmonic oscillation is normally characterized by observing alternating wide and narrow pulses of the switch- node voltage waveform. Adding a fixed-slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25 µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage and high duty cycle applications, additional slope may be required. In these applications, add a pullup resistor between the VCC and RAMP pins to increase the ramp slopecompensation. ForV >7.5V,calculatetheoptimalslopecurrentwithEquation4. OUT I =V ×5µA/V (4) OS OUT Forexample,atV =10V,I =50µA. OUT OS InstallaresistorfromtheRAMPpintoVCCusingEquation5. R =V /(I –25µA) (5) RAMP VCC OS LM5005 VCC C VCC R RAMP RAMP C AGND RAMP Copyright ' 2016, Texas Instruments Incorporated Figure13. ConnectionofExternalRampResistortoVCCwhenV >7.5V OUT 7.3.6 CurrentLimit The LM5005 contains a unique current monitoring scheme for control and overcurrent protection. When set correctly, the emulated current sense signal provides a signal that is proportional to the buck switch current with a scale factor of 0.5 V/A. The emulated ramp signal is applied to the current limit comparator. If the emulated ramp signal exceeds 1.75 V (3.5 A), the present cycle is terminated (cycle-by-cycle current limiting). In applications with small output inductance and high input voltage, the switch current may overshoot due to the propagation delay of the current limit comparator. If an overshoot must occur, the diode current sampling circuit detects the excess inductor current during the off-time of the buck switch. If the sample-and-hold DC level exceeds the 1.75-V current limit threshold, the buck switch is disabled and skip pulses until the diode current sampling circuit detects that the inductor current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation, because the inductor currentisforcedtodecayfollowinganycurrentovershoot. 7.3.7 Soft-StartCapability Thesoft-startfeaturepreventsinrushcurrentimpactingtheLM5005regulatorandtheinputsupplywhenpoweris first applied. Output voltage soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The internal soft-start current source of 10 µA gradually increases the voltage of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the noninverting input of the error amplifier. Various sequencing and tracking schemes can be implemented usingexternalcircuitsthatlimitorclampthevoltageleveloftheSSpin. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com In the event a fault is detected, including overtemperature, VCC UVLO or shutdown, the soft-start capacitor is discharged.Whenthefaultconditionisnolongerpresent,anewsoft-startsequencecommences. 7.3.8 MOSFETGateDriver The LM5005 integrates an N-channel high-side MOSFET and associated floating high-voltage gate driver. This gate driver circuit works in conjunction with an internal bootstrap diode and an external bootstrap capacitor. A 22-nF ceramic capacitor, connected with short traces between the BST and SW pins, is recommended. During the off time of the buck switch, the SW voltage is approximately –0.5 V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. When operating at a high PWM duty cycle, the buck switch is forcedoffeachcyclefor500nstoensurethatthebootstrapcapacitorisrecharged. Under light-load conditions or when the output voltage is precharged, the SW voltage may not remain low during the off-time of the buck switch. If the inductor current falls to zero and the SW voltage rises, the bootstrap capacitor may not have sufficient voltage to operate the buck switch gate driver. For these applications, connect the PRE pin to the SW pins to precharge the bootstrap capacitor. The internal precharge MOSFET and diode connected between the PRE and PGND pins turns on each cycle for 250 ns just prior to the onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode), then no currentflowsthroughtheprechargeMOSFETanddiode. 7.4 Device Functional Modes 7.4.1 ShutdownMode The SD pin provides ON and OFF control for the LM5005. When V is below approximately 0.6 V, the device is SD in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 60 µA at V = 48 V. The LM5005 also employs VCC bias rail undervoltage protection. If the VCC IN biassupplyvoltageisbelowitsUVthreshold,theregulatorremainsoff. 7.4.2 StandbyMode The bias supply subregulator has a lower enable threshold than the regulator itself. When V is above 0.6 V SD and below the standby threshold (1.225 V typically), the VCC supply is on and regulating. Switching action and outputvoltageregulationarenotenableduntilV risesabovethestandbythreshold. SD 7.4.3 Light-LoadOperation The LM5005 maintains high efficiency when operating at light loads. Whenever the load current is reduced to a level less than half the peak-to-peak inductor ripple current, the device enters discontinuous conduction mode (DCM).CalculatethecriticalconductionboundaryusingEquation6. ’I V (cid:152)(cid:11)1(cid:16)D(cid:12) I L OUT BOUNDARY 2 2(cid:152)L (cid:152)F F SW (6) Whentheinductorcurrentreacheszero,theSWnodebecomeshighimpedance.ResonantringingoccursatSW as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node. At light loads, typically below 100 mA, several pulses may be skipped in between switching cycles, effectively reducingtheswitchingfrequencyandfurtherimprovinglight-loadefficiency. 7.4.4 ThermalShutdownProtection Internal thermal shutdown circuitry is provided to protect the regulator in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the regulator is forced into a low power reset state, disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from accidentaldeviceoverheating. 14 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information 8.1.1 ReducingBiasPowerDissipation The LM5005 is a wide input voltage range buck regulator with a maximum output current of 2.5 A. In general, buck regulators operating at high input voltage can dissipate a significant amount of bias power. The VCC regulator must step-down the input voltage to a nominal V level of 7 V. A large voltage drop across the VCC CC regulator implies a large power dissipation in the LM5005. There are several techniques that can significantly reducethisbiasregulatorpowerdissipation. Figure 14 and Figure 15 depict two methods to bias the IC from the output voltage. In each case the internal VCC regulator is used to initially bias the VCC rail. After the output voltage is established, the voltage at VCC is raised above the nominal 7-V regulation level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin must never exceed 14 V. The voltage at the VCC pin must not exceed the input voltage, V . IN R BST BST C BST L F SW VOUT LM5005 PRE DF COUT IS D VCC VCC PGND C VCC Copyright ' 2016, Texas Instruments Incorporated Figure14. VCCBiasFromtheOutputVoltagefor8V < V <14V OUT R BST BST C BST L F SW VOUT LM5005 PRE DF COUT IS D VCC VCC PGND CVCC Copyright ' 2016, Texas Instruments Incorporated Figure15. VCCBiasUsinganAdditionalWindingontheBuckInductor Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Application Information (continued) Given the increased gate drive capability with a higher VCC voltage, use a resistor R of 5 Ω to 10 Ω in series BST with the bootstrap capacitor to reduce the turnon speed of the power MOSFET and curtail SW node voltage overshootandringing. 8.1.2 InputVoltageUVLOProtection The SD input supports adjustable input voltage undervoltage lockout (UVLO) with hysteresis for application specific power-up and power-down requirements. SD connects to a comparator-based input referenced to a 1.225-V bandgap voltage with 100-mV hysteresis. An external logic signal can be used to drive the SD input to toggletheoutputONandOFFandforsystemsequencingorprotection. LM5005 V IN 5(cid:29)A R UV1 SD + R UV2 1.225V Shutdown/Standby Comparator 1.125V Copyright ' 2016, Texas Instruments Incorporated Figure16. ProgrammableInputVoltageUVLOWithHysteresis If the SD pin is not used, it can be left open circuit as it is pulled high by an internal 5-µA current source. This allows self-start-up of the LM5005 when VCC is within its valid operating range above its UVLO threshold. However, many applications benefit from using a resistor divider R and R as shown in Figure 16 to UV1 UV2 establishaprecisioninputvoltageUVLOlevel. Given V and V as the input voltage turnon and turnoff thresholds, respectively, select the UVLO IN(on) IN(off) resistorsusingEquation7andEquation8. 1.225V V (cid:152) (cid:16)V R IN(off) 1.125V IN(on) UV1 5(cid:29)$ (7) 1.225V R R (cid:152) UV2 UV1 V (cid:16)1.225V(cid:14)5(cid:29)$(cid:152)5 IN(on) UV1 (8) An optional capacitor C in parallel with R provides filtering for the divider. If the input UVLO level is set at a UV UV2 low input voltage, it is possible that the maximum SD pin voltage of 7 V could be exceeded at the higher end of the input voltage operating range. In this case, use a small 6.2-V Zener diode clamp from SD to AGND such that themaximumSDoperatingvoltageisneverexceeded. 16 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 8.2 Typical Application The following design procedure assists with component selection for the LM5005. Alternately, the WEBENCH® Design Tool is available to generate a complete design. With access to a comprehensive component database, this online tool uses an iterative design procedure to create an optimized design, allowing the user to experiment withvariousdesignoptions. The schematic diagram of a 5-V, 2.5-A regulator with an input voltage range is 7 V to 75 V is given in Figure 17. The free-running switching frequency (with the SYNC pin open circuit) is 300 kHz. In terms of control loop performance,thetargetloopcrossoverfrequencyis20kHzwithaphasemargininexcessof55°. LM5005 V = 7V to 75V IN 3,4 20 VIN BST CIN1 CIN2 RNU/AV1 2 C22BnSTF 33LPFH V = 5V SD 17,18 OUT 2.2PF 100V CUV RUV2 SW N/A N/A CS 19 330pF100V COUT1 COUT2 1 VCC PRE RS 150PF 22PF 8 RT U1 15,16 DF 10: 6.3V 16V IS C R VCC T CDSH6-100C 0.47PF 20.5k: 12 OUT R SYNC FB1 5 SYNC 7 5.11k: FB optional 9 RAMP CC1 RC1 10nF 49.9k: 11 SS COMP 6 RFB2 CRAMP CSS 1.65k: 330pF 10nF PGND AGND C 13,14 10 C2 N/A Copyright ' 2016, Texas Instruments Incorporated Figure17. LM5005CircuitSchematic 8.2.1 DesignRequirements An example of the step-by-step procedure to generate power stage and compensation component values using thetypicalapplicationsetupofFigure17isgivenbelow. ThecircuitshowninFigure17isconfiguredforthefollowingspecifications: • V =7Vto75V IN • V =5V OUT • I =2.5A OUT(max) • F =300kHz SW • MinimumloadcurrentforCCM=250mA • Lineandloadregulationlessthan1%and0.1%,respectively TheBillofMaterialsforthisdesignislistedinTable1. 8.2.2 DetailedDesignProcedure 8.2.2.1 FrequencySetResistor(R ) T Resistor R sets the switching frequency. Generally, higher frequency applications are smaller but have higher T losses. A switching frequency of 300 kHz is selected in this example as a reasonable compromise for small solution size and high efficiency. Calculate the resistance of R for a 300-kHz switching frequency with T Equation9. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Typical Application (continued) 7407 R “‹k:”… (cid:16)4.3 T FSW “‹kHz”… (9) Choosetheneareststandardresistorvalueof20.5kΩforR . T 8.2.2.2 Inductor(L ) F The inductance is determined based on the switching frequency, load current, inductor ripple current, and the minimumandmaximuminputvoltagesdesignatedV andV ,respectively. IN(min) IN(max) nt IPEAK e rr I u OUT C ’I L or IVALLEY ct u d n I 0 A t T 1 S F SW Figure18. InductorCurrentWaveform To keep the converter operating in CCM, the maximum inductor ripple current ΔI must be less than twice the L minimum load current, or 0.5-A peak-to-peak. Using this value of ripple current, calculate the inductance using Equation10. V (cid:152)(cid:11)V (cid:16)V (cid:12) 5V(cid:152)(cid:11)75V(cid:16)5V(cid:12) L OUT IN(max) OUT 31(cid:29)+ F ’I (cid:152)F (cid:152)V 0.5A(cid:152)300kHz(cid:152)75V L SW IN(max) (10) Use the nearest standard value of 33 µH. An alternative method is to choose an inductance that gives an inductorripplecurrentof30%to50%oftheratedfullloadcurrentatthenominalinputvoltage. Note that the inductor must be rated for the peak inductor current, denoted as I in Figure 18, to prevent PEAK saturation. During normal loading conditions, the peak inductor current corresponds to maximum load current plus half the maximum peak-to-peak ripple current. The peak inductor current during an overload condition is limited to 3.5 A nominal (4.25 A maximum). The selected inductor in this design example (see Table 1) has a conservative 6.2-A saturation current rating. The saturation current is defined by this inductor manufacturer as thecurrentrequiredfortheinductancetoreduceby30%at20°C. 8.2.2.3 RampCapacitor(C ) RAMP With the inductor selected, calculate the value of C necessary for the emulation ramp circuit using RAMP Equation11. C “‹pF”… 10(cid:152)L “‹(cid:29)+”… RAMP F (11) WithL selectedas33µH,therecommendedC is330pF.UseacapacitorwithNP0orC0Gdielectric. F RAMP 8.2.2.4 OutputCapacitors(C ) OUT The output capacitor filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM5005 that provide various advantages. The best performance is typically obtained using ceramic or polymer electrolytic type components. Typical trade- offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while electrolytic capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting an output capacitor, the two performance characteristics to consider are the output voltage ripple andloadtransientresponse.ApproximatetheoutputvoltageripplewithEquation12. 18 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Typical Application (continued) § 1 •2 ’V ’I R 2 (cid:14)¤ ‚ OUT L ESR '8(cid:152)F (cid:152)C „ SW OUT where • ΔV isthepeak-to-peakoutputvoltageripple OUT • R istheeffectiveseriesresistance(ESR)oftheoutputcapacitor ESR • F istheswitchingfrequency SW • C istheeffectiveoutputcapacitance (12) OUT Theamountofoutputvoltagerippleisapplicationspecific.Ageneralrecommendationistokeeptheoutputripple lessthan1%oftheratedoutputvoltage. Bear in mind that ceramic capacitors are sometimes preferred because they have low ESR. However, depending on package and voltage rating of the capacitor, the effective in-circuit capacitance can drop significantly with applied voltage. The output capacitor selection also affects the output voltage droop during a load transient. The peak deviation of the output voltage during a load transient is dependent on many factors. An approximation of thetransientdipignoringloopbandwidthisobtainedusingEquation13: L (cid:152)’I 2 V ’I (cid:152)R (cid:14) F OUT(cid:16)STEP DROOP OUT(cid:16)STEP ESR C (cid:152)(cid:11)V (cid:16)V (cid:12) OUT IN OUT where • C istheminimumrequiredoutputcapacitance OUT • L isthebuckfilterinductance F • V istheoutputvoltagedeviationignoringloopbandwidthconsiderations DROOP • ΔI istheloadstepchange OUT-STEP • R istheoutputcapacitorESR ESR • V istheinputvoltage IN • V istheoutputvoltagesetpoint (13) OUT A 22-µF, 16-V ceramic capacitor with X7R dielectric and 1210 footprint and a 150-µF, 6.3-V polymer electrolytic capacitor are selected here based on a review of each capacitor's tolerance and voltage coefficient to meet output ripple specification. The ceramic capacitor provides ultra-low ESR to reduce the output ripple voltage and noise spikes, while the electrolytic capacitor provides a large bulk capacitance in a small volume for transient loadingconditions. 8.2.2.5 SchottkyDiode(D ) F ASchottkytypefreewheelingdiodeisrequiredforallLM5005applications.Selectthediode'sreversebreakdown rating for the maximum V plus some safety margin. Ultra-fast diodes are not recommended and may result in IN damage to the regulator due to reverse recovery current transients. The near ideal reverse recovery characteristics and low forward voltage drop of a Schottky diode are particularly important diode characteristics forhighinputvoltageandlowoutputvoltageapplicationscommontotheLM5005. The reverse recovery characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The benign reverse recovery characteristics of a Schottky diode minimizes the peak instantaneous power in the buck switch occurring during turnon each cycle, and the resulting switching losses of thebuckswitcharesignificantlyreduced. The diode's forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a low output voltage. Rated current for diodes vary widely from various manufactures. The worst case is to assume a short-circuit load condition. In this case the diode conducts the output current almost continuously. For the LM5005 this current can be as high as 3.5 A. Assuming a worst-case 1-V drop across the diode, the maximum diode power dissipation can be as high as 3.5 W. For this design example, a 100-V, 6-A Schottky in a DPAKpackageisselected. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Typical Application (continued) 8.2.2.6 InputCapacitors(C ) IN The regulator supply voltage has a large source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the buck switch turns on, the current into the VIN pins steps to the lower peak of the inductor current waveform, ramps up to the peak value, then drops to zero at turnoff. The average current into VIN during the on-time is the load current. The input capacitance must be selected for RMS current rating and minimumripplevoltage.AgoodapproximationfortherequiredripplecurrentratingnecessaryisI >I /2. RMS OUT Select ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage derating effects, two 2.2-µF, 100-V ceramic capacitors are used. If step input voltage transients are expected near the maximum rating of the LM5005, a careful evaluation of ringing and possible spikes at the VIN pin id required.Anadditionaldampingnetwork,snubbercircuitorinputvoltageclampmayberequiredinthesecases. 8.2.2.7 VCCCapacitor(C ) VCC ThecapacitorattheVCCpinprovidesnoisefilteringandstabilityfortheVCCregulator.Therecommendedvalue ofC is0.47µFandmustbealow-ESRceramiccapacitorofX7Rdielectricratedforatleast16V. VCC 8.2.2.8 BootstrapCapacitor(C ) BST The bootstrap capacitor connected between the BST and SW pins supplies the gate current to charge the buck switch gate at turnon. The recommended value of C is 22 nF. Choose a low ESR ceramic capacitor with X7R BST dielectricratedforatleast16V. 8.2.2.9 SoftStartCapacitor(C ) SS The capacitor connected to the SS pin determines the soft-start time, or the time for the reference voltage and the output voltage to reach their final regulated values. If t is the required soft-start time, calculate the soft-start SS capacitanceusingEquation14ormoresimplywithEquation15. t (cid:152)I t (cid:152)10(cid:29)$ C SS SS SS SS V 1.225V REF (14) CSS“‹nF”… 8.16(cid:152)tSS“‹ms”… (15) ChooseaC of10nFcorrespondingtoasoft-starttimeof1.2msforthisapplication. SS 8.2.2.10 FeedbackResistors(R andR ) FB1 FB2 Resistors R and R establish the output voltage setpoint. Based on a selected value for the lower feedback FB1 FB2 resistorR ,calculatetheupperfeedbackresistorR fromEquation16. FB2 FB1 V (cid:16)1.225V R OUT (cid:152)R FB1 1.225V FB2 (16) In general, a good starting point for R is in the range of 1 kΩ to 10 kΩ. Resistances of 5.11 kΩ and 1.65 kΩ FB2 areselectedforR andR (respectively)toachievea5-Voutputsetpointforthisdesignexample. FB1 FB2 8.2.2.11 RCSnubber(R andC ) S S A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Ultimately, excessive spikes beyond the rating of the LM5005 or the freewheeling diode can damage these devices. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are short. For the current levels typical of the LM5005 converter, a snubber resistance R between S 2 Ω and 10 Ω is adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a minimum value of C that provides adequate damping of the SW voltage waveform at full load S (seePCBLayoutforEMIReductionformoredetails). 20 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Typical Application (continued) 8.2.2.12 CompensationComponents(R ,C ,C ) C1 C1 C2 Thesecomponentsconfiguretheerroramplifiergaincharacteristicstoaccomplishastableoverallloopgain.One advantage of current-mode control is the ability to close the loop with only two feedback components, R and C1 C . The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator C1 gainoftheLM5005iscalculatedwithEquation17. GAIN G (cid:152)R 2(cid:152)R MOD-DC m(MOD) LOAD LOAD (17) The dominant low-frequency pole of the modulator is determined by the load resistance, R , and the output LOAD capacitance,C .CalculatethecornerfrequencyofthispolewithEquation18. OUT 1 f p(MOD) 2S(cid:152)R (cid:152)C LOAD OUT (18) ForR =5 ΩandC =177µF,thenf =180Hz LOAD OUT p(MOD) GAIN =2A/V ×5 Ω=10=20dB MOD-DC For this design example given R = 5 Ω and C = 177 µF, Figure 19 shows the experimentally measured LOAD OUT modulatorgainversusfrequencycharacteristic. REF LEVEL /DIV 0.000 dB 10.000 dB 0.0 deg 45.000 deg GAIN 0 PHASE 100 1k 10k START 50.000 Hz STOP 50 000.000 Hz Figure19. PWMModulatorGainandPhasePlot ComponentsR andC configuretheerroramplifierasaType-IIconfiguration,givingapoleattheoriginanda C1 C1 zero at f = 1 / (2π R C ). The error amplifier zero cancels the modulator pole leaving a single pole response Z C1 C1 at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a stable loopwith90° ofphasemargin. For the design example, select a target loop bandwidth (crossover frequency) of 20 kHz. Place the compensator zerofrequency,f ,anorderofmagnitudelessthanthetargetcrossoverfrequency.Thisconstrainstheproductof Z R and C for a desired compensation network zero frequency to be less than 2 kHz. Increasing R while C1 C1 C1 proportionally decreasing C increases the error amp gain. Conversely, decreasing R while proportionally C1 C1 increasing C , decreases the error amp gain. Select R of 49.9 kΩ and C of 10 nF. These values configure C1 C1 C1 the compensation network zero at 320 Hz. The compensator gain at frequencies greater than f is R / R , Z C1 FB1 whichisapproximately20dB. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Typical Application (continued) The compensator's bode plot is shown by Figure 20. The overall loop is predicted as the sum (in dB) of the modulatorgainandthecompensatorgainasshowninFigure21. REF LEVEL /DIV REF LEVEL /DIV 0.000 dB 10.000 dB 0.000 dB 10.000 dB 0.0 deg 45.000 deg 0.0 deg 45.000 deg PHASE GAIN GAIN PHASE 0 0 100 1k 10k 100 1k 10k START 50.000 Hz STOP 50 000.000 Hz START 50.000 Hz STOP 50 000.000 Hz Figure20.CompensatorGainandPhasePlot Figure21.OverallLoopGainandPhasePlot If a network analyzer is available, measure the modulator gain and configure the compensator gain for the desired loop transfer function. If a network analyzer is not available, design the error amplifier's compensation components using the guidelines provided. Perform step-load transient tests to verify acceptable performance. The step load goal is minimum overshoot with a damped response. Add a capacitor C to the compensation C2 network to decrease noise susceptibility of the error amplifier. The value of C must be sufficiently small, C2 because the addition of this capacitor adds a pole in the compensator transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C is C2 Equation19. f =f ×C /C (19) p2 Z C1 C2 An alternative method to decrease the error amplifier noise susceptibility is to connect a capacitor from COMP to AGND.Whenusingthismethod,thecapacitanceofC mustnotexceed100pF. C2 22 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 8.2.2.13 BillofMaterials Table1liststhebillofmaterialsforthedesignexample. Table1.LM5005BuckRegulatorBillofMaterials(1),V =5V,I =2.5A OUT OUT REFDES DESCRIPTION VENDOR PARTNUMBER QUANTITY C ,C CAPACITOR,CER,2.2µF,100V,X7R,1210 TDK C3225X7R2A225M 2 IN1 IN2 C CAPACITOR,SP,150µF,6.3V,12mΩ Panasonic EEFHE0J151R 1 OUT1 C CAPACITOR,CER,22µF,16V,X7R,1210 TDK C3225X7R1C226M 1 OUT2 C CAPACITOR,CER,330pF,100V,0603 Kemet C0603C331G1GAC 1 S C ,C CAPACITOR,CER,10nF,100V,0603 TDK C1608X7R2A103K 2 C1 SS C CAPACITOR,CER,22nF,100V,0603 TDK C1608X7R2A223K 1 BST C CAPACITOR,CER,0.47µF,16V,0604 TDK C1608X7R1C474M 1 VCC C CAPACITOR,CER,330pF,100V,0603 Kemet C0603C331G1GAC 1 RAMP DIODE,100V,6A,Schottky,DPAK CentralSemi CSHD6-100C D 1 F DIODE,100V,6A,Schottky(alternative) IR 6CWQ10FN L INDUCTOR,33µH,I 6.22A,DCR60mΩ Coiltronics/Eaton DR127-330-R 1 F SAT R RESISTOR,20.5kΩ,0603 VishayDale CRCW06032052F 1 T R RESISTOR,49.9kΩ,0603 VishayDale CRCW06034992F 1 C1 R RESISTOR,5.11kΩ,0603 VishayDale CRCW06035111F 1 FB1 R RESISTOR,1.65kΩ,0603 VishayDale CRCW06031651F 1 FB2 R RESISTOR,10Ω,1W,1206 VishayDale CRCW1206100J 1 S U WideVINRegulator,75V,2.5A TexasInstruments LM5005 1 1 (1) SeeThird-PartyProductsDisclaimer. 8.2.3 ApplicationCurves Converter efficiency and performance waveforms are shown from Figure 22 to Figure 32. Unless indicated otherwise,allwaveformsaretakenatV =48V. IN 100 90 80 (cid:8)) 70 VOUT 10 mV/DIV y ( nc 60 e ci Effi 50 VIN = 12 V VIN = 24 V 40 VIN = 36 V VIN = 48 V 30 VIN = 60 V VIN = 75 V 20 0 0.5 1 1.5 2 2.5 Output Current (A) 2 Ps/DIV D001 Figure22.TypicalEfficiencyvsInputVoltage Figure23.OutputVoltageRipple,2.5-ALoad andOutputCurrent,5-VOutput Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com V 10 V/DIV V 10 V/DIV SW SW 1 Ps/DIV 1 Ps/DIV Figure24.SWNodeVoltage,2.5-ALoad Figure25.SWNodeVoltage,0.1-ALoad VOUT 1 V/DIV VOUT 1 V/DIV V 1 V/DIV SD IOUT 1 A/DIV IOUT 1 A/DIV V 1 V/DIV SD 1 ms/DIV 1 ms/DIV Figure26.Start-UpUsingSDPin,2.5-AResistiveLoad Figure27.ShutdownUsingSDPin,2.5-AResistiveLoad VOUT 1 V/DIV VOUT 1 V/DIV V 10 V/DIV IN I 1 A/DIV OUT V 1 V/DIV SD 1 ms/DIV 1 ms/DIV Figure28.Start-UpUsingSDPin,Pre-biasedOutput Figure29.Start-UpbyApplyingV ,2.5-AResistiveLoad IN 24 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 VOUT 100 mV/DIV VOUT 100 mV/DIV I 1 A/DIV OUT I 1 A/DIV OUT 1 ms/DIV 1 ms/DIV Figure30.LoadTransientResponse,0.1-Ato2.5-ALoad Figure31.LoadTransientResponse,1.25-Ato2.5-ALoad V 10 V/DIV IN V 10 V/DIV SW V 20 mV/DIV OUT V 1 V/DIV SYNC I 1 A/DIV OUT 20 ms/DIV 1 Ps/DIV Figure32.LineTransient,12Vto60V,2.5-ALoad Figure33.SYNCINOperationat350kHz Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com 9 Power Supply Recommendations The LM5005 converter is designed to operate from a wide input voltage range from 7 V to 75 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the fully-loadedregulator.EstimatetheaverageinputcurrentwithEquation20. V (cid:152)I I OUT OUT IN V (cid:152)K IN where • ηistheefficiency (20) If the converter is connected to an input supply through long wires or PCB traces with large impedance, special care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may have an adverse affect on converter operation. The parasitic inductance in combination with the low ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps toholdtheinputvoltagesteadyduringlargeloadtransients. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The user's guide Simple Success with Conducted EMI for DC-DC Converters (SNVA489)provideshelpfulsuggestionswhendesigninganinputfilterforanyswitchingregulator. 10 Layout 10.1 Layout Guidelines PC board layout is an important and critical part of any DC-DC converter design. The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Poor layout disrupts the performance of a switching converter and surrounding circuitry by contributing to EMI, ground bounce, conduction loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter, possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade thepower-supplyperformance. The following guidelines serve to help users to design a PCB with the best power conversion performance, thermalperformance,andminimizedgenerationofunwantedEMI. 1. In a buck regulator there are two critical current conduction loops. The first loop starts from the input capacitors to the LM5005's VIN pins, to the SW pin, to the inductor and then out to the load. The second loop starts from the output capacitors' return terminals, to the LM5005's PGND pins, to the IS pins, to the freewheeling diode's anode, to the inductor and then out to the load. Minimizing the effective area of these twoloopsreducesthestrayinductanceandminimizesnoiseandpossibleerraticoperation. 2. Place the input capacitors close to the LM5005's VIN pins and exposed pad that is connected to PGND pins. Place the inductor as close as possible to the SW pins and output capacitors. As described further in PCB Layout for EMI Reduction, this placement serves to minimize the area of switching current loops and reduce the resistive loss of the high current path. Ideally, use a ground plane on the top layer that connects the PGND pins, the exposed pad of the device, and the return terminals of the input and output capacitors. For more details, see the board layout detailed in LM5005 EVM user's guide AN-1748 LM5005 Evaluation Board (SNVA298). 3. Minimize the copper area of the switch node. Route the two SW pins on a single top-layer plane to the inductor terminal using a wide trace to minimize conduction loss. The inductor can be placed on the bottom sideofthePCBrelativetotheLM5005,buttakecaretoavoidanycouplingoftheinductor'smagneticfieldto sensitivefeedbackorcompensationtraces. 4. Use a solid ground plane on layer two of the PCB, particularly underneath the LM5005 and power stage 26 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Layout Guidelines (continued) components.Thisplanefunctionsasanoiseshieldandalsoasaheatdissipationpath. 5. Make input and output power bus connections as wide and short as possible to reduce voltage drops on the input and output of the converter and to improve efficiency. Use copper planes on top to connect the multiple VINpinsandPGNDpinstogether. 6. Provide enough PCB area for proper heat-sinking. As stated in Thermal Design, use enough copper area to ensure a low R commensurate with the maximum load current and ambient temperature. Make the top θJA and bottom PCB layers with two ounce copper thickness and no less than one ounce. Use an array of heat- sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiplecopperlayersasrecommended,connectthesethermalviastotheinnerlayerheat-spreadingground planes. 7. Route the sense trace from the VOUT point of regulation to the feedback resistors away from the SW pins and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important when high resistances are used to set the output voltage. Routing the feedback trace on a different layer than the inductor and SW node trace is recommended such that a ground plane exists between the sense traceandinductororSWnodepolygontoprovidefurthercancellationofEMIonthefeedbacktrace. 8. If voltage accuracy at the load is important, ensure that the feedback voltage sense is made directly at the loadterminals.DoingsocorrectsforvoltagedropsinthePCBplanesandtracesandprovidesoptimaloutput voltage set-point accuracy and load regulation. Place the feedback resistor divider closer to the FB pin, rather than close to the load, because the FB node is the input to the error amplifier and is thus noise sensitive. 9. COMP is a also noise-sensitive node. Place the compensation components as close as possible to the FB andCOMPpins. 10. Place the components for R , C , C and C close to their respective pins. Connect all of the signal T SS RAMP VCC components' ground return connections directly to the LM5005's AGND pin. Connect the AGND and PGND pins together at the LM5005's exposed pad using the topside copper area covering the entire underside of thedevice.ConnectseveralviaswithinthisundersidecopperareatothePCB'sinternalgroundplane. 11. SeeRelatedDocumentationforadditionalimportantguidelines. 10.1.1 PCBLayoutforEMIReduction Radiated EMI generated by high slew-rate current edges relates to pulsating currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The keytoreducingradiatedEMIistoidentifythepulsingcurrentpathandminimizetheareaofthatpath. Theimportanthigh-frequencyswitchingpowerloop(or hot loop)oftheLM5005powerstageisdenotedinbluein Figure 34. The topological architecture of a buck converter means that particularly high di/dt current exists in this loop as current commutates between the externally-connected Schottky diode and the integrated high-side MOSFET during switching transitions. As such, it becomes mandatory to minimize this effective loop area, with an eye to reducing the layout-induced parasitic or stray inductances that cause excessive SW voltage overshoot andringing,noiseandgroundbounce. In general, MOSFET switching behavior and the consequences for waveform ringing, power dissipation, device stress and EMI are correlated with the parasitic inductances of the power loop. It follows that the cumulative benefits of reducing the switching loop area are increased reliability and robustness owing to lower power MOSFET voltage and current stress, increased margin for input voltage transients, and easier EMI filtering (particularlyinthemorechallenginghigh-frequencybandabove30MHz). Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Layout Guidelines (continued) C BST SW BST VIN VIN VCC High frequency power CIN CVCC Q1 loop L F V High-side SW OUT MOSFET gate driver D F C OUT IS R CS LM5005 PGND GND Figure34. LM5005PowerStageCircuitSwitchingLoops High-frequency ceramic bypass capacitors at the input side provide the primary path for the high di/dt components of the pulsing current. Position low-ESL ceramic bypass capacitors with low-inductance, short trace routes to the VIN and PGND pins. Keep the SW trace connecting to the inductor as short as possible, and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper polygon pours (shapes) for current conduction paths to minimize parasitic resistance. Place the output capacitors close to the VOUT side of the inductor and route the return connection using GND plane copper back to the PGND pins and theexposedpadoftheLM5005. 10.1.2 ThermalDesign As with any power conversion device, the LM5005 dissipates internal power while operating. The effect of this power dissipation is to raise the internal junction temperature of the LM5005 above ambient. The junction temperature (T ) is a function of the ambient temperature (T ), the power dissipation (P ) and the effective J A D thermal resistance of the device and PCB combination (R ). The maximum operating junction temperature for θJA the LM5005 is 125°C, thus establishing a limit on the maximum device power dissipation and therefore the load current at high ambient temperatures. Equation 21 and Equation 22 show the relationships between these parameters. §1(cid:16)K• P P (cid:152) (cid:16)V (cid:152)I (cid:152)(cid:11)1(cid:16)D(cid:12)(cid:16)I 2(cid:152)R (cid:152)1.5 ¤ ‚ D OUT ' K „ F OUT OUT DCR (21) T P (cid:152)T (cid:14)T J D JA A (22) An approximation for the inductor power loss in Equation 21 includes a factor of 1.5 for the core losses. Also, if a snubber is used, estimate its power loss by observation of the resistor voltage drop at both turnon and turnoff switchingtransitions. High ambient temperatures and large values of R reduce the maximum available output current. If the junction θJA temperature exceeds 165°C, the LM5005 cycles in and out of thermal shutdown. Thermal shutdown may be a signofinadequateheat-sinkingorexcessivepowerdissipation.ImprovePCBheat-sinkingbyusingmorethermal vias,alargerboard,ormoreheat-spreadinglayerswithinthatboard. 28 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 Layout Guidelines (continued) As stated in Semiconductor and IC Package Thermal Metrics (SPRA953), the values given in Thermal Information are not always valid for design purposes to estimate the thermal performance of the application. The values reported in this table are measured under a specific set of conditions that are seldom obtained in an actual application. The effective R is a critical parameter and depends on many factors (such as power θJA dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias under the package, air flow, and adjacent component placement). The LM5005's exposed pad has a direct thermal connection to PGND. This pad must be soldered directly to the PCB copper ground plane to provide an effective heat-sink and proper electrical connection. Use the documents listed in Documentation Support as a guide for optimized thermalPCBdesignandestimatingR foragivenapplicationenvironment. θJA 10.1.3 GroundPlaneDesign As mentioned previously, using one of the inner PCB layers as a solid ground plane is recommended. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry.ConnectthePGNDpinstothesystemgroundplaneusinganarrayofviasundertheLM5005'sexposed pad. Also connect the PGND pins directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and SW can be restricted to one side of the ground plane. The other side of the ground planecontainsmuchlessnoiseandisidealforsensitiveanalogtraceroutes. 10.2 Layout Example Place boot cap close Keep diode close to BST and SW pins to SW and IS pins SD Connect ceramic input cap(s) close to VIN pin VIN SYNC SW GND IS VOUT Keep COMP network close to COMP and FB pins GND Thermal vias under Place FB resistors close to FB pin LM5005 pad Figure35. ComponentSide Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com Layout Example (continued) Figure36. SolderSide(ViewedFromTop) SD Texas Instruments V I N SYNC G N T D U O V D N G Figure37. Silkscreen 30 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

LM5005 www.ti.com SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 11 Device and Documentation Support 11.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Device Support 11.2.1 DevelopmentSupport Fordevelopmentsupportseethefollowing: • ForTI'sreferencedesignlibrary,visitTIDesigns • ForTI'sWEBENCHDesignEnvironments,visitWEBENCH®DesignCenter 11.3 Documentation Support 11.3.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • AN-1748LM5005EvaluationBoard(SNVA298) • BuckRegulatorTopologiesforWideInput/OutputVoltageDifferentials (SNVA594) • WhitePapers: – Valuing Wide V , Low EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications IN (SLYY104) – Wide V Power Management ICs Simplify Design, Reduce BOM Cost, and Enhance Reliability IN (SLYY037) 11.3.1.1 PCBLayoutResources • AN-1149LayoutGuidelinesforSwitchingPowerSupplies (SNVA021) • AN-1229SimpleSwitcherPCBLayoutGuidelines(SNVA054) • ConstructingYourPowerSupply– LayoutConsiderations (SLUP230) • LowRadiatedEMILayoutMadeSIMPLEwithLM4360xandLM4600x (SNVA721) • AN-2162SimpleSuccessWithConductedEMIFromDC-DCConverters (SNVA489) • ReduceBuck-ConverterEMIandVoltageStressbyMinimizingInductiveParasitics (SLYT682) 11.3.1.2 ThermalDesignResources • AN-2020ThermalDesignByInsight,NotHindsight (SNVA419) • AN-1520AGuidetoBoardLayoutforBestThermalResistanceforExposedPadPackages (SNVA183) • SemiconductorandICPackageThermalMetrics(SPRA953) • ThermalDesignMadeSimplewithLM43603andLM43602 (SNVA719) • PowerPAD™ThermallyEnhancedPackage(SLMA002) • PowerPADMadeEasy(SLMA004) • UsingNewThermalMetrics(SBVA025) 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM5005

LM5005 SNVS397E–SEPTEMBER2005–REVISEDNOVEMBER2016 www.ti.com 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.6 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.7 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.8 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 32 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM5005

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LM5005MH NRND HTSSOP PWP 20 73 TBD Call TI Call TI -40 to 125 LM5005 MH LM5005MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LM5005 & no Sb/Br) MH LM5005MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LM5005 & no Sb/Br) MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LM5005MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LM5005MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 PackMaterials-Page2

MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.com

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