Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 LM3686 Step-Down DC-DC Converter With Integrated Post Linear Regulators System And Low-Noise Linear Regulator 1 Features 2 Applications • DC-DCRegulator • MobileTVs,Hand-HeldRadios 1 – V =1.2Vto2.5V • PersonalDigitalAssistants,Palm-TopPCs OUT_DCDC – 600-mAMaximumI • PortableInstrumentsandPersonalClients LOAD – 3-MHzTypicalPWMFixedSwitching • Battery-PoweredDevices Frequency 3 Description – AutomaticPFM/PWMModeSwitching The LM3686 is a step-down DC-DC converter with a – InternalSynchronousRectification very low-dropout linear regulator and a low-noise – InternalSoftStart linear regulator optimized for powering ultra-low • Dual-RailLinearRegulator:LILO voltage circuits. It provides three outputs with combined load current up to 900 mA over an input – LoadTransients< 50-mVPeakTypical voltagerangefrom2.7Vto5.5V. – LineTransients <1-mVPeakTypical The device offers superior features and performance – V =0.7Vto2V OUT_LILO for many applications. Automatic intelligent switching – 70-µATypicalI and300-mAMaximumI Q LOAD between PWM low-noise and PFM low-current mode • LinearRegulator:LDO offers improved system control. During full-power operation, a fixed-frequency 3 MHz (typical), PWM – LoadTransients< 80-mVPeakTypical mode drives loads from approximately 70 mA to 600 – LineTransients <1-mVPeakTypical mA maximum. Hysteretic PFM mode extends the – V =1.5Vto3.3V battery life through reduction of the quiescent current OUT_LDO – 50-µATypicalI and350-mAMaximumI to 28 μA (typical) at light load and system standby. Q LOAD Internal synchronous rectification provides high • CombinedGlobalFeatures efficiency. – V ≥ Maximum(V +1.5V,2.7V) BATT OUT_LILO – OperatesFromaSingleLi-IonCellor3-Cell DeviceInformation(1) NiMH/NiCdBatteries PARTNUMBER PACKAGE BODYSIZE(NOM) – 100-µAI and900-mAMaximumI LM3686 DSBGA(12) 2.435mm×1.687mm Q LOAD (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalApplication VBATT 2.7 V to 5.5 V 4.7 PF, 0603 EN_DCDC LM3 M3H6z86 SW PGND 1 PH 1.8 V DC-DC FB_DCDC VIN_LILO 10 PF 0603 PGND EN_LILO PGND Dual Rail LILO 0.7 V to 2 V LILO 350 mA EN_LDO 2.2 PF, 350 mA 0402 QGND VIN_LDO Linear Regulator LDO 1.2 V to 3.3 V 300 mA 1 PF, 0402 1 PF, 300 mA 0402 QGND QGND QGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................12 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................16 3 Description............................................................. 1 9 ApplicationandImplementation........................ 17 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation............................................17 9.2 TypicalApplication .................................................17 5 Description(Continued)........................................ 3 10 PowerSupplyRecommendations..................... 22 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 22 7 Specifications......................................................... 4 11.1 LayoutGuidelines................................................22 7.1 AbsoluteMaximumRatings......................................4 11.2 LayoutExample....................................................23 7.2 ESDRatings..............................................................4 11.3 DSBGAPackageAssemblyandUse...................23 7.3 RecommendedOperatingConditions.......................4 12 DeviceandDocumentationSupport................. 24 7.4 ThermalInformation..................................................4 7.5 ElectricalCharacteristics:LinearRegulator-LILO...5 12.1 DeviceSupport......................................................24 7.6 ElectricalCharacteristics:LinearRegulator-LDO...6 12.2 RelatedDocumentation .......................................24 7.7 ElectricalCharacteristics:DC-DCConverter............7 12.3 ReceivingNotificationofDocumentationUpdates24 7.8 ElectricalCharacteristics:GlobalParameters(DCDC, 12.4 CommunityResources..........................................24 LILO,andLDO)..........................................................8 12.5 Trademarks...........................................................24 7.9 TypicalCharacteristics..............................................9 12.6 ElectrostaticDischargeCaution............................24 8 DetailedDescription............................................ 11 12.7 Glossary................................................................24 8.1 Overview.................................................................11 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................12 Information........................................................... 24 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(May2013)toRevisionF Page • Deleted"oneintegrated" ........................................................................................................................................................ 1 • Deleted"fromasingleLi-Ioncellor3-cellNiMH/NiCdbatteries."......................................................................................... 1 • AddedDeviceInformationandESDRatingstables,PinConfigurationandFunctions,FeatureDescription,Device FunctionalModes,ApplicationandImplementation,PowerSupplyRecommendations,Layout,Deviceand DocumentationSupport,andMechanical,Packaging,andOrderableInformationsections................................................. 1 • CombinesomebulletitemsanddeleteparentheticalsfromFeaturestogetmorespace .................................................... 1 • Deletedout-of-dateDeviceComparisontable ...................................................................................................................... 3 • DeletedleadtemperaturefromAbsMaxperTIdatasheetstandard ................................................................................... 4 • ChangedR from"120°C/W"to"80.9°C/W";addedadditionalthermalvalues................................................................... 4 θJA • Changed"drainsconductor"to"drainsinductor"onFigure13............................................................................................ 14 ChangesfromRevisionD(April2013)toRevisionE Page • ChangedlayoutofNationalSemiconductordatasheettoTIformat.................................................................................... 22 2 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 5 Description (Continued) Three enable (EN_x) pins allow the separate operation of either the DC-DC, post-regulation linear regulator, or the linear regulator alone. If the DC-DC is not enabled during start-up of the post-regulation linear regulator, a parallel small-pass transistor supplies the linear regulator from V with maximal 50 mA. In the combined BATT operation where both enables are raised together, the small-pass transistor is deactivated and the big pass transistor provides 350 mA output current. In shutdown mode (EN_x pins pulled low), the device turns off and reducesbatteryconsumptionto2.5μA(typical). The LM3686 is available in a 12-pin DSBGA package. A high-switching frequency of 3 MHz (typical) allows the use of a few tiny surface-mount components. Only six external surface-mount components, an inductor and five ceramiccapacitors,arerequiredtoestablisha15.66mm2totalsolutionsize. 6 Pin Configuration and Functions YZRPackage YZRPackage 12-PinDSBGA 12-PinDSBGA TopView BottomView A3 B3 C3 D3 D3 C3 B3 A3 A2 B2 C2 D2 D2 C2 B2 A2 A1 B1 C1 D1 D1 C1 B1 A1 PinFunctions PIN TYPE DESCRIPTION NO. NAME A1 PGND Ground Powergroundpin A2 SW Analog SwitchingnodeconnectiontotheinternalPFETswitchandNFETsynchronousrectifier. A3 FB_DCDC Input FeedbackanaloginputfortheDC-DCconverter.Connecttotheoutputfiltercapacitor. B1 V Power Powersupplyinputforswitcher.Connecttotheinputfiltercapacitor. BATT Enableinputforthelinearregulator.Thelinearregulatorisinshutdownmodeifvoltageat B2 EN_LILO Input thispinis <0.4Vandenabledif>1.1V.Donotleavethispinfloating. EnableinputfortheDC-DCconverter.TheDC-DCconverterisinshutdownmodeifvoltage B3 EN_DCDC Input atthispinis<0.4Vandenabledif>1.1V.Donotleavethispinfloating. C1 V Input InputpowertoLDO—musttietoV atalltimes. IN_LDO BATT Enableinputforthelinearregulator.Thelinearregulatorisinshutdownmodeifvoltageat C2 EN_LDO Input thispinis <0.4Vandenabledif>1.1V.Donotleavethispinfloating. C3 QGND Ground QuietGNDpinforLDOandreferencecircuit D1 V Output Voltageoutputofthelinearregulator OUT_LDO D2 V Output Voltageoutputofthelowinputlinearregulator OUT_LILO D3 V Input InputpowertoLILO(V )connectstooutputofDCDCorstandalone. IN_LILO IN_LILO Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2)(3)(4) MIN MAX UNIT V pintoGNDandQGND –0.2 6 V BATT (GND–0.2V)to(V +0.2V)with6V EN_xpins,FB_DC-DCpin,SWpin BATT maximum Continuouspowerdissipation(5) Internallylimited Junctiontemperature,T 150 °C J-MAX Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttothepotentialattheGNDpin. (3) IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) Fordetailedsolderingspecificationsandinformation,seeAN-1112DSBGAWaferLevelChipScalePackage. (5) Internalthermalshutdowncircuitryprotectsthedevicefrompermanentdamage.ThermalshutdownengagesatT =150°C(typical)and J disengagesatT =130°C(typical). J 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Inputvoltage,V (DC-DCandLDO) 2.7 5.5 V BATT Junctiontemperature,T –40 125 °C J Ambienttemperature,T (1) –40 85 °C A (1) Inapplicationswherehighpowerdissipationand/orpoorpackagethermalresistanceispresent,themaximumambienttemperaturemay havetobederated.Maximumambienttemperature(T )isdependentonthemaximumoperatingjunctiontemperature(T = A-MAX J-MAX-OP 125°C),themaximumpowerdissipationofthedeviceintheapplication(P ),andthejunction-toambientthermalresistanceofthe D-MAX part/packageintheapplication(R ),asgivenbythefollowingequation:T =T –(R × ). θJA A-MAX J-MAX-OP θJA PD-MAX 7.4 Thermal Information LM3686 THERMALMETRIC(1) YZR(DSBGA) UNIT 12PINS R Junction-to-ambientthermalresistance 80.9 °C/W θJA R Junction-to-case(top)thermalresistance 0.4 °C/W θJC(top) R Junction-to-boardthermalresistance 16.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 16.9 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seeSemiconductorandICPackageThermalMetrics. 4 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 7.5 Electrical Characteristics: Linear Regulator - LILO Unlessotherwisenoted,limitsapplyforT =25°C,specificationsapplytotheclosed-looptypicalapplicationcircuits(linear A regulator)withV =V =3.6V(1),V =V ,V (All)=V ,C =4.7μF,C =2.2μF, IN_LDO BATT IN_LILO OUT_DCDC(NOM) EN BATT IN_DC OUT_LILO C =1μF,C =1μF,C =C =10μF.(2)(3)(4)(5) IN_LDO OUT_LDO OUT_DC IN_LILO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT EN_DC-DC=EN_LILO=ON–LARGENMOS I =1mAto350mA, OUT_LILO V =V 1.2 IN_LILO OUT_DCDC ΔVOUT_LILO, Outputvoltageaccuracy, VBATT=3.6V V VOUT_LILO VOUT-LILO IOUT_LILO=1mAto350mA, V =V 1.176 1.224 IN_LILO OUT_DCDC V =3.6V,–40°C≤T =T ≤85°C BATT A J I =1mAto350mA, OUT_LILO V =V 4 IN_LILO OUT_DCDC ΔVOUT_LILO/ Loadregulation(6) VBATT=3.6V μV/mA ΔmA I =1mAto350mA, OUT_LILO V =V 12 IN_LILO OUT_DCDC V =3.6V,–40°C≤T =T ≤85°C BATT A J V =V +1.5V(V BATT OUT_LILO IN_LILO disconnectedfromV ) 50 OUT_DCDC I =350mA V Dropoutvoltage(7) OUT mV DROP V =V +1.5V(V BATT OUT_LILO IN_LILO disconnectedfromV ) 80 OUT_DCDC I =350mA,–40°C≤T =T ≤85°C OUT A J V =V =3.6V 70 BATT IN_LILO IQ_VIN_LILO Quiescentcurrent VBATT=VIN_LILO=3.6V 90 µA –40°C≤T =T ≤85°C A J V =GND(V =0) I Short-circuitcurrentlimit OUT OUT_LILO 400 mA SC_LILO –40°C≤T =T ≤85°C A J EN_DC-DC=OFF,EN_LILO=ON–SMALLNMOS ΔV , Outputvoltageaccuracy I =1mAto50mA OUT_LILO OUT 1.176 1.224 V V V –40°C≤T =T ≤85°C OUT_LILO OUT_LILO A J V =(V +0.3V)to5.5V 0.4 IN_LILO OUT_LILO ΔΔVVOBAUTTT_LILO, Lineregulation(smallNMOS)(8) VIN_LILO=(VOUT_LILO+0.3V)to5.5V 1.5 mV/V –40°C≤T =T ≤85°C A J V =GND,–40°C≤T =T ≤ I Short-circuitcurrent OUT_LILO A J 70 SC_LILO 85°C T Start-uptime ENto0.95V 70 µs STARTUP OUT (1) V mustbeONatalltimeforbiasinginternalreferencecircuits. IN_LDO (2) AllvoltagesarewithrespecttothepotentialattheGNDpin. (3) Minimum(MIN)andmaximum(MAX)limitsarespecifiedbydesign,test,orstatisticalanalysis.Typical(TYP)numbersrepresentthe mostlikelynorm.Unlessotherwisespecified,conditionsfortypicalspecificationsare:V =3.6VandT =25°C. BATT A (4) TheparametersintheelectricalcharacteristictablearetestedatV =3.6Vunlessotherwisespecified.Forperformanceoverthe BATT inputvoltagerangerefertoTypicalCharacteristics. (5) Theinputvoltagerangesrecommendedforidealapplicationperformanceforthespecifiedoutputvoltagesare: V =2.7Vto5.5Vfor1V≤V <1.8V BATT OUT_DCDC V =(V +1V)to5.5Vfor1.8V≤V <3.6V. BATT OUT_DCDC OUT_DCDC (6) Tocalculatetheoutputvoltagefromtheloadregulationspecified,usethefollowingequation: ΔV =loadregulation(%/mA)×nominalV (V)×ΔI (mA). OUT OUT OUT (7) Dropoutvoltageisdefinedastheinputtooutputvoltagedifferentialatwhichtheoutputvoltagefallsto100mVbelowthenominaloutput voltage. (8) Tocalculatetheoutputvoltagefromthelineregulationspecified,usethefollowingequation: ΔV =lineregulation(%/V)×nominalV (V)×ΔV (V). OUT OUT IN Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com Electrical Characteristics: Linear Regulator - LILO (continued) Unlessotherwisenoted,limitsapplyforT =25°C,specificationsapplytotheclosed-looptypicalapplicationcircuits(linear A regulator)withV =V =3.6V(1),V =V ,V (All)=V ,C =4.7μF,C =2.2μF, IN_LDO BATT IN_LILO OUT_DCDC(NOM) EN BATT IN_DC OUT_LILO C =1μF,C =1μF,C =C =10μF.(2)(3)(4)(5) IN_LDO OUT_LDO OUT_DC IN_LILO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SYSTEMCHARACTERISTICS(9) SignaltoV =3.6V,V =1.8V, BATT IN_LILO 68 I =200mA,ƒ=100Hz OUT PSRR Powersupplyrejectionratio dB SignaltoV =1.8V, IN_LILO 60 I =200mA,ƒ=100kHz OUT BW=10Hzto100kHz,V =1.8V, e Outputnoisevoltage IN_LILO 166 µV N_LILO I =200mA,V =3.6V RMS OUT IN_LDO ΔV Dynamicloadtransient Pulsedload1mAto350mA ±30(10) mV OUT_LILO response di/dt=350mA/1µs V =3.1Vto3.7V ΔV Dynamicloadtransient VBATT =V ±15(10) mV IN_LILO responseonV IN_LILO OUT_DCDC BATT tr,tf=10µs,I =200mA OUT (9) Specifiedbydesign.Notproductiontested. (10) Forlineandloadtransientspecifications,the+symbolrepresentsanovershootintheoutputvoltageandthe–symbolrepresentsan undershootintheoutputvoltage.Thefirstvaluesignifiesovershootorundershootattherisingedgeandthesecondvaluesignifiesthe overshootorundershootatthefallingedge. 7.6 Electrical Characteristics: Linear Regulator - LDO Unlessotherwisenoted,limitsapplyforT =25°C.(1)(2)(3)(4) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V LDOinputvoltagerange 2.7 5.5 V IN_LDO V =3.6V,I =1mAand300mA 2.8 IN OUT_LDO V =3.6V,I =1mAand300mA IN OUT_LDO 2.744 2.856 ΔVOUT_LDO Outputvoltageaccuracy,VOUT- –40°C≤TA=TJ≤85°C V /VOUT_LDO LDO VIN=3.6V,IOUT_LDO=1mAand300mA 3 3.06 V =3.6V,I =1mAand300mA IN OUT_LDO 2.94 –40°C≤T =T ≤85°C A J ΔVOUT_LDO Loadregulation(5) I =1mAand300mA 8 μV/mA /ΔmA OUT_LDO ΔVOUT_LDO Lineregulation(6) V =(V +0.3V)to5.5V 0.2 mV/V /ΔV IN_LDO OUT_LDO(NOM) BATT I =300mA 120 V Dropoutvoltage(7) OUT mV DROP I =300mA,–40°C≤T =T ≤85°C 200 OUT A J V =0.95V,I =0mA 50 en OUT IQ Quiescentcurrent Ven=0.95V,IOUT=0mA 80 µA –40°C≤T =T ≤85°C A J I Short-circuitcurrentlimit V =GND,–40°C≤T =T ≤85°C 350 mA SC_LDO OUT A J (1) AllvoltagesarewithrespecttothepotentialattheGNDpin. (2) Minimum(MIN)andmaximum(MAX)limitsarespecifiedbydesign,test,orstatisticalanalysis.Typical(TYP)numbersrepresentthe mostlikelynorm.Unlessotherwisespecified,conditionsfortypicalspecificationsare:V =3.6VandT =25°C. BATT A (3) TheparametersintheElectricalCharacteristicstablesaretestedatV =3.6Vunlessotherwisespecified.Forperformanceoverthe BATT inputvoltagerangerefertoTypicalCharacteristics. (4) Theinputvoltagerangesrecommendedforidealapplicationperformanceforthespecifiedoutputvoltagesare V =2.7Vto5.5Vfor1V≤V <1.8V BATT OUT_DCDC V =(V +1V)to5.5Vfor1.8V≤V <3.6V BATT OUT_DCDC OUT_DCDC (5) Tocalculatetheoutputvoltagefromtheloadregulationspecified,usethefollowingequation: ΔV =loadregulation(%/mA)×nominalV (V)×ΔI (mA) OUT OUT OUT (6) Tocalculatetheoutputvoltagefromthelineregulationspecified,usethefollowingequation: ΔV =lineregulation(%/V)×nominalV (V)×ΔV (V) OUT OUT IN (7) Dropoutvoltageisdefinedastheinputtooutputvoltagedifferentialatwhichtheoutputvoltagefallsto100mVbelowthenominaloutput voltage. 6 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 Electrical Characteristics: Linear Regulator - LDO (continued) Unlessotherwisenoted,limitsapplyforT =25°C.(1)(2)(3)(4) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SYSTEMCHARACTERISTICS(8) EN_DC=EN_LILO=GND 85 I =200mA,ƒ=1kHz OUT PSRR Powersupplyrejectionratio dB SignaltoV =3.6V, IN_LDO 70 I =200mA,ƒ=10kHz OUT BW=10Hzto100kHz,V =3.6V, e Outputnoisevoltage IN_LDO 6.7 µV N_LDO I =200mA RMS OUT ΔV Dynamiclinetransientresponse VIN_LDO=3.8Vto4.4V ±2(9) mV IN_LDO tr,tf=30µs,I =1mA OUT ΔV Dynamicloadtransient Pulsedload1mAand300mA ±30(9) mV IN_LILO responseonV tr,tf=10µs BATT (8) Specifiedbydesign.Notproductiontested. (9) Forlineandloadtransientspecifications,the+symbolrepresentsanovershootintheoutputvoltageandthe–symbolrepresentsan undershootintheoutputvoltage.Thefirstvaluesignifiesovershootorundershootattherisingedgeandthesecondvaluesignifiesthe overshootorundershootatthefallingedge. 7.7 Electrical Characteristics: DC-DC Converter Unlessotherwisenoted,limitsapplyforT =25°C.(1)(2)(3)(4) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Feedbackvoltage PWMmode(5) 1.8 VFB_DCDC accuracy PWMmode(5),–40°C≤T =T ≤85°C 1.746 1.836 V A J Internalreference V 0.5 V REF voltage Pin-pinresistancefor V =3.6V R BATT 350 450 mΩ DSON(P) PFET I =100mA SW Pin-pinresistancefor V =3.6V R BATT 150 250 mΩ DSON(N) NFET I =100mA SW Quiescentcurrentfor Noload,deviceisnotswitching,FB=HIGH 28 IQ_AUTO automode Noload,deviceisnotswitching,FB=HIGH µA 40 –40°C≤T =T ≤85°C A J Switchpeakcurrent Openloop 1.22 ILIM limit A Openloop,–40°C≤T =T ≤85°C 1.035 1.375 A J Internaloscillator PWMmode 3 ƒOSC frequency MHz PWMmode,–40°C≤T =T ≤85°C 2.4 3.4 A J (1) AllvoltagesarewithrespecttothepotentialattheGNDpin. (2) Minimum(MIN)andmaximum(MAX)limitsarespecifiedbydesign,test,orstatisticalanalysis.Typical(TYP)numbersrepresentthe mostlikelynorm.Unlessotherwisespecified,conditionsfortypicalspecificationsare:V =3.6VandT =25°C. BATT A (3) TheparametersintheelectricalcharacteristictablearetestedatV =3.6Vunlessotherwisespecified.Forperformanceoverthe BATT inputvoltagerangerefertoTypicalCharacteristics. (4) Theinputvoltagerangesrecommendedforidealapplicationperformanceforthespecifiedoutputvoltagesare: V =2.7Vto5.5Vfor1V≤V <1.8V BATT OUT_DCDC V =(V +1V)to5.5Vfor1.8V≤V <3.6V BATT OUT_DCDC OUT_DCDC (5) ElectricalCharacteristicstablesreflectsopenloopdata(FB=0VandcurrentdrawnfromSWpinrampedupuntilcyclebycyclecurrent limitisactivated).Closedloopcurrentlimitisthepeakinductorcurrentmeasuredintheapplicationcircuitbyincreasingoutputcurrent untiloutputvoltagedropsby10%. Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 7.8 Electrical Characteristics: Global Parameters (DCDC, LILO, and LDO) Unlessotherwisenoted,limitsapplyforT =25°C.(1)(2)(3)(4) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Fullpowermode I =I =I =0mA,DC-DC OUT_DCDC OUT_LILO OUT_LDO isnotswitching(FB_DCDCforcedhigherthan 100 V ) OUT_DCDC V =1.1V, en Quiescentcurrentinto IQ_VBATT V Fullpowermode µA BATT I =I =I =0mA,DC-DC OUT_DCDC OUT_LILO OUT_LDO isnotswitching(FB_DCDCforcedhigherthan 130 V ) OUT_DCDC V =1.1V, en –40°C≤T =T ≤85°C A J Shutdowncurrentinto V =V =V =0V 2.5 EN_DCDC EN_LILO EN_LDO IQ_GLOBAL VBATT VEN_DCDC=VEN_LILO=VEN_LDO=0 4 µA –40°C≤T =T ≤85°C A J ENABLEPINS(EN_DCDC,EN_LILO,EN_LDO) I Enablepininput AllEN=0V .01 µA EN current AllEN=0V,–40°C≤T =T ≤85°C 1 A J V Logichighinput –40°C≤T =T ≤85°C 1.1 V IH A J V Logiclowinput –40°C≤T =T ≤85°C 0.4 V IL A J (1) AllvoltagesarewithrespecttothepotentialattheGNDpin. (2) Mininum(MIN)andmaximum(MAX)limitsarespecifiedbydesign,test,orstatisticalanalysis.Typical(TYP)numbersrepresentthe mostlikelynorm.Unlessotherwisespecified,conditionsfortypicalspecificationsare:V =3.6VandT =25°C. BATT A (3) TheparametersintheElectricalCharacteristicstablesaretestedatV =3.6Vunlessotherwisespecified.Forperformanceoverthe BATT inputvoltagerangerefertoTypicalCharacteristics. (4) Theinputvoltagerangesrecommendedforidealapplicationperformanceforthespecifiedoutputvoltagesare: V =2.7Vto5.5Vfor1V≤V <1.8V BATT OUT_DCDC V =(V +1V)to5.5Vfor1.8V≤V <3.6V BATT OUT_DCDC OUT_DCDC 8 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 7.9 Typical Characteristics Unlessotherwisespecified,typicalapplication(postregulation),V =3.6V,T =25°C,enablepinstiedtoV ,V BATT A BATT OUT_DCDC =1.8V,V =1.2V,V =2.8V. OUT_LILO OUT_LDO 1.830 1.203 VIN = 3.6V 1.202 1.825 1.201 V) V) UT VOLTAGE (11..882105 VIN = 2.9V UT VOLTAGE ( 1111....211109990987 VIN = 2.9 V VIN = 4.5 V UTP1.8.10 UTP 1.196 O VIN = 4.5 V O 1.195 VIN = 3.6 V 1.8.05 1.194 1.8.00 1.193 0 100 200 300 400 500 600 0 50 100 150 200 250 300 OUTPUT CURRENT DC-DC (mA) OUTPUT CURRENT (mA) Figure1.V vsI Figure2.V vsI OUT_DCDC OUT_DCDC OUT_LILO OUT_LILO 0 -10 -20 B) -30 d R ( -40 R S P -50 -60 ILILO= 200 mA -70 -80 100 1k 10k 100k 1000k 10000k FREQUENCY(Hz) LILO–V =3.6V IN_LILO Figure3.EfficiencyDC-DCvsOutputCurrentLILOandLDO Figure4.PSRRvsFrequency Disabled 0 -20 -40 B) d R ( -60 R S P -80 ILDO = 200 mA -100 -120 100 1k 10k 100k 1000k 10000k FREQUENCY (Hz) LDO–VIN_LDO=3.6V LDO–VIN_LDO=3.6V Figure5.PSRRvsFrequency Figure6.NoisevsFrequency Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) Unlessotherwisespecified,typicalapplication(postregulation),V =3.6V,T =25°C,enablepinstiedtoV ,V BATT A BATT OUT_DCDC =1.8V,V =1.2V,V =2.8V. OUT_LILO OUT_LDO OpenLoop Figure7.SwitchingFrequencyvsTemperature Figure8.CurrentLimitvsTemperature AllThreeEnablesTied Together Figure9.R vsTemperature DSON Figure10.Start-up 10 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 8 Detailed Description 8.1 Overview The LM3686 incorporates a high efficiency synchronous switching step-down DC-DC converter, a very low dropoutlinearregulator(LILO),andultra-low-noiselinearregulator. The DC-DC converter delivers a constant voltage from a single Li- Ion battery and input voltage rails from 2.7 V to 5.5 V to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, it has the ability to deliver up to 600-mA load current (when not powering the LILO) depending on theinputvoltage,outputvoltage,ambienttemperature,andtheinductorchosen. The linear regulator delivers a constant voltage biased from V power input typically the output voltage of IN_LILO theDC-DCconverterisused(postregulation)withamaximumloadcurrentof350mA. The other linear regulator delivers a constant voltage biased from V power input with a maximum load IN_LDO currentof300mA. Three enable pins allow the independent control of the three outputs. Shutdown mode turns off the device, offeringthelowestcurrentconsumption(I =2.5µAtypical). SHUTDOWN Besides the shutdown feature, there are two more modes of operation for the DC-DC converter, depending on thecurrentrequired: • Pulsewidthmodulation(PWM)and • Pulsefrequencymodulation(PFM). The device operates in PWM mode at load current of approximately 80 mA or higher. Lighter load current cause the device to automatically switch into PFM for reduced current consumption (I = 28 µA typical) and a Q_VBATT longerbatterylife. Additional features include soft-start, start-up mode of the linear regulator, undervoltage protection, current overloadprotection,andovertemperatureprotection. An internal reference generates a 1.8-V biasing an internal resistive divider to create a reference voltage range from 0.7 V to 1.8 V (in 50-mV steps) for the LILO and the 0.5-V reference used for the DC-DC converter. The ultra-low-noise linear regulator also has internal reference that generates a 1.8-V biasing for a internal resistor divider,thuscreatingareferencevoltagerangingfrom1.5Vto3.3V. The undervoltage lockout feature enables the device to start-up once V has reached 2.65 V typically and BATT turnsthedeviceoffifV dropsbelow2.41Vtypically. BATT NOTE Postregulation:WhentheDC-DCconverterisswitchedoffwhilethelinearregulatorisstill enabled, the LILO can still support up to 50 mA. The linear regulator LILO is turned on via a small NMOS device supplied by V The maximum current is 50 mA when this IN_LDO . small NMOS is ON. If higher current > 50 mA is desired the following condition must be met: • EN_DC=HIGH When the condition is met, the LILO transitions to the large NMOS and can support up to 350mA. Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 8.2 Functional Block Diagram VIN_LDO/VIN_VBATT VBATT VIN_LILO Driver VREF Digital LDO LILO SW Analog buck (error amplifier) VOUT_LDO VOUT_LILO PGND Buck system (Power ground) QGND (Analog ground) Copyright © 2016, Texas Instruments Incorporated AlwaysconnectV toV . IN_LDO BATT 8.3 Feature Description 8.3.1 DC-DCConverterOperation During the first part of each switching cycle, the control block in the LM3686 turns on the internal PFET switch. This allows current to flow from the input V through the switch pin SW and the inductor to the output filter BATT capacitor and load. The inductor limits the current to a ramp with a slope of (V – V ) / L, by storing BATT OUT_DCDC energyinthemagneticfield. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (– V OUT_DCDC /L). Theoutputfilterstoreschargewhentheinductorcurrentishigh,andreleasesitwhenlow,smoothingthevoltage acrosstheload. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The outputvoltageisequaltotheaveragevoltageattheSWpin. 12 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 Feature Description (continued) 8.3.1.1 PWMOperation During pulse width modulation (PWM) operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependency, feed forward inversely proportionaltotheinputvoltageisintroduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the duty-cycle comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded.ThentheNFETswitchisturnedonandtheinductorcurrentrampsdown.Thenextcycleisinitiatedby theclockturningofftheNFETandturningonthePFET. VSW 2V/DIV VBATT = 3.6V VOUT = 1.8V IOUT = 500 mA IL 200 mA/DIV VOUT 2A Cm CV/oDuIpVled TIME (330 ns/DIV) Figure11. TypicalPWMOperation 8.3.1.2 PFMOperation At very light load, the DC-DC converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two conditionsoccursforadurationof32ormoreclockcycles: 1. TheNFETcurrentreacheszero. 2. ThepeakPMOSswitchcurrentdropsbelowtheI level,(typicallyI <75mA+V /55 Ω ). MODE MODE BATT VBATT = 3.6V VSW IL VOUT = 1.8V IOUT = 20 mA VOUT TIME (1 µs/DIV) Figure12. TypicalPFMOperation Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) During PFM operation, the DC-DC converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between approximately 0.2% and approximately 1.8% above the nominal PWM output voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the high PFM threshold or the peak current exceeds the I level set for PFM mode. The typical peak current in PFM mode is: I = 112 mA + PFM PFM V /20 Ω. BATT Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the high PFM comparator threshold (see Figure 13), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero. Both output switches are then turned off, and the device enters an extremely low power mode. Quiescent supply current during this sleep mode is 28 µA(typical),whichallowstheparttoachievehighefficiencyunderextremelylightloadconditions. If the load current should increase during PFM mode (see Figure 13) causing the output voltage to fall below the low2PFMthreshold,thepartautomaticallytransitionsintofixed-frequencyPWMmode. When V = 2.7 V the device transitions from PWM to PFM mode at approximately 35 mA output current and BATT from PFM mode to PWM mode at approximately 95 mA. When V = 3.6 V, PWM-to-PFM transition happens at BATT approximately 42 mA and PFM-to-PWM transition happens at approximately 115 mA. When V = 4.5 V, BATT PWM-to-PFM transition happens at approximately 60 mA and PFM-to-PWM transition happens at approximately 135mA. High PFM Threshold PFM Mode at Light Load ~1.017*Vout Load current increases Low1 PFM Threshold ~1.006*Vout sxAZ i - Current load increases, IrpPefafumecnt h tlioimel ndit iNncdudufreraunrticet niotlnsontr THrVehgigarooehcl ts ihanPhegtFoodeMld, TLhtouPrwerFns EP hoTFonMld, dLTrotahowwrwe2sas PhrVdoFoslMudt Low2 PFM Threshold I inductor = 0 sleep mode Vout A Low2 PFM Threshold, six PWM Mode at switch back to PWMmode - Z Moderate to Heavy Loads Figure13. OperationInPFMModeandTransfertoPWMMode 8.3.1.3 InternalSynchronousRectification While in PWM mode, the DC-DC converter uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 14 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 Feature Description (continued) 8.3.1.4 CurrentLimiting A current limit feature allows the LM3686 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1220 mA (typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold. This allows the inductor current more time to decay,therebypreventingrunaway. 8.3.1.5 SoftStart The DC-DC converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch- current limit is increased in steps. Soft start is activated only if EN_DCDC goes from logic low to logic high after V reaches2.7V.Softstartisimplementedbyincreasingswitchcurrentlimitinstepsof200mA,400mA,600 BATT mA and 1220 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with a 10 µF output capacitor and 200 mA load is 350 µsandwith1mAloadis200µs. 8.3.2 LinearRegulatorOperation(LILO) In a typical post-regulation application the power input voltage V for the linear regulator is generated by the IN_LILO DC-DC converter. Using a buck converter to reduce the battery voltage to a lower input voltage for the linear regulatortranslatestohigherefficiencyandlowerpowerdissipation. It is also possible to operate the linear regulator independent of the DC-DC converter output voltage either from V V orfromadifferentsource(V )–(I =50mAmaximuminindependentmode). IN_LDO/ BATT IN_LILO OUT_LILO An input capacitor of 1 µF at V is needed to be added if no other filter or bypass capacitor is present in the IN_LILO V path. IN_LILO 8.3.2.1 Start-upMode If V > V + 250 mV the main regulator is active, offering a rated output current of 350 mA and IN_LILO OUT_LILO(NOM) suppliedbyV (largeNMOS). IN_LILO If V < V + 150 mV the start-up LILO is active, providing a reduced rated output current of 50 IN_LILO OUT_LILO(NOM) mAtypical,suppliedbyV (smallNMOS). BATT Figure14. Start-UpSequence,V =V =V =V EN_DCDC EN_LILO EN_LDO BATT 8.3.3 CurrentLimiting(LDOandLILO) The LM3686 incorporates also a current limit for the LDO and LILO to protect itself and external components during overload conditions at their outputs. In the event of a peak overcurrent condition at V or V , OUT_LDO OUT_LILO theoutputcurrentthroughtheNFETpassdeviceislimited. Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 8.4 Device Functional Modes Table1.EnableCombinations EN_DCDC EN_LILO EN_LDO FUNCTION 0 0 0 Nooutputs 0 0 1 Linearregulatorenabledonly(EN_LDO),supplyfromV ,I =300mA IN_LDO OUT_MAX 0 1 0 LinearregulatorenabledonlyLILOsuppliesfromV , IN_LDO I =50mA,V >=V OUT_MAX IN_LDO OUT_LILO 1 0 0 DC-DCconverterenabledonly 1 1 0 LinearregulatorandDC-DCenabled 1. V <V +150mV(typical),thesmallNMOSdeviceisactive(I =50 IN_LILO OUT_LILO MAX mA)andsuppliedbyV . IN_LDO 2. If V > V + 250 mV (typical), the large NMOS device is active (I = IN_LILO OUT_LILO MAX 350mA)andsuppliedbyV .MaxiumcurrentofDC-DCwhenEN_LILO=High IN_LILO is250mA(1)(2) 1 1 1 DC-DCconverterandlinearregulatoractive. LinearregulatorstartsafterDC-DCconverter. (1) TheLILOisturnedonviaasmallNMOSdevicesuppliedbyV Themaximumcurrentis50mAwhenthissmallNMOSisON.If IN_LDO. highercurrent>50mAisdesiredthisconditionmustbedone:EN_DC=HIGH. (2) Whentheswitcherisenabled,atransitionoccursfromthesmallNMOStoalargerNMOS.ThetransitionoccurswhenV > IN_LILO V +250mV.IfV <V +150mV,theLILOswitchesbacktosmallNMOS(switcherEN=low). OUT_LILO IN_LILO OUT_LILO 1.8V VOUT-DCDC 0V 1.2V VOUT-LILO 0V LARGE NMOS IOUT-LILO > 50 mA FET OF LILO (SMALL NMOS) IOUT-LILO 7 50 mA (SMALL NMOS TO LARGE NMOS TRANSITION) Figure15. ModeTransition 16 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The LM3686 is a step-down DC-DC converter with integrated low-dropout linear regular and a low-noise linear regulator optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3-cell NiMH/NiCd batteries. It provides three outputs with combined load current up to 900 mA over an input-voltage range from 2.7 V to 5.5 V. 9.2 Typical Application VBATT 2.7 V to 5.5 V 4.7 PF, 0603 EN_DCDC LM3686 PGND 1 PH 3 MHz SW 1.8 V DC-DC FB_DCDC VIN_LILO 10 PF 0603 PGND EN_LILO PGND Dual Rail LILO 0.7 V to 2 V LILO 350 mA EN_LDO 2.2 PF, 350 mA 0402 QGND VIN_LDO Linear Regulator LDO 1.2 V to 3.3 V 300 mA 1 PF, 0402 1 PF, 300 mA 0402 QGND QGND QGND Copyright © 2016, Texas Instruments Incorporated Figure16. LM3686TypicalApplication 9.2.1 DesignRequirements Fortypicalstep-downDC-DCconverterapplications,usetheparameterslistedinTable2. Table2.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltage 2.7Vto5.5V Outputvoltage 1.8V Outputcurrent 100mA Minimumswitchingfrequency 2.55MHz RMSnoise,10Hzto100kHz 166μV RMS PSRRat100kHz 60dB Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 9.2.2 DetailedDesignProcedure 9.2.2.1 ApplicationSelection TI strongly recommends selection of the required components for the LM3686 device as described within the data sheet. If other components are selected, the device will not perform up to standards, and electrical characteristicscannotbeensured. 9.2.2.2 InductorSelection There are two main considerations when choosing an inductor: the inductor must not saturate, and the inductor current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. The minimum value of inductance to ensure good performanceis0.7µHatI (typical)DCcurrentovertheambienttemperaturerange. Shieldedinductorsradiate LIM lessnoiseandarepreferred.Therearetwomethodstochoosetheinductorsaturationcurrentrating. 9.2.2.2.1 Method1 The saturation current must be greater than the sum of the maximum load current and the worst case average- to-peakinductorcurrent.Thiscanbewrittenas: I >I +I (1) SAT OUT_DCDC_MAX RIPPLE where ISAT ! IOUTMAX + IRIPPLE § • § • § • where IRIPPLE =¤'VBAT2T x- VLOUT‚„x¤'VVBOAUTTT‚„x¤'1f‚„ • I :average-to-peakinductorcurrent RIPPLE • I :maximumloadcurrent(600mA) OUT_DCDCMAX • V :maximuminputvoltageinapplication BATT • L:minimuminductorvalueincludingworstcasetolerances(30%dropcanbeconsideredforMethod1) • f:minimumswitchingfrequency(2.55MHz) (2) 9.2.2.2.2 Method2 A more conservative and recommended approach is to choose an inductor that has a saturation current rating greaterthanthemaximumcurrentlimitof1375mA. A 1-µH inductor with a saturation current rating of at least 1375 mA is recommended for most applications. Resistance of the inductor must less than 0.3 Ω for good efficiency. Table 3 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded- bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, intheeventthatnoisefromlow-costbobbinmodelsisunacceptable. Table3.SuggestedInductorsandTheirSuppliers MODEL VENDOR DIMENSIONSL×W×H(mm) DCR(maximum) BRL2518T1R0M TAIYOYUDEN 2.5×1.8×1.2 80 MDT2520CR1R0M TOKO 2.5×2.0×1.0 80 KSLI252010AG1R0 HITACHIMETALS 2.5×2.0×1.0 75 9.2.2.3 ExternalCapacitors As common with most regulators, the LM3686 requires external capacitors to ensure stable operation. The LM3686 is specifically designed for portable applications requiring minimum board space and the smallest size components.Thesecapacitorsmustbecorrectlyselectedforgoodperformance. 18 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 9.2.2.4 InputCapacitorSelection 9.2.2.4.1 C IN_DC-DC Aceramicinputcapacitorof4.7µF,6.3Vissufficientformostapplications.Placetheinputcapacitorascloseas possible to the V pin of the device. A larger value may be used for improved input voltage filtering. Use X7R BATT or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The minimum input capacitance to ensure good performance is 2.2 µF at 3-V DC bias; 1.5 µF at 5-V DC bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3686 DC-DC converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. The low ESR of a ceramic capacitor provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple currentrating.Theinputcurrentripplecanbecalculatedas: § 2 • IRMS = IOUTMAX x VVBOAUTTT x¤¤'1 - VVBOAUTTT +1r2‚‚„ (VBATT - VOUT) x VOUT r = L x f x IOUTMAX x VBATT The worst case is when VBATT = 2 x VOUT (3) 9.2.2.4.2 C IN_LILO If the LILO is used as post regulation no additional capacitor is needed at V as the output filter capacitor of IN_LILO theDC-DCconverterisclosebyandthereforesufficient. Incaseofindependentmodeuse,a1-µFceramiccapacitorisrecommendedatV ifnootherfiltercapacitor IN_LILO is present in the V supply path. This capacitor must be located a distance of not more than 1 cm from the IN_LILO V inputpinandreturnedtoQ . IN_LILO GND 9.2.2.4.3 C IN_LDO An input capacitor is required for stability. TI recommends using a 1-µF ceramic capacitor and connected betweentheV andQGND. IN_LDO 9.2.2.5 OutputCapacitor 9.2.2.5.1 C OUT_DCDC A ceramic output capacitor of 10 µF, 6.3 V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested fromthemaspartofthecapacitorselectionprocess. The minimum output capacitance to ensure good performance is 5.75 µF at 1.8-V DC bias including tolerances and over ambient temperature range. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low equivalent series resistance (ESR)toperformthesefunctions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the R and ESR canbecalculatedas: Voltagepeak-to-peakrippleduetocapacitancecanbeexpressedas: IRIPPLE VPP-C = 4 x f x C (4) Voltagepeak-to-peakrippleduetoESRcanbeexpressedas: V =(2×I )×R (5) PP-ESR RIPPLE ESR Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com Because these two components are out of phase, the root mean squared (RMS) value can be used to get an approximatevalueofpeak-to-peakripple.Thepeak-to-peakripplevoltage,RMSvaluecanbeexpressedas: V = V 2 + V 2 PP-RMS PP-C PP-ESR (6) Note that the output voltage ripple is dependent on the inductor current ripple and the ESR of the output capacitor (R ). The R is frequency dependent (as well as temperature dependent); make sure the value ESR ESR usedforcalculationsisattheswitchingfrequencyofthepart. 9.2.2.5.2 C OUT_LILO The linear regulator is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X7R, Z5U, or Y5V) in the 2.2-µF range (up to 10 µF) and with an ESR between 3 mΩ to300mΩ issuitableasC intheLM3686applicationcircuit. OUT_LIN This capacitor must be located a distance of not more than 1 cm from the V pin and returned to a clean OUT_LILO analogground.Tantalumorfilmcapacitorsmayalsobeusedatthedeviceoutput,V butthesearenotas OUT_LILO attractiveforreasonsofsizeandcost(seeTable4). 9.2.2.5.3 C OUT_LDO A ceramic capacitor in the 1-uF to 2.2-uF range, and with ESR between 5 mΩ to 500 mΩ, is suitable for the linearregulator.Connectthisoutputcapacitornomorethan1cmfromV andQGND. OUT_LDO F)P100% 0603, 10V, X5R 1 m. o N 80% of % UE ( 60% L A P V 0402, 6.3V, X5R A 40% C 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure17. GraphShowingATypicalVariationInCapacitancevsDCBias Table4.SuggestedCapacitorsandTheirSuppliers CAPACITANCE(µF) MODEL VOLTAGERATING(V) Vendor Type CaseSize/Inch(mm) 10 C1608X5R0J106K 6.3 TDK Ceramic,X5R 0603(1608) 4.7 C1608X5R0J475 6.3 TDK Ceramic,X5R 0603(1608) 2.2 C1608X5R0J225M 6.3 TDK Ceramic,X5R 0603(1608) 1 C1005JB0J105KT 6.3 TDK Ceramic,X5R 0402(1005) 20 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 9.2.3 ApplicationCurves Figure18.VBATTLineTransientResponse Figure19. LineTransientResponse PWMMode:100mAto PFMMode:1mAto 350mA 150mA Figure20.LoadTransientResponseDC-DC Figure21.LoadTransientResponseDC-DC LILO50mAto250mA LDO100mAto250mA Figure22.LoadTransientResponse Figure23.LoadTransientResponse Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 10 Power Supply Recommendations The LM3686 requires a single supply input voltage. This voltage can range between 2.7 V to 5.5 V and must be abletosupplyenoughcurrentforagivenapplication. 11 Layout 11.1 Layout Guidelines PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or instability.ImplementgoodlayoutfortheLM3686byfollowingafewsimpledesignrules: 1. Place the LM3686, inductor,and filter capacitor close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the V BATT andPGNDpin.Placetheoutputcapacitorofthelinearregulatorclosetotheoutputpin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LM3686 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LM3686 by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction preventsmagneticfieldreversalbetweenthetwohalf-cyclesandreducesradiatednoise. 3. Connect the ground pins of the LM3686 and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the groundplane.ItalsoreducesgroundbounceattheLM3686bygivingitalowimpedancegroundconnection. RouteSGNDtotheground-planebyaseparatetrace. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. Thisreducesvoltageerrorscausedbyresistivelossesacrossthetraces. 5. Route noise sensitive traces, such as the voltage feedback path (FB_DCDC), away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3686 circuit, must be direct, and must be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter voltage feedback trace. A good approach is to route the feedback trace on another layer and to haveagroundplanebetweenthetoplayerandlayeronwhichthefeedbacktraceisrouted. 6. Placenoisesensitivecircuitry,suchasradioIFblocks,awayfromtheDC-DCconverter,CMOSdigitalblocks and other noisy circuitry. Interference with noise sensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive pre- amplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal plane; power to it is post-regulated to reduce conducted noise, a good field of application for the on-chip low- dropoutlinearregulator. 22 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

LM3686 www.ti.com SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 11.2 Layout Example Figure24. LM3686Layout 11.3 DSBGA Package Assembly and Use Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board must be used to facilitate placement of the device. The pad style used with DSBGA package must be the non-solder mask defined (NSMD) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder mask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See AN-1112 DSBGA Wafer Level Chip Scale Package for specific instructions how to do this. The 12-pin package used for LM3686 has 300 micron solder balls and requires 275 micron pads for mounting on the circuit board. The trace to each pad must enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad must not exceed 183 micron, for a section approximately 183 micron long or longer, as a thermal relief —then each trace must neck up or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3686 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1 and B1 because PGND and VBATT are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps. The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with frontside shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light, in theredandinfraredrange,shiningontheexposeddieedgesofthepackage. Copyright©2008–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM3686

LM3686 SNVS520F–AUGUST2008–REVISEDNOVEMBER2016 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 12.2 Related Documentation Foradditionalinformation,seethefollowing: AN-1112DSBGAWaferLevelChipScalePackage 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 24 SubmitDocumentationFeedback Copyright©2008–2016,TexasInstrumentsIncorporated ProductFolderLinks:LM3686

PACKAGE OPTION ADDENDUM www.ti.com 26-Oct-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LM3686TLE-AADW/NOPB ACTIVE DSBGA YZR 12 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -30 to 85 SUEB & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 26-Oct-2016 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Oct-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LM3686TLE-AADW/NOPB DSBGA YZR 12 250 178.0 8.4 1.83 2.49 0.76 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Oct-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LM3686TLE-AADW/NOPB DSBGA YZR 12 250 210.0 185.0 35.0 PackMaterials-Page2

MECHANICAL DATA YZR0012xxx 0.600±0.075 D E TLA12XXX (Rev C) D: Max = 2.465 mm, Min =2 .405 mm E: Max = 1.717 mm, Min =1 .656 mm 4215049/A 12/12 NOTES: A.Alllineardimensionsareinmillimeters.DimensioningandtolerancingperASMEY14.5M-1994. B.Thisdrawingissubjecttochangewithoutnotice. www.ti.com

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