Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 LM21305 3-V to 18-V, 5-A, Adjustable Frequency Synchronous Buck Converter 1 Features 2 Applications • High-EfficiencySynchronousDC-DCConverter: • DC-DCConvertersandPOLModules 1 – IntegratedLowR PowerMOSFETs • DSPandFPGACoreVoltageSupplies DSon – WideInputVoltageRange:3Vto18V • TelecommunicationsInfrastructure – LoadCurrentasHighas5A • EmbeddedComputing,Servers,andStorage – SwitchingFrequency:300kHzto1.5MHz 3 Description • ExternalFrequencySynchronization The LM21305 is a full-featured, 5-A, synchronous • Accurate0.598-VFeedbackVoltageReference buck dc-dc converter optimized for solution size, • Ultra-FastLineandLoadTransientResponse: flexibility, and high conversion efficiency. High-power – PeakCurrent-ModeControl density LM21305 designs are easily achieved by virtue of monolithic integration of high-side and low- – InternalSlopeCompensation side power MOSFETs, high switching frequency, – High-BandwidthErrorAmplifier peak current-mode control, and optimized thermal • Ultra-LowShutdownQuiescentCurrent design. The efficiency of the LM21305 is maximized at light loads with diode emulation mode operation • WideDuty-CycleOperatingRange: and at heavy loads by optimal design of the MOSFET – T :70nsforLowV ON-MIN OUT adaptive gate drivers to minimize switch dead-times – T :50nsforHighDutyCycle andbody-diodeconductionlosses. OFF-MIN • DiodeEmulationModeatLightLoads The LM21305 accepts a wide input voltage range of • IntegratedBiasSupplyLDOSub-Regulators 3 V to 18 V for interface to various intermediate bus voltages, including 3.3-V, 5-V, and 12-V rails. A 1.5% • InternalSoft-StartFunction: voltage reference and 70-ns, high-side MOSFET – MonotonicStartupintoPre-BiasedLoads minimum controllable on-time enable output voltages • PrecisionEnableInputwithHysteresis as low as 0.598 V with excellent setpoint accuracy. • Open-DrainPGOODIndicator The LM21305 is available in a 5-mm × 5-mm2 WQFN-28 thermally-enhanced package with 0.5-mm • InternalInputUndervoltageLockout(UVLO) pitch. • Cycle-by-CycleOvercurrentProtection • OutputOvervoltageProtection(OVP) DeviceInformation(1) • ThermalShutdownProtectionwithHysteresis PARTNUMBER PACKAGE BODYSIZE(NOM) • 5-mmx5-mmWQFN-28 PowerPAD™Package LM21305 WQFN(28) 5.00mm×5.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalApplicationCircuit TypicalEfficiencyat12V,500kHz V = 3V...18V *VOUT tracks VIN if VIN < 3.4V 100 IN PVIN CBOOT 95 CBOOT 90 CIN AVIN L VOUT = 3.3V 10 (cid:29)F EN SW 3.3 (cid:29)H (%) 85 Y 80 PGOLOMD21305FB RFB1 COUT ENC 75 CFRQ 47 (cid:29)F CI SYNC FREQ COMP RFB2 FFI 70 E 65 2V5 5V0 RC VOUT=5V RFRQ CC1 60 VVOOUUTT==31..38VV 55 VOUT=1.2V AGND PGND VOUT=0.8V 50 0 1 2 3 4 5 LOADCURRENT(A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................17 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 18 3 Description............................................................. 1 9.1 ApplicationInformation............................................18 4 RevisionHistory..................................................... 2 9.2 TypicalApplication..................................................18 5 Description(continued)......................................... 3 10 PowerSupplyRecommendations..................... 30 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 31 11.1 LayoutGuidelines.................................................31 7 Specifications......................................................... 5 11.2 LayoutExample....................................................33 7.1 AbsoluteMaximumRatings......................................5 12 DeviceandDocumentationSupport................. 34 7.2 ESDRatings..............................................................5 7.3 RecommendedOperatingConditions.......................5 12.1 DeviceSupport ....................................................34 7.4 ThermalInformation..................................................6 12.2 DocumentationSupport........................................34 7.5 ElectricalCharacteristics..........................................6 12.3 CommunityResources..........................................34 7.6 TypicalCharacteristics..............................................8 12.4 Trademarks...........................................................34 12.5 ElectrostaticDischargeCaution............................35 8 DetailedDescription............................................ 11 12.6 Glossary................................................................35 8.1 Overview.................................................................11 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................11 Information........................................................... 35 8.3 FeatureDescription.................................................12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(March2013)toRevisionG Page • ChangedFeatures,Applications,andDescriptionsectionsandpage1graphics................................................................. 1 • AddedFeatureDescriptionsection,ESDRatingstable,DeviceFunctionalModessection,Applicationand Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation Supportsection,andMechanical,Packaging,andOrderableInformationsection. .............................................................. 1 • ChangedPrecisionEnablesection....................................................................................................................................... 15 2 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 5 Description (continued) The LM21305 offers flexible system configuration with programmable switching frequency from 300 kHz to 1.5 MHz using one resistor or by external clock synchronization for beat-frequency-sensitive and multi-regulator applications.On-chipbiassupplylow-dropout(LDO)sub-regulatorseliminatetheneedforanexternalbiaspower and simplify circuit board layout. The device also offers an internal soft-start to limit inrush current and provide monotonic startup capability into unbiased and pre-biased loads, integrated boot diodes, cycle-by-cycle current limiting, and thermal shutdown. Peak current-mode control with a high-gain error amplifier maintains stability throughouttheentireinputvoltageandloadcurrentranges,enablingexcellentlineandloadtransientresponse. The LM21305 features internal output overvoltage protection (OVP) and overcurrent protection (OCP) circuits for increased system reliability. An integrated open-drain, PGOOD indicator provides output voltage monitoring, power-rail sequencing capability, and fault indication. Other features include thermal shutdown with automatic recovery, low PWM minimum on-time, low shutdown quiescent current, and precision enable with hysteresis for programmablelineundervoltagelockout(UVLO). 6 Pin Configuration and Functions RSGPackage 28-PinWQFNwithExposedThermalPad TopView 4 3 2 1 0 1 1 1 1 1 9 8 D B D P D D D N F O M N N N G O O G G G A G C P P P 15 P 7 EN PGND 16 6 FREQ SW 17 5 AGND SW 18 PAD 4 AGND SW 19 3 AGND SW 20 2 AGND PVIN 21 1 2V5 PVIN T D O VIN VIN GN V0 BO VIN VIN A A A 5 C P P 2 3 4 5 6 7 8 2 2 2 2 2 2 2 Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com PinFunctions PIN Type(1) DESCRIPTION NAME NO. 2.5-VoutputoftheinternalLDOregulator.BypasstoAGNDwitha0.1-µFceramiccapacitor. 2V5 21 P Loadingthispinisnotrecommended. 5.0-VoutputoftheinternalLDOregulator.BypasstoPGNDwitha1-µFceramiccapacitor. 5V0 25 P Loadingthispinisnotrecommended. Analoggroundfortheinternalbiascircuitryandsignalreturnconnectionforanalogfunctions, AGND 14,17–20,24 G includingCOMPnetwork,frequencyadjustresistor,and2V5decouplingcapacitor. Analogpowerinput.AVINpowerstheinternal2.5-Vand5.0-VLDOsthatprovidebias AVIN 22,23 P currentandinternaldriverpower,respectively.AVINcanbeconnectedtoPVINthrougha low-passRCfilterorcanbesuppliedbyaseparaterail. High-sidebootstrapconnectiontodrivethehigh-sideMOSFET.Connecta100-nFbootstrap CBOOT 26 P capacitorbetweentheCBOOTandSWpins. Compensationnode.Thispinisanoutputvoltagecontrollooperroramplifieroutput. COMP 11 A Connectanexternalcompensationnetworktoensurestability. Precisionenablepin.Useanexternaldividertosetthedeviceturn-onthreshold.Ifnotused, EN 15 I connecttheENpintoAVIN. Voltagefeedbackpin.Connectthispintotheoutputvoltagedirectlyorthrougharesistor FB 13 A dividertosettheoutputvoltagerange. Frequencyadjustpin.ConnectaresistorfromFREQtoAGNDtosettheinternaloscillator FREQ 16 A frequency.ConnectFREQtoanexternalclocksourceviaacouplingcapacitorto synchronizetotheexternalclockfrequency. PVIN 1,2,27,28 P InputvoltagetothepowerMOSFETsinsidethedevice. SwitchnodeoutputofthepowerMOSFETs.VoltageswingsfromPVINtoGNDonthispin. SW 3-6 P SWalsodeliverscurrenttotheexternalinductor. PGND 7–10 G Powergroundconnectionfortheinternalpowerswitches. Open-drainoutputwith16μsofbuilt-indeglitchtime.Ifhigh,thisstatuspinindicatesthatthe PGOOD 12 OD outputvoltageisregulatedwithintolerance.Connecta10-kΩto100-kΩresistortoapullup voltagesource,forexamplethe5V0railorauxiliarysystemvoltagerail. Exposedpadatthebackofthedevice.ConnectPADtoPGND,butPADcannotbeusedas PAD PAD — theprimarygroundconnection.UsemultipleviasunderPADtoconnecttothesystem groundplaneforoptimalthermalperformance. (1) P:Power,A:Analog,I:DigitalInput,OD:OpenDrain,G:Ground. 4 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 7 Specifications 7.1 Absolute Maximum Ratings see (1)(2) MIN MAX UNIT PVIN,AVIN,SW,EN,PGOODtoAGND −0.3 20 V CBOOTtoAGND −0.3 25 V CBOOTtoSW −0.3 5.5 V 5V0,FB,COMP,FREQtoAGND −0.3 6 V 2V5toAGND −0.3 3 V AGNDtoPGND −0.3 0.3 V Maximumcontinuouspowerdissipation,P (3) Internallylimited D-MAX Junctiontemperature,T 150 °C J-MAX Storagetemperature,T –65 150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitaryorAerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) Theamountofabsolutemaximumpowerdissipationallowedinthedevicedependsontheambienttemperatureandcanbecalculated usingtheformulaP=(T –T )/θ ,whereT isthejunctiontemperature,T istheambienttemperature,andθ isthejunction-to- J A JA J A JA ambientthermalresistance.Junction-to-ambientthermalresistanceishighlyapplicationandboard-layoutdependent.Inapplications wherehighpowerdissipationexists,specialcaremustbepaidtothermaldissipationissuesinPCBdesign.Internalthermalshutdown circuitryprotectsthedevicefrompermanentdamage. 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)(2) ±2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(3) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossiblewiththenecessaryprecautions.Pinslistedas±2000Vmayactuallyhavehigherperformance. (2) Thehumanbodymodelisa100-pFcapacitordischargedthrougha1.5-kΩresistorintoeachpin(MIL-STD-8833015.7). (3) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan250-VCDMispossiblewiththenecessaryprecautions.Pinslistedas±500Vmayactuallyhavehigherperformance. 7.3 Recommended Operating Conditions MIN MAX UNIT PVINtoPGND,AGND 3 18 V AVINtoPGND,AGND 3 18 V Junctiontemperature −40 125 °C Ambienttemperature(1) –40 85 °C (1) Inapplicationswherehighpowerdissipationorpoorpackagethermalresistanceispresent,themaximumambienttemperaturemay havetobederated.Maximumambienttemperature(T )isdependentonthemaximumoperatingjunctiontemperature(T = A-MAX J-MAX-OP 125°C),themaximumpowerdissipationofthedeviceintheapplication(P ),andthejunction-toambientthermalresistanceofthe D-MAX partorpackageintheapplication(θ ),asgivenbythefollowingequation:T =T –(θ ×P ). JA A-MAX J-MAX-OP JA D-MAX Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 7.4 Thermal Information LM21305 THERMALMETRIC(1) RSG(WQFN) UNIT 28PINS R Junction-to-ambientthermalresistance 36.9 °C/W θJA R Junction-to-case(top)thermalresistance 22 °C/W θJC(top) R Junction-to-boardthermalresistance 9.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 9.8 °C/W JB R Junction-to-case(bottom)thermalresistance 2.1 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 7.5 Electrical Characteristics AlltypicallimitsapplyforT =25°C,andallmaximumandminimumlimitsapplyoverthefulloperatingtemperaturerange(T J J =–40°Cto+125°C).Unlessotherwisespecified,V =V =V =12V,V =3.3V,I =0A.(1)(2)(2) IN PVIN AVIN OUT OUT PARAMETER TESTCONDITIONS MIN TYP MAX UNIT GENERAL V Feedbackpinfactory-defaultvoltage 0.588 0.598 0.608 V FB-default ΔV /ΔI Loadregulation I =0.1Ato5A 0.02 %/A OUT OUT OUT ΔV /ΔV Lineregulation V =3Vto18V 0.01 %/V OUT IN PVIN R High-sideswitchon-resistance I =5A 44 mΩ DSonHS DS R Low-sideswitchon-resistance I =5A 22 mΩ DSonLS DS I High-sideswitchcurrentlimit High-sideMOSFET 5.9 7 7.87 A CL-HS I Low-sideswitchcurrentlimit Low-sideMOSFET(3) 5.9 8 10.2 A CL-LS I Low-sideswitchnegativecurrentlimit Low-sideMOSFET –7 –4.1 –1.64 A NEG-CL-LS V =V =5V 0.1 2 AVIN PVIN I Quiescentcurrent,disabled µA SD V =V =18V 1 4.1 AVIN PVIN Quiescentcurrent,enabled,not I V =V =18V 9 9.7 mA Q switching AVIN PVIN I Feedbackpininputbiascurrent V =0.598V 1 nA FB FB G Erroramplifiertransconductance 2400 µs M A Erroramplifiervoltagegain 65 dB VOL V OVPtrippingthreshold Risingthreshold,percentageofV 103.5% 109.5% 115% IH-OVP OUT V OVPhysteresiswindow PercentageofV –4.3% HYST-OVP OUT V AVINUVLOrisingthreshold 2.84 2.93 2.987 V UVLO-HI-AVIN V AVINUVLOfallingthreshold 2.66 2.73 2.83 V UVLO-LO-AVIN V AVINUVLOhysteresiswindow 195 mV UVLO-HYS-AVIN V InternalLDO1outputvoltage Measuredat5V0pin,1-kΩload 4.88 V 5V0 Recommendedcapacitanceconnected C Ceramiccapacitor 1 µF OUT-CAP-5V0 to5V0pin (1) Alllimitsarespecifiedbydesign,testorstatisticalanalysis.Allelectricalcharacteristicshavingroom-temperaturelimitsaretestedduring productionwithT =25°C.Allhotandcoldlimitsarespecifiedbycorrelatingtheelectricalcharacteristicstoprocessandtemperature J variationsandapplyingstatisticalprocesscontrol. (2) Capacitors:lowESRsurface-mountceramiccapacitors(MLCCs)areusedinsettingelectricalcharacteristics. (3) Thelow-sideswitchcurrentlimitisensuredtobehigherthanthehigh-sidecurrentlimit. 6 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Electrical Characteristics (continued) AlltypicallimitsapplyforT =25°C,andallmaximumandminimumlimitsapplyoverthefulloperatingtemperaturerange(T J J =–40°Cto+125°C).Unlessotherwisespecified,V =V =V =12V,V =3.3V,I =0A.(1)(2)(2) IN PVIN AVIN OUT OUT PARAMETER TESTCONDITIONS MIN TYP MAX UNIT GENERAL(continued) I Short-circuitcurrentof5V0pin 31 mA SHORT-5V0 V InternalLDO2outputvoltage Measuredat2V5pin,1-kΩload 2.47 V 2V5 Recommendedcapacitanceconnected Ceramiccapacitor C 100 nF OUT-CAP-2V5 to2V5pin I Short-circuitcurrentof2V5pin 47 mA SHORT-2V5 VF CBOOTdiodeforwardvoltage Measuredfrom5V0toCBOOTat10mA 0.76 V CBOOT-D I CBOOTleakagecurrent V =5.5V,notswitching 0.65 µA CBOOT CBOOT StartuptimefromENhightothe T 160 µs STARTUP-DELAY beginningofinternalsoft-start SS Internalsoft-start 10%to90%V 1.41 2.7 4.15 ms FB OSCILLATOR Oscillatorfrequency,nominal F R =61.9kΩ,0.025% 695 750 795 kHz OSC-NOM measuredatSWpin FRQ Maximumoscillatorfrequency F R =28.4kΩ 1500 kHz OSC-MAX measuredatSWpin FRQ Minimumoscillatorfrequency F R =167.5kΩ 300 kHz OSC-MIN measuredatSWpin FRQ F =1.5MHz,V =3.3V,V =1V, T Minimumoff-timemeasuredatSWpin SW IN FB 50 ns OFF-MIN voltagedividerratio=3.3 T Minimumon-timemeasuredatSWpin F =1.5MHz,voltagedividerratio=1 70 ns ON-MIN SW LOGIC V ENpinrisingthreshold 1.1 1.2 1.3 V IH-EN V ENpinhysteresiswindow 130 200 302 mV HYST-EN I ENpininputcurrent V =12V 18 23 µA EN-IN EN V PGOODUVrisingthreshold PercentageofV 87.5% 93% 97.5% IH-UV-PGOOD OUT V PGOODUVhysteresisthreshold PercentageofV –4.2% HYST-UV-PGOOD OUT I PGOODsinkcurrent V =0.2V 3 mA OL-PGOOD OL I PGOODleakagecurrent V =18V 460 nA OH-PGOOD OH THERMALSHUTDOWN T Thermalshutdown(4) 160 °C SD T Thermalshutdownhysteresis(4) 10 °C SD-HYS (4) Specifiedbydesign. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 7.6 Typical Characteristics V =12V,V =3.3V,F =500kHz,T =25°C,L=3.3µH,andC =100µF(ceramic),(unlessotherwisespecified) IN OUT SW A OUT 100 100 95 95 90 90 %) 85 %) 85 ( ( Y 80 Y 80 C C EN 75 EN 75 FICI 70 FICI 70 F F E 65 E 65 VOUT=5V 60 VOUT=3.3V 60 VOUT=3.3V VOUT=1.8V VOUT=1.8V 55 VOUT=1.2V 55 VOUT=1.2V VOUT=0.8V VOUT=0.8V 50 50 0 1 2 3 4 5 0 1 2 3 4 5 LOADCURRENT(A) LOADCURRENT(A) F =300kHz F =300kHz SW SW Figure1.EfficiencywithPVIN=AVIN=5V Figure2.EfficiencywithPVIN=AVIN=12V 100 100 95 95 90 90 %) 85 %) 85 ( ( Y 80 Y 80 C C EN 75 EN 75 CI CI FI 70 FI 70 F F E 65 E 65 VOUT=5V 60 VOUT=3.3V 60 VOUT=3.3V VOUT=1.8V VOUT=1.8V 55 VOUT=1.2V 55 VOUT=1.2V VOUT=0.8V VOUT=0.8V 50 50 0 1 2 3 4 5 0 1 2 3 4 5 LOADCURRENT(A) LOADCURRENT(A) F =500kHz F =500kHz SW SW Figure3.EfficiencywithPVIN=AVIN=5V Figure4.EfficiencywithPVIN=AVIN=12V 100 100 95 95 90 90 %) 85 %) 85 ( ( Y 80 Y 80 C C EN 75 EN 75 FICI 70 FICI 70 F F E 65 E 65 VOUT=5V 60 VOUT=3.3V 60 VOUT=3.3V VOUT=1.8V VOUT=1.8V 55 VOUT=1.2V 55 VOUT=1.2V VOUT=0.8V VOUT=0.8V 50 50 0 1 2 3 4 5 0 1 2 3 4 5 LOADCURRENT(A) LOADCURRENT(A) FSW=1MHz FSW=1MHz Figure5.EfficiencywithPVIN=AVIN=5V Figure6.EfficiencywithPVIN=AVIN=12V 8 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Typical Characteristics (continued) V =12V,V =3.3V,F =500kHz,T =25°C,L=3.3µH,andC =100µF(ceramic),(unlessotherwisespecified) IN OUT SW A OUT 0.10 0.10 N (%) 0.05 N (%) 0.05 O O ULATI 0.00 ULATI 0.00 G G RE RE D E LOA-0.05 LIN-0.05 -0.10 -0.10 0 1 2 3 4 5 3 6 9 12 15 18 LOAD CURRENT (A) INPUT VOLTAGE, PVIN (V) Figure7.LoadRegulation(%V ) Figure8.LineRegulation(%V ) OUT OUT 1.0 10 A) N (%) 0.5 NT (m 9 O E ATI RR 8 UL 0.0 CU EG NT 7 R E T C OU-0.5 ES V QUI 6 -40°C 25°C 85°C -1.0 5 -40 -20 0 20 40 60 80 100 3 6 9 12 15 18 TEMPERATURE (°C) INPUT VOLTAGE (V) Figure9.V Regulation(%)vsTemperature Figure10.InputQuiescentCurrent,NotSwitching OUT 70 1800 60 High-Side RDSon(m(cid:13)) 1600 1400 50 z) (cid:13)R(m)DSON 3400 EQUENCY (kH11680200000000 20 R F 400 10 -40°C Low-Side RDSon(m(cid:13)) 200 2152°5C°C 0 0 -40 -20 0 20 40 60 80 100 0 20 40 60 80100120140160180 TEMPERATURE (°C) RFRQ(k(cid:13)) Figure11.High-SideandLow-SideMOSFETR Figure12.SwitchingFrequencyvsR DS(on) FRQ vsTemperature Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) V =12V,V =3.3V,F =500kHz,T =25°C,L=3.3µH,andC =100µF(ceramic),(unlessotherwisespecified) IN OUT SW A OUT IOUT 1A/DIV EN 1V/DIV VOUT 1V/DIV PGOOD 1V/DIV PGOOD 1V/DIV EN 1V/DIV VOUT 1V/DIV IOUT 1A/DIV 2 ms/DIV 2 ms/DIV Figure13.Soft-Start,NoLoad Figure14.Soft-StartwithResistiveLoad EN 1V/DIV VOUT 1V/DIV PGOOD 1V/DIV IOUT 1A/DIV 2 ms/DIV Figure16.SwitchingWaveformwithNoLoadConnected Figure15.Soft-Startwith2-VPre-BiasVoltage,NoLoad (DCMOperation) Figure17.SwitchingWaveformwith5-ALoad Figure18.LoadTransientResponse,0.1Ato5A 10 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 8 Detailed Description 8.1 Overview The LM21305 employs a current-mode control loop with slope compensation to accurately regulate the output voltage over substantial load, line, and temperature ranges. The switching frequency is programmable between 300 kHz and 1.5 MHz through a resistor or an external synchronization signal. The LM21305 is available in a thermally-enhanced WQFN-28 packages with 0.5-mm lead pitch. The device offers high levels of integration by including power MOSFETs, low-dropout (LDO) bias supply regulators, and comprehensive fault protection features to enable highly flexible, reliable, energy-efficient, and high density regulator solutions. Multiple fault conditionsareaccommodated,includingovervoltage,undervoltage,overcurrent,andovertemperature. The 0.598-V reference is compared to the feedback signal at the error amplifier (EA). The PWM modulator block compares the on-time current sense information with the summation of the EA output (control voltage) and slope compensation signal. The PWM modulator outputs on and off signals to the high-side and low-side MOSFET drivers. Adaptive dead-time control is applied to the PWM output such that MOSFET shoot-through current is avoided.ThedriversthenamplifythePWMsignalstocontroltheintegratedhigh-sideandlow-sideMOSFETs. 8.2 Functional Block Diagram R1 C7 C6 C5 2V5 AVIN 5V0 CBOOT VIN LDO2 LDO1 PVIN 2.5V 5V C1 OTP ISENSE HS UVLO FET C2 OCP SS EN Non- + overlap L1 VOUT - REF EA PPWWMM PWM Control Logic SSWW C3 1.2V Non- PGOOD Input Slope OVP overlap UVLO Comp Output UV, OV Z cross AGND OTP LS FET OCP Rev OCP FB OSC/ Sync FREQ COMP PGND SYNC R1 C5 R4 C4 Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 8.3 Feature Description 8.3.1 SynchronousDC-DCSwitchingConverter The LM21305 employs a buck type (step-down) dc-dc converter architecture. The device uses many advanced features to achieve excellent voltage regulation and efficiency. This easy-to-use regulator has two integrated power MOSFET switches and is capable of supplying up to 5 A of continuous output current. The regulator uses peak current-mode control with slope compensation scaled with switching frequency to optimize stability and transient response over the entire output voltage and switching frequency ranges. Peak current-mode control also provides inherent line feed-forward, cycle-by-cycle current limiting, and easy loop compensation. The switching frequency is adjusted between 300 kHz and 1.5 MHz. The device can operate with a small external LC filter and still provides very low output voltage ripple. The precision internal voltage reference allows the output to be set as low as 0.598 V. Using an external compensation circuit, the regulator crossover frequency can be selectedbasedontheswitchingfrequencytoprovidefastlineandloadtransientresponse. The switching regulator is specifically designed for highly-efficient operation throughout the load range. Synchronous rectification yields high efficiency for low output voltage and heavy load current situations, whereas discontinuous conduction mode (DCM) and diode emulation mode (DEM) enable high-efficiency conversion at lighter load current conditions. Fault protection features include: high-side and low-side MOSFET current limiting, negative current limiting on the low-side MOSFET, overvoltage protection, and thermal shutdown. The device is available in a WQFN-28 package featuring an exposed pad to aid thermal dissipation. Use the LM21305 in numerousapplicationstoefficientlystep-downfromawiderangeofinputrails:3Vto18V. 8.3.2 PeakCurrent-ModeControl In most applications, the peak current-mode control architecture used in the LM21305 requires only two external components to achieve a stable design. External compensation allows the user to set the crossover frequency and phase margin, thus optimizing the transient performance of the device. For duty cycles above 50%, all peak current-mode controlled buck converters require the addition of an additional ramp to avoid sub-harmonic oscillation. This linear ramp is commonly referred to as slope compensation. The amount of slope compensation in the LM21305 automatically changes depending on the switching frequency: the higher the switching frequency,thelargertheslopecompensation.Thisadaptiveamplitudeslopecompensationfeaturefacilitatesuse ofsmallerinductorsinhigh-switchingfrequencyapplicationswherehigherpowerdensityiscritical. 8.3.3 SwitchingFrequencySettingandSynchronization The LM21305 switching regulator operates over a frequency ranging from 300 kHz to 1.5 MHz. The switching frequency is set or controlled in two ways. One is by selecting the external resistor connected to the FREQ pin to set the internal free-running oscillator frequency that determines the switching frequency. Connect an external 100-pFcapacitor,C ,fromFREQtoAGNDasanoisefilter,asshowninFigure19. FRQ LM21305 CFRQ FREQ RFRQ Figure19. SwitchingFrequencySetbyExternalResistor The other way is to synchronize the switching frequency to an external clock in the range of 300 kHz to 1.5 MHz. Applytheexternalclockthrougha100-pFcouplingcapacitor,C ,asshowninFigure20. FRQ LM21305 CFRQ External FREQ Clock RFRQ Figure20. SwitchingFrequencySynchronizedtotheExternalClock 12 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Feature Description (continued) The recommendations for the external clock include peak-to-peak voltage above 1.5 V, duty cycle between 20% and 80%, and an edge rate faster than 100 ns. Circuits that use an external clock must still use a resistor connected from FREQ to AGND. The external clock frequency must be within –10% to +50% of the free-running frequency set by R . This arrangement allows the regulator to continue operating at approximately the same FRQ switching frequency if the external clock fails and the coupling capacitor on the clock side is grounded or pulled tologichigh. If the external clock fails low, timeout circuits prevent the high-side MOSFET from staying off for longer than 1.5 times the switching period, T = 1 / F . At the end of this timeout period, the regulator begins to switch at the SW SW frequencysetbyR . FRQ If the external clock fails high, timeout circuits again prevent the high-side MOSFET from staying off longer than 1.5 times the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed 1 MHz until the voltage on the FREQ pin has decayed to approximately 0.6 V. This decay follows the time constantofC andR and,whencomplete,theregulatorswitchesatthefrequencysetbyR . FRQ FRQ FRQ 8.3.4 Light-LoadOperation The LM21305 offers increased efficiency at light loads by allowing discontinuous conduction mode (DCM). When the load current is less than half of the inductor ripple current the device enters DCM, thus preventing negative inductorcurrent.TheoutputcurrentatthecriticalconductionboundaryiscalculatedaccordingtoEquation1: ’I V (cid:152)(cid:11)1(cid:16)D(cid:12) I L OUT BOUNDARY 2 2(cid:152)L(cid:152)F SW where • Disthedutycycleofthehigh-sideMOSFET,equaltothehigh-sideMOSFETon-timedividedbytheswitching period (1) For more details, see the Calculating the Duty Cycle subsection in the Detailed Design Procedure section. Several diagrams are provided in Figure 21 that illustrate continuous conduction mode (CCM), discontinuous conduction mode (DCM), and the boundary condition. In DCM, whenever the inductor current reaches zero the SW node becomes high impedance. Ringing occurs on this pin as a result of the LC tank circuit formed by the inductor and the effective parasitic capacitance at the switch node. At very light loads, usually below 100 mA, several pulses are skipped in between switching cycles, effectively reducing the switching frequency and further improvinglight-loadefficiency. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Feature Description (continued) e g Continuous Conduction Mode (CCM) a Volt VIN e d o n h c wit S Time (s) nt Continuous Conduction Mode (CCM) e urr C ctor IAVERAGE u d n I Time (s) nt e urr DCM - CCM Boundary C or ct u nd IAVERAGE I Time (s) e g Discontinuous Conduction Mode (DCM) a olt VIN V e d o n h c wit S Time (s) nt e urr Discontinuous Conduction Mode (DCM) C or ct du IPeak n I Time (s) Figure21. CCMandDCMOperation 14 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Feature Description (continued) 8.3.5 PrecisionEnable The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.2 V (typical). The EN pin has 200 mV (typical) of hysteresis and disables the output when the enable voltage falls below 1.0 V (typical). If the EN pin is not used, pull this pin up to AVIN via a 10-kΩ to 100-kΩ resistor. Given that EN has a precise turn- on threshold, use an external resistor divider network from an external voltage to configure the device to turn on at a precise voltage. The precision enable circuits remains active even when the device is disabled. From Figure22,calculatetheturn-onvoltagewithadividerusingEquation2: § R • V 1.2 V(cid:152)¤1(cid:14) EN1 ‚ EN(cid:16)EXT ' R „ EN2 (2) V EN-EXT LM21305 R EN1 EN R EN2 Figure22. UseanExternalResistorDividertoSettheENThreshold 8.3.6 DeviceEnable,Soft-Start,andPre-BiasStartupCapability TheLM21305canbeturnedoffbyremovingAVINorbypullingtheENpinlow.Toenablethedevice,theENpin must be high with the presence of AVIN and PVIN. When enabled, the device engages the internal soft-start circuit. The soft-start feature allows the regulator output to gradually reach the steady-state operating point, thus reducing stresses on the input supply and controlling startup current. Soft-start begins at the rising edge of EN with AVIN above the UVLO level. PVIN must be high when soft-start begins. The LM21305 allows AVIN to be higherthanPVIN,orPVINhigherthanAVIN,providedthatbothvoltagesarewithintheiroperatingranges. Soft-startoftheLM21305iscontrolledinternally,and2.7msistypicallyrequiredtofinishthesoft-startsequence. PGOODtransitionshighaftersoft-startiscomplete. The LM21305 is in a pre-biased state when the device initiates startup with an output voltage greater than zero. This condition often occurs in multi-rail applications, such as when powering an field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or digital signal processor (DSP) loads. In these applications, the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM21305 is a synchronous converter, the device does not pull the output low when a pre-bias condition exists. During startup, the LM21305 is in diode emulation mode with the low-side MOSFET turned off whenzerocrossingoftheinductorcurrentisdetected. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Feature Description (continued) 8.3.7 PeakCurrentProtectionandNegativeCurrentLimiting The LM21305 switching regulator detects the peak inductor current and limits it to 7 A, typical. To determine the average current from the peak current, the inductor size, input and output voltage, and switching frequency must beknown.TheaveragecurrentlimitisfoundfromEquation3: ’I I I (cid:16) L AVE(cid:16)LIMIT PEAK(cid:16)LIMIT 2 (3) When the peak inductor current sensed in the high-side MOSFET reaches the current limit threshold, an overcurrent event is triggered, the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the inductor current to ramp down until the next switching cycle. When the high-side overcurrent condition persists, theoutputvoltageisdecreasedbythereducedhigh-sideMOSFETon-time. In cases such as output short-circuit or when high-side MOSFET minimum on-time conditions are reached, the high-side MOSFET current limiting may not be sufficient to limit the inductor current. The LM21305 features an additional low-side MOSFET current limit to prevent the inductor current from running away. The low-side MOSFET current limit, 8 A typical, is set higher than the high-side current limit. When the low-side MOSFET current is higher than the limit level, PWM pulses are skipped until a low-side overcurrent is not detected during the entire low-side MOSFET conduction time. Normal PWM switching subsequently occurs when the condition is removed. High-side and low-side MOSFET current protections result in a current limit that does not aggressively foldback for brief overcurrent events, and at the same time provides frequency and voltage foldback protection during hard short-circuit conditions. The low-side MOSFET also has a negative current limit, –4.1 A typical, for secondary protection that can engage during response to overvoltage events. If the negative current limit is triggered, the low-side MOSFET is turned off. The negative current is forced to go through the high-side MOSFETbodydiodeandquicklyreduces. 8.3.8 PGOODIndicator To implement an open-drain, power-good function for sequencing and fault detection, use the PGOOD pin of the LM21305. The PGOOD open-drain MOSFET is pulled low during output undervoltage and overvoltage, UVLO, and thermal shutdown. The PGOOD function has a 16-µs glitch filter to prevent false-flag operation for short excursions in the output voltage, such as during line and load transients. When the FB voltage is typically within –7% to 9.5% of the reference voltage, PGOOD is high. The thresholds track with the output voltage because the PGOOD comparator and the regulation loop share the same reference. Pull PGOOD high with an external resistor (10 kΩ to 100 kΩ is recommended) to an external logic supply. PGOOD can also be pulled-up to either the 5V0 rail or to the output voltage through an appropriate resistor, as desired. Tie PGOOD to AGND if the functionisnotrequired. 8.3.9 InternalBiasRegulators The LM21305 contains two internal low dropout (LDO) regulators to produce internal driving and bias voltage rails from AVIN. One LDO produces 5 V to power the internal MOSFET drivers, the other LDO produces 2.5 V to power the internal bias circuitry. Bypass both the 5V0 or 2V5 LDOs to the analog ground (AGND) with an external ceramic capacitor (1 μF and 0.1 μF are recommended, respectively). Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. Applications with high input voltage and high switching frequency increase die temperature because of the higher power dissipation within the LDOs. Connecting a load to the 5V0 or 2V5 pins is not recommended because doing so degrades their driving capability to internal circuitry, further pushing the LDOs into their RMS current ratings and increasing powerdissipationanddietemperature. The LM21305 allows AVIN to be as low as 3 V, which makes the voltage at the 5V0 LDO lower than 5 V. Low supply voltage at the MOSFET drivers increases on-state resistance of the high-side and low-side power MOSFETs and reduces efficiency of the regulator. When AVIN is between 3 V and 5.5 V, the best practice is to short the 5V0 pin to AVIN to avoid the voltage drop on the internal LDO. However, the device can be damaged if the 5V0 pin is pulled to a voltage higher than 5.5 V. For efficiency considerations, use AVIN = 5 V if possible. When AVIN is above 5 V, reduced efficiency can be observed at light load because of the power loss of the LDOs. When AVIN is close to 3 V, increased MOSFET on-state resistance can reduce efficiency at high load currents. 16 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Feature Description (continued) 8.3.10 MinimumOn-TimeConsiderations Minimumon-time,T ,isthesmallestdurationoftimethatthehigh-sideMOSFETconducts,typically70nsin ON-MIN the LM21305. In CCM operation, the minimum on-time limit corresponds to a minimum duty cycle as shown in Equation4: D F (cid:152)T MIN SW ON(cid:16)MIN (4) The minimum on-time becomes relevant when operating simultaneously at high input voltage and high switching frequency. As Equation 4 shows, reducing the operating frequency alleviates the minimum on-time constraint. Foragivenswitchingfrequencyandoutputvoltage,themaximumPVINisapproximatedbyEquation5: V 1 V OUT (cid:152) PVIN(max) F T SW ON(cid:16)MIN (5) Similarly, if the input voltage is fixed, the maximum switching frequency without reaching the minimum on-time constraintisfoundbyEquation6: V 1 F OUT (cid:152) SW(max) V T PVIN(max) ON(cid:16)MIN (6) In rare cases where steady-state operation at minimum duty cycle is unavoidable, the regulator automatically skipscyclestokeepV regulated,similartolight-loadDCMoperation. OUT 8.4 Device Functional Modes 8.4.1 OvervoltageandUndervoltageHandling The LM21305 has built-in undervoltage protection (UVP) and overvoltage protection (OVP) using FB voltage comparators to control the power MOSFETs. The rising OVP threshold is typically set at 109.5% of the nominal voltage setpoint. Whenever excursions occur in the output voltage above the OVP threshold, the device terminates the present on-pulse, turns on the low-side MOSFET, and pulls PGOOD low. The low-side MOSFET remains on until either the FB voltage falls back into regulation or the inductor current zero-cross is detected. If the output reaches the falling UVP threshold, typically 88.8% of the nominal setpoint, the device continues switchingandPGOODisassertedandpullslow.AsdetailedinthePGOODIndicatorsection,PGOODhas16 μs of built-in deglitch time to both the rising and falling edges to avoid false tripping during transient glitches. OVP is disabledduringsoft-starttopreventfalsetriggering. 8.4.2 UndervoltageLockout(UVLO) The LM21305 has a built-in undervoltage lockout (UVLO) protection circuit that prevents the device from switching until the AVIN voltage reaches 2.93 V (typical). The UVLO threshold has typically 195 mV of hysteresis thatkeepsthedevicefromrespondingtopower-onglitchesduringstartup. 8.4.3 ThermalProtection Internal thermal shutdown circuitry is provided to protect the LM21305 in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM21305 turns off the power MOSFETs and resets soft-start. After the junction temperature cools to approximately 150°C, the LM21305 starts up using the normalstartuproutine. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The LM21305 is a step-down dc-dc converter, typically used to convert a higher dc voltage to a lower dc voltage with a maximum output current of 5 A. The following design procedure can be used to select components for the LM21305.Alternately,theWEBENCH®designtool canbeusedtogenerateacompletedesign.Thistoolusesan iterative design procedure and has access to a comprehensive database of components that allows the tool to createanoptimizeddesignandallowstheusertoexperimentwithvariousdesignoptions. As well as numerous LM21305 reference designs populated in the TI Designs reference design library, the LM21305QuickStartCalculatorisalsoavailableasafreedownload. 9.2 Typical Application This section walks the designer through the steps necessary to select the external components to build a fully- functional, efficient, step-down power supply. As with any dc-dc converter, numerous tradeoffs are possible to optimize the design for efficiency, size, and performance. These tradeoffs are taken into account and highlighted throughout this discussion. To facilitate component selection discussions, the typical application circuit shown in Figure23isusedasareference. VIN PVIN CBOOT CIN1 CIN2 CIN3 CBOOT L VOUT RF SW AVIN CF 0.598V RFB1 COUT1 COUT2 REN FB EN LM21305 RFB2 C2V5 2V5 COMP Cc1 Rc 5V0 RPG C5V0 CFRQ PGOOD FREQ AGND PGND RFRQ Figure23. LM21305TypicalApplicationCircuit 18 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Typical Application (continued) 9.2.1 DesignRequirements Table1showstheBillofMaterialsforanLM21305converter. Table1.BillofMaterials(F =500kHz) SW V 1.2V 1.8V 2.5V 3.3V 5V PACKAGE OUT C TANT,47µF,25V TANT,47µF,25V TANT,47µF,25V TANT,47µF,25V TANT,47µF,25V CASED IN1 C 10µF,25V,X5R 10µF,25V,X5R 10µF,25V,X5R 10µF,25V,X5R 22µF,25V,X5R 1210 IN2 C 0.1µF,25V,X7R 0.1µF,25V,X7R 0.1µF,25V,X7R 0.1µF,25V,X7R 0.1µF,25V,X7R 1206 IN3 C 1.0µF,25V,X7R 1.0µF,25V,X7R 1.0µF,25V,X7R 1.0µF,25V,X7R 1.0µF,25V,X7R 0603 F C ,C 0.1µF,16V,X7R 0.1µF,16V,X7R 0.1µF,16V,X7R 0.1µF,16V,X7R 0.1µF,16V,X7R 0603 2V5 BOOT C 1.0µF,16V,X7R 1.0µF,16V,X7R 1.0µF,16V,X7R 1.0µF,16V,X7R 1.0µF,16V,X7R 0603 5V0 C 100pF,25V,X7R 100pF,25V,X7R 100pF,25V,X7R 100pF,25V,X7R 100pF,25V,X7R 0603 FRQ C 3.3nF,16V,X7R 3.3nF,16V,X7R 3.3nF,16V,X7R 3.3nF,16V,X7R 3.3nF,16V,X7R 0603 C1 C ,C 47µF,6.3V,X5R 47µF,6.3V,X5R 47µF,6.3V,X5R 47µF,6.3V,X5R 47µF,10V,X5R 1206 OUT1 OUT2 L 1.5µH,10A 2.2µH,10A 2.2µH,10A 3.3µH,10A 3.3µH,10A SMD R 1Ω,5% 1Ω,5% 1Ω,5% 1Ω,5% 1Ω,5% 0603 F R ,R 100kΩ,1% 100kΩ,1% 100kΩ,1% 100kΩ,1% 100kΩ,1% 0603 FRQ PG R ,R 10kΩ,1% 10kΩ,1% 10kΩ,1% 10kΩ,1% 10kΩ,1% 0603 FB2 EN R 3.32kΩ,1% 4.22kΩ,1% 5.10kΩ,1% 7.15kΩ,1% 8.2kΩ,1% 0603 C R 10kΩ,1% 20kΩ,1% 31.6kΩ,1% 45.3kΩ,1% 73.2kΩ,1% 0603 FB1 9.2.2 DetailedDesignProcedure 9.2.2.1 SettingtheOutputVoltage Connect the FB pin of the LM21305 directly to V or through a feedback resistor divider network to scale up OUT from the 0.598-V feedback voltage to the desired output voltage. Figure 24 shows the resistor divider connection andtheFBpin. VOUT LM21305 RFB1 FB RFB2 Figure24. SettingtheOutputVoltagebyResistorDivider TheoutputvoltageisfoundbyEquation7: § R • V 0.598 V(cid:152)¤1(cid:14) FB1 ‚ OUT ' R „ FB2 (7) Forexample,ifthedesiredoutputvoltageis1.8V,R =20kΩ andR =10kΩcanbeused. FB1 FB2 Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 9.2.2.2 CalculatingtheDutyCycle Thefirstparametertocalculateforanybuckconverterisdutycycle.Inanideal(no-loss)buckconverter,theduty cycleisfoundbyEquation8: V D OUT IDEAL V PVIN (8) In applications with low output voltage (< 1.2 V) and high load current (> 3 A), the losses must not be ignored when calculating the duty cycle. Considering the effect of conduction losses associated with the MOSFETs and inductor,thedutycycleisapproximatedbyEquation9: V (cid:14)I (cid:152)(cid:11)R (cid:14)R (cid:12) D OUT OUT DSonLS DCR V (cid:14)I (cid:152)(cid:11)R (cid:16)R (cid:12) IN OUT DSonLS DSonHS (9) R and R are the on-state resistances of the high-side and low-side MOSFETs, respectively. R is DSonHS DSonLS DCR the equivalent dc resistance of the inductor used in the output filter. Other parasitics, such as printed circuit board(PCB)traceresistance,canbeincludedifdesired.I istheloadcurrentandisalsoequaltotheaverage OUT inductorcurrent.Thedutycycleincreasesslightlywhenloadcurrentincreases. 9.2.2.3 InputCapacitors PVIN is the supply voltage for the switcher power stage and is the input source that delivers the output power to the load. The input capacitors on the PVIN rail supply the large ac switching current drawn by the switching action of the internal power MOSFETs. The input current of a buck converter is discontinuous and the ripple current supplied by the input capacitor can be quite large. The input capacitor must be rated to handle this current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. ThemaximumRMScurrentisgivenbyEquation10: V (cid:152)(cid:11)V (cid:16)V (cid:12) I I (cid:152) OUT PVIN OUT RMS(cid:16)CIN OUT V PVIN (10) ThepowerdissipationoftheinputcapacitorisgivenbyEquation11: P I 2(cid:152)R D(cid:16)CIN RMS(cid:16)CIN ESR(cid:16)CIN where • R istheESRoftheinputcapacitor (11) ESR–CIN Equation 10 has a maximum at PVIN = 2 V , where I ≅ I / 2 and D ≅ 50%. This simple worst-case OUT RMS-CIN OUT condition is commonly used for design purposes because even significant deviations from the worst-case duty cycle operating point do not offer much difference. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. Several capacitors can be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during load current changes. A 1-µF ceramic bypass capacitor is also recommended directly adjacent to the device between the PVIN and PGND pins. See Figure 38 and the Layout Guidelines section. 9.2.2.4 AVINFilter Add an RC filter to prevent any switching noise on PVIN from interfering with the internal analog circuits connected to AVIN, as shown in the schematic of Figure 23 and denoted by components R and C . There is a F F practical limit to the resistance of resistor R because the AVIN pin draws a short 60-mA burst of current during F startup. If R is too large, the resulting voltage drop can trigger the UVLO comparator. A recommended 1-Ω F resistorand1-μFcapacitorprovidesapproximately10dBofattenuationata500-kHzswitchingfrequency. 20 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 9.2.2.5 SwitchingFrequencySelection The LM21305 supports a wide range of switching frequencies: 300 kHz to 1.5 MHz. The choice of switching frequency is usually a compromise between conversion efficiency and the size of the circuit. A lower switching frequency implies reduced switching losses (including gate drive and switch transition losses) and usually results in higher overall efficiency. However, a higher switching frequency allows use of smaller LC output filter components and thus a more compact design. Lower inductance also helps transient response (higher large- signal slew rate of the inductor current) and reduces the DCR losses. The optimal switching frequency is usually a tradeoff in a given application and thus must be determined on a case-by-case basis. In practice, the optimal switching frequency is related to input voltage, output voltage, most common load current level, external component choices, and circuit size requirements. The choice of switching frequency is also limited if an operatingconditiontriggersT orT ;seetheMinimumOn-TimeConsiderationssectionformoredetail. ON-MIN OFF-MIN UseEquation12orFigure25tocalculatetheresistancetoobtainadesiredfrequencyofoperation. F >kHz@ 31000(cid:152)R (cid:16)0.9>k:@ SW FRQ (12) 1800 1600 1400 z) H 1200 k Y ( 1000 C N E 800 U Q E 600 R F 400 200 0 0 20 40 60 80 100 120 140 160 180 RFRQ (k:) Figure25. ExternalResistorSelectiontoSet theSwitchingFrequency 9.2.2.6 FilterInductor A general recommendation for the filter inductor in an LM21305 application is to keep a peak-to-peak ripple current between 25% and 50% of the maximum load current of 5 A. The filter inductor must have a sufficiently high saturation current rating and a DCR as low as possible. Calculate the peak-to-peak inductor current ripple currentfromEquation13: V (cid:152)(cid:11)1(cid:16)D(cid:12) ’I OUT L F (cid:152)L SW (13) SelecttheinductanceasshownbyEquation14: V (cid:152)(cid:11)1(cid:16)D(cid:12) V (cid:152)(cid:11)1(cid:16)D(cid:12) OUT dL d OUT F (cid:152)0.5(cid:152)I F (cid:152)0.25(cid:152)I SW OUT(max) SW OUT(max) (14) The peak inductor current at full load corresponds to the maximum output current plus the ripple current, as showninEquation15: ’I I I (cid:14) L(max) L(max) OUT(max) 2 (15) Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Choose an inductor with a saturation current rating at maximum operating temperature that is higher than the overcurrent protection limit. In general, having lower inductance is desirable in switching power supplies because lower inductance equates to faster transient response, lower DCR, and reduced size for more compact designs. However, too low of an inductance implies large inductor ripple current such that OCP is falsely triggered at the fullload.Largerinductorripplecurrentalsoimplieshigheroutputvoltageripple. When the inductance is determined, choose the type of inductor to meet the application requirements. Ferrite designs have very low core losses and are preferred at high switching frequencies, thus design goals can then concentrate on copper loss and preventing saturation. However, ferrite core material saturates hard, meaning that inductance collapses abruptly when the saturation current is exceeded. The hard saturation results in an largeincreaseininductorripplecurrentandoutputvoltageripple.Donotallowthecoretosaturate! 9.2.2.7 OutputCapacitor The LM21305 is designed to function with a wide variety of LC filters. Using as little output capacitance as possible is generally desirable to keep cost and size down. Choose the output capacitor, C , carefully because OUT it directly affects the steady-state output voltage ripple, loop stability, and the voltage overshoot and undershoot duringaloadtransient. The output voltage ripple is essentially composed of two parts, resistive and capacitive. More specifically, the inductor ripple current flowing through the equivalent series resistance (ESR) of the output capacitors gives a resistivecomponentasgivenbyEquation16: ’V ’I (cid:152)R OUT(cid:16)ESR L ESR (16) Also, consider the inductor ripple current charging and discharging the output capacitors, producing a capacitive ripplevoltagecomponentgivenbyEquation17: ’I ’V L OUT(cid:16)C 8(cid:152)F (cid:152)C SW OUT (17) Figure 26 shows an illustration of the two ripple components. The actual peak-to-peak voltage ripple is smaller thanthesumofthetwopeaksbecausethetworipplecomponentsarenotinphase.Thecumulativeoutputripple isgivenbyEquation18: § 1 •2 ’V ’I R 2 (cid:14)¤ ‚ OUT L ESR '8(cid:152)F (cid:152)C „ SW OUT (18) I L ßI L time ßV287¯(65 time ßV OUT¯C time Figure26. InductorCurrentandTwoComponentsofOutputVoltageRipple 22 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Output capacitance is usually limited by system transient performance specifications if the system requires tight voltage regulation with the presence of large current steps and fast slew rates. When a fast or large load transient occurs, output capacitors provide the required charge before the inductor current slews to the appropriate level. The initial output voltage deviation is equal to the load current step multiplied by ESR. V OUT continues to droop until the control loop response increases the inductor current to supply the load. To maintain a small overshoot or undershoot during a load transient, small ESR and large capacitance are desired. However, these factors also come with the penalty of higher cost and size. Thus, the motivation is to seek a fast control loopresponsetoreducetheoutputvoltagedeviation. One or more ceramic capacitors are generally recommended because these capacitors have very low ESR and remain capacitive up to high frequencies. Choose an X5R or X7R capacitor dielectric to maintain proper tolerance. Other types of capacitors (such as tantalum, POSCAP, and OSCON) are used if bulk energy storage is required. Such electrolytic capacitors have lower ESR zero frequency (relative to ceramic capacitors) that can influence the control loop, particularly if the zero frequency is close to the desired crossover target. If high switching frequency and high loop crossover frequency are warranted, an all-ceramic capacitor design is often moreappealing. 9.2.2.8 EfficiencyConsiderations The efficiency of a switching regulator is defined as the output power divided by the input power times 100%. EfficiencyisalsofoundbyusingEquation19: P K 1(cid:16) DISS P IN (19) Analyzing individual losses is often useful to determine what is limiting the efficiency and what change can produce the most improvement. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LM21305-based converters: 1) conduction losses; 2) switching and gate drive losses; and 3) bias losses. Conduction losses are the I2R losses in parasitic resistances including MOSFET on-state resistances R , equivalent inductor dc resistance R , and PCB trace resistances R . DSon DCR TRACE ApproximatetheconductionlossusingEquation20: P I 2(cid:11)D(cid:152)R (cid:14)(cid:11)1(cid:16)D(cid:12)(cid:152)R (cid:14)R (cid:14)R (cid:12) COND OUT DSonHS DSonLS DCR TRACE (20) Lower the total conduction loss by reducing these parasitic resistances. For example, the LM21305 is designed to have low R internal MOSFET switches. Keep the inductor DCR low, and ensure that the traces that DSon conductthecurrentarewide,thick,andasshortaspossible.Obviously,conductionlossesincreasinglyaffectthe efficiencyatheavierloads.RMScurrentsthroughtheinputandoutputcapacitorESRalsogenerateloss. Switching losses include all the dissipation caused by the switching action of the two power MOSFETs. Each time the switch node swings from low to high or vice versa, charges are applied or removed from the parasitic capacitance from the SW node to GND. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge moves from 5V0 to ground. Furthermore, each time a power MOSFET is turned on or off,atransitionlossisgeneratedrelatedtotheoverlapofvoltageandcurrent.Thelow-sideMOSFETbodydiode generates reverse recovery loss and dead-time conduction loss. All of these losses must be evaluated and carefully considered to design a high-efficiency switching power converter. Because these losses only occur during switching, reducing the switching frequency always helps reduce the switching loss and the resultant improvementinefficiencyismorepronouncedatlighterload. The current drawn from AVIN is equivalent to I and the associated power loss is V × I because the DRIVE AVIN DRIVE 5V0 rail is an LDO output from AVIN. The other portion of AVIN power loss is the bias current through the 2V5 rail that equals V × I . Powering AVIN from a 5-V system rail provides an optimal tradeoff between bias AVIN BIAS powerlossandswitchingloss. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 9.2.2.9 LoadCurrentDeratingWhenDutyCycleExceeds50% The LM21305 is optimized for lower duty cycle operation (for example, high input-to-output voltage ratio). The high-side MOSFET is designed to be half the size of the low-side MOSFET, thus optimizing the relative levels of switching loss in the high-side switch and the conduction loss in the low-side switch. The continuous current rating of the low-side switch is the maximum load current of 5 A, whereas the high-side MOSFET is rated at 2.5 A. If the LM21305 is operating with duty cycles higher than 50%, the maximum output current must be derated, asshowninEquation21. I 5(cid:152)Min“(cid:11)1.5(cid:16)D(cid:12),1” OUT(max) ‹ … (21) DeratingofthemaximumloadcurrentwhenD >50%isalsoshowninFigure27. IOUT-MAX 5.0A 2.5A 0 50% 100% D Figure27. LM21305MaximumLoadCurrentDeratingwhenD >50% 9.2.2.10 ControlLoopCompensation This section does not provide a rigorous analysis of current-mode control, but rather a simplified yet relatively accurate method to determine the control loop compensation network. The LM21305 employs a peak current- mode controller and, therefore, the control loop block diagram representation involves two feedback loops, as showninFigure28. VREF + VC(s) + VOUT(s) Fcomp(s) - - Compensator Fp(s) x Fh(s) Power Stage Loop T(s) H(s) Feedback Figure28. ControlBlockDiagramofaPeakCurrent-ModeControlledBuckConverter 24 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 The inner feedback loop derives its feedback from the sensed inductor current and the outer loop monitors the output voltage. The LM21305 compensation components installed from COMP to AGND are shown in Figure 29. The purpose of the compensator block is to stabilize the control loop and achieve high performance in terms of loadtransientresponse,audiosusceptibility,andoutputimpedance.TheLM21305typicallyrequiresonlyasingle resistor R and capacitor C for compensation. However, depending on the location of the power stage ESR C C1 zero,asecond(small)capacitor,C ,mayberequiredtocreateahigh-frequencypole. C2 LM21305 COMP RC CC1 Figure29. LM21305CompensationNetwork The overall loop transfer function is a product of the power stage transfer function, internal amplifier gains and thefeedbacknetworktransferfunctionandisexpressedbyEquation22: T(cid:11)s(cid:12) Gain (cid:152)F (cid:11)s(cid:12)(cid:152)F (cid:11)s(cid:12)(cid:152)F (cid:11)s(cid:12) 0 p h comp where • Gain includesallthedcgainsintheloop, 0 • F (s)representsthepowerstagepoleandzero(includingtheinnercurrentloop), p • F (s)representsthesamplingeffectinsuchacurrent-modeconverter,and h • F (s)isthecompensationnetworkimpedance (22) comp Figure30showsanasymptoticapproximationplotoftheloopgain. Gain 0 sC C1 F /2 SW 0 dB fzcomp fp f C f ESR = f pcomp Figure30. LM21305LoopGainAsymptoticApproximation The loop gain determines both static and dynamic performance of the converter. The power stage response is fixed by the selection of the power components and the compensator is therefore designed around the power stageresponsetoachievethedesiredloopresponse.Thegoalistodesignacontrolloopcharacteristicwithhigh crossoverfrequency(orloopbandwidth)andadequategainandphasemarginsunderalloperationconditions. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 9.2.2.11 CompensationComponentsSelection To select the compensation components, a desired crossover frequency must be selected. Select f equal to or C lowerthan1/6oftheswitchingfrequency.TheeffectofF (s)canbeignoredtosimplifythedesign.Thecapacitor h ESR zero is also assumed to be at least three times higher than f . Calculate the compensation resistor using C Equation23: 1 f V R (cid:152) C 302(cid:152) OUT (cid:152)f (cid:152)C C Gain f V C OUT 0 P FB (23) C does not affect the crossover frequency f , but sets the compensator zero f and affects the phase C1 C Zcomp margin of the loop. For a fast design, C = 4.7 nF gives adequate performance in most LM21305 applications. C1 Higher C capacitance gives higher phase margin but at the expense of longer transient response settling time. C1 Setthecompensationzeronohigherthanf /3toensureenoughphasemargin,asimpliedbyEquation24: C 3 C C1 2(cid:152)S(cid:152)R (cid:152)f C C (24) 9.2.2.12 PlottingtheLoopGain To include the effect of F (s) and the ESR zero, plot the complete loop gain using a software tool (such as h MATLAB, Mathcad, or Excel). Determine the loop gain constituents as follows. First, calculate the dc gain of the powerstageusingEquation25: V R Gain 0.021(cid:152) OUT (cid:152) OUT 0 V R FB 1(cid:14) OUT (cid:152)(cid:11)m Dc(cid:16)0.5(cid:12) F (cid:152)L C SW (25) wherem fortheLM21305isgivenbyEquation26: C 4(cid:152)F (cid:152)L m 1(cid:14) SW C V (cid:16)V IN OUT (26) andD'=1 −D.UsetheminimumR inthecalculationofR =V /I . OUT OUT OUT OUT F (s)isexpressedusingEquation27: p 1(cid:14)s (cid:11)2(cid:152)S(cid:152)f (cid:12) F (cid:11)s(cid:12) ESR P 1(cid:14)s (cid:11)2(cid:152)S(cid:152)f (cid:12) P (27) where the power stage pole (including slope compensation effect) and ESR zero frequencies are given respectivelybyEquation28andEquation29: 1 § 1 1 • f ¤ (cid:14) (cid:11)m (cid:152)Dc(cid:16)0.5(cid:12)‚ P 2(cid:152)S(cid:152)C R F (cid:152)L C ' „ OUT OUT SW (28) 1 f ESR 2(cid:152)S(cid:152)C (cid:152)R OUT ESR (29) ThehighfrequencybehaviorF (s)isexpressedbyEquation30: h 1 F (cid:11)s(cid:12) h s s2 1(cid:14) (cid:14) Z (cid:152)Q Z 2 n P n (30) wheretherelevantfrequencyandqualityfactoraregivenbyEquation31 Z S(cid:152)F n SW 1 Q P S(cid:152)(cid:11)m (cid:152)Dc(cid:16)0.5(cid:12) C (31) 26 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 ThecompensationnetworkimpedanceisgiveninEquation32: 1 F (cid:11)s(cid:12) R (cid:14) COMP C s(cid:152)C C1 (32) Using the above equations, it becomes an easy task to plot the loop gain T(s) and determine the loop performancemetrics,suchascrossoverfrequencyandphasemargin. 9.2.2.13 HighFrequencyConsiderations F (s) represents the additional magnitude and phase drop around F / 2 caused by the switching behavior of h SW the current-mode converter. F (s) contains a pair of double poles with quality factor Q at half of the switching h p frequency. Good practice is to check that Q is between 0.15 and 2, ideally around 0.6. If Q is too high, the p p resonant peaking at F / 2 can become severe and coincide with sub-harmonic oscillations in the duty cycle SW and inductor current. If Q is too low, the two complex poles split, the converter begins to function as a voltage- p modecontrolledconverter,andthecompensationschemeusedabovemustbeadjusted. Inatypicalconverterdesignwithceramicoutputcapacitors,theESRzerofrequency,f ,istypicallythreetimes ESR higher than the desired crossover frequency f . If f is lower than F / 2, add a capacitor C between COMP C ESR SW C2 andAGNDtogiveahigh-frequencypole,asshowninEquation33: 1 C C2 2(cid:152)S(cid:152)R (cid:152)f C ESR (33) Select C much smaller than C to avoid affecting the compensation zero. The high-frequency pole also C2 C1 provideshigh-frequencynoiseattenuationatCOMP. 9.2.2.14 BootstrapCapacitor Use a capacitor between CBOOT and SW to supply the gate drive charge when the high-side MOSFET is turning on. Ensure that the capacitor is large enough to supply the charge without significant voltage drop. A 0.1- µFceramicbootstrapcapacitorisrecommendedinLM21305applications. 9.2.2.15 5V0and2V5Capacitors The 5V0 and 2V5 pins are internal bias rail LDO outputs. As previously mentioned, the two LDOs are used for internal circuits only and must not be substantially loaded. Output capacitors are needed to stabilize the LDOs. Ceramiccapacitorswithinaspecifiedrangemustbeusedtomeetstabilityrequirements.ChooseanX5RorX7R dielectric rated for the required operating temperature range. Use Table 2 to choose a suitable LDO output capacitor. Table2.BiasRailLDOCapacitance CAPACITOR(RecommendedCapacitance,Dielectric, RAIL NOMINALVOLTAGE MinimumVoltageRating) 5V0 4.88V 1µF±20%,X7R,16V 2V5 2.47V 0.1µF±20%,X7R,10V Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 9.2.2.16 MaximumAmbientTemperature As with any power conversion device, the LM21305 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature, T , is a function of the ambient temperature, T , the power dissipation and the effective thermal J A resistance, R , of the device and PCB combination. The maximum internal die temperature for the LM21305 is θJA 125°C, thus establishing a limit on the maximum device power dissipation and therefore the load current at high ambienttemperatures.Equation34showstherelationshipsbetweentheseparameters. (cid:11) (cid:12) T (cid:16)T K 1 I J A (cid:152) (cid:152) OUT (cid:11) (cid:12) R 1(cid:16)K V TJA OUT (34) High ambient temperatures and large values of R reduce the maximum available output current. If the junction θJA temperature exceeds 160°C, the LM21305 cycles in and out of thermal shutdown. If thermal shutdown occurs, then this shutdown is a sign of inadequate heat-sinking or excessive power dissipation in the device. Improve PCBheat-sinkingbyusingmorethermalvias,alargerboard,ormoreheat-spreadinglayerswithinthatboard. As stated in application note Semiconductor and IC Package Thermal Metrics, SPRA953, the values given in the Thermal Information table are not valid for design purposes to estimate the thermal performance of the application. The values reported in the Thermal Information table are measured under a specific set of conditions thatareseldomobtainedinanactualapplication.TheeffectiveR isacriticalparameteranddependsonmany θJA factors (such as power dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias underthepackage,airflow,andadjacentcomponentplacement).TheLM21305usesanadvancedpackagewith a heat-spreading pad (DAP) on the bottom. This pad must be soldered directly to the PCB copper ground plane to provide an effective heat-sink, as well as a proper electrical connection. Use the resources listed in Resources for Thermal PCB Design as a guide to optimal thermal PCB design and estimating R for a given application θJA environment. 28 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 9.2.3 ApplicationCurves For additional details on the wavefroms shown in this section, see AN-2175 LM21305 POL Demonstration ModuleandReferenceDesign,SNVA497. VIN 2V/DIV VIN 2V/DIV IOUT 1A/DIV VOUT VOUT 0.5V/DIV 0.5V/DIV PGOOD PGOOD 1V/DIV 1V/DIV 1 ms/DIV 1 ms/DIV VIN=12V,VOUT=1.8V NoLoad VIN=12V,VOUT=1.8V IOUT=5-AResistiveLoad Figure31.Startup Figure32.Startup EN 1V/DIV VOUT 20 mV/DIV VOUT PGOOD 0.5V/DIV 1V/DIV 0.9V 1 ms/DIV 1 Ps/DIV VIN=12V,VOUT=1.8V NoLoad VIN=12V,VOUT=1.8V IOUT=0.5-Ato5-ALoad (Pre-Biasedto0.9V) Figure33.EnableON Figure34.OutputRippleWaveform IOUT 1A/DIV 5A VOUT 50 mV/DIV IOUT 1A/DIV VOUT 3.75A 50 mV/DIV 1.8V 1.8V 1.25A 0.5A 40 Ps/DIV 40 Ps/DIV VIN=12V,VOUT=1.8V IOUT=0.5-Ato5-ALoad VIN=12V,VOUT=1.8V IOUT=1.25-Ato3.75-ALoad Figure35.LoadTransientResponse Figure36.LoadTransientResponse Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 10 Power Supply Recommendations The LM21305 converter is designed to operate from an input voltage supply range between 3 V and 18 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current totheloadedregulator.EstimatetheaverageinputcurrentwithEquation35. V (cid:152)I I OUT OUT IN V (cid:152)K IN where • ηistheefficiency (35) If the regulator is connected to the input supply through long wires or PCB traces with large impedance, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse affect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input capacitors, can form an under-damped resonant circuit. This circuit can cause overvoltage transients at the PVIN pin each time the input supply is cycled on and off. The parasitic resistance causes the PVIN voltage to dip when the load on the regulator is switched on or exhibits a transient. If the regulator is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset. The best way to solve these types of issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to hold the input voltage steady during largeloadtransients. Sometimes an EMI input filter is used in front of the regulator, which can lead to instability as well as some of the effects mentioned previously, unless carefully designed. The user guide Simple Success with Conducted EMI for DC-DC Converters, SNVA489, provides helpful suggestions when designing an input filter for any switching regulator. 30 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 11 Layout 11.1 Layout Guidelines PC board layout is an important and critical part of any dc-dc converter design. The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Poor layout disrupts the performance of a dc-dc converter and surrounding circuitry by contributing to EMI, ground bounce, resistive voltage loss in the traces, and thermal problems. Erroneous signals can reach the dc-dc converter, possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade thepower-supplyperformance. The following guidelines serve to help users to design a PCB with the best power conversion performance, thermalperformance,andminimizedgenerationofunwantedEMI. 1. LocatetheinputcapacitorsascloseaspossibletothePVINandPGNDpins,andplacetheinductorasclose aspossibletotheSWpinsandoutputcapacitors.Thisplacementistominimizetheareaofswitchingcurrent loops and reduce the resistive loss of the high current path. Based on the LM21305 pinout, place a 1-µF to 10-µF ceramic capacitor right by pins 1, 2, and 7, across the SW node trace, as an addition to the bulk input capacitors. Using a size 1206 or 1210 capacitor allows enough copper width for the SW node to be routed underneath the capacitor for good conduction (see the LM21305 evaluation board layout detailed in applicationnoteAN-2042LM21305EvaluationBoard,SNVA432). 2. Keep the SW node area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, minimize the total area of this node to help mitigate radiated EMI. Place theinductorascloseaspossibletotheSWpins. 3. Use a solid ground plane on layer two of the PCB, particularly underneath the LM21305 and power stage components.Thisplanefunctionsasanoiseshieldandalsoasaheatdissipationpath. 4. Make input and output power bus connections as wide and short as possible to reduce any voltage drops on the input or output of the converter and to improve efficiency. Use copper planes on top to connect the multiplePVINpinsandPGNDpinstogether. 5. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section, use enough copper area to ensure a low R commensurate with the maximum load current and ambient θJA temperature. Make the top and bottom PCB layers with two ounce copper and no less than one ounce. Use an array of heat-sinking vias to connect the exposed pad (DAP) to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers (recommended), connect these thermal vias to the inner layer heat-spreadinggroundplanes. 6. Route the feedback trace from VOUT to the feedback divider resistors away from the SW pin and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important when high resistances are used to set the output voltage. Routing the feedback trace on a different layer than the inductor and SW node trace is recommended such that a ground plane exists between the feedback trace andinductororSWnodepolygontoprovidefurthercancellationofEMIonthefeedbacktrace. 7. If voltage accuracy at the load is important, ensure that the feedback voltage sense is made directly at the loadterminals.DoingsocorrectsforvoltagedropsinthePCBplanesandtracesandprovidesoptimaloutput voltage setpoint accuracy and load regulation. Placing the resistor divider closer to the FB node, rather than close to the load, is always better because the FB node is the input to the error amplifier and is thus noise sensitive. COMP is a noise-sensitive node and the compensation components must be located as close as possibletothedevice. 8. Use short, low-inductance traces for the C capacitor. Locate C as close as possible to the CBOOT BOOT BOOT andSWpins. 9. Placethebypasscapacitorsforthe5V0and2V5railsclosetotheirrespectivepins. 10. PlacethefrequencysetresistoranditsassociatedcapacitorclosetotheFREQpin. 11. SeePCBLayoutResourcesforadditionalguidelines. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com Layout Guidelines (continued) 11.1.1 CompactPCBLayoutforEMIReduction Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimizeradiatedEMIistoidentifythepulsingcurrentpathandminimizetheareaofthatpath. The main switching loop of the LM21305 power stage is denoted by #1 in Figure 37. The topological architecture of a buck converter means that particularly high di/dt current flows in loop #1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing its effective loop area. For loop #2 however, the di/dt through inductor L and capacitor C is naturally limited by the inductor. Keeping the area of loop #2 small is F OUT not nearly as important as that of loop #1. Also important are the gate drive loops of the low-side and high-side MOSFETs, which are inherently tight by virtue of the integrated power MOSFETs and gate drivers of the LM21305. V IN PVIN C LM21305 IN High di/dt High-side Q1 loop MOSFET L F gate driver SW VOUT #1 C OUT #2 Low-side Q 2 MOSFET gate driver PGND GND Figure37. DC-DCBuckRegulatorwithPowerStageCircuitSwitchingLoops High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitors as close as possible to the PVIN and PGND pins is the key to EMI reduction. Keep the SW trace connecting to the inductor as short as possible, and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. Place the output capacitors close to the V side of the OUT inductorandroutethereturnusingGNDplanecopperbacktotheLM21305PGNDpinandexposedPAD. 11.1.2 GroundPlaneandThermalDesignConsiderations As mentioned previously, using one of the middle layers as a solid ground plane is recommended. A ground plane provides shielding for sensitive circuits and traces. This plane also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. The PGND pins are connected to the source of the internal low-side power MOSFET. Connect these pins directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce because of load variations. The PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much lessnoiseandcanbeusedforsensitiveroutes. 32 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 Layout Guidelines (continued) Provide adequate device heat-sinking by using the exposed pad (DAP) of the LM21305 as the primary thermal path. Use a minimum 4-by-4 array of 10 mil thermal vias to connect the DAP to the system ground plane for heat-sinking. Evenly distribute the vias under the DAP. Use as much copper as possible for system ground plane on the top and bottom layers for best heat dissipation. A four-layer board with copper thickness, starting from the top, of 2 oz, 1 oz, 1 oz, 2 oz and with proper layout provides low impedance, proper shielding, and low thermal resistance.SeeResourcesforThermalPCBDesign foradditionalthermaldesignguidelines. 11.2 Layout Example Figure38andFigure39showanexampleofanLM21305PCBlayout.Onlythetopandbottomlayercopperand top silkscreen are shown. For more details, see application note AN-2175 LM21305 POL Demonstration Module andReferenceDesign,SNVA497. Figure38. PCBTopLayerCopperandSilkscreen Figure39. PCBBottomLayerCopperandSilkscreen Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM21305

LM21305 SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 DevelopmentSupport • LM21305QuickstartDesignTool • PowerLab™ • WEBENCH®DesignCenter 12.2 Documentation Support 12.2.1 RelatedDocumentation • AN-2042LM21305EvaluationBoard,SNVA432 • AN-2175LM21305POLDemonstrationModuleandReferenceDesign,SNVA497 • AN-2162SimpleSuccesswithConductedEMIfromDC-DCConverters,SNVA489 • AN-1187LeadlessLeadframePackage(LLP),SNOA401 • UsingNewThermalMetricsApplicationReport,SBVA025 • 6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current, SNVS822 • SemiconductorandICPackageThermalMetrics,SPRA953 12.2.2 PCBLayoutResources • AN-1149LayoutGuidelinesforSwitchingPowerSupplies,SNVA021 • AN-1229SimpleSwitcherPCBLayoutGuidelines,SNVA054 • ConstructingYourPowerSupply– LayoutConsiderations,SLUP230 • LowRadiatedEMILayoutMadeSIMPLEwithLM4360xandLM4600x,SNVA721 12.2.3 ResourcesforThermalPCBDesign • AN-2020ThermalDesignByInsight,NotHindsight,SNVA419 • AN-1520AGuidetoBoardLayoutforBestThermalResistanceforExposedPadPackages,SNVA183 • SPRA953BSemiconductorandICPackageThermalMetrics,SPRA953 • SNVA719ThermalDesignmadeSimplewithLM43603andLM43602,SNVA719 • SLMA002 PowerPAD™ThermallyEnhancedPackage,SLMA002 • SLMA004PowerPADMadeEasy,SLMA004 • SBVA025UsingNewThermalMetrics,SBVA025 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 34 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:LM21305

LM21305 www.ti.com SNVS639G–DECEMBER2009–REVISEDDECEMBER2015 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:LM21305

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LM21305SQ/NOPB ACTIVE WQFN RSG 28 1000 Green (RoHS SN Level-2A-260C-4 -40 to 85 21305SQ & no Sb/Br) WEEK LM21305SQE/NOPB ACTIVE WQFN RSG 28 250 Green (RoHS SN Level-2A-260C-4 -40 to 85 21305SQ & no Sb/Br) WEEK LM21305SQX/NOPB ACTIVE WQFN RSG 28 4500 Green (RoHS SN Level-2A-260C-4 -40 to 85 21305SQ & no Sb/Br) WEEK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LM21305SQ/NOPB WQFN RSG 28 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM21305SQE/NOPB WQFN RSG 28 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM21305SQX/NOPB WQFN RSG 28 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LM21305SQ/NOPB WQFN RSG 28 1000 210.0 185.0 35.0 LM21305SQE/NOPB WQFN RSG 28 250 213.0 191.0 55.0 LM21305SQX/NOPB WQFN RSG 28 4500 367.0 367.0 35.0 PackMaterials-Page2

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