LIS35DE MEMS motion sensor 3-axis - ±2g/±8g smart digital output “piccolo” accelerometer Feature ■ 2.16 V to 3.6 V supply voltage ■ 1.8V compatible IOs ■ < 1 mW power consumption ■ ±2g/±8g dynamically selectable full-scale ■ I2C/SPI digital output interface LGA14 (3x5x0.9mm) ■ Programmable multiple interrupt generator ■ Click and double click recognition process developed by ST to produce inertial sensors and actuators in silicon. ■ Embedded high pass filter The IC interface is manufactured using a CMOS ■ 10000g high shock survivability process that allows to design a dedicated circuit ■ ECOPACK® RoHS and “Green” compliant which is trimmed to better match the sensing (see Section8) element characteristics. The LIS35DE has dynamically user selectable full Applications scales of ±2g/±8g and it is capable of measuring ■ Free-fall detection accelerations with an output data rate of 100 Hz or 400 Hz. ■ Motion activated functions The device may be configured to generate inertial ■ Gaming and virtual reality input devices wake-up/free-fall interrupt signals when a ■ Vibration monitoring and compensation programmable acceleration threshold is crossed at least in one of the three axes. Thresholds and Description timing of interrupt generators are programmable by the end user on the fly. The LIS35DE is an ultra compact low-power three The LIS35DE is available in plastic Thin Land axis linear accelerometer. It includes a sensing Grid Array package (TGA) and it is designed to element and an IC interface able to provide the operate over an extended temperature range from measured acceleration to the external world through I2C/SPI serial interface. -40°C to +85°C. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated Table 1. Device summary Order code Temp range, °C Package Packing LIS35DE -40 to +85 LGA14 Tray LIS35DETR -40 to +85 LGA14 Tape and reel April 2009 Doc ID 15594 Rev 1 1/39 www.st.com 39

Contents LIS35DE Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.3 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/39 Doc ID 15594 Rev 1

LIS35DE Contents 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 25 7.4 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.11 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.12 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.13 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.14 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.15 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.16 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.17 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.18 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.19 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.20 CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.21 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.22 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.23 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 15594 Rev 1 3/39

List of tables LIS35DE List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Mechanical characteristics @ Vdd=2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Electrical characteristics @ Vdd=2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 18 Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18 Table 15. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18 Table 16. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 18. CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 20. CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 21. High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 22. CTRL_REG3 [interrupt CTRL register] (22h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 23. CTRL_REG3 [interrupt CTRL register] (22h) register description . . . . . . . . . . . . . . . . . . . 26 Table 24. Data signal on Int pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 25. STATUS_REG (27h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 26. STATUS_REG (27h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 27. OUT_X (29h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 28. OUT_Y (2Bh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 29. OUT_Z (2Dh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 30. FF_WU_CFG_1 (30h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 31. FF_WU_CFG_1 (30h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 32. FF_WU_SRC_1 (31h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 33. FF_WU_SRC_1 (31h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 34. FF_WU_THS_1 (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 35. FF_WU_THS_1 (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 36. FF_WU_DURATION_1 (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 37. FF_WU_DURATION_1 (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 38. FF_WU_CFG_2 (34h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 39. FF_WU_CFG_2 (34h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 40. FF_WU_SRC_2 (35h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 41. FF_WU_SRC_2 (35h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 42. FF_WU_THS_2 (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 43. FF_WU_THS_2 (36h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 44. FF_WU_DURATION_2 (37h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 45. FF_WU_DURATION_2 (37h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 46. CLICK_CFG (38h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 47. CLICK_CFG (38h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 48. Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 49. CLICK_SRC (39h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4/39 Doc ID 15594 Rev 1

LIS35DE List of tables Table 50. CLICK_SRC (39h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 51. CLICK_THSY_X (3Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 52. CLICK_THSY_X (3Bh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 53. CLICK_THSZ (3Ch) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 54. CLICK_THSZ (3Ch) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 55. CLICK_TimeLimit (3Dh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 56. CLICK_Latency (3Eh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 57. CLICK_Window (3Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 15594 Rev 1 5/39

List of figures LIS35DE List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. LIS35DE electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Multiple bytes SPI Read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Multiple bytes SPI Write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. LGA14: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6/39 Doc ID 15594 Rev 1

LIS35DE Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram X+ Y+ CHARGE Z+ AMPLIFIER CS a A/D I2C SCL/SPC MUX CONVERTER CONTROL LOGIC SDA/SDO/SDI Z- SPI SDO Y- X- CONTROL LOGIC INT 1 TRIMMING REFERENCE CLOCK & CIRCUITS INTERRUPT GEN. INT 2 1.2 Pin description Figure 2. Pin connection Z 1 6 1 Y X 13 6 8 13 8 TOP VIEW BOTTOM VIEW Doc ID 15594 Rev 1 7/39

Block diagram and pin description LIS35DE T able 2. Pin description Pin# Name Function 1 Vdd_IO Power supply for I/O pins 2 GND 0V supply 3 Reserved Connect to Vdd 4 GND 0V supply 5 GND 0V supply 6 Vdd Power supply SPI enable 7 CS I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) 8 INT 1 Inertial interrupt 1 9 INT 2 Inertial interrupt 2 10 GND 0V supply 11 Reserved Connect to Gnd SPI serial data output 12 SDO I2C less significant bit of the device address SDA I2C serial data (SDA) 13 SDI SPI serial data input (SDI) SDO 3-wire interface serial data output (SDO) SCL I2C serial clock (SCL) 14 SPC SPI serial port clock (SPC) 8/39 Doc ID 15594 Rev 1

LIS35DE Mechanical and electrical specifications 2 Mechanical and electrical specifications 2.1 Mechanical characteristics T = 25°C unless otherwise noted Table 3. Mechanical characteristics @ Vdd=2.5 V(1) Symbol Parameter Test conditions Min. Typ.(2) Max. Unit FS bit set to 0(3) ±2.0 ±2.3 FS Measurement range g FS bit set to 1 ±9.2 Dres Device resolution FS bit set to 0 72 mg FS bit set to 0 15 18 21 So Sensitivity mg/digit FS bit set to 1 61 72 83 Sensitivity change vs TCSO FS bit set to 0 ±0.01 %/°C temperature Typical zero-g level offset FS bit set to 0 ±60 mg TyOff accuracy(4) FS bit set to 1 ±80 mg Zero-g level change vs TCOff Max delta from 25°C ±0.5 mg/°C temperature BW System bandwidth(5) ODR/2 Hz Top Operating temperature range -40 +85 °C Wh Product weight 20 mgram 1. The product is factory calibrated at 2.5 V. The device can be used from 2.16 V to 3.6 V. 2. Typical specifications are not guaranteed. 3. Verified by wafer level test and measurement of initial offset and sensitivity. 4. Typical zero-g level offset value after MSL3 preconditioning. 5. ODR is output data rate. Refer to Table4 for specifications. Doc ID 15594 Rev 1 9/39

Mechanical and electrical specifications LIS35DE 2.2 Electrical characteristics T = 25°C unless otherwise noted Table 4. Electrical characteristics @ Vdd=2.5 V (1) Symbol Parameter Test conditions Min. Typ.(2) Max. Unit Vdd Supply voltage 2.16 2.5 3.6 V Vdd_IO I/O pins supply voltage(3) 1.71 Vdd+0.1 V Idd Supply current T = 25°C, ODR=100 Hz 0.3 0.45 mA Current consumption in IddPdn T = 25°C 1 5 µA power-down mode Digital high level input 0.8*Vdd VIH V voltage _IO 0.2*Vdd VIL Digital low level input voltage V _IO 0.9*Vdd VOH High level output voltage V _IO 0.1*Vdd VOL Low level output voltage V _IO DR=0 100 ODR Output data rate Hz DR=1 400 BW System bandwidth(4) ODR/2 Hz Ton Turn-on time(5) 3/ODR s Top Operating temperature range -40 +85 °C 1. The product is factory calibrated at 2.5V. The device can be used from 2.16 V to 3.6 V. 2. Typical specification are not guaranteed. 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Filter cut-off frequency. 5. Time to obtain valid data after exiting power-down mode. 10/39 Doc ID 15594 Rev 1

LIS35DE Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Value (1) Symbol Parameter Unit Min. Max. tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 5 th(CS) CS hold time 8 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 ns tv(SO) SDO valid output time 50 th(SO) SDO output hold time 6 tdis(SO) SDO output disable time 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI slave timing diagram (a) CS (3) (3) tsu(CS) tc(SPC) th(CS) SPC (3) (3) t t su(SI) h(SI) SDI (3) MSB IN LSB IN (3) tv(SO) th(SO) tdis(SO) SDO (3) MSB OUT LSB OUT (3) 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors a. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port Doc ID 15594 Rev 1 11/39

Mechanical and electrical specifications LIS35DE 2.3.2 I2C - Inter IC control interface Subject to general operating conditions for Vdd and top. Table 6. I2C slave timing values I2C standard mode (1) I2C fast mode (1) Symbol Parameter Unit Min Max Min Max f(SCL) SCL clock frequency 0 100 0 400 KHz tw(SCLL) SCL clock low time 4.7 1.3 µs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0.01 3.45 0.01 0.9 µs tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb (2) 300 ns tf(SDA) tf(SCL) SDA and SCL fall time 300 20 + 0.1Cb (2) 300 th(ST) START condition hold time 4 0.6 Repeated START condition tsu(SR) setup time 4.7 0.6 µs tsu(SP) STOP condition setup time 4 0.6 Bus free time between STOP tw(SP:SR) and START condition 4.7 1.3 1. Data based on standard I2C protocol requirement, not tested in production 2. Cb = total capacitance of one bus line, in pF Figure 4. I2C Slave timing diagram (b) REPEATED START START t su(SR) SDA tw(SP:SR) START tf(SDA) tr(SDA) tsu(SDA) th(SDA) t STOP su(SP) SCL t t t t t h(ST) w(SCLL) w(SCLH) r(SCL) f(SCL) b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port 12/39 Doc ID 15594 Rev 1

LIS35DE Mechanical and electrical specifications 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. T able 7. Absolute maximum ratings Symbol Ratings Maximum value Unit Vdd Supply voltage -0.3 to 6 V Vdd_IO I/O pins supply voltage -0.3 to 6 V Input voltage on any control pin Vin -0.3 to Vdd_IO +0.3 V (CS, SCL/SPC, SDA/SDI/SDO) 3000g for 0.5 ms A Acceleration (any axis, powered, Vdd=2.5V) POW 10000g for 0.1 ms 3000g for 0.5 ms A Acceleration (any axis, unpowered) UNP 10000g for 0.1 ms T Operating temperature range -40 to +85 °C OP T Storage temperature range -40 to +125 °C STG 4 (HBM) kV ESD Electrostatic discharge protection 1.5 (CDM) kV 200 (MM) V Note: Supply voltage on any pin should never exceed 6.0 V This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part Doc ID 15594 Rev 1 13/39

Mechanical and electrical specifications LIS35DE 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensor. 2.5.2 Zero-g level Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors. 2.5.3 Click and double click recognition The click and double click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction. If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pin (INT1 and/or INT2). A more advanced feature allows to generate and interrupt request when a “double click” with programmable time between the two events enabling a “mouse button like” use. This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli. 14/39 Doc ID 15594 Rev 1

LIS35DE Functionality 3 Functionality The LIS35DE is a ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface. 3.1 Sensing element A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in fF range. 3.2 IC interface The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by analog-to-digital converters. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS35DE features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS35DE may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins. 3.3 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows the user to use the device without further calibration. Doc ID 15594 Rev 1 15/39

Application hints LIS35DE 4 Application hints Figure 5. LIS35DE electrical connection Vdd Vdd_IO 6 1 Z 1 Y X 13 10uF 6 Top VIEW 8 100nF 8 13 TOP VIEW DIRECTIONS OF THE DETECTABLE ACCELERATIONS O D S CS INT 1 INT 2 SDO SDA/SDI/ SCL/SPC GND Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 6 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the I2C/SPI interface.When using the I2C, CS must be tied high. The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the I2C/SPI interface. 4.1 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendation are available at www.st.com. 16/39 Doc ID 15594 Rev 1

LIS35DE Digital interfaces 5 Digital interfaces The registers embedded inside the LIS35DE may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). T able 8. Serial interface pin description PIN Name PIN description SPI enable CS I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C serial clock (SCL) SCL/SPC SPI Serial port clock (SPC) I2C serial data (SDA) SDA/SDI/SDO SPI serial data input (SDI) 3-wire interface serial data output (SDO) SDO SPI serial data output (SDO) 2 5.1 I C serial interface The LIS35DE I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below. T able 9. Serial interface pin description Term Description Transmitter The device which sends data to the bus Receiver The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a Master transfer Slave The device addressed by the master There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS35DE. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as the normal mode. Doc ID 15594 Rev 1 17/39

Digital interfaces LIS35DE 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS35DE is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometer to the same I2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I2C embedded inside the LIS35DE behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmits to the slave with direction unchanged. Table10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Command SAD[6:1] SAD[0] = SDO R/W SAD+R/W Read 001110 0 1 00111001 (39h) Write 001110 0 0 00111000 (38h) Read 001110 1 1 00111011 (3Bh) Write 001110 1 0 00111010 (3Ah) Table 11. Transfer when Master is writing one byte to slave Master ST SAD + W SUB DATA SP Slave SAK SAK SAK 18/39 Doc ID 15594 Rev 1

LIS35DE Digital interfaces Table 12. Transfer when Master is writing multiple bytes to slave Master ST SAD + W SUB DATA DATA SP Slave SAK SAK SAK SAK Table 13. Transfer when Master is receiving (reading) one byte of data from slave Master ST SAD + W SUB SR SAD + R NMAK SP Slave SAK SAK SAK DATA Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave Master ST SAD + W SUB SR SAD + R MAK Slave SAK SAK SAK DATA Table 15. Transfer when Master is receiving (reading) multiple bytes of data from slave Master MAK NMAK SP Slave DATA DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS35DE SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Doc ID 15594 Rev 1 19/39

Digital interfaces LIS35DE Figure 6. Read and write protocol CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 MS AD5 AD4AD3 AD2 AD1 AD0 SDO DO7DO6DO5DO4DO3DO2DO1DO0 CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drives SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remains unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. 20/39 Doc ID 15594 Rev 1

LIS35DE Digital interfaces 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI RW MSAD5AD4AD3AD2AD1AD0 SDO DO7DO6DO5DO4DO3DO2DO1DO0 The SPI read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 8. Multiple bytes SPI Read protocol (2 bytes example) CS SPC SDI RW MS AD5AD4AD3AD2AD1AD0 SDO DO7DO6DO5DO4DO3DO2DO1DO0DO15D O14D O13D O12D O11D O10D O9DO8 5.2.2 SPI write Figure 9. SPI write protocol CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 MS AD5 AD4AD3 AD2 AD1 AD0 Doc ID 15594 Rev 1 21/39

Digital interfaces LIS35DE The SPI write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 10. Multiple bytes SPI Write protocol (2 bytes example) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW MSAD5AD4AD3AD2AD1AD0 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI serial interface mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 MS AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode. 22/39 Doc ID 15594 Rev 1

LIS35DE Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 16. Register address map Register address Name Type Default Comment Hex Binary Reserved (do not modify) 00-1F Reserved Ctrl_Reg1 rw 20 010 0000 00000111 Ctrl_Reg2 rw 21 010 0001 00000000 Ctrl_Reg3 rw 22 010 0010 00000000 HP_filter_reset r 23 010 0011 dummy Dummy register Reserved (do not modify) 24-26 Reserved Status_Reg r 27 010 0111 00000000 -- r 28 010 1000 Not used OutX r 29 010 1001 output -- r 2A 010 1010 Not used OutY r 2B 010 1011 output -- r 2C 010 1100 Not used OutZ r 2D 010 1101 output Reserved (do not modify) 2E-2F Reserved FF_WU_CFG_1 rw 30 011 0000 00000000 FF_WU_SRC_1(ack1) r 31 011 0001 00000000 FF_WU_THS_1 rw 32 011 0010 00000100 FF_WU_DURATION_1 rw 33 011 0011 00000000 FF_WU_CFG_2 rw 34 011 0100 00000000 FF_WU_SRC_2 (ack2) r 35 011 0101 00000000 FF_WU_THS_2 rw 36 011 0110 00000000 FF_WU_DURATION_2 rw 37 011 0111 00000000 CLICK_CFG rw 38 011 1000 00000000 CLICK_SRC (ack) r 39 011 1001 00000000 -- 3A Not used CLICK_THSY_X rw 3B 011 1011 00000000 CLICK_THSZ rw 3C 011 1100 00000000 CLICK_TimeLimit rw 3D 011 1101 00000000 Doc ID 15594 Rev 1 23/39

Register mapping LIS35DE Table 16. Register address map (continued) Register address Name Type Default Comment Hex Binary CLICK_Latency rw 3E 011 1110 00000000 CLICK_Window rw 3F 011 1111 00000000 Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 24/39 Doc ID 15594 Rev 1

LIS35DE Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 CTRL_REG1 (20h) Table 17. CTRL_REG1 (20h) register DR PD FS 0(1) 0(1) Zen Yen Xen 1. CTRL_REG1[4:3] value is loaded at boot, ‘0’ value must not be changed. Table 18. CTRL_REG1 (20h) register description DR Data rate selection. Default value: 0 (0: 100 Hz output data rate; 1: 400 Hz output data rate) PD Power Down Control. Default value: 0 (0: power down mode; 1: active mode) FS Full Scale selection. Default value: 0 (refer to Table2 for typical full scale value) Zen Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Yen Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) Xen X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) DR bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100Hz. By changing the content of DR to “1” the selected data-rate will be set equal to 400Hz. PD bit allows to turn on the turn the device out of power-down mode. The device is in power- down mode when PD = “0” (default value after boot). The device is in normal mode when PD is set to 1. Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1. The default value is 1. Doc ID 15594 Rev 1 25/39

Register description LIS35DE 7.2 CTRL_REG2 (21h) Table 19. CTRL_REG2 (21h) register HP_FF_ HP_FF_ SIM BOOT -- FDS HP_coeff2 HP_coeff1 WU2 WU1 Table 20. CTRL_REG2 (21h) register description SIM SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FDS Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) HP FF_WU2 High Pass filter enabled for FreeFall/WakeUp # 2. Default value: 0 (0: filter bypassed; 1: filter enabled) HP_FF_WU1 High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0 (0: filter bypassed; 1: filter enabled) HP_coeff2 High pass filter cut-off frequency configuration. Default value: 00 HP_coeff1 (See table below) SIM bit selects the SPI serial interface mode. When SIM is ‘0’ (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad. BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers is changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to ‘0’. FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft. Table 21. High pass filter cut-off frequency configuration ft (Hz) ft (Hz) HP_coeff2,1 (DR=100 Hz) (DR=400 Hz) 00 2 8 01 1 4 26/39 Doc ID 15594 Rev 1

LIS35DE Register description Table 21. High pass filter cut-off frequency configuration (continued) ft (Hz) ft (Hz) HP_coeff2,1 (DR=100 Hz) (DR=400 Hz) 10 0.5 2 11 0.25 1 7.3 CTRL_REG3 [interrupt CTRL register] (22h) Table 22. CTRL_REG3 [interrupt CTRL register] (22h) register IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0 Table 23. CTRL_REG3 [interrupt CTRL register] (22h) register description IHL Interrupt active high, low. Default value 0. (0: active high; 1: active low) PP_OD Push-pull/Open Drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) I2CFG2 Data Signal on Int2 pad control bits. Default value 000. I2CFG1 (see table below) I2CFG0 I1CFG2 Data Signal on Int1 pad control bits. Default value 000. I1CFG1 (see table below) I1CFG0 Table 24. Data signal on Int pad control bits I1(2)_CFG2 I1(2)_CFG1 I1(2)_CFG0 Int1(2) pad 0 0 0 GND 0 0 1 FF_WU_1 0 1 0 FF_WU_2 0 1 1 FF_WU_1 OR FF_WU_2 1 0 0 Data Ready 1 1 1 Click interrupt 7.4 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter. Doc ID 15594 Rev 1 27/39

Register description LIS35DE 7.5 STATUS_REG (27h) Table 25. STATUS_REG (27h) register ZXYOR ZOR YOR XOR ZYXDA ZDA YDA XDA Table 26. STATUS_REG (27h) register description X, Y and Z axis Data Overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has over written the previous one before it is read) Z axis Data Overrun. Default value: 0 ZOR (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis Data Overrun. Default value: 0 YOR (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis Data Overrun. Default value: 0 XOR (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) ZYXDA X, Y and Z axis new Data Available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) ZDA Z axis new Data Available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) YDA Y axis new Data Available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) XDA X axis new Data Available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available) 7.6 OUT_X (29h) Table 27. OUT_X (29h) register XD7 XD_6 XD5 XD4 XD3 XD2 XD1 XD0 X axis output data. 7.7 OUT_Y (2Bh) Table 28. OUT_Y (2Bh) register YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 28/39 Doc ID 15594 Rev 1

LIS35DE Register description Y axis output data. 7.8 OUT_Z (2Dh) Table 29. OUT_Z (2Dh) register ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 Z axis output data. 7.9 FF_WU_CFG_1 (30h) Table 30. FF_WU_CFG_1 (30h) register AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 31. FF_WU_CFG_1 (30h) register description And/Or combination of Interrupt events. Default value: 0 AOI (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by LIR reading FF_WU_SRC_1 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 ZHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 ZLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 YHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 YLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 XHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 XLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Doc ID 15594 Rev 1 29/39

Register description LIS35DE 7.10 FF_WU_SRC_1 (31h) Table 32. FF_WU_SRC_1 (31h) register X IA ZH ZL YH YL XH XL Table 33. FF_WU_SRC_1 (31h) register description Interrupt Active. Default value: 0 IA (0: no interrupt has been generated; 1: one ore more interrupt has been generated) Z High. Default value: 0 ZH (0: no interrupt, 1: ZH event has occurred) Z Low. Default value: 0 ZL (0: no interrupt; 1: ZL event has occurred) Y High. Default value: 0 YH (0: no interrupt, 1: YH event has occurred) Y Low. Default value: 0 YL (0: no interrupt, 1: YL event has occurred) X High. Default value: 0 XH (0: no interrupt, 1: XH event has occurred) X Low. Default value: 0 XL (0: no interrupt, 1: XL event has occurred) Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allows the refreshment of data in the FF_WU_SRC_1 register if the latched option is chosen. 7.11 FF_WU_THS_1 (32h) Table 34. FF_WU_THS_1 (32h) register DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 35. FF_WU_THS_1 (32h) register description Resetting mode selection. Default value: 0 DCRM (0: counter resetted; 1: counter decremented) THS6, THS0 Free-fall / wake-up Threshold: default value: 000 0100 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented. 30/39 Doc ID 15594 Rev 1

LIS35DE Register description 7.12 FF_WU_DURATION_1 (33h) Table 36. FF_WU_DURATION_1 (33h) register D7 D6 D5 D4 D3 D2 D1 D0 Table 37. FF_WU_DURATION_1 (33h) register description D7 - D0 Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified 7.13 FF_WU_CFG_2 (34h) Table 38. FF_WU_CFG_2 (34h) register AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 39. FF_WU_CFG_2 (34h) register description AOI And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) LIR Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by reading FF_WU_SRC_2 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) ZHIE Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZLIE Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) YHIE Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) YLIE Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) XHIE Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) XLIE Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Doc ID 15594 Rev 1 31/39

Register description LIS35DE 7.14 FF_WU_SRC_2 (35h) Table 40. FF_WU_SRC_2 (35h) register X IA ZH ZL YH YL XH XL Table 41. FF_WU_SRC_2 (35h) register description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) ZH Z High. Default value: 0 (0: no interrupt; 1: ZH event has occurred) ZL Z Low. Default value: 0 (0: no interrupt; 1: ZL event has occurred) YH Y High. Default value: 0 (0: no interrupt; 1: YH event has occurred) YL Y Low. Default value: 0 (0: no interrupt; 1: YL event has occurred) XH X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) XL X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred) Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option is chosen. 7.15 FF_WU_THS_2 (36h) Table 42. FF_WU_THS_2 (36h) register DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 43. FF_WU_THS_2 (36h) register description DCRM Resetting mode selection. Default value: 0 (0: counter resetted; 1: counter decremented) THS6, THS0 Free-fall / wake-up Threshold. Default value: 000 0000 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented. 32/39 Doc ID 15594 Rev 1

LIS35DE Register description 7.16 FF_WU_DURATION_2 (37h) Table 44. FF_WU_DURATION_2 (37h) register D7 D6 D5 D4 D3 D2 D1 D0 Table 45. FF_WU_DURATION_2 (37h) register description D7 - D0 Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified. Doc ID 15594 Rev 1 33/39

Register description LIS35DE 7.17 CLICK_CFG (38h) Table 46. CLICK_CFG (38h) register - LIR Double_Z Single_Z Double_Y Single_Y Double_X Single_X Table 47. CLICK_CFG (38h) register description Latch Interrupt request into CLICK_SRC reg with the CLICK_SRC reg LIR refreshed by reading CLICK_SRC reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on double click event on Z axis. Default value: 0 Double_Z (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on Z axis. Default value: 0 Single_Z (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on double click event on Y axis. Default value: 0 Double_Y (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on Y axis. Default value: 0 Single_Y (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on double click event on X axis. Default value: 0 Double_X (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on X axis. Default value: 0 Single_X (0: disable interrupt request; 1: enable interrupt request) Table 48. Click interrupt configurations Double_Z / Y / X Single_Z / Y / X Click output 0 0 0 0 1 Single 1 0 Double 1 1 Single OR Double 34/39 Doc ID 15594 Rev 1

LIS35DE Register description 7.18 CLICK_SRC (39h) Table 49. CLICK_SRC (39h) register X IA Double_Z Single_Z Double_Y Single_Y Double_X Single_X Table 50. CLICK_SRC (39h) register description Interrupt Active. Default value: 0 IA (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Double click on Z axis event. Default value: 0 Double_Z (0: no interrupt; 1: Double Z event has occurred) Single click on Z axis event. Default value: 0 Single_Z (0: no interrupt; 1: Single Z event has occurred) Double click on Y axis event. Default value: 0 Double_Y (0: no interrupt; 1: Double Y event has occurred) Single click on Y axis event.Default value: 0 Single_Y (0: no interrupt; 1: Single Y event has occurred) Double click on X axis event. Default value: 0 Double_X (0: no interrupt; 1: Double X event has occurred) Single click on X axis event. Default value: 0 Single_X (0: no interrupt; 1: Single X event has occurred) 7.19 CLICK_THSY_X (3Bh) Table 51. CLICK_THSY_X (3Bh) register THSy3 THSy2 THSy1 THSy0 THSx3 THSx2 THSx1 THSx0 Table 52. CLICK_THSY_X (3Bh) register description THSy3 - THSy0 Click Threshold on Y axis. Default value: 0000 THSx3 - THSx0 Click Threshold on X axis. Default value: 0000 From 0.5g (0001) to 7.5g (1111) with step of 0.5g. 7.20 CLICK_THSZ (3Ch) Table 53. CLICK_THSZ (3Ch) register X X X X THSz3 THSz2 THSz1 THSz0 Doc ID 15594 Rev 1 35/39

Register description LIS35DE Table 54. CLICK_THSZ (3Ch) register description THSz3 - THSz0 Click Threshold on Z axis. Default value: 0000 From 0.5g (0001) to 7.5g (1111) with step of 0.5g. 7.21 CLICK_TimeLimit (3Dh) Table 55. CLICK_TimeLimit (3Dh) register Dur7 Dur6 Dur5 Dur4 Dur3 Dur2 Dur1 Dur0 From 0 to 127.5msec with step of 0.5msec. 7.22 CLICK_Latency (3Eh) Table 56. CLICK_Latency (3Eh) register Lat7 Lat6 Lat5 Lat4 Lat3 Lat2 Lat1 Lat0 From 0 to 255 msec with step of 1 msec. 7.23 CLICK_Window (3Fh) Table 57. CLICK_Window (3Fh) register Win7 Win6 Win5 Win4 Win3 Win2 Win1 Win0 From 0 to 255 msec with step of 1 msec. 36/39 Doc ID 15594 Rev 1

LIS35DE Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 12. LGA14: mechanical data and package dimensions mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A1 0.920 1.000 0.0362 0.0394 A2 0.700 0.0275 A3 0.180 0.220 0.260 0.0071 0.0087 0.0102 D1 2.850 3.000 3.150 0.1122 0.1181 0.1240 E1 4.850 5.000 5.150 0.1909 0.1968 0.2027 e 0.800 0.0315 d 0.300 0.0118 L1 4.000 0.1575 N 1.360 0.0535 N1 1.200 0.0472 P1 0.965 0.975 0.985 0.0380 0.0384 0.0386 P2 0.640 0.650 0.660 0.0252 0.0256 0.0260 T1 0.750 0.800 0.850 0.0295 0.0315 0.0335 T2 0.450 0.500 0.550 0.0177 0.0197 0.0217 R 1.200 1.600 0.0472 0.0630 h 0.150 0.0059 k 0.050 0.0020 LGA14 (3x5x0.92mm) Pitch 0.8mm i 0.100 0.0039 Land Grid Array Package s 0.100 0.0039 7773587 C Doc ID 15594 Rev 1 37/39

Revision history LIS35DE 9 Revision history T able 58. Document revision history Date Revision Changes 29-Apr-2009 1 Initial release 38/39 Doc ID 15594 Rev 1

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