LD49300 3 A very low-dropout voltage regulator Datasheet - production data Applications • Graphics processors • PC add-in cards • Microprocessor core voltage supply PPAK • Low voltage digital ICs • High efficiency linear power supplies • SMPS post regulators Features Description • Input voltage range: The LD49300 is a high-bandwidth, low-dropout, – V = 1.4 V to 5.5 V I 3.0 A voltage regulator, ideal for powering core – V = 3 V to 6 V BIAS voltages of low power microprocessors. The • Stable with ceramic capacitors LD49300 implements a dual supply configuration, • ±1.5% initial tolerance which guarantees a very low output impedance and a fast transient response. The LD49300 • Maximum dropout voltage (V - V ) 400 mV I O requires a bias input supply and a main input over the operating temperature range supply, allowing ultra-low input voltages on the • Adjustable output voltage starting from 0.8 V main supply rail. The input supply operates from • Very fast transient response (up to 10 MHz 1.4 V to 5.5 V and bias supply requires between 3 bandwidth) V and 6 V to work properly. The LD49300 offers fixed output voltages from 0.8 V to 1.8 V and • Excellent line and load regulation adjustable output voltages from 0.8 V. The specifications LD49300 requires a minimum output capacitance • Logic-controlled shutdown option for stability, and works optimally with small • Thermal shutdown and current limit protection ceramic capacitors. • Junction temperature range: - 25 °C to 125 °C Table 1. Device summary Order codes Package Packaging LD49300PT08R (1) PPAK (tape and reel) 2500 pieces per reel LD49300PT10R PPAK (tape and reel) 2500 pieces per reel LD49300PT12R PPAK (tape and reel) 2500 pieces per reel 1. Adjustable version. May 2014 DocID12861 Rev 4 1/23 This is information on a product in full production. www.st.com

Contents LD49300 Contents 1 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 Input supply voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2 Bias supply voltage (VBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6 Power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.7 Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 PPAK package heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.9 Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 DocID12861 Rev 4

LD49300 Typical application circuits 1 Typical application circuits Figure 1. Adjustable version Figure 2. Fixed version with enable DocID12861 Rev 4 3/23 23

Alternative application circuits LD49300 2 Alternative application circuits Figure 3. Single supply voltage solution Figure 4. LD49300 and DC-DC pre-regulator to reduce power dissipation 4/23 DocID12861 Rev 4

LD49300 Pin configuration 3 Pin configuration Figure 5. Pin connection (top view) Table 2. Pin description Pin Symbol Note EN Enable (input): logic high = enable, logic low = shutdown 1 ADJ Adjustable regulator feedback input connected to resistor voltage divider 2 V Input voltage regulator IN 3 GND Ground (tab is connected to ground) 4 V Regulator output OUT 5 V Input bias voltage powers the circuitry on the regulator except the output power device BIAS DocID12861 Rev 4 5/23 23

Diagram LD49300 4 Diagram Figure 6. Block diagram 6/23 DocID12861 Rev 4

LD49300 Maximum ratings 5 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit V Supply voltage -0.3 to 7 V IN -0.3 to V + 0.3 V Output voltage IN V OUT -0.3 to V + 0.3 BIAS V Bias supply voltage -0.3 to 7 V BIAS V Enable input voltage -0.3 to 7 V EN P Power dissipation Internally limited D T Storage temperature range -50 to 150 °C STG Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to ground. Table 4. Operating ratings Symbol Parameter Value Unit V Supply voltage 1.4 to 5.5 V IN V Output voltage 0.8 to 4.5 V OUT V Bias supply voltage 3 to 6 V BIAS V Enable input voltage 0 to V V EN BIAS T Junction temperature range - 25 to 125 °C J DocID12861 Rev 4 7/23 23

Electrical characteristics LD49300 6 Electrical characteristics T = - 25 °C to 125 °C; V = V + 2.1 V(1); V = V + 1 V; V = V (2); I = 10 mA; J BIAS O I O EN BIAS O C =1 µF; C = 10 µF; C = 1 µF; unless otherwise specified. Typical values are referred I O BIAS to T = 25 °C. J Table 5. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit T = 25 °C, fixed voltage option -1.5 1.5 J V Output voltage accuracy % O T = -25 °C to 125 °C -3 3 J V Line regulation V = V + 1 V to 5.5 V -0.1 0.1 %/V LINE I O V Load regulation I = 0 mA to 3 A, V ≥ 3 V 1 % LOAD L BIAS I = 1.5 A 200 L V Dropout voltage (V - V ) mV DROP I O I = 3 A 400 L V Dropout voltage (V - V ) I = 3 A(1) 1.5 2.1 V DROP BIAS O L I = 0 mA 4 6 L I Ground pin current mA GND I = 3 A 4 6 L I Ground pin current in shutdown V ≤ 0.4 V(2) 5 µA GND_SHD EN I = 0 mA 3 5 L I Current through V mA VBIAS BIAS I = 3 A 3 5 L I Current limit V = 0 V 4.5 A L O Enable input(2) Enable input threshold (fixed Regulator enable 1.4 V V EN voltage only) Regulator shutdown 0.4 I Enable pin input current 0.1 1 µA EN Reference T = 25 °C 0.788 0.8 0.812 J V Reference voltage V REF T = -25 °C to 125 °C 0.776 0.8 0.824 J V = 2.5 V ± 0.5 V, V = 1 V SVR Supply voltage rejection I O 68 dB F = 120 Hz, V = 3.3 V BIAS 1. For V ≤ 1 V, V dropout specification is not applied due to 3 V minimum V input. O BIAS BIAS 2. Fixed output voltage version only. 8/23 DocID12861 Rev 4

LD49300 Typical characteristics 7 Typical characteristics Figure 7. Reference voltage vs. temperature Figure 8. Output voltage vs. temperature Figure 9. Load regulation vs. temperature Figure 10. Line regulation vs. temperature (cid:6)(cid:10) (cid:37)(cid:1)(cid:9) (cid:34) (cid:48) (cid:45) Figure 11. Output voltage vs. input voltage Figure 12. Dropout voltage (V -V ) vs. IN OUT temperature (I = 1.5 A) OUT (cid:57)(cid:12) (cid:80) (cid:40)(cid:3)(cid:11) (cid:42) (cid:36) (cid:55) (cid:47) (cid:50) (cid:57) (cid:55)(cid:3) (cid:56) (cid:50) (cid:51) (cid:50) (cid:53) (cid:39) (cid:55)(cid:40)(cid:48)(cid:51)(cid:40)(cid:53)(cid:36)(cid:55)(cid:56)(cid:53)(cid:40)(cid:3) DocID12861 Rev 4 9/23 23

Typical characteristics LD49300 Figure 13. Dropout voltage (V -V ) vs. Figure 14. V pin current vs. temperature IN OUT BIAS temperature (I = 3 A) OUT (cid:57)(cid:12) (cid:80) (cid:40)(cid:3)(cid:11) (cid:42) (cid:36) (cid:55) (cid:47) (cid:50) (cid:57) (cid:55)(cid:3) (cid:56) (cid:50) (cid:51) (cid:50) (cid:53) (cid:39) (cid:55)(cid:40)(cid:48)(cid:51)(cid:40)(cid:53)(cid:36)(cid:55)(cid:56)(cid:53)(cid:40)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) Figure 15. Noise vs. frequency Figure 16. Quiescent current vs. temperature Figure 17. Supply voltage rejection vs. output Figure 18. Stable region vs. C and high ESR OUT current 10/23 DocID12861 Rev 4

LD49300 Typical characteristics Figure 19. Stable region vs. C and low ESR Figure 20. V and V start-up transient OUT BIAS IN response (V and V startup at the same IN BIAS time) V =V =V =3.1V, V =1V, C =1µF IN BIAS EN OUT OUT Figure 21. V start-up transient response Figure 22. V start-up transient response IN IN (V startup before than V ) T = 300 μs (V startup before than V ) T = 30 μs BIAS IN rise BIAS IN rise VIN=2.5V, VBIAS=VEN=3.1V, VOUT=1V, COUT=1µF VIN=2.5V, VBIAS=VEN=3.1V, VOUT=1V, COUT=1µF DocID12861 Rev 4 11/23 23

Typical characteristics LD49300 Figure 23. V start-up transient response Figure 24. Load transient response IN (V startup before than V and V = V ) BIAS IN EN IN VIN=VEN=2.5V, VBIAS=3.1V, VOUT=1V, COUT=1µF VIN=2.5V, VBIAS=5V, VOUT=1.8V, IOUT=10mA to 3A, C = 10 µF OUT 12/23 DocID12861 Rev 4

LD49300 Application hints 8 Application hints The LD49300 is a low-dropout linear regulator, designed for high-current applications requiring a fast transient response. The LD49150 has separate input and bias voltage ports, in order to reduce dropout voltage. Thanks to the LD49300, a minimum quantity of external components is required. 8.1 Input supply voltage (V ) IN V provides the LD49300 with power input current. The minimum input voltage can be as IN low as 1.4 V, allowing conversion from very low voltage supplies to achieve low output voltage levels and low power dissipation. 8.2 Bias supply voltage (V ) BIAS The LD49300 control circuitry is supplied by V pin, which requires a very low bias BIAS current (3 mA typ.) even at the maximum output current level (3 A). A bypass capacitor on V pin improves the LD49300 performance during line and load transient. The small BIAS ceramic capacitor from V to ground reduces high frequency noise that could be injected BIAS into the control circuitry. In typical applications, one ceramic chip capacitor of 1 µF may be used. V input voltage has to be 2.1 V above the output voltage, with a minimum V BIAS BIAS input voltage of 3 V. 8.3 External capacitors To assure regulator stability, input and output capacitors are required as shown in the typical application circuit. 8.4 Output capacitor The LD49300 requires a minimum output capacitance to maintain stability. At least 1 µF ceramic chip capacitor is required. However, specific capacitor selection assures the transient response. 1 µF ceramic chip capacitor satisfies most applications but 10 µF capacitor guarantees a better transient performance. In applications where V level is close IN to the maximum operating voltage (V > 4 V), a 10 µF minimum output capacitor avoids the IN overvoltage stress on the input/output power pins during short-circuit conditions due to parasitic inductive effect. The output capacitor has to be as closer as possible to the LD49300 output pin. ESR output capacitor (equivalent series resistance) has to be within the stable region as shown in Section7: Typical characteristics. Both ceramic and tantalum capacitors are suitable. 8.5 Minimum load current The LD49300 does not require a minimum load to maintain the output voltage regulation. DocID12861 Rev 4 13/23 23

Application hints LD49300 8.6 Power sequencing recommendations To assure the correct biasing and settling of the regulator internal circuitry during the start- up phase, as well as to avoid overvoltage spikes on the output, the correct power sequencing has to be provided. As general rule, V and V signal timings should be chosen properly, so that they are IN EN applied to the device after V voltage has already been settled on its minimum operative BIAS value (see Section8.2: Bias supply voltage (VBIAS)). This can be achieved, for instance, by avoiding too slow V rising edges (T > 10 ms). BIAS r Provided that the above condition is satisfied, when fast V transient input (T < 100 µs) is IN r present, a smooth startup, with limited overvoltage on the output, can be achieved simultaneously by V and V voltage (refer to Figure20, Figure21 and Figure22). IN BIAS In the fixed voltage version, overvoltage spikes can be reduced during very fast startup (T r << 100 µs) by pulling V pin up to V voltage (see Figure23). EN IN 8.7 Power dissipation/heatsinking In relation to the maximum power dissipation and maximum ambient temperature of the application, a heatsink may be required. Junction temperature has to be within the specified range under operating conditions. The total power dissipation of the device is given by: Equation 1 P = V x I + V x I - V x I D IN IN BIAS BIAS OUT OUT where: • V = input supply voltage IN • V = bias supply voltage BIAS • V = output voltage OUT • I = load current OUT θ The required thermal resistance for the heatsink is given by the following formula: SA Equation 2 θ θ θ = (T - T /P ) - ( + ) SA J A D JC CS T , the maximum allowed temperature rise depends on T , the maximum ambient Rmax Amax temperature of the application, and T , the maximum allowable junction temperature: Jmax Equation 3 T = T - T Rmax Jmax Amax θ The maximum allowable value for junction-to-ambient thermal resistance, , can be JA calculated as follows: Equation 4 θ = T / P JAmax Rmax D For PPAK package only. 14/23 DocID12861 Rev 4

LD49300 Application hints The thermal resistance depends on the amount of copper area or heatsink, and on the air flow. If θ maximum allowable value is ≥ 100 °C/W for PPAK package, no heatsink is JA needed since the package can dissipate enough heat to satisfy these requirements. If the θ value for allowable falls below these limits, a heatsink is required as described below. JA 8.8 PPAK package heatsinking PPAK package uses the copper plane on the PCB as a heatsink. The tab of this package is soldered to the copper plane for heatsinking. The PCB ground plane can be used as a heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual-layer PCB, it can be the unbroken GND area on the bottom layer thermally connected to the tab through-via holes. θ Figure25 shows curve for PPAK package for different copper area sizes, using a typical JA PCB: thickness 1/16 G10 FR4. θ Figure 25. vs. copper area for PPAK package JA 8.9 Adjustable regulator design The LD49300 adjustable version allows the output voltage to be fixed anywhere between 0.8 V and 4.5 V using two resistors as shown in the typical application circuit. For example, to fix R1 resistor value between V and ADJ pin, the resistor value between ADJ and OUT GND (R2) is calculated as follows: Equation 5 R2 = R1 [0.8 / (V - 0.8)] OUT where V is the desired output voltage. OUT R1 values should be lower than 10 kΩ to obtain a better load transient performance. Higher values up to 100 kΩ are suitable. DocID12861 Rev 4 15/23 23

Application hints LD49300 8.10 Enable The LD49300 fixed output voltage version features an active high enable input (EN) that allows the on-off control of the regulator. EN input threshold is guaranteed between 0.4 V and 1.4 V. The regulator is in shutdown mode when V < 0.4 V and it is in operating mode EN (V activated) when V > 1.4 V. If it is not in use, EN pin has to be tied directly to V to OUT EN IN keep the regulator continuously activated. EN pin has not to be left with high impedance. 16/23 DocID12861 Rev 4

LD49300 Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID12861 Rev 4 17/23 23

Package mechanical data LD49300 Figure 26. PPAK drawing 0078180_F 18/23 DocID12861 Rev 4

LD49300 Package mechanical data Table 6. PPAK mechanical data mm Dim. Min. Typ. Max. A 2.2 2.4 A1 0.9 1.1 A2 0.03 0.23 B 0.4 0.6 B2 5.2 5.4 C 0.45 0.6 C2 0.48 0.6 D 6 6.2 D1 5.1 E 6.4 6.6 E1 4.7 e 1.27 G 4.9 5.25 G1 2.38 2.7 H 9.35 10.1 L2 0.8 1 L4 0.6 1 L5 1 L6 2.8 R 0.20 V2 0° 8° DocID12861 Rev 4 19/23 23

Packaging mechanical data LD49300 10 Packaging mechanical data Figure 27. PPAK tape 10 pitches cumulative tolerance on tape +/- 0.2 mm Top cover P0 D P2 T tape E F K0 W B1 B0 For machine ref. only A0 P1 D1 including draft and radii concentric around B0 User direction of feed R Bending radius User direction of feed AM08852v1 20/23 DocID12861 Rev 4

LD49300 Packaging mechanical data Figure 28. PPAK reel T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius Tape slot G measured at hub in core for tape start 25 mm min. width AM08851v2 Table 7. PPAK tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID12861 Rev 4 21/23 23

Revision history LD49300 11 Revision history Table 8. Document revision history Date Revision Changes 20-Nov-2006 1 Initial release. 01-Dec-2006 2 Add note in cover page. 29-Jun-2010 3 Modified Section8.6: Power sequencing recommendations on page14. Changed the part numbers LD49300xx08, LD49300xx10 and LD49300xx12 to LD49300. Changed the title. 26-May-2014 4 Updated the description in cover page and Section9: Package mechanical data. Added Section10: Packaging mechanical data. Minor text changes. 22/23 DocID12861 Rev 4

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