L9758 Automotive multiple supply for engine control Datasheet - production data  Programmable 1 V or 1.5 V, 10% @ 10 mA, standby memory regulator (V ) KAM  Programmable 3.3 V or 2.6 V, 10% @ 10 mA alternate standby regulator (VSTBY)  Four 5 V ± 7 mV @ 50 mA protected tracking regulators, one of them with selectable external voltage reference.  Independent reset signals, RST5 and RSTL for the V , V supplies. DD5 DDL (cid:51)(cid:82)(cid:90)(cid:72)(cid:85)(cid:54)(cid:50)(cid:16)(cid:22)(cid:25)  Independent standby voltage monitor STANDBY_OK  Two power supply enable signals for different (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:27)(cid:19)(cid:27)(cid:20)(cid:25)(cid:20)(cid:22)(cid:20)(cid:25)(cid:51)(cid:54) voltage level signals Features  Battery voltage thresholding - IGN  Logic level thresholding - PSU_EN  AEC-Q100 qualified  Buck converter pre-regulated supply rated for a Description minimum of 2 A (RMS)  Optional Boost converter for low battery The L9758 is a multiple output voltage regulator conditions utilizing linear, switchmode (buck and boost) and tracking regulators to support high end  5 V, 2% @ 1 A, V low dropout (LDO) DD5 automotive microcontrollers used in powertrain regulator applications.  Programmable 3.3 V or 2.6 V, 2% @ 1 A, V DDL The L9758 provides two standby power LDO regulator with external pass transistor regulators as well as controllable LDO regulators.  Programmable microcontroller core voltage LDO regulator, V 2% @ 1 A with external The L9758 has power on reset functionality and CORE voltage divider and pass transistor controlled slew rate of the VDD5, VDDL and V . CORE Table 1. Device summary Order code Temperature range Package Packing L9758 Tube -40 °C to +125 °C PowerSO-36 E-L9758BBTR Tape & Reel September 2016 DocID14273 Rev 5 1/30 This is information on a product in full production. www.st.com

Contents L9758 Contents 1 Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 General DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 BUCK pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Boost pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 VDDL linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 VCORE linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 VKAM linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 VSTBY linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 VSA, VSB, VSC, VSD tracking linear regulator . . . . . . . . . . . . . . . . . . . . 18 4.10 RST5 and RSTL reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 IGN and PSU_EN inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 STBY_OK signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 General function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Switching pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 VDD5, VDDL and VCORE linear regulators . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Tracking regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 VKAM and VSTBY linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 RESET monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8 Reference current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/30 DocID14273 Rev 5

L9758 Contents 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 Entry into RUN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 Low voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 High voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 PowerSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DocID14273 Rev 5 3/30 3

List of tables L9758 List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2. Pins description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 3. Control pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 5. Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 6. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 7. General DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 8. BUCK pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9. Boost pre-regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 10. VDD5 linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 11. VDDL linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 12. VCORE linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 13. VKAM linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 14. VSTBY linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 15. VSA, VSB, VSC, VSD tracking linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 16. RST5 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 17. RSTL reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 18. IGN and PSU_EN inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 19. STBY_OK signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 20. PowerSO-36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 21. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4/30 DocID14273 Rev 5

L9758 List of figures List of figures Figure 1. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 2. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 3. Current reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 4. Power up/down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 5. PowerSO-36 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DocID14273 Rev 5 5/30 5

Pins configuration L9758 1 Pins configuration Figure 1. Pins connection (top view) (cid:42)(cid:49)(cid:39) (cid:3)(cid:20) (cid:22)(cid:25) (cid:54)(cid:58) (cid:57)(cid:37)(cid:36)(cid:55) (cid:3)(cid:21) (cid:22)(cid:24) (cid:41)(cid:39)(cid:37)(cid:46) (cid:57)(cid:37)(cid:36)(cid:55)(cid:66)(cid:54)(cid:58) (cid:3)(cid:22) (cid:22)(cid:23) (cid:57)(cid:37) (cid:37)(cid:50)(cid:50)(cid:54)(cid:55) (cid:3)(cid:23) (cid:3)(cid:22)(cid:22) (cid:57)(cid:39)(cid:39)(cid:24) (cid:53)(cid:40)(cid:54)(cid:66)(cid:54) (cid:3)(cid:24) (cid:3)(cid:22)(cid:21) (cid:57)(cid:39)(cid:39)(cid:47)(cid:66)(cid:39)(cid:53)(cid:57) (cid:42)(cid:49)(cid:39)(cid:66)(cid:54) (cid:3)(cid:25) (cid:22)(cid:20) (cid:57)(cid:39)(cid:39)(cid:47)(cid:66)(cid:41)(cid:39)(cid:37)(cid:46) (cid:57)(cid:37)(cid:36)(cid:55)(cid:66)(cid:54) (cid:3)(cid:26) (cid:22)(cid:19) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40)(cid:66)(cid:41)(cid:39)(cid:37)(cid:46) (cid:44)(cid:42)(cid:49) (cid:3)(cid:27) (cid:21)(cid:28) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40)(cid:66)(cid:39)(cid:53)(cid:57) (cid:44)(cid:42)(cid:49)(cid:66)(cid:50)(cid:49) (cid:3)(cid:28) (cid:21)(cid:27) (cid:57)(cid:51)(cid:53)(cid:50)(cid:42)(cid:22) (cid:51)(cid:54)(cid:56)(cid:66)(cid:40)(cid:49) (cid:3)(cid:20)(cid:19) (cid:3)(cid:21)(cid:26) (cid:38)(cid:50)(cid:53)(cid:40)(cid:66)(cid:39)(cid:44)(cid:54) (cid:57)(cid:54)(cid:39) (cid:3)(cid:20)(cid:20) (cid:3)(cid:21)(cid:25) (cid:57)(cid:51)(cid:53)(cid:50)(cid:42)(cid:20) (cid:57)(cid:54)(cid:38) (cid:3)(cid:20)(cid:21) (cid:3)(cid:21)(cid:24) (cid:57)(cid:51)(cid:53)(cid:50)(cid:42)(cid:21) (cid:57)(cid:54)(cid:37) (cid:3)(cid:20)(cid:22) (cid:3)(cid:21)(cid:23) (cid:57)(cid:46)(cid:36)(cid:48) (cid:57)(cid:54)(cid:36) (cid:3)(cid:20)(cid:23) (cid:3)(cid:21)(cid:22) (cid:57)(cid:54)(cid:55)(cid:37)(cid:60) (cid:55)(cid:53)(cid:36)(cid:38)(cid:46)(cid:66)(cid:53)(cid:40)(cid:41) (cid:3)(cid:20)(cid:24) (cid:3)(cid:21)(cid:21) (cid:54)(cid:55)(cid:37)(cid:60)(cid:66)(cid:50)(cid:46) (cid:53)(cid:40)(cid:41)(cid:66)(cid:54)(cid:40)(cid:47) (cid:3)(cid:20)(cid:25) (cid:3)(cid:21)(cid:20) (cid:53)(cid:54)(cid:55)(cid:24) (cid:57)(cid:54)(cid:66)(cid:39)(cid:44)(cid:54) (cid:3)(cid:20)(cid:26) (cid:3)(cid:21)(cid:19) (cid:53)(cid:54)(cid:55)(cid:47) (cid:53)(cid:40)(cid:59)(cid:55) (cid:3)(cid:20)(cid:27) (cid:3)(cid:20)(cid:28) (cid:53)(cid:54)(cid:55)(cid:66)(cid:55)(cid:44)(cid:48) (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:27)(cid:19)(cid:27)(cid:20)(cid:25)(cid:20)(cid:23)(cid:24)(cid:19)(cid:51)(cid:54) T able 2. Pins description Pin # Name Description 1 GND Power ground 2 VBAT Battery power source 3 VBAT_SW Switched battery power source 4 BOOST External boost transistor predriver output 5 RES_S Boost (+) current comparator input 6 GND_S Boost (-) current comparator input 7 VBAT_S Battery feedback for boost controller 8 IGN Ignition switch 9 IGN_ON Ignition state 10 PSU_EN Power supply enable 11 VSD Tracking regulator D 12 VSC Tracking regulator C 13 VSB Tracking regulator B 14 VSA Tracking regulator A 15 TRACK_REF Tracking A voltage reference 6/30 DocID14273 Rev 5

L9758 Pins configuration Table 2. Pins description (continued) Pin # Name Description 16 REF_SEL Tracking A voltage reference selection 17 VS_DIS Sensor supply disable 18 REXT External current reference resistance 19 RST_TIM Reset timer adjustment 20 RSTL VDDL regulator reset output 21 RST5 VDD5 regulator reset output 22 STBY_OK Standby regulator monitor 23 VSTBY Standby regulator output 24 VKAM Standby memory regulator output 25 VPROG2 Standby regulator voltage selection (VSTBY) 26 VPROG1 Standby memory regulator voltage selection (VKAM) 27 CORE_DIS VDDL and VCORE disable 28 VPROG3 VDDL voltage selection 29 VCORE_DRV VCORE external pass transistor predriver output 30 VCORE_FDBK VCORE feedback 31 VDDL_FDBK VDDL feedback 32 VDDL_DRV VDDL external pass transistor predriver output 33 VDD5 VDD5 linear regulator output 34 VB Switching preregulator output 35 FDBK Switching voltage feedback 36 SW Buck regulator switch output T able 3. Control pins description Logic Type of Pin name Description level I/O Low Enter in Stand-by Mode if also PSU_EN is low Pull IGN High Enter in Run Mode down Low IGN is high Open IGN_ON High IGN is low drain Low Enter in Stand-by Mode if also IGN is low Pull PSU_EN High Enter in Run Mode down Low Enable VSB, VSC, VSD tracking regulators Pull VS_DIS High Disable VSB, VSC, VSD tracking regulators down DocID14273 Rev 5 7/30 29

Pins configuration L9758 Table 3. Control pins description (continued) Logic Type of Pin name Description level I/O Low Voltage reference for VSA tracking regulator is VDD5 Pull Ref_Sel High Voltage reference for VSA tracking regulator is down VTRACK_REF Low VDDL output regulator out of range (under voltage) Open RSTL High VDDL output regulator fully operational collector Low VDD5 output regulator out of range (under voltage) Open RST5 High VDD5 output regulator fully operational collector Low VKAM regulator output programmed to 1V VPROG1 Pull up High VKAM regulator output programmed to 1.5V Low VSTBY regulator output programmed to 2.6V VPROG2 Pull up High VSTBY regulator output programmed to 3.3V Low VDLL regulator output programmed to 2.6V VPROG3 Pull up High VDLL regulator output programmed to 3.3V Low Enable VDLL and VCORE linear regulators Pull CORE_DIS High Disable VDLL and VCORE linear regulators down Low VSTBY output regulator out of range (under voltage) Open STBY_OK High VSTBY output regulator fully operational drain 8/30 DocID14273 Rev 5

L9758 Functional block diagram 2 Functional block diagram Figure 2. Functional block diagram (cid:57)(cid:51)(cid:53)(cid:50)(cid:42)(cid:21) (cid:54)(cid:55)(cid:37)(cid:60)(cid:66)(cid:50)(cid:46) (cid:57)(cid:37)(cid:36)(cid:55) (cid:54)(cid:55)(cid:37)(cid:60)(cid:3)(cid:57)(cid:85)(cid:72)(cid:74) (cid:57)(cid:54)(cid:55)(cid:37)(cid:60) (cid:54)(cid:55)(cid:37)(cid:60) (cid:57)(cid:37)(cid:36)(cid:55) (cid:21)(cid:17)(cid:25)(cid:57)(cid:18)(cid:22)(cid:17)(cid:22)(cid:57)(cid:15)(cid:3)(cid:20)(cid:19)(cid:80)(cid:36) (cid:37)(cid:68)(cid:81)(cid:71)(cid:74)(cid:68)(cid:83) (cid:20)(cid:3)(cid:151)(cid:41) (cid:20)(cid:19)(cid:3)(cid:151)(cid:41) (cid:57)(cid:51)(cid:53)(cid:50)(cid:42)(cid:20) (cid:57)(cid:46)(cid:36)(cid:48)(cid:3)(cid:57)(cid:85)(cid:72)(cid:74) (cid:57)(cid:46)(cid:36)(cid:48) (cid:57)(cid:53)(cid:37)(cid:56)(cid:36)(cid:49)(cid:55) (cid:21)(cid:21)(cid:3)(cid:151)(cid:43) (cid:57)(cid:37)(cid:36)(cid:55)(cid:66)(cid:54)(cid:58) (cid:20)(cid:57)(cid:18)(cid:20)(cid:17)(cid:24)(cid:57)(cid:15)(cid:3)(cid:20)(cid:19)(cid:80)(cid:36) (cid:20)(cid:3)(cid:151)(cid:41) (cid:22)(cid:19)(cid:19)(cid:151)(cid:41) (cid:54)(cid:58) (cid:21)(cid:21)(cid:3)(cid:151)(cid:43) (cid:57)(cid:37)(cid:36)(cid:55)(cid:66)(cid:54) (cid:37)(cid:88)(cid:70)(cid:78) (cid:19)(cid:17)(cid:20) (cid:37)(cid:42)(cid:53)(cid:50)(cid:49)(cid:40)(cid:50)(cid:39)(cid:54)(cid:54)(cid:66)(cid:66)(cid:54)(cid:54)(cid:55) (cid:37)(cid:82)(cid:82)(cid:86)(cid:87)(cid:38)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79) (cid:54)(cid:48)(cid:51)(cid:54)(cid:3)(cid:50)(cid:86)(cid:70)(cid:17)(cid:11)(cid:24)(cid:3)(cid:48)(cid:43)(cid:93)(cid:12) (cid:38)(cid:51)(cid:75)(cid:88)(cid:68)(cid:80)(cid:85)(cid:74)(cid:83)(cid:72) (cid:47)(cid:76)(cid:81)(cid:72)(cid:37)(cid:42)(cid:68)(cid:53)(cid:68)(cid:85)(cid:72)(cid:68)(cid:20)(cid:3)(cid:81)(cid:57)(cid:73)(cid:83)(cid:17)(cid:71)(cid:17)(cid:24)(cid:82)(cid:57)(cid:79)(cid:87)(cid:15)(cid:68)(cid:3)(cid:20)(cid:74)(cid:17)(cid:72)(cid:19)(cid:3)(cid:36)(cid:38)(cid:82)(cid:81)(cid:87)(cid:54)(cid:85)(cid:82)(cid:90)(cid:79)(cid:79)(cid:72)(cid:54)(cid:51)(cid:76)(cid:85)(cid:87)(cid:88)(cid:70)(cid:82)(cid:75)(cid:83)(cid:90)(cid:80)(cid:83)(cid:72)(cid:79)(cid:92)(cid:82)(cid:85)(cid:71)(cid:72) (cid:41)(cid:57)(cid:57)(cid:57)(cid:39)(cid:37)(cid:38)(cid:38)(cid:37)(cid:50)(cid:50)(cid:46)(cid:53)(cid:53)(cid:40)(cid:40)(cid:66)(cid:66)(cid:41)(cid:39)(cid:39)(cid:53)(cid:37)(cid:57)(cid:46) (cid:21)(cid:21)(cid:3)(cid:151)(cid:41) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40)(cid:66)(cid:41)(cid:39)(cid:37)(cid:46) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40) (cid:20)(cid:19)(cid:46) (cid:53)(cid:40)(cid:59)(cid:55) (cid:54)(cid:50)(cid:41)(cid:55) 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(cid:40)(cid:49)(cid:66)(cid:53)(cid:40)(cid:42) (cid:42)(cid:49)(cid:39) (cid:56)(cid:83)(cid:18)(cid:39)(cid:81) (cid:54)(cid:50)(cid:41)(cid:55)(cid:3)(cid:54)(cid:55)(cid:36)(cid:53)(cid:55) (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:27)(cid:19)(cid:27)(cid:20)(cid:25)(cid:20)(cid:23)(cid:24)(cid:21)(cid:51)(cid:54) DocID14273 Rev 5 9/30 29

Operating conditions L9758 3 Operating conditions 3.1 Absolute maximum ratings This part may be irreparably damaged if taken outside the specified absolute maximum ratings. Operation above the absolute maximum ratings may also cause a decrease in reliability. Table 4. Absolute maximum ratings Symbol Parameter Value Unit V , BAT V , Battery supply voltage -0.3 to 40 V BAT_SW V BAT_S V Ignition input voltage (with at least 10K external resistance) -2.0 to 40 V IGN Digital input voltages (PSU_EN, VS_EN, VPROG1, VPROG2, V -0.3 to 7 V I-digital VPROG3, VDDL/VCORE_EN, REF_SEL) Analog input voltages (REXT, TRACK_REF, RST_TIM V -0.3 to 7 V I-analog VDDL_FDBK, VCORE_FDBK) V Linear regulator supply (VB) -0.3 to 40 V B V Switching feedback (FDBK) -0.3 to 40 V FDBK V Buck regulator switch output (SW) -2 to 40 V SW Digital output voltages (IGN_ON, RSTL, RST5, BOOST, V -0.3 to 7 V O-digital STBY_OK) V Regulator output voltages (VDD5, VSTBY, VKAM) -0.3 to 7 V OR V Regulator output voltages (VSA, VSB, VSC, VSD) -3 to 40 V VSx V , CORE_DRV External regulator predriver output (VCORE_DRV, VDDL_DRV) -0.3 to 15 V V DDL_DRV I Switching preregulator current 0 to 4.2 A SMPS T Operating temperature -40 to 125 °C op T Storage temperature -50 to 150 °C stg T Max junction temperature 150 °C j V Max ESD (human body model) ±2 KV ESD Warning: Exceeding these values might destroy this part. This part is not guaranteed to function properly at these ratings. T he CMOS inputs and outputs should never go above 5V + 0 .3 V or below GND - 0.3V without protection (series resistance). If this occurs, the device might be destroyed by latch-up and/or the output levels might not be controlled by the inputs. Unused inputs must be connected to GND and unused outputs should be left open and programmed to a low state. Unused I/O pins should be programmed as outputs, left open, and programmed to a low state. 10/30 DocID14273 Rev 5

L9758 Operating conditions 3.2 Operating ranges Full specification parameters cannot be guaranteed outside the operating ranges. Once the condition has returned within the specified operating ranges, the part will recover with no damage or degradation. T able 5. Operating ranges Symbol Parameter Value Unit 4 to 26.5 V , V , BATV BAT_SW Battery supply voltage 4 to 40 V BAT_S ( t < 400ms) Ignition input voltage (with at least 10K external V 4 to 26.5 V IGN resistance) Digital input voltages (PSU_EN,VS_EN,VPROG1, V l -0.3 to 5.3 V I-digita VPROG2, VPROG3, VDDL/VCORE_EN, REF_SEL) Analog input voltages (REXT, TRACK_REF, V -0.3 to 5.3 V I-analog RST_TIM VDDL_FDBK, VCORE_FDBK) I Switching preregulator average current 0 to 2.5 A AVE T Operating temperature -40 to 125 °C op T Junction temperature -40 to 150 °C j 3.3 Thermal data T able 6. Thermal data Symbol Parameter Value Unit R Thermal resistance junction-to-case 2 °C/W th(j-case) DocID14273 Rev 5 11/30 29

Electrical characteristics L9758 4 Electrical characteristics All voltage values are, if not otherwise stated, relative to ground.Current flow into a pin is positive. If not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps. 4.1 General DC characteristics T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 7. General DC characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Quiescent current at pin V = 0 V; I BAT - - 150 μA BAT_SW_SB BAT_SW V = 12 V BAT_SW Supply current in OFF I I + I - - 120 μA Q_OFF state VBAT_SW VBAT Low voltage inhibit Low V - 3.5 - 3.9 V LVI_LOW threshold Low voltage inhibit High V - 4.0 - 4.5 V LVI_HIGH threshold Low voltage inhibit V - 0.3 - 1 V LVI_HYS hysteresis V Linear Start-up voltage - 3.8 - 4.8 V ST V Rext Voltage - 1.18 - 1.24 V REXT V VS_EN input threshold - 0.8 - 2 V TH_VSEN VDDL/VCORE_EN V - 0.8 - 2 V VDDL/VCORE_EN input threshold PROG1 input Low V - - - 0.8 V PROG1_LOW Voltage PROG2 input Low V - - - 0.8 V PROG2_LOW Voltage PROG3 input Low V - - - 0.8 V PROG3_LOW Voltage V Vddl Power-up enable - 1 - 2 V DDL_ENUP 12/30 DocID14273 Rev 5

L9758 Electrical characteristics 4.2 BUCK pre-regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V; unless otherwise specified. amb BAT BAT_SW T able 8. BUCK pre-regulator Symbol Parameter Test condition Min. Typ. Max. Unit R = 10.0 kΩ ±1% F Operating frequency ext 300 - 450 kHz SW V = 13.5 V BAT_SW High side switch ON R V = 6.0 V - - 0.25 Ω dsON resistance BAT_SW Average current during I V = 3.0V 0.3 - 0.7 A ST_MAX start-up B 7.0 V < V < 18 V V Output voltage BAT_SW 5.5 - 6.1 V BREG 0.25 A < I <2.0 A VBAT 100% Duty Cycle operation Vb100 6.2 - 7.8 V threshold Voltage sensed at VBAT_SW pin 100% Duty Cycle operation Vb100h 0.05 - 0.8 V threshold hysteresis Vpre Load regulation ΔI = 0.1 A –2 A V = 13.5 V - - 400 mV VB BAT_SW L = 22 μH, C = 22 μF X7R Vrpre Voltage ripple, p-p - - 300 mV V = 13.5 V BAT_SW Ts Start time L = 22 μH, C = 22 μF X7R - - 1.4 ms DCmin Minimum duty cycle - 10 - 18 % V = 13.5 V I = 0.5 A 70 EFF Efficiency BAT_SW VB - - % V = 13.5 V I = 2 A 70 BAT_SW VB L 15 22 30 μH Output Inductance - Rs 75 mΩ C 10 100 μF Output capacitance - - ESR 0 160 mΩ V < 26.5 V Ov Power-up overvoltage BAT_SW 15 - 200 mV 0.25 A < I <2.0 A VBAT Tr_sw 7.0 V < V < 18 V SW rising and falling time BAT_SW 10 - 150 μs Tf_sw IVBAT <2.0 A (20%, 80%) DocID14273 Rev 5 13/30 29

Electrical characteristics L9758 4.3 Boost pre-regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 9. Boost pre-regulator Symbol Parameter Test condition Min. Typ. Max. Unit R = 10.0 kΩ ±1% FSW Operating frequency ext 300 - 450 kHz V = 13.5 V BAT_SW V Output voltage 4.0 V < V < 7 V, 0.25 A < I < 2.0 A 8.5 - 10 V B_REG BAT_S VB BoostONth Boost enable threshold 7.0 - 8.3 V Voltage sensed at VBAT_S pin BoostOFFth Boost disable threshold 7.0 - 8.3 V Boost operation threshold V Voltage sensed at VBAT_S pin 0.05 - 0.9 V BOOST_HY hysteresis V Load regulation ΔI = 0.1 A–2 A V = 4 V - - 600 mV BOOST VB BAT_S L = 22 μH, C = 300 μF X7RX7R V Voltage ripple, p-p - - 600 mV R_VBOOST V = 4 V BAT_S Boost predriver low level V I = 1 mA - - 0.2 V OLB voltage sink Boost predriver low level V I = 200 μA 4.8 - - V OHB voltage source T Boost predriver rise time Cl = 1 nF 50 - 180 ns RB T Boost predriver fall time Cl = 1 nF 20 - 100 ns FB L 30 μH Output inductance - 15 22 Rs 75 mΩ C 100 300 900 μF Output capacitance - ESR 10 200 mΩ R Sensing resistor - 40 50 - mΩ SENSE 14/30 DocID14273 Rev 5

L9758 Electrical characteristics 4.4 VDD5 linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 10. VDD5 linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit 5 mA < I < 1 A V => 5.7 V 4.9 5.1 DD5 BAT_SW 5 mA < I < 800 mA DD5 VDD5 Output voltage VBAT_SW = 5.5 V - V 5 mA < IDD5 < 1 A VBAT_SW  4 V 3.3 4.0 I Current limit V = 4.75 V 1200 - 2500 mA DD5_LIM DD5 C Ceramic or Tantalum 4.7 100 μF DD5 Output capacitor - ESR C = 4.7 μF 0 160 mΩ R Ripple rejection F = 375 kHz 26 - - dB RDD5 ΔVB/Δt < 70 V/ms V Maximum overshoot - - 5.5 V DD5_MAX V = 4V → 8 V BAT_SW Output voltage slew rate V /t 5 mA < I < 1 A V = 13.5 V 10 - 20 V/ms DD5 at power-up DD5 BAT_SW I Load current - 5 - 1000 mA DD5 V lineR Line regulation 6.0 V < V < 7 V -25 - +25 mV DD5 B V loadR Load regulation 5 mA < I < 1 A -25 - +25 mV DD5 DD5 V -V Start up V -V during start up 0.5 - 3.1 mV DD5 ddl DD5 ddl 4.5 VDDL linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW Table 1 1. VDDL linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit 5 mA < I < 1 A, V = Open DDL PROG3 4.0 V < V < 18 V 3.23 3.37 BAT_SW V Output voltage - V DDL 5 mA <I < 1 A, V = Low 2.55 2.65 DDL PROG3 4.0 V < V < 18 V BAT_SW C 4.7 100 μF DDL Output capacitor Ceramic or Tantalum - ESR 0 160 mΩ RR Ripple rejection F = 375 kHz 26 - - dB DDL DocID14273 Rev 5 15/30 29

Electrical characteristics L9758 Table 11. VDDL linear regulator (continued) Symbol Parameter Test condition Min. Typ. Max. Unit 5 mA <I < 1 A, V = Open 3.75 DDL PROG3 4.0 V < V < 18 V BAT_SW ΔVB/Δt < 70 V/ms Maximum V - - V DDL_MAX overshoot 5 mA < I < 1 A, V = Low 3.6 DDL PROG3 4.0 V < V < 18 V BAT_SW ΔVB/Δt < 70 V/ms Output voltage ΔV /Δt slew rate at power- 5 mA <I < 1 A V =13.5 V 5 - 25 V/ms DDL DDL BAT_SW up I Load current - 5 - 1000 mA DDL V lineR Line regulation 5.5 V < V < 7 V -8 - +8 mV DDL BAT_SW V loadR Load regulation 5 mA < I < 1 A -8 - +8 mV DDL DDL 4.6 VCORE linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 12. VCORE linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit 5 mA < I < 1 A; V Output voltage CORE 1.47 - 1.53 V CORE 4.0 V < V < 18 V BAT_SW CddL 4.70 100 μF Output capacitor Ceramic or Tantalum - ESR 0 160 mΩ RRddL Ripple rejection F= 375 kHz 26 - - dB Maximum 5 mA < I < 1 A V CORE - - 1.7 V CORE_M overshoot 4.0 V < V < 18 V BAT_SW Output voltage ΔV /Δt slew rate at power- 5 mA < I < 1 A V =13.5 V 5 - 25 V/ms CORE CORE BAT_SW up I Load current - 5 - 1000 mA CORE Range of V Using external resistor divider 1.05 1.5 2.8 V CORE_PROG programmability V Feedback voltage - 0.98 - 1.02 V CORE_FBK V lineR Line regulation 5.5 V < V < 7 V -25 - +25 mV CORE BAT_SW V loadR Load regulation 5 mA < I < 1 A -25 - +25 mV CORE CORE 16/30 DocID14273 Rev 5

L9758 Electrical characteristics 4.7 VKAM linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 13. VKAM linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit 0.1mA < I < 10mA, V = Low 0.9 1.1 VKAM PROG1 4.0V < V < 18V V Output voltage BAT - V KAM 0.1mA < I < 10mA, V =Open 1.37 1.65 VKAM PROG1 4.0V < V < 18V BAT C 0.1 4.7 μF VKAM Output capacitor Ceramic - ESR 0 20 mΩ RR Ripple rejection F=375 kHz 26 - dB VKAM 0.1 mA < I < 10 mA, V = Low 1.2 Maximum overshoot VKAM PROG1 4 V < V < 18 V VKAM_M (absolute value 0.1 mA B<A IT < 10 mA, V = Open - - 1.7 V relative to GND) VKAM PROG1 4 V < V < 18 V BAT Iddkamsh Current limit V = 0.5 V 11 - 50 mA KAM I Load current - 0.1 - 10 mA KAM V lineR Line regulation 6 V < V < 18 V -25 - +25 mV KAM BAT V loadR Load regulation 0.1 mA < I < 10 mA -25 - +25 mV KAM KAM 4.8 VSTBY linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 14. VSTBY linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit 0.1 mA < I < 10 mA, V = Low 2.47 2.73 STBY PROG2 4 V < V < 18 V V Output voltage BAT - V STBY 0.1 mA < I < 10 mA, V = Open 3.13 3.47 STBY PROG2 4 V < V < 18 V BAT C 0.1 10 μF STBY Output capacitor Ceramic - ESR 0 20 mΩ RR Ripple rejection F = 350 kHz 26 - - dB STBY 0.1 mA < I < 10 mA, V = Low 3.05 STBY PROG2 Maximum overshoot 4 V < V < 18 V VSTBY_M (absolute value 0.1 mA B<A IT < 10 mA, V = Open - - 3.75 V relative to GND) STBY PROG2 4 V < V < 18 V BAT I sh Current limit V = 0.5 V 11 - 50 mA STBY STBY I Load current - 0.1 - 10 mA STBY V lineR Line regulation 6 V < V <18 V -25 - +25 mV STBY BAT V loadR Load regulation 0.1 mA < I < 10 mA -25 - +25 mV STBY STBY DocID14273 Rev 5 17/30 29

Electrical characteristics L9758 4.9 VSA, VSB, VSC, VSD tracking linear regulator T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 15. VSA, VSB, VSC, VSD tracking linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit Output voltage 1 mA < I < 50 mA, 6 V < V < 18 V -7 10 ΔV t1 BAT_SW - mV TRK tracking accuracy 1 mA < It1 < 5 0mA, 4 V < VBAT_SW < 6 V -50 50 I sh Current limit V = 4.75 V 51 - 100 mA TRK tck C 1 16 μF TRK Output load capacitor Ceramic or Tantalum - ESR 0 3 mΩ Ctckmin Minimum output 1 μF Ceramic or Tantalum - ESRmin capacitor for stability 0 3 Ω RR Ripple rejection F= 375 kHz 26 - - dB TRK Vdrop Dropout voltage I = 50 mA - - 300 mV load T Thermal shutdown Vtck = 4.75 V (current limitation) 165 - 185 °C TSD T Thermal hysteresis Vtck = 4.75 V (current limitation) 5 - 15 °C HYST I Load current - 1 - 50 mA TRK 4.10 RST5 and RSTL reset signals T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 16. RST5 reset signals Symbol Parameter Test condition Min. Typ. Max. Unit Reset “high” leakage I V = 5.15 V -3.0 - - μA RST5_H current RST5 V Reset “low” output VDD5 = 4.5 V Ire = 5 mA - - 0.4 V RST5_L voltage V = 1.0 V Ire = 1 mA 0.4 DD5 Reset threshold V – V ΔV /Δt < 0 4.5 - DD5 V FTH_RST5 decreasing DD5 0.2 Reset threshold V – V ΔV /Δt > 0 4.5 - DD5 V RTH_RST5 increasing DD5 0.07 Reset threshold V - 50 - - mV HY_RST5 hysteresis Reset activation out t - 15 - 25 μs ACT_RST5 of tolerance duration t Reset delay 4.7 kΩ < R < 47 kΩ 1 - 10 ms DEL_RST5 ext t Reset delay accuracy R ±1% -15 - +15 % ERR_RST5 ext 18/30 DocID14273 Rev 5

L9758 Electrical characteristics T able 17. RSTL reset signals Symbol Parameter Test condition Min. Typ. Max. Unit Reset “high” I V = 5.15 V -3.0 - - μA RSTL_H leakage current DDL V Reset “low” output VDDL=5.0V Ire=5mA - - 0.4 V RSTL_L voltage V =1.0V Ire=1mA 0.4 DDL Reset threshold V – V ΔV /Δt < 0, V =Low 2.375 - DDL V FTH_RSTL decreasing DDL PROG3 0.05 Reset threshold V – V ΔV /Δt < 0, V =Low 2.375 - DDL V RTH_RSTL increasing DDL PROG3 0.02 Reset threshold V – V ΔV /Δt < 0, V =Open 3.13 - DDL V FTH_RSTL_O decreasing DDL PROG3 0.05 Reset threshold V – V ΔV /Δt < 0, V =Open 3.13 - DDL V RTH_RSTL_O increasing DDL PROG3 0.02 Reset threshold V - 40 - - mV HY_RSTL hysteresis Reset activation out t - 15 - 25 μs ACT_RSTL of tolerance duration t Reset delay 1nF < C < 10nF; 4.7kΩ < R < 47kΩ 1 - 10 ms DEL_RSTL EXT ext Reset delay t R ±1% -15 - +15 % ERR_RSTL accuracy ext 4.11 IGN and PSU_EN inputs T = -40 °C to 125 °C, V = V = 5.5 to 26.5 V, unless otherwise specified. amb BAT BAT_SW T able 18. IGN and PSU_EN inputs Symbol Parameter Test condition Min. Typ. Max. Unit V IGN input threshold threshold @ IGN pin 2 - 3.6 V TH_IGN IGN input threshold V - 0.2 - 1.4 V HYS_IGN hysteresis R IGN pull-down resistor - 300 - 1100 kΩ PD_IGN 0.55* V PSU_EN input threshold - 0.9 - V TH_PSUEN V STBY PSU_EN input threshold V - 0.2 - 0.8 V HYS_PSUEN hysteresis R PSU pull-down resistor - 50 - 230 kΩ PD_PSUEN IGN_ON “low” output V Iol=1mA 0.4 V OL_IGNON voltage IGN external input R 10 50 kΩ IGN_EXT resistance DocID14273 Rev 5 19/30 29

Electrical characteristics L9758 4.12 STBY_OK signal T = -40°C to 125°C, V = V = 5.5 to 26.5V, unless otherwise specified. amb BAT BAT_SW T able 19. STBY_OK signal Symbol Parameter Conditions Min Typ Max Units T VstanbyOK threshold ΔV /Δt <0 -8,5 - -3,5 % h_stbyok STBY T STBY_OK filter time - 15 - 25 μs stbydly T STBY_OK delay accuracy - 10 - 60 μs stbyok STBY_OK low output V V = 1 V I =1 mA - - 0.4 V ol_stbyok voltage STBY stbyok 20/30 DocID14273 Rev 5

L9758 Functional description 5 Functional description 5.1 General function The L9758 is equipped with 9 linear voltage regulators. A buck boost switch mode power supply as pre regulator for the 7 main regulators is used to reduce the power consumption in the system. Two standby regulators can be used to bias the system on off-mode. These two regulators are equipped with an independent bandgap voltage reference. The current consumption of these two linear regulators is specified to be less than 120 μA in OFF state. If these standby functions are not used the current consumption on the battery can be reduced by not connecting the VBAT. Under this condition the device enters immediately in the run mode, the pin PSU_REN looses his function. The quiescent current on the VBAT_SW can be reduced to maximum 10 μA with 12 V battery voltage in off mode. The main regulators can be activated with the IGN input. With an external resistor higher than 10 kΩ in series to the IGN pin a battery compliant signal can be used. In the functional block diagram (see F igure2) a resistor value of 51kΩ is used together with a 100 nF capacitor for noise robustness on IGN. 5.2 Switching pre-regulator The switching pre-regulator is a buck or a buck-boost current control mode regulator. The optional boost operation for low battery conditions can be selected connecting external logic level low side NCH FET and an external diode in series to the inductor. The external parts required to complete the switching regulator are an inductor, recirculation diode and input and output filtering capacitor. The compensation network is inside the device. With a constant switching frequency of 350 kHz, the pre-regulator controls the output voltage (the voltage at the VB and FDBK pins) to the limits stated in the electrical characteristics table varying the duty cycle. The 350 kHz are related to R = 10 kΩ (see EXT S ection5.8). At low battery voltages, in buck configuration, the pre-regulator runs with the duty cycle up to 100%. In buck-boost configuration normally it runs at 350 kHz but for a limited range of input voltage it could enter in pulse skipping mode to control the output voltage. A soft start function is implemented reducing the current limitation during the power-up phase. 5.3 VDD5, VDDL and VCORE linear regulators The VDD5 output is a fully integrated low drop out regulator. The V and V supplies DDL CORE will be implemented via an external N-channel pass MOS, with the control being internal to the IC. If the pass MOS is not used, two low current (max 30 mA) regulators are available connecting directly VDDL_FDBK to VDDL_DRV and VCORE_FDBK to VCORE_DRV with a resistor divider.The output of the pre-regulator is used as the source of these supplies. V is a fixed 5V nominal output, while V and V are programmable. DD5 DDL CORE DocID14273 Rev 5 21/30 29

Functional description L9758 The V voltage is selectable with the VPROG3 pin: 2.5 V if connected to GND and 3.3 V DDL if left open (an internal pull-up is present). V voltage is programmable connecting an CORE external resistor divider at the feedback pin (VCORE_FDBK). Once programmed to a value at power-up, this value cannot change during the power cycle. Purposely the system runs at a single fixed value for V and V for the life of the DDL CORE product. All the linear regulators start with a controlled slew rate when the pre-regulated voltage reaches V threshold as indicated in the electrical characteristics table. All the DDL_ENUP linear regulators are short circuit protected with a limited current. 5.4 Tracking regulators Four low drop-out tracking regulators (VSA, VSB, VSC and VSD) are supplied by the output of the switching pre-regulator. They track the output voltage of the VDD5 linear regulator with the accuracy as specified in the electrical characteristic table. The VSA regulator also tracks an external voltage reference (TRACK_REF pin) and the tracking voltage is selected by the REF_SEL pin. If REF_SEL is tied High (5 V) then V is tracked. If REF_SEL is left open then V TRK_REF DD5 is tracked. There is an internal pull-down on REF_SEL. The tracking supplies are intended to drive loads that are external to the ECU so they are short circuit protected with the current limited. The outputs of the tracking regulators also withstand short circuit to the battery. A short circuit to GND, continuous or intermittent on one tracking supply will not affect any other supply, including the preregulator output voltage V . In addition to these requirements, B all sensor supplies shall be capable of operating with up to a 15 μF load on the supply line. This load may be present during initial startup, or be applied after the supply has been powered up. In either case, the application of this load shall not cause the tracking regulators to be permanently disabled. VSB, VSC and VSD regulators can be disabled with VS_EN pin. 5.5 VKAM and VSTBY linear regulators These two outputs are fully integrated low quiescent current low drop out regulators. The input VBAT is used as the source of these supplies. These outputs are operational during both standby and run mode; these are the only outputs operational during standby (V not BAT present). The VKAM regulator has two programmable levels: 1.0 V (VPROG1 pin connected to GND) or 1.5 V (if this pin is left open, an internal pull-up is present). The V regulator has two programmable levels: 2.6 V (VPROG2 pin connected to GND) STBY or 3.3 V (if this pin is left open, an internal pull-up is present). The STBY_OK pin indicates when the V is out of range (voltage below the threshold STBY indicated in the electrical characteristic table). Once driven low it should stay low for a minimal amount of time allowing external circuitry to latch. 22/30 DocID14273 Rev 5

L9758 Functional description 5.6 RESET monitors RST5 is the reset signal tied to the V supply. This is an open collector active low signal DD5 that pulls low when V is out of range. DD5 RSTL is the reset signal for the V supply. This is an open collector active low signal that DDL pulls low when V is out of range. RST5 and RSTL are also driven low when STBY_OK DDL pin is driven low, regardless of the status of V and V . DD5 DDL Reset Delay is the time duration from when the output (V or V ) is within range to DD5 DDL when the reset pin (RST5 or RSTL) is released. RST5 and RSTL use separate timers. This delay is programmable via an external resistor connected to RST_TIM pin. A value of 4 .7kΩ corresponds to 1 ms and 47 kΩ to 10 ms. All values in between are linear approximated. The timer delay is common however the attack and release times are only dependant on the condition of the respective supplies (V or V ). DD5 DDL 5.7 Thermal protection The tracking regulators incorporate thermal limit with shutdown. When the junction temperature reaches the shutdown threshold, if there is a tracking regulator in current limitation, it switches off and all the other regulators stay on. When the temperature decreases the regulator restarts. The over temperature shutdown has a hysteresis to avoid thermal pumping. 5.8 Reference current The L9758 provides a DC voltage at the REXT pin. An external resistor to ground creates a reference current which is mirrored internally for use in the device. The reference current is used to supply all the analog blocks and to charge and discharge an integrated capacitor to generate a 5 MHz clock for the switching functionality. Figure 3. Current reference generator (cid:44)(cid:44)(cid:85)(cid:85)(cid:72)(cid:72)(cid:73)(cid:73) (cid:14)(cid:14) (cid:44)(cid:44)(cid:85)(cid:85)(cid:72)(cid:72)(cid:73)(cid:73) (cid:16)(cid:16) (cid:14)(cid:14) (cid:57)(cid:57) (cid:53)(cid:53)(cid:72)(cid:72)(cid:91)(cid:91)(cid:87)(cid:87) (cid:16)(cid:16) (cid:85)(cid:85)(cid:72)(cid:72)(cid:73)(cid:73) (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:28)(cid:19)(cid:27)(cid:20)(cid:25)(cid:19)(cid:26)(cid:21)(cid:26)(cid:51)(cid:54) The circuit is designed for a 10 kΩ resistor. For all affected parameters, this resistor value is mentioned in the electrical characteristics section. DocID14273 Rev 5 23/30 29

Operating modes L9758 6 Operating modes There are two modes of operation of the power supply: standby and run mode. However during RUN mode, there are three input voltage regions: low voltage, normal voltage and high voltage. A brief definition and description of each of these operating regions is described below. 6.1 Standby mode STANDBY mode is defined by the following conditions:  VBAT is within the required voltage range  VBAT_SW may or may not be present  IGN is in the OFF state  PSU_EN is not asserted by the microprocessor During standby mode, all functions are shutdown except the two standby supplies, VKAM and VSTBY, and the circuitry monitoring IGN and PSU_EN. During standby mode, current consumption is minimized. The standby functions are powered from VBAT. There is no currents drawn from VBAT_SW or any other input except those required to perform the standby functions. Outputs, other than IGN_ON are disabled, sourcing nor sinking current. 6.2 Run mode RUN mode is defined by the following conditions:  VBAT is within the required range  VBAT_SW is within the required range  Either IGN is in the Run state and/or PSU_EN is in the active state During RUN mode, all functions can be enabled. All functions listed above, with the exception of the standby functions, are powered by VBAT_SW. If VBAT is not present, the circuit is fully running with the exception of PSU_EN and the standby functions (VKAM and VSTBY). In this condition the entry into the RUN MODE can only be performed by the IGN pin and the circuit is kept running until IGN pin is pulled low. 6.2.1 Entry into RUN mode RUN mode is entered when at least one of the two signals IGN_SW or PSU_EN goes in the active state. These two signals may be applied in any order or simultaneously. When the IGN input is valid, the active low IGN_ON signal is asserted. The design of VDD5, VDDL and VCORE regulators limits the slew rate of the output voltages during the start-up as indicated in the electrical characteristic table and ensures that V is always greater than V and V . DD5 DDL CORE As indicated in F igure4, the switching regulator starts first with soft start control or reduced current limitation. When the VB voltage reaches the VDDL_ENUP threshold all the linear regulators start with controlled slew-rate. The slew-rate control is done controlling the slew 24/30 DocID14273 Rev 5

L9758 Operating modes rate of the common voltage reference so the slew is different for each regulator because all start together and reach the steady-state at the same time but with different voltage levels. 6.3 Power down The power down sequence starts when both IGN and PSU_EN signal are low. In this phase there is no control of the linear regulator output voltages. The falling slew-rate is defined from load currents and load capacitors. A voltage comparator controls VDDL voltage and ensures that the VDDL supply voltage will drop below 2V before initiating a new power-up sequence. Figure 4. Power up/down sequence (cid:44)(cid:42)(cid:49) (cid:82)(cid:85) (cid:51)(cid:54)(cid:56)(cid:66)(cid:40)(cid:49) (cid:57)(cid:87)(cid:75)(cid:66)(cid:54)(cid:87)(cid:68)(cid:85)(cid:87) (cid:57)(cid:37) (cid:54)(cid:82)(cid:73)(cid:87)(cid:3)(cid:86)(cid:87)(cid:68)(cid:85)(cid:87) (cid:57)(cid:39)(cid:39)(cid:24) (cid:54)(cid:79)(cid:72)(cid:90)(cid:3)(cid:85)(cid:68)(cid:87)(cid:72) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79) (cid:57)(cid:39)(cid:39)(cid:47) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40) (cid:44)(cid:81)(cid:71)(cid:88)(cid:70)(cid:87)(cid:82)(cid:85)(cid:3) (cid:70)(cid:88)(cid:85)(cid:85)(cid:72)(cid:81)(cid:87) (cid:38)(cid:88)(cid:85)(cid:85)(cid:72)(cid:81)(cid:87) (cid:79)(cid:76)(cid:80)(cid:76)(cid:87)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:53)(cid:54)(cid:55)(cid:24) (cid:53)(cid:54)(cid:55)(cid:47) (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:28)(cid:19)(cid:27)(cid:20)(cid:25)(cid:19)(cid:26)(cid:22)(cid:21)(cid:51)(cid:54) DocID14273 Rev 5 25/30 29

Operating modes L9758 6.4 Low voltage operation When L9758 is up and running it is fully operational with the VBAT and VBAT_SW pin voltages down to V . When L9758 is up and running and the supply voltages are less LVI_LOW than 5.5 V and are grater than or equal to V if the boost option is used the device is LVI_LOW fully operational. If only the buck regulator is used the L9758 operates as follows:  Switching regulator runs at 100% duty cycle;  VKAM and VSTBY regulators are fully operational;  VDDL fully operational;  VCORE fully operational;  VDD5 out of range with output voltage no less than 3.2 V;  Tracking regulators out of range with output voltages no less than 3.2 V;  Reset monitor RST5 and RSTL fully operational, with reset at RST5 pin is allowed. 6.5 High voltage operation The L9758 is fully operational during jump start when the battery is temporarily replaced with a higher voltage source to aid starting the engine (26.5 V for 1 minute). The L9758 is fully operational during positive battery transient such as load dump (40 V maximum voltage with durations of up to 400 ms). 26/30 DocID14273 Rev 5

L9758 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 PowerSO-36 package information Figure 5. PowerSO-36 package outline (cid:49) (cid:49) (cid:68)(cid:21) (cid:70) (cid:68)(cid:20) (cid:69) (cid:72) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:36) (cid:72)(cid:22) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:37) (cid:40) (cid:39) (cid:79)(cid:72)(cid:68)(cid:71) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:3)(cid:36) (cid:36) (cid:39) (cid:39) (cid:49) (cid:49) (cid:42) (cid:42) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:22)(cid:25) (cid:20)(cid:28) (cid:68)(cid:22) (cid:86)(cid:79)(cid:88)(cid:74) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:37) (cid:22) (cid:37) (cid:40) (cid:40)(cid:21) (cid:40)(cid:20) (cid:42)(cid:36)(cid:42)(cid:40) (cid:19)(cid:17)(cid:22)(cid:24) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:39)(cid:20) (cid:20) (cid:20)(cid:27) (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:39) (cid:39) (cid:42)(cid:49) (cid:42)(cid:49) (cid:42) (cid:38) (cid:11)(cid:38)(cid:50)(cid:51)(cid:47)(cid:36)(cid:49)(cid:36)(cid:53)(cid:44)(cid:55)(cid:60)(cid:12) (cid:75)(cid:91)(cid:23)(cid:24)(cid:131) (cid:69) (cid:19)(cid:17)(cid:20)(cid:21)(cid:3)(cid:3)(cid:48)(cid:36)(cid:3)(cid:3)(cid:37) (cid:19)(cid:19)(cid:28)(cid:25)(cid:20)(cid:20)(cid:28)(cid:66)(cid:41)(cid:66)(cid:27)(cid:38) (cid:42)(cid:36)(cid:39)(cid:42)(cid:20)(cid:28)(cid:19)(cid:27)(cid:20)(cid:25)(cid:19)(cid:27)(cid:21)(cid:26)(cid:51)(cid:54) DocID14273 Rev 5 27/30 29

Package information L9758 T able 20. PowerSO-36 package mechanical data Dimensions Ref Millimeters Inches(1) Min. Typ. Max. Min. Typ. Max. A - - 3.60 - - 0.1417 a1 0.10 - 0.30 0.0039 0.0118 a2 - 3.30 - - 0.1299 a3 0 - 0.10 - - 0.0039 b 0.22 - 0.38 0.0087 - 0.0150 c 0.23 - 0.32 0.0091 - 0.0126 D(2) 15.80 - 16.00 0.6220 - 0.6299 D1 9.40 - 9.80 0.3701 - 0.3858 E 13.90 - 14.5 0.5472 - 0.5709 E1(2) 10.90 - 11.10 0.4291 - 0.4370 E2 - - 2.90 - - 0.1142 E3 5.80 - 6.20 0.2283 - 0.2441 e - 0.65 - - 0.0256 - e3 - 11.05 - - 0.4350 - G 0 - 0.10 0 - 0.0039 H 15.50 - 15.90 0.6102 - 0.6260 h - - 1.10 - - 0.0433 L 0.8 - 1.10 0.0315 - 0.0433 N 10° (max) s 8° (max) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15 mm (0.006”). Critical dimensions are "a3", "E" and "G".. 28/30 DocID14273 Rev 5

L9758 Revision history 8 Revision history Table 21. Document revision history Date Revision Changes 12-Dec-2007 1 Initial release. Updated S ection1: Pins configuration. Updated F igure2: Functional block diagram. Updated S ection3: Operating conditions. Updated Ta ble7: General DC characteristics and T able12: VCORE linear regulator. 17-Nov-2010 2 Added S ection5.1: General function. Updated S ection5.2: Switching pre-regulator, S ection5.6: RESET monitors and S ection5.8: Reference current. Updated S ection5.3: VDD5, VDDL and VCORE linear regulators on page21. Update Ta ble10, T able11, T able12, T able13 and 23-Nov-2010 3 Ta ble14. 20-Sep-2013 4 Updated disclaimer. Updated: – Title in cover page (added ‘Automotive’); – Features on page1 (added ‘AEC-Q100 qualified’ and 06-Sep-2016 5 car icon); – Ta ble1: Device summary on page1. – Ta ble7: General DC characteristics on page12 – Package information on page27. DocID14273 Rev 5 29/30 29

L9758 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 30/30 DocID14273 Rev 5