L6564 10-pin transition mode PFC controller Datasheet - production data  Inductor saturation protection  AC brownout detection  Low ( ≤100 µA) start-up current  6 mA max. operating bias current  1% (at T = 25 °C) internal reference voltage J  -600/+800 mA totem pole gate driver with SSOP10 active pull-down during UVLO  SSOP10 package Features Applications  Fast “bidirectional” input voltage feed-forward  PFC preregulators for: (1/V2 correction) – High-end AC-DC adapter/charger  Accurate adjustable output overvoltage – Desktop PC, server, web server protection – IEC61000-3-2 or JEITA-MITI compliant  Protection against feedback loop SMPS disconnection (latched shutdown)  SMPS for LED luminaires Figure 1. Block diagram (cid:3) (cid:61)(cid:61)(cid:38)(cid:38)(cid:39)(cid:39) (cid:57)(cid:57)(cid:70)(cid:70)(cid:70)(cid:70) (cid:26)(cid:26) (cid:20)(cid:20)(cid:19)(cid:19) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:50)(cid:50)(cid:46)(cid:46) (cid:25)(cid:25) (cid:19)(cid:19)(cid:19)(cid:19)(cid:17)(cid:17)(cid:17)(cid:17)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:17)(cid:17)(cid:17)(cid:17)(cid:26)(cid:26)(cid:22)(cid:22)(cid:24)(cid:23)(cid:24)(cid:23)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57) (cid:14)(cid:14)(cid:16)(cid:16)(cid:16)(cid:16) (cid:39)(cid:39)(cid:50)(cid:50)(cid:76)(cid:76)(cid:57)(cid:57)(cid:86)(cid:86)(cid:51)(cid:51)(cid:68)(cid:68)(cid:69)(cid:69)(cid:79)(cid:79)(cid:72)(cid:72) (cid:47)(cid:47)(cid:66)(cid:66)(cid:50)(cid:50)(cid:57)(cid:57)(cid:51)(cid:51)(cid:19)(cid:19)(cid:20)(cid:20)(cid:17)(cid:17)(cid:17)(cid:17)(cid:26)(cid:26)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:57) (cid:61)(cid:61)(cid:39)(cid:39)(cid:72)(cid:72)(cid:72)(cid:72)(cid:85)(cid:85)(cid:87)(cid:87)(cid:82)(cid:82)(cid:14)(cid:14)(cid:72)(cid:72)(cid:16)(cid:16)(cid:3)(cid:3)(cid:70)(cid:70)(cid:38)(cid:38)(cid:87)(cid:87)(cid:88)(cid:88)(cid:82)(cid:82)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:81)(cid:81)(cid:87)(cid:87) (cid:44)(cid:44)(cid:81)(cid:81)(cid:85)(cid:85)(cid:72)(cid:72)(cid:87)(cid:87)(cid:57)(cid:57)(cid:72)(cid:72)(cid:73)(cid:73)(cid:72)(cid:72)(cid:82)(cid:82)(cid:85)(cid:85)(cid:85)(cid:85)(cid:81)(cid:81)(cid:79)(cid:79)(cid:72)(cid:72)(cid:87)(cid:87)(cid:68)(cid:68)(cid:68)(cid:68)(cid:81)(cid:81)(cid:79)(cid:79)(cid:74)(cid:74)(cid:3)(cid:3)(cid:70)(cid:70)(cid:54)(cid:54)(cid:72)(cid:72)(cid:72)(cid:72)(cid:88)(cid:88)(cid:86)(cid:86)(cid:83)(cid:83)(cid:83)(cid:83)(cid:79)(cid:79)(cid:92)(cid:92)(cid:3)(cid:3)(cid:37)(cid:37)(cid:171)(cid:171)(cid:88)(cid:88)(cid:86)(cid:86) (cid:53)(cid:53)(cid:53)(cid:40)(cid:40)(cid:40)(cid:57)(cid:57)(cid:57)(cid:42)(cid:42)(cid:42)(cid:50)(cid:50)(cid:50)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55)(cid:47)(cid:47)(cid:47)(cid:36)(cid:36)(cid:36)(cid:36)(cid:36)(cid:36)(cid:42)(cid:42)(cid:42)(cid:55)(cid:55)(cid:55)(cid:50)(cid:50)(cid:50)(cid:40)(cid:40)(cid:40)(cid:53)(cid:53)(cid:53) (cid:56)(cid:56)(cid:56)(cid:56)(cid:56)(cid:56)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57)(cid:57)(cid:47)(cid:47)(cid:47)(cid:47)(cid:47)(cid:47)(cid:50)(cid:50)(cid:50)(cid:50)(cid:50)(cid:50) (cid:14)(cid:14) (cid:54)(cid:54)(cid:54)(cid:54) (cid:52)(cid:52)(cid:52)(cid:52)(cid:20)(cid:20)(cid:20)(cid:20) (cid:28)(cid:28) (cid:42)(cid:42)(cid:39)(cid:39) (cid:20)(cid:20)(cid:17)(cid:17)(cid:25)(cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:57)(cid:57) (cid:14)(cid:14) (cid:53)(cid:53)(cid:53)(cid:53) (cid:39)(cid:39)(cid:53)(cid:53)(cid:44)(cid:44)(cid:57)(cid:57)(cid:40)(cid:40)(cid:53)(cid:53) (cid:16)(cid:16) (cid:9)(cid:9)(cid:3)(cid:3)(cid:38)(cid:38)(cid:47)(cid:47)(cid:36)(cid:36)(cid:48)(cid:48)(cid:51)(cid:51) (cid:54)(cid:54)(cid:55)(cid:55)(cid:36)(cid:36)(cid:53)(cid:53)(cid:55)(cid:55)(cid:40)(cid:40)(cid:53)(cid:53) (cid:54)(cid:54)(cid:87)(cid:87)(cid:68)(cid:68)(cid:85)(cid:85)(cid:87)(cid:87)(cid:72)(cid:72)(cid:85)(cid:85) (cid:50)(cid:50)(cid:41)(cid:41)(cid:41)(cid:41) (cid:21)(cid:21) (cid:38)(cid:38)(cid:50)(cid:50)(cid:48)(cid:48)(cid:51)(cid:51) (cid:39)(cid:39)(cid:44)(cid:44)(cid:54)(cid:54)(cid:36)(cid:36)(cid:37)(cid:37)(cid:47)(cid:47)(cid:40)(cid:40) (cid:39)(cid:39)(cid:76)(cid:76)(cid:86)(cid:86)(cid:68)(cid:68)(cid:69)(cid:69)(cid:79)(cid:79)(cid:72)(cid:72) (cid:52)(cid:52)(cid:52) (cid:54)(cid:54)(cid:54) (cid:47)(cid:47)(cid:66)(cid:66)(cid:50)(cid:50)(cid:57)(cid:57)(cid:51)(cid:51) (cid:44)(cid:44)(cid:49)(cid:49)(cid:57)(cid:57) (cid:20)(cid:20) (cid:16)(cid:16)(cid:16) (cid:52)(cid:52)(cid:20)(cid:20) (cid:47)(cid:47)(cid:40)(cid:40)(cid:37)(cid:37) (cid:50)(cid:50)(cid:49)(cid:49)(cid:18)(cid:18)(cid:50)(cid:50)(cid:41)(cid:41)(cid:41)(cid:41)(cid:3)(cid:3)(cid:38)(cid:38)(cid:82)(cid:82)(cid:50)(cid:50)(cid:81)(cid:81)(cid:87)(cid:87)(cid:57)(cid:57)(cid:85)(cid:85)(cid:82)(cid:82)(cid:51)(cid:51)(cid:79)(cid:79) (cid:53)(cid:53)(cid:53) (cid:56)(cid:56)(cid:57)(cid:57)(cid:47)(cid:47)(cid:50)(cid:50) (cid:21)(cid:21)(cid:17)(cid:17)(cid:24)(cid:24)(cid:3)(cid:3)(cid:57)(cid:57) (cid:14)(cid:14)(cid:14) (cid:40)(cid:40)(cid:85)(cid:85)(cid:85)(cid:85)(cid:82)(cid:82)(cid:85)(cid:85)(cid:3)(cid:3)(cid:36)(cid:36)(cid:80)(cid:80)(cid:83)(cid:83)(cid:79)(cid:79)(cid:76)(cid:76)(cid:73)(cid:73)(cid:76)(cid:76)(cid:72)(cid:72)(cid:85)(cid:85) (cid:48)(cid:48)(cid:56)(cid:56)(cid:47)(cid:47)(cid:55)(cid:55) (cid:22)(cid:22) (cid:42)(cid:42)(cid:49)(cid:49)(cid:39)(cid:39) (cid:27)(cid:27) (cid:16)(cid:16)(cid:16) (cid:16)(cid:16) (cid:14)(cid:14) (cid:20)(cid:20)(cid:18)(cid:18)(cid:57)(cid:57)(cid:21)(cid:21) (cid:48)(cid:48)(cid:56)(cid:56)(cid:47)(cid:47)(cid:55)(cid:55)(cid:44)(cid:44)(cid:51)(cid:51)(cid:47)(cid:47)(cid:44)(cid:44)(cid:40)(cid:40)(cid:53)(cid:53) (cid:44)(cid:44)(cid:71)(cid:71)(cid:72)(cid:72)(cid:68)(cid:68)(cid:79)(cid:79)(cid:3)(cid:3)(cid:85)(cid:85)(cid:72)(cid:72)(cid:70)(cid:70)(cid:87)(cid:87)(cid:76)(cid:76)(cid:73)(cid:73)(cid:76)(cid:76)(cid:72)(cid:72)(cid:85)(cid:85) (cid:14)(cid:14)(cid:14) (cid:38)(cid:38)(cid:54)(cid:54) (cid:23)(cid:23) (cid:50)(cid:50)(cid:49)(cid:49)(cid:18)(cid:18)(cid:50)(cid:50)(cid:41)(cid:41)(cid:41)(cid:41)(cid:3)(cid:3)(cid:38)(cid:38)(cid:82)(cid:82)(cid:81)(cid:81)(cid:87)(cid:87)(cid:85)(cid:85)(cid:82)(cid:82)(cid:79)(cid:79) (cid:14)(cid:14)(cid:16)(cid:16) (cid:19)(cid:19)(cid:19)(cid:19)(cid:17)(cid:17)(cid:17)(cid:17)(cid:27)(cid:27)(cid:27)(cid:27)(cid:3)(cid:27)(cid:3)(cid:27)(cid:57)(cid:57)(cid:3)(cid:3)(cid:57)(cid:57) (cid:48)(cid:48)(cid:39)(cid:39)(cid:36)(cid:36)(cid:40)(cid:40)(cid:44)(cid:44)(cid:49)(cid:49)(cid:55)(cid:55)(cid:40)(cid:40)(cid:54)(cid:54)(cid:38)(cid:38)(cid:3)(cid:3)(cid:39)(cid:39)(cid:55)(cid:55)(cid:53)(cid:53)(cid:50)(cid:50)(cid:50)(cid:50)(cid:53)(cid:53)(cid:51)(cid:51) (cid:20)(cid:20)(cid:17)(cid:17)(cid:26)(cid:26)(cid:3)(cid:3)(cid:57)(cid:57) (cid:14)(cid:14)(cid:16)(cid:16) (cid:39)(cid:39)(cid:76)(cid:76)(cid:86)(cid:86)(cid:68)(cid:68)(cid:69)(cid:69)(cid:79)(cid:79)(cid:72)(cid:72) (cid:24)(cid:24) (cid:57)(cid:57)(cid:41)(cid:41)(cid:41)(cid:41) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:26)(cid:23)(cid:89)(cid:20) September 2013 DocID16202 Rev 5 1/33 This is information on a product in full production. www.st.com

Contents L6564 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Voltage feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . 25 7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 DocID16202 Rev 5

L6564 List of tables List of tables Table 1. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Summary of L6564 idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. SSOP10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID16202 Rev 5 3/33 33

List of figures L6564 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. IC consumption vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CC Figure 4. IC consumption vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 J Figure 5. V Zener voltage vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CC J Figure 6. Startup and UVLO vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 J Figure 7. Feedback reference vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 J Figure 8. E/A output clamp levels vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 J Figure 9. UVLO saturation vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 J Figure 10. OVP levels vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 J Figure 11. Inductor saturation threshold vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 J Figure 12. Vcs clamp vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 J Figure 13. ZCD sink/source capability vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 J Figure 14. ZCD clamp level vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 J Figure 15. R discharge vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 J Figure 16. Line drop detection threshold vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 J Figure 17. V - V dropout vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MULTpk VFF J Figure 18. PFC_OK threshold vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 J Figure 19. PFC_OK FFD threshold vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 J Figure 20. Multiplier characteristics at V = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FF Figure 21. Multiplier characteristics at V = 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FF Figure 22. Multiplier gain vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 J Figure 23. Gate drive clamp vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 J Figure 24. Gate drive output saturation vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 J Figure 25. Delay to output vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 J Figure 26. Start-up timer period vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 J Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18 Figure 28. Voltage feed-forward: squarer-divider (1/V2) block diagram and transfer characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 29. R · C as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21 FF FF Figure 30. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 31. THD optimization: standard TM PFC controller (left side) and L6564 (right side) . . . . . . . 23 Figure 32. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24 Figure 33. Interface circuits that let dc-dc converter's controller IC disable the L6564 . . . . . . . . . . . . 25 Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic . . . . . . . . 27 Figure 35. L6564 100W TM PFC: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . . . . . . . . . 28 Figure 36. L6564 100W TM PFC: compliance to JEITA-MITI standard. . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 37. L6564 100 W TM PFC: input current waveform at 230 - 50 Hz - 100 W load. . . . . . . . . . . 28 Figure 38. L6564 100W TM PFC: input current waveform at 100 V - 50 Hz - 100 W load . . . . . . . . . 28 Figure 39. SSOP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/33 DocID16202 Rev 5

L6564 Description 1 Description The L6564 device is a current mode PFC controller operating in transition mode (TM) and represents the compact version of the L6563S device as it embeds the same driver, reference and control stages in a very compact 10-pin SSOP10 package. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide range mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage mode error amplifier and an accurate (1% at T = 25 °C) internal voltage reference. The loop stability is optimized by the voltage J feed-forward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (“bidirectional”). In addition to overvoltage protection able to control the output voltage during transient conditions, the IC also provides protection against feedback loop failures or erroneous settings. Other on-board protection functions allow brownout conditions and boost inductor saturation to be safely handled. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for the high power MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that require compliance with the EN61000-3-2 and JEITA-MITI standards. DocID16202 Rev 5 5/33 33

Maximum ratings L6564 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Pin Parameter Value Unit V 10 IC supply voltage (I  20 mA) Self-limited V CC CC --- 1, 3, 6 Max. pin voltage (I 1 mA) Self-limited V pin --- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V -10 (source) I 7 Zero current detector max. current mA ZCD 10 (sink) V pin 5 Maximum withstanding voltage range +/- 1750 V FF test condition: CDF-AEC-Q100-002 1 to 4 Other pins “human body model” +/- 2000 V 6 to 10 Acceptance criteria: “normal performance” 2.2 Thermal data Table 2. Thermal data Symbol Parameter Value Unit R Max. thermal resistance, junction-to-ambient 120 °C/W thJA Ptot Power dissipation at T = 50 °C 0.75 W A T Junction temperature operating range -40 to 150 °C J T Storage temperature -55 to 150 °C stg 6/33 DocID16202 Rev 5

L6564 Pin connection 3 Pin connection Figure 2. Pin connection (cid:44)(cid:44)(cid:49)(cid:49)(cid:57)(cid:57) (cid:20)(cid:20) (cid:20)(cid:20)(cid:19)(cid:19) (cid:57)(cid:57)(cid:70)(cid:70)(cid:70)(cid:70) (cid:38)(cid:38)(cid:50)(cid:50)(cid:48)(cid:48)(cid:51)(cid:51) (cid:21)(cid:21) (cid:28)(cid:28) (cid:42)(cid:42)(cid:39)(cid:39) (cid:48)(cid:48)(cid:56)(cid:56)(cid:47)(cid:47)(cid:55)(cid:55) (cid:22)(cid:22) (cid:27)(cid:27) (cid:42)(cid:42)(cid:49)(cid:49)(cid:39)(cid:39) (cid:38)(cid:38)(cid:54)(cid:54) (cid:23)(cid:23) (cid:26)(cid:26) (cid:61)(cid:61)(cid:38)(cid:38)(cid:39)(cid:39) (cid:57)(cid:57)(cid:41)(cid:41)(cid:41)(cid:41) (cid:24)(cid:24) (cid:25)(cid:25) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:50)(cid:50)(cid:46)(cid:46) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:26)(cid:24)(cid:89)(cid:20) Table 3. Pin description N° Name Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator 1 INV is fed into the pin through a resistor divider. The pin normally features high impedance. Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 2 COMP To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output will be inhibited (burst-mode operation). Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider 3 MULT and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. 4 CS A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never 5 V connect the pin directly to GND but with a resistor ranging from 100 K (minimum) to 2 M FF (maximum). This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The IC restarts as the voltage at the pin goes above 0.88 V. DocID16202 Rev 5 7/33 33

Pin connection L6564 Table 3. Pin description (continued) N° Name Function PFC preregulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC preregulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V, 6 PFC_OK a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling V . bringing its value lower than 6 V before to move up to Turn-on CC threshold. If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. Boost inductor’s demagnetization sensing input for transition mode operation. A negative-going 7 ZCD edge triggers MOSFET’s turn-on. 8 GND Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive the Power MOSFET’s and IGBT’s 9 GD with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. Supply Voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass 10 V capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the CC IC. 8/33 DocID16202 Rev 5

L6564 Electrical characteristics 4 Electrical characteristics T = -25 to 125 °C, V = 12 V, C = 1 nF between the pin GD and GND, C = 1 µF and J CC O FF R = 1 M between the pin V and GND; unless otherwise specified. FF FF Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage V Operating range After turn-on 10.3 22.5 V CC V Turn-on threshold (1) 11 12 13 V CCOn V Turn-off threshold (1) 8.7 9.5 10.3 V CCOff V V for resuming from latch OVP latched 5 6 7 V CCrestart CC Hys Hysteresis 2.3 2.7 V V Zener voltage I = 20 mA 22.5 25 28 V Z CC Supply current I Start-up current Before turn-on, V = 10 V 90 150 µA start-up CC I Quiescent current After turn-on, V = 1 V 4 5 mA q MULT I Operating supply current At 70 kHz 5 6.0 mA CC V > V AND V < V 180 280 µA PFC_OK PFC_OK_S INV FFD I Idle state quiescent current qdis V < V 1.5 2.2 mA PFC_OK PFC_OK_D I Quiescent current V > V OR V < 2.3 V 2.2 3 mA q PFC_OK PFC_OK_S COMP Multiplier input I Input bias current V = 0 to 3 V -0.2 -1 µA MULT MULT V Linear operation range 0 to 3 V MULT V Internal clamp level I = 1 mA 9 9.5 V CLAMP MULT Vcs V = 0 to 0.4 V, V = 1 V Output max. slope MULT VFF 1.33 1.66 V/V ∆VMULT VCOMP = upper clamp K Gain(2) V = 1 V, V = 4 V 0.375 0.45 0.525 1/V M MULT COMP Error amplifier Voltage feedback input TJ = 25 °C 2.475 2.5 2.525 V V INV threshold 10.3 V < V < 22.5 V(3) 2.455 2.545 CC Line regulation V = 10.3 V to 22.5 V 2 5 mV CC I Input bias current V = 0 to 4 V -0.2 -1 µA INV INV V Internal clamp level I = 1 mA 8 9 V INVCLAMP INV Gv Voltage gain Open loop 60 80 dB GB Gain-bandwidth product 1 MHz DocID16202 Rev 5 9/33 33

Electrical characteristics L6564 Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Source current V = 4 V, V = 2.4 V 2 4 mA COMP INV I COMP Sink current V = 4 V, V = 2.6 V 2.5 4.5 mA COMP INV Upper clamp voltage I = 0.5 mA 5.7 6.2 6.7 SOURCE V Burst-mode voltage (3) 2.3 2.4 2.5 V COMP Lower clamp voltage I = 0.5 mA(3) 2.1 2.25 2.4 SINK Boost inductor saturation detector V Threshold on current sense (3) 1.6 1.7 1.8 V CS_th I E/A input pull-up current After V > V , before restarting 5 10 13 µA INV CS CS_th Start-up timer t Start-up delay First cycle after wakeup 25 50 75 µs START_DEL 75 150 300 t Timer period µs START Restart after V > V 150 300 600 CS CS_th Current sense comparator I Input bias current V = 0 1 µA CS CS t Leading edge blanking 100 150 250 ns LEB td Delay to output 100 200 300 ns (H-L) V Current sense reference VCOMP = upper clamp, 1.0 1.08 1.16 V CSclamp clamp V =1 V, V = 1 V MULT VFF V = 0, V = 3 V 40 70 MULT VFF Vcs Current sense offset mV ofst V = 3 V, V = 3 V 20 MULT VFF PFC_OK functions I Input bias current V = 0 to 2.6 V -0.1 -1 µA PFC_OK PFC_OK V Clamp voltage I = 1 mA 9 9.5 V PFC_OK_C PFC_OK V OVP threshold (1) voltage rising 2.435 2.5 2.565 V PFC_OK_S V Restart threshold after OVP (1) voltage falling 2.34 2.4 2.46 V PFC_OK_R V Disable threshold (1) voltage falling 0.12 0.35 V PFC_OK_D V Disable threshold (1) voltage falling T = 25 °C 0.17 0.23 0.29 V PFC_OK_D J V Enable threshold (1) voltage rising 0.15 0.38 V PFC_OK_E V Enable threshold (1) voltage rising T = 25 °C 0.21 0.27 0.32 V PFC_OK_E J Feedback failure detection V V = V 1.61 1.66 1.71 V FFD threshold (V falling) PFC_OK PFC_OK_S INV 10/33 DocID16202 Rev 5

L6564 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Voltage feed-forward V Linear operation range 1 3 V VFF V < V 800 CC CCOn V Dropout V -V mV MULTpk VFF V > or = to V 20 CC CCOn ∆V Line drop detection thresh. Below peak value 40 70 100 mV VFF ∆V Line drop detection thresh. Below peak value T = 25 °C 50 70 90 mV VFF J T = 25 °C 7.5 10 12.5 J R Internal discharge resistor k DISCH 5 20 V Disable threshold (2) voltage falling 0.745 0.8 0.855 V DIS V Enable threshold (2) voltage rising 0.845 0.88 0.915 V EN Zero current detector V Upper clamp voltage I = 2.5 mA 5.0 5.7 V ZCDH ZCD V Lower clamp voltage I = - 2.5 mA -0.3 0 0.3 V ZCDL ZCD Arming voltage V 1.1 1.4 1.9 V ZCDA (positive-going edge) Triggering voltage V 0.5 0.7 0.9 V ZCDT (negative-going edge) I Input bias current V = 1 to 4.5 V 1 µA ZCDb ZCD I Source current capability -2.5 -4 mA ZCDsrc I Sink current capability 2.5 5 mA ZCDsnk Gate driver V Output low voltage I = 100 mA 0.6 1.2 V OL sink V Output high voltage I = 5 mA 9.8 10.3 V OH source I Peak source current -0.6 A srcpk I Peak sink current 0.8 A snkpk t Voltage fall time 30 60 ns f t Voltage rise time 45 110 ns r V Output clamp voltage I = 5 mA; V = 20 V 10 12 15 V Oclamp source CC UVLO saturation V = 0 to V , I = 2 mA 1.1 V CC CCon sink 1. Parameters tracking each other   V  V 2.5 MULT COMP 2. The multiplier output is given by: Vcs  VCS_Ofst KM 2 V 3. Parameters tracking each other VFF DocID16202 Rev 5 11/33 33

Typical electrical performance L6564 5 Typical electrical performance Figure 3. IC consumption vs. V Figure 4. IC consumption vs. T CC J     100 10 Operating 10 Quiescent Disabled or 1 during OVP Icc [mA]0.11 CfT =jo 7==01 2kn5HF°zC c current (mA) VCf =oC7C =0= k11Hn2FVz Latched off I 0.1 0.01 Before Start up VccOFF VccON 0.001 0.01 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 150 175 Vcc [V] Tj (C) Figure 5. V Zener voltage vs. T Figure 6. Startup and UVLO vs. T CC J J     28 13 12 VCC-ON 27 11 26 10 VCC-OFF V25 V 9 24 8 23 7 22 6 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) 12/33 DocID16202 Rev 5

L6564 Typical electrical performance Figure 7. Feedback reference vs. T Figure 8. E/A output clamp levels vs. T J J     2.6 7 Uper Clamp 6 VCC = 12V 2.55 5 VCC = 12V NV (V) 2.5 MP (V) 4 pin I VCO 3 Lower Clamp 2 2.45 1 2.4 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 9. UVLO saturation vs. T Figure 10. OVP levels vs. T J J     1 2.5 0.9 2.48 VCC = 0V 0.8 OVP Th 2.46 0.7 0.6 els (V) 2.44 v e V 0.5 OK l _ 2.42 C 0.4 PF 2.4 0.3 Restart Th 0.2 2.38 0.1 2.36 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) DocID16202 Rev 5 13/33 33

Typical electrical performance L6564 Figure 11. Inductor saturation threshold vs. T Figure 12. Vcs clamp vs. T J J     1.9 1.4 1.8 1.7 1.3 1.6 VCC = 12V S pin (V) 1.5 CSx (V)1.2 VCOMP =Upper clamp C V 1.4 1.3 1.1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 13. ZCD sink/source capability vs. T Figure 14. ZCD clamp level vs. T J J     8 7 Sink current 6 Upper Clamp 6 4 5 Dsrc (mA) 02 VCC = 12V D pin (V)34 VIzCcCd == ±122.V5mV C C IZ-2 VZ2 Source current -4 1 Lower Clamp -6 0 -8 -1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) 14/33 DocID16202 Rev 5

L6564 Typical electrical performance Figure 15. R discharge vs. T Figure 16. Line drop detection threshold vs. T J J     20 90 18 80 16 70 14 60 12 50 Ohm 10 mV k 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 17. V - V dropout vs. T Figure 18. PFC_OK threshold vs. T MULTpk VFF J J     2 0.4 1.5 0.35 1 0.3 0.5 0.25 (mV) 0 Th (V)0.2 ON -0.5 0.15 OFF -1 0.1 -1.5 0.05 -2 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 19. PFC_OK FFD threshold vs. T J   2 1.9 1.8 D Th (V)1.7 VFF 1.6 1.5 1.4 -50 -25 0 25 50 75 100 125 150 175 Tj(C) DocID16202 Rev 5 15/33 33

Typical electrical performance L6564 Figure 20. Multiplier characteristics at V = 1 V Figure 21. Multiplier characteristics at V = 3 V FF FF     1.2 700 VCOMP 1.1 VCOMP Upper voltage clamp 600 1 5.5 Upper voltage 5.0V 0.9 4.5V 500 0.8 5.5V VCS (V)000...567 4.0V VCS (mV)340000 45..50VV 0.4 3.5V 4.0V 200 0.3 3.5V 0.2 3.0 100 3.0V 0.1 2.6V 2.6V 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 0.5 1 1.5 2 2.5 3 3.5 VMULT (V) VMULT (V) Figure 22. Multiplier gain vs. T Figure 23. Gate drive clamp vs. T J J     0.5 12.9 VCC = 20V 12.85 0.4 12.8 Gain (1/V) VVVCCMCOU M=LT P1 =2=V V4FVF = 1V V 12.75 0.3 12.7 0.2 12.65 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) 16/33 DocID16202 Rev 5

L6564 Typical electrical performance Figure 24. Gate drive output saturation vs. T Figure 25. Delay to output vs. T J J   12 300 High level 10 250 8 s)200 V 6 D(H-L) (n VCC = 12V T150 4 100 2 Low level 0 50 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 26. Start-up timer period vs. T J   450 After OCP 400 350 300 us)250 e ( Tim200 Timer 150 100 First Cicle 50 0 -50 -25 0 25 50 75 100 125 150 175 Tj (C) DocID16202 Rev 5 17/33 33

Application information L6564 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage V of the PFC preregulator close O to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure27). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum V that can be expected. O Example: V = 400 V, V = 434 V. Select: R3 = 8.8 M; then: R4 = 8.8 M· 2.5/(434-2.5) = 51 k. O OX When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Notice that the R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both the INV and PFC_OK pins. Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram (cid:3) (cid:57)(cid:57)(cid:82)(cid:82)(cid:88)(cid:88)(cid:87)(cid:87) (cid:53)(cid:53)(cid:22)(cid:22)(cid:68)(cid:68) (cid:53)(cid:53)(cid:22)(cid:22) (cid:53)(cid:53)(cid:22)(cid:22)(cid:69)(cid:69) (cid:19)(cid:19)(cid:19)(cid:19)(cid:17)(cid:17)(cid:17)(cid:17)(cid:21)(cid:21)(cid:21)(cid:21)(cid:22)(cid:26)(cid:22)(cid:26)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:57) (cid:14)(cid:14) (cid:39)(cid:39)(cid:76)(cid:76)(cid:86)(cid:86)(cid:68)(cid:68)(cid:69)(cid:69)(cid:79)(cid:79)(cid:72)(cid:72) (cid:26)(cid:26) (cid:16)(cid:16) (cid:53)(cid:53)(cid:20)(cid:20)(cid:68)(cid:68) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:50)(cid:50)(cid:46)(cid:46) (cid:21)(cid:21)(cid:21)(cid:21)(cid:17)(cid:17)(cid:17)(cid:17)(cid:24)(cid:23)(cid:24)(cid:23)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:57) (cid:16)(cid:16) (cid:50)(cid:50)(cid:57)(cid:57)(cid:51)(cid:51) (cid:47)(cid:47)(cid:66)(cid:66)(cid:50)(cid:50)(cid:57)(cid:57)(cid:51)(cid:51) (cid:14)(cid:14) (cid:53)(cid:53)(cid:20)(cid:20) (cid:53)(cid:53)(cid:20)(cid:20)(cid:69)(cid:69) (cid:20)(cid:20)(cid:17)(cid:17)(cid:25)(cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:57)(cid:57) (cid:14)(cid:14) (cid:16)(cid:16) (cid:41)(cid:41)(cid:85)(cid:85)(cid:72)(cid:72)(cid:84)(cid:84)(cid:88)(cid:88)(cid:72)(cid:72)(cid:81)(cid:81)(cid:70)(cid:70)(cid:92)(cid:92) (cid:38)(cid:38)(cid:50)(cid:50)(cid:48)(cid:48)(cid:51)(cid:51) (cid:21)(cid:21) (cid:70)(cid:70)(cid:82)(cid:82)(cid:80)(cid:80)(cid:83)(cid:83)(cid:72)(cid:72)(cid:81)(cid:81)(cid:86)(cid:86)(cid:68)(cid:68)(cid:87)(cid:87)(cid:76)(cid:76)(cid:82)(cid:82)(cid:81)(cid:81) (cid:16)(cid:16)(cid:16) (cid:20)(cid:20) (cid:44)(cid:44)(cid:49)(cid:49)(cid:57)(cid:57) (cid:21)(cid:21)(cid:17)(cid:17)(cid:24)(cid:24)(cid:3)(cid:3)(cid:57)(cid:57) (cid:14)(cid:14)(cid:14) (cid:40)(cid:40)(cid:85)(cid:85)(cid:85)(cid:85)(cid:82)(cid:82)(cid:85)(cid:85)(cid:3)(cid:3)(cid:36)(cid:36)(cid:80)(cid:80)(cid:83)(cid:83)(cid:79)(cid:79)(cid:76)(cid:76)(cid:73)(cid:73)(cid:76)(cid:76)(cid:72)(cid:72)(cid:85)(cid:85) (cid:53)(cid:53)(cid:23)(cid:23) (cid:53)(cid:53)(cid:21)(cid:21) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:24)(cid:25)(cid:89)(cid:20) 18/33 DocID16202 Rev 5

L6564 Application information 6.2 Feedback failure protection (FFP) The OVP function described above handles “normal” overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, the comparator detects the voltage at the INV pin. If the voltage is lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the V voltage of the L6564 device goes below 6 V. CC The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.23 V will shut down the IC, reducing its consumption below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either the resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the preregulator. 6.3 Voltage feed-forward The power stage gain of PFC preregulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-off in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means having fc 4 Hz at 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feed-forward can compensate for the gain variation with the line voltage and allow minimizing all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure28). DocID16202 Rev 5 19/33 33

Application information L6564 Figure 28. Voltage feed-forward: squarer-divider (1/V2) block diagram and transfer characteristic (cid:3) (cid:53)(cid:53)(cid:53)(cid:72)(cid:72)(cid:72)(cid:70)(cid:70)(cid:70)(cid:87)(cid:87)(cid:87)(cid:76)(cid:76)(cid:76)(cid:73)(cid:73)(cid:73)(cid:76)(cid:76)(cid:76)(cid:72)(cid:72)(cid:72)(cid:71)(cid:71)(cid:71)(cid:3)(cid:3)(cid:3)(cid:80)(cid:80)(cid:80)(cid:68)(cid:68)(cid:68)(cid:76)(cid:76)(cid:76)(cid:81)(cid:81)(cid:81)(cid:86)(cid:86)(cid:86) (cid:57)(cid:57)(cid:57)(cid:70)(cid:70)(cid:70)(cid:86)(cid:86)(cid:86)(cid:91)(cid:91)(cid:91) (cid:21)(cid:21)(cid:21) (cid:40)(cid:40)(cid:40)(cid:18)(cid:18)(cid:18)(cid:36)(cid:36)(cid:36)(cid:3)(cid:3)(cid:3)(cid:82)(cid:82)(cid:82)(cid:88)(cid:88)(cid:88)(cid:87)(cid:87)(cid:87)(cid:83)(cid:83)(cid:83)(cid:88)(cid:88)(cid:88)(cid:87)(cid:87)(cid:87) (cid:70)(cid:70)(cid:70)(cid:88)(cid:88)(cid:88)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:87)(cid:87)(cid:87) (cid:11)(cid:11)(cid:11)(cid:57)(cid:57)(cid:57)(cid:38)(cid:38)(cid:38)(cid:50)(cid:50)(cid:50)(cid:48)(cid:48)(cid:48)(cid:51)(cid:51)(cid:51)(cid:12)(cid:12)(cid:12) (cid:47)(cid:47)(cid:47)(cid:25)(cid:25)(cid:25)(cid:24)(cid:24)(cid:24)(cid:25)(cid:25)(cid:25)(cid:22)(cid:22)(cid:23)(cid:43)(cid:43) (cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:72)(cid:72)(cid:72)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:70)(cid:70)(cid:70)(cid:72)(cid:72)(cid:72) (cid:11)(cid:11)(cid:11)(cid:57)(cid:57)(cid:57)(cid:70)(cid:70)(cid:70)(cid:86)(cid:86)(cid:86)(cid:91)(cid:91)(cid:91)(cid:12)(cid:12)(cid:12) (cid:48)(cid:48)(cid:48)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55)(cid:44)(cid:44)(cid:44)(cid:51)(cid:51)(cid:51)(cid:47)(cid:47)(cid:47)(cid:44)(cid:44)(cid:44)(cid:40)(cid:40)(cid:40)(cid:53)(cid:53)(cid:53) (cid:20)(cid:20)(cid:20)(cid:17)(cid:17)(cid:17)(cid:24)(cid:24)(cid:24) (cid:57)(cid:57)(cid:57)(cid:38)(cid:38)(cid:38)(cid:50)(cid:50)(cid:50)(cid:48)(cid:48)(cid:48)(cid:51)(cid:51)(cid:51)(cid:32)(cid:32)(cid:32)(cid:23)(cid:23)(cid:23)(cid:57)(cid:57)(cid:57)(cid:3)(cid:3)(cid:3) (cid:5)(cid:5)(cid:5)(cid:76)(cid:76)(cid:76)(cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72)(cid:68)(cid:68)(cid:68)(cid:79)(cid:79)(cid:79)(cid:5)(cid:5)(cid:5)(cid:3)(cid:3)(cid:3)(cid:71)(cid:71)(cid:71)(cid:76)(cid:76)(cid:76)(cid:82)(cid:82)(cid:82)(cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72) (cid:36)(cid:36)(cid:36)(cid:70)(cid:70)(cid:70)(cid:87)(cid:87)(cid:87)(cid:88)(cid:88)(cid:88)(cid:68)(cid:68)(cid:68)(cid:79)(cid:79)(cid:79) (cid:44)(cid:44)(cid:44)(cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72)(cid:68)(cid:68)(cid:68)(cid:79)(cid:79)(cid:79) (cid:16)(cid:16)(cid:16) (cid:20)(cid:20)(cid:20)(cid:18)(cid:18)(cid:18)(cid:57)(cid:57)(cid:57) (cid:21)(cid:21)(cid:21) (cid:22)(cid:22)(cid:22) (cid:20)(cid:20)(cid:20) (cid:14)(cid:14)(cid:14) (cid:48)(cid:48)(cid:48)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55) (cid:28)(cid:28)(cid:28)(cid:17)(cid:17)(cid:17)(cid:24)(cid:24)(cid:24)(cid:57)(cid:57)(cid:57) (cid:48)(cid:48)(cid:48)(cid:36)(cid:36)(cid:36)(cid:44)(cid:44)(cid:44)(cid:49)(cid:49)(cid:49)(cid:54)(cid:54)(cid:54)(cid:3)(cid:3)(cid:3)(cid:39)(cid:39)(cid:39)(cid:53)(cid:53)(cid:53)(cid:50)(cid:50)(cid:50)(cid:51)(cid:51)(cid:51) (cid:19)(cid:19)(cid:19)(cid:17)(cid:17)(cid:17)(cid:24)(cid:24)(cid:24) (cid:39)(cid:39)(cid:39)(cid:40)(cid:40)(cid:40)(cid:55)(cid:55)(cid:55)(cid:40)(cid:40)(cid:40)(cid:38)(cid:38)(cid:38)(cid:55)(cid:55)(cid:55)(cid:50)(cid:50)(cid:50)(cid:53)(cid:53)(cid:53) (cid:24)(cid:24)(cid:24) (cid:57)(cid:57)(cid:57)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41) (cid:19)(cid:19)(cid:19) (cid:19)(cid:19)(cid:19) (cid:19)(cid:19)(cid:19)(cid:17)(cid:17)(cid:17)(cid:27)(cid:27)(cid:27) (cid:20)(cid:20)(cid:20) (cid:21)(cid:21)(cid:21) (cid:22)(cid:22)(cid:22) (cid:23)(cid:23)(cid:23) (cid:38)(cid:38)(cid:38)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41) (cid:53)(cid:53)(cid:53)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41) (cid:57)(cid:57)(cid:57)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:32)(cid:32)(cid:32)(cid:57)(cid:57)(cid:57)(cid:48)(cid:48)(cid:48)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:24)(cid:26)(cid:89)(cid:20) In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the preregulator's output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6564 device realizes a NEW voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor C and FF a resistor RFF, both connected from the pin V (#5) to ground, complete an internal peak- FF holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). In this way, in case of sudden line voltage rise, C will be rapidly FF charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges C avoiding long settling time before reaching the new voltage level. The discharge of C FF FF is stopped as its voltage equals the voltage on the pin MULT or if the voltage on the pin V FF falls below 0.88 V, to prevent the “Brownout protection” function from being improperly activated (see Section6.6: Power management/housekeeping functions on page25). As a result of the V pin functionality, an acceptably low steady-state ripple and low current FF distortion can be achieved with a limited undershoot or overshoot on the preregulator's output. 20/33 DocID16202 Rev 5

L6564 Application information The twice-mains-frequency (2 fL) ripple appearing across CFF is triangular with a peak-to- peak amplitude that, with good approximation, is given by: Equation 1 2V MULTpk V  FF 14fR C L FF FF where f is the line frequency. The amount of 3rd harmonic distortion introduced by this L ripple, related to the amplitude of its 2fL component, will be: Equation 2 100 D % 3 2fR C L FF FF Figure29 shows a diagram that helps choose the time constant R · C based on the FF FF amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for the time constant R · C below which improper activation of the V fast discharge may FF FF FF occur. In fact, the twice-mains-frequency ripple across C under steady state conditions FF must be lower than the minimum line drop detection threshold (V = 40 mV). FF_min Therefore: Equation 3 V 2 MULTpk_max 1 V R C  VFF_min FF FF 4f L_min Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 29. R · C as a function of 3rd harmonic distortion introduced in the input FF FF current   10 1 f = 50 Hz L R · C [s] FF FF 0.1 f = 60 Hz L 0.01 0.1 1 10 D % 3 DocID16202 Rev 5 21/33 33

Application information L6564 6.4 THD optimizer circuit The L6564 device is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high- frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC preregulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure30 shows the internal block diagram of the THD optimizer circuit. Figure 30. THD optimizer circuit (cid:87)(cid:87)(cid:87) (cid:87)(cid:87)(cid:87) (cid:87)(cid:87)(cid:87) (cid:21)(cid:21)(cid:21)(cid:21) (cid:20)(cid:20)(cid:20)(cid:20)(cid:3)(cid:3)(cid:3)(cid:3)(cid:18)(cid:18)(cid:18)(cid:18)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:57) (cid:38)(cid:38)(cid:38)(cid:50)(cid:50)(cid:50)(cid:48)(cid:48)(cid:48)(cid:51)(cid:51)(cid:51) (cid:57)(cid:57)(cid:57)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41) (cid:14)(cid:14)(cid:14) (cid:87)(cid:87)(cid:87)(cid:82)(cid:82)(cid:82)(cid:3)(cid:3)(cid:3)(cid:51)(cid:51)(cid:51)(cid:58)(cid:58)(cid:58)(cid:48)(cid:48)(cid:48) (cid:48)(cid:48)(cid:48)(cid:48)(cid:56)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55)(cid:55)(cid:44)(cid:44)(cid:44)(cid:44)(cid:51)(cid:51)(cid:51)(cid:51)(cid:47)(cid:47)(cid:47)(cid:47)(cid:44)(cid:44)(cid:44)(cid:44)(cid:40)(cid:40)(cid:40)(cid:40)(cid:53)(cid:53)(cid:53)(cid:53) (cid:70)(cid:70)(cid:70)(cid:82)(cid:82)(cid:82)(cid:80)(cid:80)(cid:80)(cid:83)(cid:83)(cid:83)(cid:68)(cid:68)(cid:68)(cid:85)(cid:85)(cid:85)(cid:68)(cid:68)(cid:68)(cid:87)(cid:87)(cid:87)(cid:82)(cid:82)(cid:82)(cid:85)(cid:85)(cid:85) (cid:48)(cid:48)(cid:48)(cid:56)(cid:56)(cid:56)(cid:47)(cid:47)(cid:47)(cid:55)(cid:55)(cid:55) (cid:14)(cid:14)(cid:14) (cid:87)(cid:87)(cid:87) (cid:50)(cid:50)(cid:50)(cid:50)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:41)(cid:54)(cid:54)(cid:54)(cid:54)(cid:40)(cid:40)(cid:40)(cid:40)(cid:55)(cid:55)(cid:55)(cid:55) (cid:87)(cid:87)(cid:87) (cid:42)(cid:42)(cid:42)(cid:42)(cid:40)(cid:40)(cid:40)(cid:40)(cid:49)(cid:49)(cid:49)(cid:49)(cid:40)(cid:40)(cid:40)(cid:40)(cid:53)(cid:53)(cid:53)(cid:53)(cid:36)(cid:36)(cid:36)(cid:36)(cid:55)(cid:55)(cid:55)(cid:55)(cid:50)(cid:50)(cid:50)(cid:50)(cid:53)(cid:53)(cid:53)(cid:53) (cid:35)(cid:35)(cid:35)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:68)(cid:68)(cid:68)(cid:70)(cid:70)(cid:70)(cid:20)(cid:20)(cid:20) (cid:35)(cid:35)(cid:35)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:68)(cid:68)(cid:68)(cid:70)(cid:70)(cid:70)(cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:33)(cid:33)(cid:33)(cid:3)(cid:3)(cid:3)(cid:57)(cid:57)(cid:57)(cid:68)(cid:68)(cid:68)(cid:70)(cid:70)(cid:70)(cid:20)(cid:20)(cid:20) (cid:87)(cid:87)(cid:87) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:24)(cid:27)(cid:89)(cid:20) 22/33 DocID16202 Rev 5

L6564 Application information Figure 31. THD optimization: standard TM PFC controller (left side) and L6564 (right side)   Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current MOSFET's draVind vroaltiange MOSFET's draiVn dvorlatainge Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the V pin (see Section6.3: Voltage feed-forward) so as to FF have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure31, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC preregulator - thus reducing the effectiveness of the optimizer circuit. 6.5 Inductor saturation detection Boost inductor's hard saturation may be a fatal event for a PFC preregulator: the current up- slope becomes so large (50 - 100 times steeper, see Figure32) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. DocID16202 Rev 5 23/33 33

Application information L6564 However, in some applications such as ac-dc adapters, where the PFC preregulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6564 device is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC will be attempted to restart by the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, the system safety will be considerably increased. Figure 32. Effect of boost inductor saturation on the MOSFET current and detection method 24/33 DocID16202 Rev 5

L6564 Application information 6.6 Power management/housekeeping functions A communication line with the control IC of the cascaded dc-dc converter can be established via the disable function included in the PFC_OK pin (see Section6.2: Feedback failure protection (FFP) on page19 for more details). Typically this line is used to allow the PWM controller of the cascaded dc-dc converter to shut down the L6564 device in case of light load and to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like those are shown in Figure32. Needless to say, this operation assumes that the cascaded dc-dc converter stage works as the master and the PFC stage as the slave or, in other words, that the dc-dc stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. Figure 33. Interface circuits that let dc-dc converter's controller IC disable the L6564 (cid:3) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:25)(cid:25)(cid:25)(cid:25)(cid:36)(cid:36) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:25)(cid:25)(cid:23)(cid:23) (cid:57)(cid:57)(cid:38)(cid:38)(cid:38)(cid:38) (cid:24)(cid:24) (cid:25)(cid:25) (cid:57)(cid:57)(cid:38)(cid:38)(cid:38)(cid:38)(cid:66)(cid:66)(cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38) (cid:57)(cid:57)(cid:38)(cid:38)(cid:38)(cid:38) (cid:20)(cid:20)(cid:19)(cid:19) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:50)(cid:50)(cid:46)(cid:46) (cid:25)(cid:25) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:28)(cid:28)(cid:28)(cid:28)(cid:36)(cid:36) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:25)(cid:25)(cid:23)(cid:23) (cid:28)(cid:28) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:54)(cid:54)(cid:55)(cid:55)(cid:50)(cid:50)(cid:51)(cid:51) (cid:3) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:50)(cid:50)(cid:46)(cid:46) (cid:25)(cid:25) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:28)(cid:28)(cid:20)(cid:20) (cid:47)(cid:47)(cid:25)(cid:25)(cid:24)(cid:24)(cid:25)(cid:25)(cid:23)(cid:23) (cid:27)(cid:27) (cid:51)(cid:51)(cid:41)(cid:41)(cid:38)(cid:38)(cid:66)(cid:66)(cid:54)(cid:54)(cid:55)(cid:55)(cid:50)(cid:50)(cid:51)(cid:51) (cid:36)(cid:48)(cid:19)(cid:21)(cid:21)(cid:25)(cid:20)(cid:89)(cid:20) Another function available is the brownout protection which is basically a not-latched shutdown function that is activated when a condition of mains under voltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC preregulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. Brownout threshold is internally fixed at 0.8 V and is sensed on pin V FF (5) during the voltage falling and 80 mV threshold hysteresis prevents from rebounding at input voltage turn off. In Table5 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. DocID16202 Rev 5 25/33 33

Application information L6564 Table 5. Summary of L6564 idle states Typical IC Condition Caused or revealed bey IC behavior Restart condition consumption UVLO V < V Disabled V > V 90 µA CC CCOff CC CCOn PFC_OK > V PFC_OK_S V < V then Feedback disconnected AND Latched CC CCrestart 180 µA V > V INV < 1.66 V CC CCOn Standby PFC_OK < V Stop switching PFC_OK > V 1.5 mA PFC_OK_D PFC_OK_E AC brownout V < V Stop switching RUN > V 1.5 mA FF DIS EN OVP PFC_OK > V Stop switching PFC_OK < V 2.2 mA PFC_OK_S PFC_OK_R Low consumption COMP < 2.4 V Burst mode COMP > 2.4 V 2.2 mA Saturated Vcs > V Doubled T Auto restart 2.2 mA boost inductor CS_th start 26/33 DocID16202 Rev 5

L6564 Application examples and ideas 7 Application examples and ideas Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic (cid:41)(cid:20) (cid:47)(cid:21) (cid:39)(cid:21) (cid:48)(cid:46)(cid:39)(cid:54)(cid:3)(cid:20)(cid:15)(cid:24)(cid:45)(cid:18)(cid:3)(cid:20)(cid:22)(cid:16)(cid:24)(cid:15)(cid:19)(cid:27) (cid:41)(cid:56)(cid:54)(cid:40)(cid:3)(cid:23)(cid:36) (cid:43)(cid:41)(cid:21)(cid:27)(cid:21)(cid:25)(cid:16)(cid:21)(cid:47)(cid:19)(cid:20)(cid:22)(cid:60)(cid:20)(cid:53)(cid:24)(cid:16)(cid:55)(cid:19)(cid:20) (cid:42)(cid:37)(cid:39)(cid:56)(cid:20)(cid:23)(cid:45) (cid:54)(cid:53)(cid:58)(cid:21)(cid:25)(cid:21)(cid:19)(cid:51)(cid:52)(cid:16)(cid:59)(cid:59)(cid:59)(cid:57)(cid:19)(cid:19)(cid:21) (cid:20)(cid:49)(cid:23)(cid:19)(cid:19)(cid:24) (cid:49)(cid:55)(cid:53)(cid:38)(cid:20)(cid:3)(cid:21)(cid:53)(cid:24)(cid:16)(cid:54)(cid:21)(cid:22)(cid:26) (cid:48)(cid:46)(cid:45)(cid:39)(cid:21)(cid:54)(cid:3)(cid:20)(cid:15)(cid:24)(cid:18)(cid:3)(cid:21)(cid:16)(cid:24)(cid:15)(cid:19)(cid:27) (cid:22) (cid:20) (cid:21) (cid:97) (cid:14) (cid:25) (cid:24) (cid:20) (cid:21) (cid:27) (cid:22) (cid:54)(cid:55)(cid:39)(cid:55)(cid:43)(cid:22)(cid:21)(cid:47)(cid:19)(cid:25) (cid:21) (cid:28)(cid:19)(cid:16)(cid:21)(cid:25)(cid:23)(cid:57)(cid:68)(cid:70)(cid:20) (cid:23)(cid:26)(cid:38)(cid:19)(cid:49)(cid:20) (cid:23) (cid:22) (cid:97) (cid:66) (cid:23)(cid:26)(cid:38)(cid:19)(cid:24)(cid:49)(cid:3)(cid:16)(cid:3)(cid:23)(cid:19)(cid:19)(cid:57) (cid:23)(cid:38)(cid:26)(cid:25)(cid:88)(cid:41)(cid:3)(cid:16)(cid:3)(cid:23)(cid:24)(cid:19)(cid:57) (cid:53)(cid:22) (cid:38)(cid:23)(cid:26)(cid:23)(cid:19)(cid:49) (cid:38)(cid:23)(cid:49)(cid:26)(cid:26) (cid:53)(cid:20)(cid:19)(cid:23)(cid:19)(cid:53) (cid:47)(cid:47)(cid:39)(cid:23)(cid:20)(cid:23)(cid:23)(cid:27) (cid:53)(cid:20)(cid:48)(cid:21)(cid:19) (cid:22)(cid:48)(cid:22) (cid:39)(cid:24) (cid:37)(cid:61)(cid:59)(cid:26)(cid:28)(cid:16)(cid:38)(cid:20)(cid:27) (cid:53)(cid:25) (cid:22)(cid:48)(cid:22) (cid:53)(cid:24) (cid:53)(cid:20)(cid:27)(cid:26)(cid:19)(cid:46) (cid:25)(cid:27)(cid:46) (cid:53)(cid:20)(cid:48)(cid:27)(cid:19) (cid:53)(cid:20)(cid:19) (cid:53)(cid:28) (cid:20)(cid:48)(cid:19) (cid:53)(cid:20)(cid:20) (cid:21)(cid:48)(cid:26) (cid:21)(cid:48)(cid:21) (cid:53)(cid:20)(cid:22) (cid:53)(cid:20)(cid:23) (cid:25)(cid:21)(cid:46) (cid:21)(cid:26)(cid:46) (cid:53)(cid:20)(cid:25) (cid:20)(cid:27)(cid:19)(cid:46) (cid:53)(cid:20)(cid:21) (cid:21)(cid:48)(cid:26) (cid:53)(cid:20)(cid:24) (cid:24)(cid:20)(cid:46) (cid:45)(cid:51)(cid:59)(cid:22) (cid:19)(cid:53)(cid:19) (cid:53)(cid:20)(cid:27) (cid:53)(cid:20)(cid:26) (cid:38)(cid:25)(cid:27)(cid:28)(cid:49) (cid:27)(cid:21)(cid:46) (cid:56)(cid:47)(cid:25)(cid:20)(cid:24)(cid:25)(cid:23) (cid:38)(cid:20)(cid:19) (cid:38)(cid:20)(cid:20) (cid:20)(cid:48)(cid:24) (cid:38)(cid:27) (cid:20)(cid:19)(cid:19)(cid:49) (cid:23)(cid:26)(cid:88)(cid:41)(cid:16)(cid:24)(cid:19)(cid:57) (cid:25)(cid:27)(cid:19)(cid:49) (cid:20) (cid:44)(cid:49)(cid:57) (cid:57)(cid:38)(cid:38) (cid:20)(cid:19) (cid:52)(cid:20) (cid:21) (cid:38)(cid:50)(cid:48)(cid:51) (cid:42)(cid:39) (cid:28) (cid:54)(cid:55)(cid:41)(cid:26)(cid:49)(cid:48)(cid:24)(cid:19)(cid:49) (cid:38)(cid:20)(cid:21) (cid:22) (cid:48)(cid:56)(cid:47)(cid:55) (cid:42)(cid:49)(cid:39) (cid:27) (cid:53)(cid:21)(cid:20) (cid:43)(cid:43)(cid:54)(cid:40)(cid:20)(cid:36)(cid:55)(cid:16)(cid:54)(cid:44)(cid:49)(cid:46) (cid:21)(cid:49)(cid:21) (cid:53)(cid:20)(cid:28) (cid:21)(cid:26)(cid:53) (cid:53)(cid:21)(cid:21) (cid:24)(cid:20)(cid:46) (cid:23) (cid:38)(cid:54) (cid:61)(cid:38)(cid:39) (cid:26) (cid:53)(cid:21)(cid:23) (cid:20)(cid:19)(cid:19)(cid:46) (cid:21)(cid:21)(cid:19)(cid:53) (cid:24) (cid:57)(cid:41)(cid:41) (cid:51)(cid:41)(cid:38)(cid:16)(cid:50)(cid:46) (cid:25) (cid:53)(cid:21)(cid:24) (cid:53)(cid:21)(cid:25) (cid:53)(cid:22)(cid:21) (cid:38)(cid:20)(cid:25) (cid:19)(cid:53)(cid:23)(cid:26) (cid:19)(cid:53)(cid:25)(cid:27) (cid:20)(cid:48)(cid:19) (cid:21)(cid:49)(cid:21) (cid:38)(cid:20)(cid:22) (cid:20)(cid:88)(cid:41) (cid:38)(cid:20)(cid:24) (cid:21)(cid:21)(cid:19)(cid:83) (cid:45)(cid:22) (cid:53)(cid:22)(cid:20) (cid:38)(cid:50)(cid:49)(cid:22) (cid:20)(cid:19)(cid:53) (cid:20) (cid:57)(cid:38)(cid:38) (cid:53)(cid:20)(cid:46)(cid:22)(cid:19) (cid:21) (cid:42)(cid:49)(cid:39) (cid:22) (cid:50)(cid:49)(cid:18)(cid:50)(cid:41)(cid:41) DocID16202 Rev 5 27/33 33

Application examples and ideas L6564 Figure 35. L6564 100W TM PFC: compliance to Figure 36. L6564 100W TM PFC: compliance to EN61000-3-2 standard JEITA-MITI standard   Measured value EN61000-3-2 class-D limits Measured value JEITA-MITI Class-D limits 1 10 A] 0.1 A] 1 ent [ ent [ 0.1 urr0.01 urr C C c c 0.01 ni ni o o m0.001 m Har Har0.001 0.0001 0.0001 1 3 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 1315 171921 2325 272931 33 35 37 39 Harmonic Order [n] Harmonic Order [n] Figure 37. L6564 100 W TM PFC: input current Figure 38. L6564 100W TM PFC: input current waveform at 230 - 50 Hz - 100 W load waveform at 100 V - 50 Hz - 100 W load 28/33 DocID16202 Rev 5

L6564 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 39. SSOP10 package outline 8140761 rev. A DocID16202 Rev 5 29/33 33

Package mechanical data L6564 Table 6. SSOP10 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 1.75 A1 0.10 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 4.80 4.90 5 E 5.80 6 6.20 E1 3.80 3.90 4 e 1 h 0.25 0.50 L 0.40 0.90 K 0° 8° 30/33 DocID16202 Rev 5

L6564 Order codes 9 Order codes Table 7. Ordering information Order codes Package Packing L6564D Tube SSOP10 L6564DTR Tape and reel DocID16202 Rev 5 31/33 33

Revision history L6564 10 Revision history Table 8. Document revision history Date Revision Changes 08-Sep-2009 1 Initial release. Updated: Figure1, Figure19, Figure27, Figure29, Table3, 23-Dec-2010 2 Table4, Table5, Chapter6.2, Chapter6.3. 28-Sep-2011 3 Updated: Table4, Chapter6.3 and Table6 20-Oct-2011 4 Updated: Chapter7 Corrected package name in Section1: Description on page5, titles of Figure39, Table6 and Table7, reversed order of Figure39 and 12-Sep-2013 5 Table6 in Section8: Package mechanical data on page29. Minor modifications throughout document. 32/33 DocID16202 Rev 5

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