L6562 TRANSITION-MODE PFC CONTROLLER 1 Features Figure 1. Packages ■ REALISED IN BCD TECHNOLOGY ■ TRANSITION-MODE CONTROL OF PFC PRE- REGULATORS ■ PROPRIETARY MULTIPLIER DESIGN FOR DIP-8 SO-8 MINIMUM THD OF AC INPUT CURRENT Table 1. Order Codes ■ VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION Part Number Package ■ ULTRA-LOW (≤70µA) START-UP CURRENT L6562N DIP-8 ■ LOW (≤4 mA) QUIESCENT CURRENT L6562D SO-8 ■ EXTENDED IC SUPPLY VOLTAGE RANGE L6562DTR Tape & Reel ■ ON-CHIP FILTER ON CURRENT SENSE ■ DISABLE FUNCTION DESKTOP PC, MONITOR) UP TO 300W ■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE – HI-END AC-DC ADAPTER/CHARGER VOLTAGE – ENTRY LEVEL SERVER & WEB SERVER ■ -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP 2 Description ■ DIP-8/SO-8 PACKAGES ECOPACK® The L6562 is a current-mode PFC controller oper- 1.1 APPLICATIONS ating in Transition Mode (TM). Pin-to-pin compati- ■ PFC PRE-REGULATORS FOR: ble with the predecessor L6561, it offers improved performance. – IEC61000-3-2 COMPLIANT SMPS (TV, Figure 2. Block Diagram COMP MULT CS 2 3 4 1 INV - MULTIPLIER AND 40K + THD OPTIMIZER 2.5V 5pF VOLTAGE OVERVOLTAGE - + REGULATOR DETECTION VCC 8 VCC INTERNAL SUPPLY 7V R Q 15 V 25 V S R1 7 GD + UVLO DRIVER R2 VREF2 - Sstatortper ZERO CURRENT DETECTOR + 2.1 V STARTER 1.6 V - DISABLE 6 5 GND ZCD Rev. 8 November 2005 1/16

L6562 2 Description (continued) The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25°C) internal voltage reference. The device features extremely low consumption (≤70 µA before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS- FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solu- tion for EN61000-3-2 compliant SMPS's up to 300W. Table 2. Absolute Maximum Ratings Symbol Pin Parameter Value Unit VCC 8 IC Supply voltage (Icc = 20 mA) self-limited V --- 1 to 4 Analog Inputs & Outputs -0.3 to 8 V IZCD 5 Zero Current Detector Max. Current -50 (source) mA 10 (sink) Ptot Power Dissipation @Tamb = 50°C (DIP-8) 1 W (SO-8) 0.65 Tj Junction Temperature Operating range -40 to 150 °C Tstg Storage Temperature -55 to 150 °C Figure 3. Pin Connection (Top view) INV 1 8 Vcc COMP 2 7 GD MULT 3 6 GND CS 4 5 ZCD Table 3. Thermal Data Symbol Parameter SO8 Minidip Unit Rth j-amb Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W 2/16

L6562 Table 4. Pin Description N° Pin Function 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre- regulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes. Table 5. Electrical Characteristics (T = -25 to 125°C, V = 12, C = 1 nF; unless otherwise specified) j CC O Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE VCC Operating range After turn-on 10.3 22 V VCCon Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V Hys Hysteresis 2.2 2.8 V VZ Zener Voltage ICC = 20 mA 22 25 28 V SUPPLY CURRENT Istart-up Start-up Current Before turn-on, VCC =11V 40 70 µA Iq Quiescent Current After turn-on 2.5 3.75 mA ICC Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During OVP (either static or 2.2 mA dynamic) or VZCD =150 mV MULTIPLIER INPUT IMULT Input Bias Current VVFF = 0 to 4 V -1 µA VMULT Linear Operation Range 0 to 3 V ∆V Output Max. Slope VMULT = 0 to 0.5V 1.65 1.9 V/V ∆----V--------C----S----- VCOMP = Upper clamp MULT K Gain (2) VMULT = 1 V, VCOMP = 4 V 0.5 0.6 0.7 1/V ERROR AMPLIFIER VINV Voltage Feedback Input Tj = 25 °C 2.465 2.5 2.535 V Threshold 10.3 V < Vcc < 22 V (1) 2.44 2.56 Line Regulation Vcc = 10.3 V to 22V 2 5 mV IINV Input Bias Current VINV = 0 to 3 V -1 µA 3/16

L6562 Table 5. Electrical Characteristics (continued) (T = -25 to 125°C, V = 12, C = 1 nF; unless otherwise specified) j CC O Symbol Parameter Test Condition Min. Typ. Max. Unit Gv Voltage Gain Open loop 60 80 dB GB Gain-Bandwidth Product 1 MHz ICOMP Source Current VCOMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 mA VCOMP Upper Clamp Voltage ISOURCE = 0.5 mA 5.3 5.7 6 V Lower Clamp Voltage ISINK = 0.5 mA (1) 2.1 2.25 2.4 V CURRENT SENSE COMPARATOR ICS Input Bias Current VCS = 0 -1 µA td(H-L) Delay to Output 200 350 ns VCS clamp Current sense reference clamp VCOMP = Upper clamp 1.6 1.7 1.8 V VCSoffset Current sense offset VMULT = 0 30 mV VMULT = 2.5V 5 ZERO CURRENT DETECTOR VZCDH Upper Clamp Voltage IZCD = 2.5 mA 5.0 5.7 6.5 V VZCDL Lower Clamp Voltage IZCD = -2.5 mA 0.3 0.65 1 V VZCDA Arming Voltage (3) 2.1 V (positive-going edge) VZCDT Triggering Voltage (3) 1.6 V (negative-going edge) IZCDb Input Bias Current VZCD = 1 to 4.5 V 2 µA IZCDsrc Source Current Capability -2.5 -5.5 mA IZCDsnk Sink Current Capability 2.5 mA VZCDdis Disable threshold 150 200 250 mV VZCDen Restart threshold 350 mV IZCDres Restart Current after Disable 30 75 µA STARTER tSTART Start Timer period 75 130 300 µs OUTPUT OVERVOLTAGE IOVP Dynamic OVP triggering current 35 40 45 µA Hys Hysteresis (3) 30 µA Static OVP threshold (1) 2.1 2.25 2.4 V GATE DRIVER VOH IGDsource = 20 mA 2 2.6 Dropout Voltage IGDsource = 200 mA 2.5 3 V VOL IGDsink = 200 mA 0.9 1.9 V tf Voltage Fall Time 30 70 ns tr Voltage Rise Time 40 80 ns VOclamp Output clamp voltage IGDsource = 5mA; Vcc = 20V 10 12 15 V UVLO saturation VCC = 0 to VCCon, Isink=10mA 1.1 V (1) All parameters are in tracking (2) The multiplier output is given by: V = K⋅V ⋅(V –2.5) cs MULT COMP (3) Parameters guaranteed by design, functionality tested in production. 4/16

L6562 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 6. IC consumption vs. T j ICC Icc 10 (mA) [mA] Operating 5 10 Quiescent 2 5 1 Disabled or 1 during OVP 0.5 0.5 Vcc = 12 V Co = 1 nF 0.1 0.2 f = 70 kHz 0.05 Co = 1nF 0.1 0.01 f = 70 kHz Before start-up 0.005 Tj= 25°C 0.05 0 0.02 0 5 10 15 20 25 -50 0 50 100 150 Vcc(V) Tj (°C) Figure 5. Start-up & UVLO vs. Tj Figure 7. Vcc Zener voltage vs. Tj 12.5 VccZ28 (V) VCC-ON (V) 12 27 11.5 26 11 25 10.5 24 10 VCC-OFF 9.5 23 (V) 9 22 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) 5/16

L6562 Figure 8. Feedback reference vs. T Figure 11. Delay-to-output vs. T j j VREF 2.6 tD(H-L)500 (V) (ns) Vcc = 12 V Vcc = 12 V 400 2.55 300 2.5 200 2.45 100 2.4 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) Figure 9. OVP current vs. T Figure 12. Multiplier characteristic j IOVP 41 VCS (pin 4) VCOMP (pin 2 ) (µA) (V) upper voltage (V) Vcc = 12 V clamp 1.6 3.5 5.0 40.5 1.4 5 4. 4.0 1.2 3.2 40 1.0 0.8 3.0 0.6 39.5 0.4 0.2 2.8 39 2.6 -50 0 50 100 150 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Tj (°C) VMULT( pin 3) (V) Figure 10. E/A output clamp levels vs. Tj Figure 13. Multiplier gain vs. Tj Vpin2 K 1 (V) 6 Vcc = 12 V Upper clamp 0.8 VCOMP =4 V 5 Vcc = 12 V VMULT =1V 0.6 4 0.4 3 0.2 Lower clamp 2 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) 6/16

L6562 Figure 14. Vcs clamp vs. T Figure 17. ZCD source capability vs. T j j VCSx 2 IZCDsrc0 (V) (mA) Vcc = 12 V VZCD= lower clamp 1.8 -2 1.6 -4 1.4 Vcc = 12 V -6 1.2 VCOMP= Upper clamp 1 -8 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) Figure 15. Start-up timer vs. T Figure 18. Gate-drive output low saturation j Tstart 150 Vpin7[V] (µs) Vcc = 12 V 4 Tj = 25 °C 140 Vcc = 11 V SINK 3 130 2 120 1 110 0 100 0 200 400 600 800 1,000 -50 0 50 100 150 I [mA] Tj (°C) GD Figure 16. ZCD clamp levels vs. T Figure 19. Gate-drive output high saturation j VZCD7 Vpin7[V] (V) -1.5 Upper clamp 6 Tj = 25 °C Vcc - 2.-02 Vcc = 11 V SOURCE 5 Vcc = 12 V IZCD= ±2.5 mA Vcc - -22.5.5 4 Vcc - 3.-03 3 Vcc - -33..55 2 Vcc - 4.-04 1 Lower clamp -4.5 0 0 100 200 300 400 500 600 700 -50 0 50 100 150 I [mA] GD Tj (°C) 7/16

L6562 Figure 20. Gate-drive clamp vs. T Figure 21. UVLO saturation vs. T j j Vpin7clamp Vpin7 15 1.1 (V) (V) Vcc = 20 V Vcc = 0 V 1 14 0.9 13 0.8 12 0.7 11 0.6 10 0.5 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) 4 Application Information 4.1 Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo- nents, the current through R1, I , equals that through R2, I . Considering that the non-inverting input of R1 R2 the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then: 2.5 Vo–2.5 I = -------- = I = ---------------------- . R2 R2 R1 R1 If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: Vo–2.5+∆Vo I' = ---------------------------------------- . R1 R1 The difference current ∆I =I' -I =I' -I =∆Vo/R1 will flow through the compensation network and en- R1 R1 R2 R1 R1 ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about 37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv- ered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is main- tained until the current falls below approximately 10 µA, which re-enables the internal starter and allows switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function is then: ∆Vo = R1⋅40⋅10–6 . An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ∆Vo. Since ∆Vo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400 V, ∆Vo = 40 V. Then: R1=40V/40µA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tol- erance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value. 8/16

L6562 When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nom- inal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier out- put will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its lin- ear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system. 4.2 THD optimizer circuit The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instan- taneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current MOSFET's drVaidn rvaoinltage MOSFET's draVind vraolitnage To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high- frequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key waveforms of a standard TM PFC controller are compared to those of the L6562. Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to 9/16

L6562 the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rec- tifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre- regulator - thus making the action of the optimizer circuit little effective. Figure 23. Typical application circuit (250W, Wide-range mains) D3 1N5406 T 18R0 4kΩ18R0 5kΩ 1ND41850 C5 12 nF R14 STTDH15L06 2N.5T CΩ R11 VPoo==420500VW 750 kΩ R1 D2 100 Ω R50 10 kΩ R12 1.5 MΩ 1N5248B R6 C3 2.2 µF 750 kΩ 68 kΩ BRIDGE FUSE + STBR606 41C0 µ01FV 68C02 3nF 5A/250V 1.5R M2Ω 8 5 2 1 R7 (85V t oV 2a6c5V) - 3 L65662 47 10 Ω 7 S°CT/PWM1 2OhNeSaMt 5si0nk 140C5006 µV F C2 10nF C29 22R k3Ω 2225 µVF 10C04 nF 0.R393 Ω 0R.3130Ω 9.5R31 3k Ω 1W 1W - Boost Inductor Spec: EB0057-C (COILCRAFT) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic T 18R0 4kΩ18R0 5kΩ 1ND48150 C5 12 nF R14 STTDH11L06 2N.5T CΩ R11 PVoo==8400W0V 750 kΩ R1 D2 100 Ω R50 12 kΩ R12 750 kΩ 1N5248B R6 C3 680 nF 750 kΩ 68 kΩ BRIDGE C1 C23 FUSE + DF06M 04.4070 µVF 330 nF 4A/250V 75R0 2kΩ 8 5 2 1 R7 33 Ω MOS C6 - 3 L6562 7 STP8NM50 47 µF Vac 450V (85V to 265V) 6 4 C2 10nF C29 10R k3Ω 2225 µVF 10C04 nF 0.R892 Ω 0R.8120Ω 9.R531 3k Ω 0.6 W 0.6 W - Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1 mm 10/16

L6562 Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) η (%) PF THD (%) 85 86.4 394.79 12.8 80.16 92.8 0.998 3.6 110 84.6 394.86 12.8 80.20 94.8 0.996 4.2 135 83.8 394.86 12.8 80.20 95.7 0.991 4.9 175 83.2 394.87 15.5 80.20 96.4 0.981 6.5 220 82.9 394.87 15.7 80.20 96.7 0.956 7.8 265 82.7 394.87 15.9 80.20 97.0 0.915 9.2 Note: measurements done with the line filter shown in figure 23 Table 7. EVAL6562N: Evaluation results at half load Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) η (%) PF THD (%) 85 42.8 394.86 6.6 40.20 93.9 0.994 5.5 110 42.5 394.90 6.6 40.20 94.6 0.985 6.2 135 42.5 394.91 6.7 40.20 94.6 0.967 7.1 175 42.5 394.93 8.0 40.19 94.6 0.939 8.3 220 42.6 394.94 8.2 40.19 94.3 0.869 9.8 265 42.6 394.94 8.3 40.19 94.3 0.776 11.4 Note: measurements done with the line filter shown in figure 23 11/16

L6562 Table 8. EVAL6562N: No-load measurements Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) 85 0.4 396.77 0.45 0 110 0.3 396.82 0.55 0 135 0.3 396.83 0.60 0 175 (*) 0.4 396.90 1.00 0 220 (*) 0.4 396.95 1.40 0 265 (*) 0.5 396.98 1.65 0 (*) Vcc = 12V supplied externally Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation B81133 B81133 to the AC to 470 nF, X2 680 nF, X2 source EVAL6562N EPCOS EPCOS B82732 47 mH, 1.3A EPCOS 12/16

L6562 5 Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 27. DIP-8 Mechanical Data & Package Dimensions mm inch DIM. OUTLINEAND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICALDATA A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 DIP-8 Z 1.52 0.060 13/16

L6562 Figure 28. SO-8 Mechanical Data & Package Dimensions mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 0˚ (min.), 8˚ (max.) ddd 0.10 0.004 Note: (1)Dimensions D does not include mold flash, protru- SO-8 sions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). 0016023 C 14/16

L6562 6 Revision History Table 9. Revision History Date Revision Description of Changes January 2004 5 First Issue June 2004 6 Modified the Style-look in compliance with the “Corporate Technical Publications Design Guide”. Changed input of the power amplifier connected to Multiplier (Fig. 2). May 2005 7 Modified Table 2: Absolute Maximim Ratings. November 2005 8 Added in Section 5 the ECOPACK® certicate of conformity. 15/16

L6562 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 16/16

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