L6230 DMOS driver for three-phase brushless DC motor Datasheet - production data Description The L6230 is a DMOS fully integrated three- phase motor driver with overcurrent protection, optimized for FOC application thanks to the independent current senses. PowerSO36 Realized in BCDmultipower technology, the device combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. An uncommitted comparator with open-drain output is available. Available in PowerSO36 and VFQFPN32 5 x 5 VFQFPN32 packages the L6230 device features non- dissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown. Features Table 1. Device summary  Operating supply voltage from 8 to 52 V Order codes Package Packaging  2.8 A output peak current (1.4 A RMS) L6230PD Tube  R 0.73  typ. value at T = 25 °C PowerSO36 DS(on) J L6230PDTR Tape and reel  Integrated fast freewheeling diodes L6230Q Tube  Operating frequency up to 100 kHz VFQFPN32 L6230QTR Tape and reel  Non-dissipative overcurrent detection and protection  Cross conduction protection  Diagnostic output  Uncommitted comparator  Thermal shutdown  Undervoltage lockout Application  BLDC motor driving  Sinusoidal / six-step driving  Field oriented control driving system August 2016 DocID18094 Rev 3 1/25 This is information on a product in full production. www.st.com

Contents L6230 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Six-step driving method with BEMF zero-crossing detection . . . . . . . . . . 18 6.4 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 DocID18094 Rev 3

L6230 Block diagram 1 Block diagram Figure 1. Block diagram (cid:28)(cid:12)(cid:22)(cid:22)(cid:26) (cid:28)(cid:25)(cid:11) (cid:28)(cid:12)(cid:22)(cid:22)(cid:26) (cid:28)(cid:12)(cid:22)(cid:22)(cid:26) (cid:28)(cid:13)(cid:23) (cid:13)(cid:17)(cid:11)(cid:24)(cid:16)(cid:15) (cid:26)(cid:17)(cid:15)(cid:24)(cid:20)(cid:11)(cid:19) (cid:23)(cid:27)(cid:20)(cid:23) (cid:23)(cid:24)(cid:22)(cid:26)(cid:15)(cid:13)(cid:26)(cid:18)(cid:22)(cid:21) (cid:22)(cid:13)(cid:14)(cid:5) (cid:22)(cid:27)(cid:26)(cid:5) (cid:22)(cid:13)(cid:14)(cid:5) (cid:5)(cid:4)(cid:1)(cid:28) (cid:22)(cid:13)(cid:14) (cid:22)(cid:13)(cid:14)(cid:6) (cid:22)(cid:13)(cid:14)(cid:7) (cid:25)(cid:15)(cid:21)(cid:25)(cid:15)(cid:5) (cid:14)(cid:18)(cid:11)(cid:16)(cid:3)(cid:15)(cid:21) (cid:28)(cid:12)(cid:22)(cid:22)(cid:26) (cid:22)(cid:13)(cid:14)(cid:6) (cid:22)(cid:27)(cid:26)(cid:6) (cid:18)(cid:21)(cid:5) (cid:16)(cid:11)(cid:26)(cid:15) (cid:5)(cid:4)(cid:1)(cid:28) (cid:19)(cid:22)(cid:16)(cid:18)(cid:13) (cid:15)(cid:21)(cid:5) (cid:18)(cid:21)(cid:6) (cid:15)(cid:21)(cid:6) (cid:25)(cid:15)(cid:21)(cid:25)(cid:15)(cid:6) (cid:18)(cid:21)(cid:7) (cid:28)(cid:12)(cid:22)(cid:22)(cid:26) (cid:28)(cid:25)(cid:12) (cid:15)(cid:21)(cid:7) (cid:5)(cid:4)(cid:1)(cid:28) (cid:9)(cid:1)(cid:28) (cid:22)(cid:13)(cid:14)(cid:7) (cid:22)(cid:27)(cid:26)(cid:7) (cid:5)(cid:4)(cid:1)(cid:28) (cid:28)(cid:22)(cid:19)(cid:26)(cid:11)(cid:16)(cid:15) (cid:24)(cid:15)(cid:16)(cid:27)(cid:19)(cid:11)(cid:26)(cid:22)(cid:24) (cid:25)(cid:15)(cid:21)(cid:25)(cid:15)(cid:7) (cid:13)(cid:23)(cid:22)(cid:27)(cid:26) (cid:2) (cid:13)(cid:23)(cid:2) (cid:3) (cid:13)(cid:23)(cid:3) (cid:13)(cid:22)(cid:20)(cid:23)(cid:11)(cid:24)(cid:11)(cid:26)(cid:22)(cid:24) (cid:11)(cid:20)(cid:4)(cid:7)(cid:10)(cid:10)(cid:8)(cid:9) DocID18094 Rev 3 3/25 25

Electrical data L6230 2 Electrical data 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Parameter Value Unit V Supply voltage VSA = VSB = V 60 V S S Differential voltage between: VSA, VSA = VSB = V = 60 V; V OUT1, OUT2, SENSE1, SENSE2 S 60 V OD V = GND and VSB, OUT3, SENSE3 SENSEx V Bootstrap peak voltage VSA = VSB = V V + 10 V BOOT S S V , V Logic inputs voltage range -0.3 to +7 V IN EN V , V Voltage range at CP- and CP+ pins -0.3 to +7 V CP- CP+ V Voltage range at SENSEx pins -1 to +4 V SENSE Pulsed supply current (for each VS VSA = VSB = V ; I S 3.55 A S(peak) pin) T < 1 ms PULSE RMS supply current (for each VS I VSA = VSB = V 1.4 A S pin) S Storage and operating temperature T , T -40 to 150 °C stg OP range 2.2 Recommended operating conditions Table 3. Recommended operating conditions Symbol Parameter Parameter Min Max Unit V Supply voltage VSA = VSB = V 8 52 V S S Differential voltage between VSA, VSA = VSB = VS; VOD OUT1A, OUT2A, SENSE1, SENSE2 VSENSE1 = VSENSE2 = 52 V and VSB, OUT1B, OUT2B, SENSE3 V SENSE3 V , V Voltage range at CP- and CP+ pins -0.1 5 V CP- CP+ Common mode voltage at the V 0 3 V CPCM comparator inputs pulsed t < t -6 6 V W rr V Voltage range at pins SENSEx SENSE DC -1 1 V I RMS output current 1.4 A OUT T Operating junction temperature -25 +125 °C J f Switching frequency 100 kHz sw 4/25 DocID18094 Rev 3

L6230 Electrical data 2.3 Thermal data Table 4. Thermal data Value Symbol Parameter Unit PowerSO36 VFQFPN32 R Maximum thermal resistance junction ambient(1) 36 - °C/W th(j-amb)1 R Maximum thermal resistance junction ambient(2) 16 - °C/W th(j-amb)1 R Maximum thermal resistance junction ambient(3) 63 - °C/W th(j-amb)2 R Maximum thermal resistance junction ambient(4) - 42 °C/W th(j-amb)3 1. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm). 2. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes and a ground layer. 3. Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board. 4. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC). DocID18094 Rev 3 5/25 25

Pin connection L6230 3 Pin connection Figure 2. Pin connection PowerSO36 (top view) (cid:19)(cid:21)(cid:17) (cid:5) (cid:7)(cid:10) (cid:19)(cid:21)(cid:17) (cid:21)(cid:3)(cid:16)(cid:3) (cid:6) (cid:7)(cid:9) (cid:21)(cid:3)(cid:16)(cid:3) (cid:21)(cid:3)(cid:16)(cid:3) (cid:7) (cid:7)(cid:8) (cid:21)(cid:3)(cid:16)(cid:3) (cid:27)(cid:24)(cid:14) (cid:8) (cid:7)(cid:7) (cid:27)(cid:24)(cid:15) (cid:22)(cid:26)(cid:25)(cid:6) (cid:9) (cid:7)(cid:6) (cid:22)(cid:26)(cid:25)(cid:7) (cid:21)(cid:3)(cid:16)(cid:3) (cid:10) (cid:7)(cid:5) (cid:21)(cid:3)(cid:16)(cid:3) (cid:27)(cid:16)(cid:23) (cid:11) (cid:7)(cid:4) (cid:27)(cid:15)(cid:22)(cid:22)(cid:25) (cid:24)(cid:18)(cid:21)(cid:24)(cid:18)(cid:6) (cid:12) (cid:6)(cid:13) (cid:18)(cid:21)(cid:7) (cid:20)(cid:21)(cid:5) (cid:13) (cid:6)(cid:12) (cid:16)(cid:23)(cid:2) (cid:18)(cid:21)(cid:5) (cid:5)(cid:4) (cid:6)(cid:11) (cid:18)(cid:21)(cid:6) (cid:20)(cid:21)(cid:7) (cid:5)(cid:5) (cid:6)(cid:10) (cid:20)(cid:21)(cid:6) (cid:24)(cid:18)(cid:21)(cid:24)(cid:18)(cid:5) (cid:5)(cid:6) (cid:6)(cid:9) (cid:24)(cid:18)(cid:21)(cid:24)(cid:18)(cid:7) (cid:16)(cid:23)(cid:1) (cid:5)(cid:7) (cid:6)(cid:8) (cid:16)(cid:23)(cid:22)(cid:26)(cid:25) (cid:21)(cid:3)(cid:16)(cid:3) (cid:5)(cid:8) (cid:6)(cid:7) (cid:21)(cid:3)(cid:16)(cid:3) (cid:22)(cid:26)(cid:25)(cid:5) (cid:5)(cid:9) (cid:6)(cid:6) (cid:17)(cid:20)(cid:14)(cid:19)(cid:2)(cid:18)(cid:21) (cid:21)(cid:3)(cid:16)(cid:3) (cid:5)(cid:10) (cid:6)(cid:5) (cid:21)(cid:3)(cid:16)(cid:3) (cid:21)(cid:3)(cid:16)(cid:3) (cid:5)(cid:11) (cid:6)(cid:4) (cid:21)(cid:3)(cid:16)(cid:3) (cid:19)(cid:21)(cid:17) (cid:5)(cid:12) (cid:5)(cid:13) (cid:19)(cid:21)(cid:17) Note: The slug is internally connected to pins 1, 18, 19, and 36 (GND pins). Figure 3. Pin connection VFQFPN32 (top view) (cid:4) (cid:5) (cid:17) (cid:17) (cid:4) (cid:23) (cid:23) (cid:20)(cid:15) (cid:21)(cid:25)(cid:24) (cid:15)(cid:22)(cid:1) (cid:23)(cid:17)(cid:20) (cid:19)(cid:20)(cid:6) (cid:17)(cid:20)(cid:4) (cid:19)(cid:20)(cid:4) (cid:23)(cid:17)(cid:20) (cid:6)(cid:5) (cid:6)(cid:4) (cid:6)(cid:3) (cid:5)(cid:12) (cid:5)(cid:11) (cid:5)(cid:10) (cid:5)(cid:9) (cid:5)(cid:8) (cid:18)(cid:20)(cid:16) (cid:7) (cid:26)(cid:15)(cid:22) (cid:20)(cid:15) (cid:5) (cid:5)(cid:6) (cid:21)(cid:25)(cid:24)(cid:5) (cid:20)(cid:15) (cid:6) (cid:5)(cid:5) (cid:26)(cid:23)(cid:13) (cid:20)(cid:15) (cid:7) (cid:5)(cid:4) (cid:18)(cid:20)(cid:16) (cid:20)(cid:15) (cid:8) (cid:5)(cid:3) (cid:26)(cid:23)(cid:14) (cid:20)(cid:15) (cid:9) (cid:4)(cid:12) (cid:21)(cid:25)(cid:24)(cid:6) (cid:20)(cid:15) (cid:10) (cid:4)(cid:11) (cid:20)(cid:15) (cid:20)(cid:15) (cid:11) (cid:4)(cid:10) (cid:26)(cid:14)(cid:21)(cid:21)(cid:24) (cid:16)(cid:19)(cid:13)(cid:18)(cid:2)(cid:17)(cid:20) (cid:20)(cid:15) (cid:15)(cid:22)(cid:21)(cid:25)(cid:24) (cid:23)(cid:17)(cid:20)(cid:23)(cid:17)(cid:6) (cid:19)(cid:20)(cid:5) (cid:5)(cid:17)(cid:20) (cid:15)(cid:22)(cid:2) (cid:17)(cid:20)(cid:6) Note: The pins 2 to 8 are connected to the die PAD. The die PAD must be connected to the GND pin. 6/25 DocID18094 Rev 3

L6230 Pin connection Table 5. Pin description Pin Type Function VBOOT Power supply Bootstrap voltage needed for driving the upper power MOSFETs. VCP Output Charge pump oscillator output. Double function: chip Enable as input and overcurrent/overtemperature indication as output. LOW logic level switches OFF all power MOSFETs, putting the power Logic DIAG-EN stages in high impedance status. output/input An internal open-drain transistor pulls to GND the pin when an overcurrent on one of the high-side MOSFETs is detected or during thermal protection. IN1 Logic input Logic input half bridge 1. EN1 Logic input Enable input half bridge 1. IN2 Logic input Logic input half bridge 2. EN2 Logic input Enable input half bridge 2. IN3 Logic input Logic input half bridge 3. EN3 Logic input Enable input half bridge 3. CP- Analog input Inverting input of internal comparator. CP+ Analog input Non-inverting input of internal comparator. CPOUT Output Open-drain output of internal comparator. Half bridge 3 source pin. This pin must be connected to power ground SENSE3 through a sensing power resistor. OUT3 Power output Output half bridge 3. Half bridge 3 power supply voltage. it must be connected to the supply VSB Power supply voltage together with pin VSA. Half bridge 2 source pin. This pin must be connected to power ground SENSE2 through a sensing power resistor. OUT2 Power output Output half bridge 2. Half bridge 1 source pin. This pin must be connected to power ground SENSE1 through a sensing power resistor. OUT1 Power output Output half bridge 1. Half bridge 1 and half bridge 2 power supply voltage. It must be VSA Power supply connected to the supply voltage together with pin VSB. GND Ground Ground terminal. DocID18094 Rev 3 7/25 25

Electrical characteristics L6230 4 Electrical characteristics V = 48 V, T = 25 °C, unless otherwise specified. S A Table 6. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit V Turn-on threshold 5.8 6.3 6.8 V Sth(ON) V Turn-off threshold 5 5.5 6 V Sth(OFF) All bridges OFF; I Quiescent supply current 5 10 mA S T = -25 °C to 125 °C(1) J T Thermal shutdown temperature 165 C j(OFF) Output DMOS transistors High-side / low-side switch ON TJ = 25 °C 0.73 0.85  R DS(on) resistance T =125 °C(1) 1.18 1.35  J DIAG-EN = LOW; OUT = V 2 mA S I Leakage current DSS DIAG-EN = LOW; OUT = GND -0.3 mA Source drain diodes V Forward ON voltage I = 1.4 A, DIAG-EN = LOW 1.15 1.3 V SD SD t Reverse recovery time I = 1.4 A 300 ns rr f t Forward recovery time 200 ns fr Logic inputs (INx, ENx, DIAG-EN) V Low level logic input voltage 0.8 V IL V High level logic input voltage 2 V IH I Low level logic input current GND logic input voltage -10 µA IL I High level logic input current 7 V logic input voltage 10 µA IH Switching characteristics Enable to output turn-on delay t 500 650 800 ns D(ON)EN time(2) t Enable to output turn-off delay time(2) 500 1000 ns D(OFF)EN Other logic inputs to OUT turn-ON delay t 1.6 µs D(ON)IN time I = 1.4 A, resistive load LOAD Other logic inputs to OUT turn-OFF t 800 ns D(OFF)IN delay time t Output rise time(2) 40 250 ns RISE t Output fall time(2) 40 250 ns FALL t Dead time 0.5 1 µs DT f Charge pump frequency T = -25 °C to 125 °C(1) 0.6 1 MHz CP J 8/25 DocID18094 Rev 3

L6230 Electrical characteristics Table 6. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Comparator V Offset voltage V = 0.5 V -14 +14 mV OFFSET CP- t Propagation delay (3) 500 ns prop I Inputs bias current 10 µA BIAS R Open-drain ON resistance 40 60  CPOUT Overcurrent detection and protection I Supply overcurrent protection threshold T = -25 to 125 °C(1) 2 2.8 3.55 A SOVER J R Open-drain ON resistance I = 4 mA 40 60  DIAG DIAG t OCD turn-ON delay time(4) I = 4 mA; C < 100 pF 200 ns OCD(ON) DIAG DIAG t OCD turn-OFF delay time(4) I = 4 mA; C < 100 pF 100 ns OCD(OFF) DIAG DIAG 1. Tested at 25 °C in a restricted range and guaranteed by characterization. 2. See Figure4. 3. Measured applying a voltage of 1 V to the pin CP- and a voltage drop from 2 V to 0 V to the pin CP+. 4. See Figure5. Figure 4. Switching characteristic definition DIAG-EN V th(ON) V th(OFF) t I OUT 90% 10% t D01IN1316 t t FALL RISE t t D(OFF)EN D(ON)EN DocID18094 Rev 3 9/25 25

Electrical characteristics L6230 Figure 5. Overcurrent detection timing definition IOUT ISOVER ON BRIDGE OFF VDIAG-EN 90% 10% D02IN1387 tOCD(ON) tOCD(OFF) 10/25 DocID18094 Rev 3

L6230 Circuit description 5 Circuit description 5.1 Power stages and charge pump The L6230 device integrates a three-phase bridge, which consists of 6 power MOSFETs connected as shown in the block diagram (see Figure1 on page3), each power MOS has an R = 0.73  (typical value at 25 °C) with an intrinsic fast freewheeling diode. Cross DS(ON) conduction protection is implemented by using a dead time (t = 1 µs typical value) set by DT the internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of a bridge. Pins VSA and VSB must be connected together to the supply voltage (V ). S Using the N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (V ) is obtained BOOT through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure6. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table7. Table 7. Charge pump external component values Component Value C 220 nF BOOT C 10 nF P D1 1N4148 D2 1N4148 Figure 6. Charge pump circuit (cid:17) (cid:15) (cid:11)(cid:2) (cid:10) (cid:9)(cid:13)(cid:13)(cid:16) (cid:11)(cid:3) (cid:10) (cid:14) (cid:17)(cid:10)(cid:14) (cid:17)(cid:9)(cid:13)(cid:13)(cid:16) (cid:17)(cid:15)(cid:8) (cid:17)(cid:15)(cid:9) (cid:8)(cid:12)(cid:1)(cid:4)(cid:7)(cid:7)(cid:5)(cid:6) DocID18094 Rev 3 11/25 25

Circuit description L6230 5.2 Logic inputs Pins INx and ENx are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in Figure7. Typical value for turn-on and turn-off thresholds are respectively V = 1.8 V and V = 1.3 V. th(ON) th(OFF) The pin DIAG-EN has identical input structure with the exception that the drain of the overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in Figure8 or Figure9. If driven by an open-drain (collector) structure, a pull-up resistor R and a capacitor C are connected as shown in EN EN Figure8. If the driver is a standard push-pull structure the resistor R and the capacitor C EN EN are connected as shown in Figure9. The resistor R should be chosen in the range from EN 2.2 k to 180 k. Recommended values for R and C are respectively 10 k and 5.6 nF. EN EN More information on selecting the values can be found in Section5.3: Non-dissipative overcurrent detection and protection. Figure 7. Logic inputs internal structure 5V ESD PROTECTION D01IN1329 Figure 8. Pin DIAG-EN open collector driving 5V 5V R EN OPEN DIAG-EN COLLECTOR OUTPUT C EN ESD PROTECTION D01IN1330 Figure 9. Pin DIAG-EN push-pull driving 5V REN DIAG-EN PUSH-PULL OUTPUT C EN ESD PROTECTION D01IN1331 12/25 DocID18094 Rev 3

L6230 Circuit description 5.3 Non-dissipative overcurrent detection and protection The L6230 device integrates an overcurrent detection circuit (OCD) for full protection. This circuit provides output-to-output and output-to-ground short-circuit protection as well. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure10 shows a simplified schematic for the overcurrent detection circuit. To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I . When the REF output current reaches the detection threshold (typically I = 2.8 A), the OCD SOVER comparator signals a fault condition. When a fault condition is detected, an internal open- drain MOS with a pull down capability of 4 mA connected to the pin DIAG is turned on. The pin DIAG-EN can be used to signal the fault condition to a C and to shut down the three-phase bridge simply by connecting the pin to an external R-C (see R , C ). EN EN Figure 10. Overcurrent protection simplified schematic (cid:26)(cid:31)(cid:30)(cid:9) (cid:32)(cid:29)(cid:14) (cid:26)(cid:31)(cid:30)(cid:10) (cid:26)(cid:31)(cid:30)(cid:11) (cid:32)(cid:29)(cid:15) (cid:21)(cid:22)(cid:20)(cid:21)(cid:5)(cid:29)(cid:22)(cid:17)(cid:18)(cid:1)(cid:17)(cid:24)(cid:26)(cid:29) (cid:21)(cid:22)(cid:20)(cid:21)(cid:5)(cid:29)(cid:22)(cid:17)(cid:18)(cid:1)(cid:17)(cid:24)(cid:26)(cid:29) (cid:21)(cid:22)(cid:20)(cid:21)(cid:5)(cid:29)(cid:22)(cid:17)(cid:18)(cid:1)(cid:17)(cid:24)(cid:26)(cid:29) (cid:22)(cid:9) (cid:22)(cid:10) (cid:22)(cid:11) (cid:27)(cid:26)(cid:33)(cid:18)(cid:28)(cid:1)(cid:29)(cid:18)(cid:25)(cid:29)(cid:18) (cid:27)(cid:26)(cid:33)(cid:18)(cid:28)(cid:1)(cid:29)(cid:18)(cid:25)(cid:29)(cid:18) (cid:27)(cid:26)(cid:33)(cid:18)(cid:28)(cid:1)(cid:29)(cid:18)(cid:25)(cid:29)(cid:18) (cid:42)(cid:16)(cid:1)(cid:39)(cid:40)(cid:1)(cid:23)(cid:26)(cid:20)(cid:22)(cid:16) (cid:30)(cid:26)(cid:1)(cid:20)(cid:14)(cid:30)(cid:18) (cid:9)(cid:1)(cid:35)(cid:36)(cid:37)(cid:37) (cid:27)(cid:26)(cid:33)(cid:38)(cid:18)(cid:1)(cid:35)(cid:28)(cid:36)(cid:1)(cid:37)(cid:17)(cid:37)(cid:41)(cid:24)(cid:26)(cid:29) (cid:27)(cid:26)(cid:33)(cid:38)(cid:18)(cid:1)(cid:35)(cid:28)(cid:36)(cid:1)(cid:37)(cid:17)(cid:37)(cid:41)(cid:24)(cid:26)(cid:29) (cid:9)(cid:1)(cid:35)(cid:36)(cid:37)(cid:37) (cid:27)(cid:26)(cid:33)(cid:38)(cid:18)(cid:1)(cid:35)(cid:28)(cid:36)(cid:1)(cid:37)(cid:17)(cid:37)(cid:41)(cid:24)(cid:26)(cid:29) (cid:9)(cid:1)(cid:35)(cid:36)(cid:37)(cid:37) (cid:32)(cid:17)(cid:17) (cid:23)(cid:26)(cid:20)(cid:22)(cid:16) (cid:4) (cid:26)(cid:16)(cid:17) (cid:22)(cid:9)(cid:1)(cid:7)(cid:1)(cid:38) (cid:22)(cid:10)(cid:7)(cid:1)(cid:38) (cid:28)(cid:18)(cid:25) (cid:17)(cid:22)(cid:14)(cid:20)(cid:5)(cid:18)(cid:25) (cid:16)(cid:26)(cid:24)(cid:27)(cid:14)(cid:28)(cid:14)(cid:30)(cid:26)(cid:28) (cid:22)(cid:9)(cid:4)(cid:22)(cid:10)(cid:1)(cid:7)(cid:1)(cid:38) (cid:16)(cid:18)(cid:25) (cid:22)(cid:25)(cid:30)(cid:18)(cid:28)(cid:25)(cid:14)(cid:23) (cid:22)(cid:28)(cid:18)(cid:19) (cid:26)(cid:27)(cid:18)(cid:25)(cid:5)(cid:17)(cid:28)(cid:14)(cid:22)(cid:25) (cid:28)(cid:17)(cid:29)(cid:2)(cid:26)(cid:25)(cid:3) (cid:12)(cid:8) (cid:1)(cid:30)(cid:34)(cid:27)(cid:6) (cid:26)(cid:32)(cid:18)(cid:28)(cid:30)(cid:18)(cid:24)(cid:27)(cid:18)(cid:28)(cid:14)(cid:30)(cid:31)(cid:28)(cid:18) (cid:22)(cid:11)(cid:7)(cid:1)(cid:38) (cid:22)(cid:28)(cid:18)(cid:19) (cid:17)(cid:8)(cid:10)(cid:22)(cid:25)(cid:9)(cid:11)(cid:13)(cid:9)(cid:32)(cid:9) Figure11 shows the overcurrent detection operation. The disable time t before DISABLE recovering the normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by C and R values and its EN EN magnitude is reported in Figure12. The delay time t before turning off the bridge when DELAY an overcurrent has been detected depends only by the C value. Its magnitude is reported EN in Figure13. The C is also used for providing immunity to the pin DIAG-EN against fast transient EN noises. Therefore the value of the C should be chosen as big as possible according to the EN maximum tolerable delay time and the R value should be chosen according to the desired EN disable time. The resistor R should be chosen in the range from 2.2 k to 180 k. Recommended EN values for the R and C are respectively 100 k and 5.6 nF that allow obtaining 200 s EN EN disable time. DocID18094 Rev 3 13/25 25

Circuit description L6230 Figure 11. Overcurrent protection waveforms IOUT ISOVER DIAG-EN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON BRIDGE tDELAY tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN tD(OFF)EN D02IN1383 Figure 12. t versus C and R DISABLE EN EN 11110033 RREENN== 222200kk RREENN== 110000kk RREENN== 4477kk RREENN== 3333kk RREENN== 1100kk µs]µs] 110000 [[ EE LL BB AA DISDIS tt 1100 11 11 1100 110000 CCEENN [[nnFF]] Figure 13. t versus C DELAY EN 10 tdelay [s] 1 0.1 1 10 100 Cen [nF] 14/25 DocID18094 Rev 3

L6230 Application information 6 Application information Some typical applications using the L6230 device are shown in this section. A high quality ceramic capacitor (C ) in the range of 100 nF to 200 nF should be placed between the 2 power pins VS and VS and ground near the L6230 to improve the high frequency filtering A B on the power supply and reduce high frequency transients generated by the switching. The capacitor (C ) connected from the DIAG-EN input to ground sets the shutdown time when EN an overcurrent is detected (see Section5.3: Non-dissipative overcurrent detection and protection). The current sensing inputs (SENSEX) should be connected to the sensing resistors R with a trace length as short as possible in the layout. The sense resistors SENSE should be non-inductive resistors to minimize the dI/dt transients across the resistors. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see pin description in Table5 on page10). It is recommended to keep power ground and signal ground separated on the PCB. Table 8. Component values for typical application Component Value C 100 µF 1 C 100 nF 2 C 220 nF BOOT C 5.6 nF EN C 10 nF P D 1N4148 1 D 1N4148 2 R 100 k EN The examples reported describe some typical application to drive a 3-phase BLDC motor using the L6230 device. In the first example is shown a field oriented control (FOC) system, with this method it is possible to provide smooth and precise motor control of BLDC motors. A six-step driving method with current control is reported in the second example, the inputs sequence is generated by an external controller and the L6230 comparator is used to obtain the information for the peak current control. Finally, the third example shows how to implement a sensorless motor control system, the information on the rotor position is achieved by BEMF zero-crossing detection. DocID18094 Rev 3 15/25 25

Application information L6230 6.1 Field oriented control driving method In this configuration (see Figure14) three sensing resistors are required, one for each channel. The sensing signals coming from the output power stage are conditioned by external operational amplifiers which provide the proper feedback signals to the AtoD converter and the system controller. According to the feedback signals the six input lines are generated by the controller. Note that some filtering and level shifting RC networks should be added between the sense resistor and the correspondent op-amp input. The uncommitted internal comparator with open-drain output is available. Figure 14. F.O.C. typical application (cid:26) (cid:17)(cid:23) (cid:2) (cid:30)(cid:27)(cid:13) (cid:16)(cid:20)(cid:13)(cid:18)(cid:3)(cid:17)(cid:23) (cid:17)(cid:23)(cid:13)(cid:14)(cid:21)(cid:17) (cid:30) (cid:27) (cid:15) (cid:15) (cid:15) (cid:11)(cid:1)(cid:3)(cid:1)(cid:9)(cid:6)(cid:1)(cid:30)(cid:16)(cid:15) (cid:5) (cid:6) (cid:16) (cid:30)(cid:27)(cid:14) (cid:17)(cid:23) (cid:5) (cid:25)(cid:24)(cid:31)(cid:17)(cid:26) (cid:15) (cid:18)(cid:26)(cid:24)(cid:29)(cid:23)(cid:16) (cid:25) (cid:20)(cid:23)(cid:5) (cid:20)(cid:23)(cid:5) (cid:3) (cid:30)(cid:15)(cid:25) (cid:16) (cid:17)(cid:23)(cid:5) (cid:17)(cid:23)(cid:5) (cid:6) (cid:15) (cid:14)(cid:24)(cid:24)(cid:28) (cid:20)(cid:23)(cid:6) (cid:20)(cid:23)(cid:6) (cid:27)(cid:20)(cid:18)(cid:23)(cid:13)(cid:21) (cid:30)(cid:14)(cid:24)(cid:24)(cid:28) (cid:18)(cid:26)(cid:24)(cid:29)(cid:23)(cid:16) (cid:26)(cid:27)(cid:17)(cid:23)(cid:27)(cid:17) (cid:17)(cid:23)(cid:6) (cid:17)(cid:23)(cid:6) (cid:27)(cid:17)(cid:23)(cid:27)(cid:17)(cid:5) (cid:26)(cid:27)(cid:17)(cid:23)(cid:27)(cid:17) (cid:20)(cid:23)(cid:7) (cid:20)(cid:23)(cid:7) (cid:27)(cid:17)(cid:23)(cid:27)(cid:17)(cid:6) (cid:26) (cid:17)(cid:23)(cid:7) (cid:17)(cid:23)(cid:7) (cid:27)(cid:17)(cid:23)(cid:27)(cid:17) (cid:27)(cid:17)(cid:23)(cid:27)(cid:17)(cid:7) (cid:27)(cid:36)(cid:35)(cid:38)(cid:32)(cid:37)(cid:1)(cid:33)(cid:39)(cid:38)(cid:34)(cid:36)(cid:40)(cid:36)(cid:39)(cid:38)(cid:36)(cid:38)(cid:35) (cid:13)(cid:16)(cid:15) (cid:2) (cid:15)(cid:25)(cid:2) (cid:3) (cid:15)(cid:25)(cid:24)(cid:29)(cid:28) (cid:15)(cid:25)(cid:3) (cid:24)(cid:29)(cid:28)(cid:5) (cid:28)(cid:19)(cid:26)(cid:17)(cid:17)(cid:3)(cid:25)(cid:19)(cid:13)(cid:27)(cid:17)(cid:1) (cid:22) (cid:24)(cid:29)(cid:28)(cid:6) (cid:22)(cid:24)(cid:28)(cid:24)(cid:26) (cid:24)(cid:29)(cid:28)(cid:7) (cid:18)(cid:23)(cid:16) (cid:13)(cid:22)(cid:4)(cid:7)(cid:12)(cid:12)(cid:8)(cid:10) 16/25 DocID18094 Rev 3

L6230 Application information 6.2 Six-step driving method with current control In this configuration only one sense resistor is needed, the three OUT pins are connected together to the R (see Figure15). SENSE The inverting input comparator CP- monitors the voltage drop across the external sense resistor connected between the source of the three lower power MOS transistors and ground. As the current in the motor increases the voltage across the R increases SENSE proportionally. When the voltage drop across the sense resistor becomes greater than the reference voltage applied at non-inverting input CP+ the internal open-drain is switched on pulling down the CPOUT pin. This signal could be managed by the controller to generate the proper input sequence for the six-step driving method with current control and select what current decay method to implement. When the sense voltage decreases below the CP+ voltage, the internal open-drain is switched off and the voltage at the CPOUT pin starts to increase charging the capacitor C . CPOUT The reference voltage at the pin CP+ will be set according to the sense resistor value and the desired regulated current (V ≈ R x I ). A very simple way to obtain CP+ SENSE TARGET variable voltage is the low-pass filtering of the PWM signal coming from a controller. Figure 15. Six-step with current control typical application (cid:25) (cid:16)(cid:22) (cid:2) (cid:29)(cid:26)(cid:12) (cid:15)(cid:19)(cid:12)(cid:17)(cid:3)(cid:16)(cid:22) (cid:16)(cid:22)(cid:12)(cid:13)(cid:20)(cid:16) (cid:29) (cid:26) (cid:14) (cid:14) (cid:10)(cid:1)(cid:3)(cid:1)(cid:9)(cid:6)(cid:1)(cid:29)(cid:15)(cid:14) (cid:5) (cid:15) (cid:29)(cid:26)(cid:13) (cid:16)(cid:22) (cid:5) (cid:24)(cid:23)(cid:30)(cid:16)(cid:25) (cid:17)(cid:25)(cid:23)(cid:28)(cid:22)(cid:15) (cid:19)(cid:22)(cid:5) (cid:19)(cid:22)(cid:5) (cid:3) (cid:29)(cid:14)(cid:24) (cid:15) (cid:16)(cid:22)(cid:5) (cid:16)(cid:22)(cid:5) (cid:6) (cid:14) (cid:13)(cid:23)(cid:23)(cid:27) (cid:19)(cid:22)(cid:6) (cid:19)(cid:22)(cid:6) (cid:26)(cid:19)(cid:17)(cid:22)(cid:12)(cid:20) (cid:29)(cid:13)(cid:23)(cid:23)(cid:27) (cid:17)(cid:25)(cid:23)(cid:28)(cid:22)(cid:15) (cid:25)(cid:26)(cid:16)(cid:22)(cid:26)(cid:16) (cid:16)(cid:22)(cid:6) (cid:16)(cid:22)(cid:6) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:5) (cid:19)(cid:22)(cid:7) (cid:19)(cid:22)(cid:7) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:6) (cid:16)(cid:22)(cid:7) (cid:16)(cid:22)(cid:7) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:7) (cid:14)(cid:24)(cid:3) (cid:25) (cid:14)(cid:24)(cid:2) (cid:24)(cid:30)(cid:21) (cid:14)(cid:24)(cid:2) (cid:34)(cid:41)(cid:40)(cid:38)(cid:1)(cid:32)(cid:40)(cid:39)(cid:43)(cid:41)(cid:40)(cid:37)(cid:37)(cid:33)(cid:41) (cid:25)(cid:14)(cid:24)(cid:23)(cid:28)(cid:27) (cid:14) (cid:14)(cid:24)(cid:2) (cid:14)(cid:44)(cid:41)(cid:41)(cid:33)(cid:39)(cid:43)(cid:1)(cid:32)(cid:40)(cid:39)(cid:43)(cid:41)(cid:40)(cid:37) (cid:14)(cid:24)(cid:23)(cid:28)(cid:27) (cid:42)(cid:36)(cid:35)(cid:39)(cid:31)(cid:37) (cid:14) (cid:23)(cid:28)(cid:27)(cid:5) (cid:14)(cid:24)(cid:23)(cid:28)(cid:27) (cid:27)(cid:18)(cid:25)(cid:16)(cid:16)(cid:3)(cid:24)(cid:18)(cid:12)(cid:26)(cid:16)(cid:1) (cid:21) (cid:23)(cid:28)(cid:27)(cid:6) (cid:21)(cid:23)(cid:27)(cid:23)(cid:25) (cid:23)(cid:28)(cid:27)(cid:7) (cid:17)(cid:22)(cid:15) (cid:12)(cid:21)(cid:4)(cid:7)(cid:11)(cid:11)(cid:8)(cid:10) DocID18094 Rev 3 17/25 25

Application information L6230 6.3 Six-step driving method with BEMF zero-crossing detection The BEMF zero-crossing information can be used to evaluate the rotor position; in this way no Hall effect sensors nor encoder are needed. In the six-step driving mode one of the three phases is left in the high impedance state. Comparing the voltage of this phase with the center-tap voltage we can detect the BEMF zero-crossing. In the shown example (see Figure16), the OUT1 phase voltage is monitored by the CP+; the center-tap voltage is obtained as combination of three phase voltages and monitored by the CP- pin. Only when the OUT1 is in high impedance, the CPOUT will perform a commutation each time a BEMF zero-crossing is detected. In this configuration one sense resistor is needed, the three OUT pins are connected together to the R . SENSE Figure 16. Six-step with zero-crossing detection typical application (cid:25)(cid:16)(cid:22) (cid:2) (cid:29)(cid:26)(cid:12) (cid:15)(cid:19)(cid:12)(cid:17)(cid:3)(cid:16)(cid:22) (cid:16)(cid:22)(cid:12)(cid:13)(cid:20)(cid:16) (cid:10)(cid:1)(cid:3)(cid:1)(cid:9)(cid:29)(cid:6)(cid:1)(cid:26)(cid:29)(cid:15)(cid:14) (cid:14)(cid:5) (cid:14)(cid:6) (cid:15)(cid:5) (cid:14)(cid:16)(cid:22) (cid:17)(cid:24)(cid:25)(cid:23)(cid:23)(cid:30)(cid:28)(cid:16)(cid:22)(cid:25)(cid:15) (cid:14)(cid:24) (cid:19)(cid:22)(cid:5) (cid:19)(cid:22)(cid:5) (cid:3) (cid:29)(cid:14)(cid:24) (cid:15)(cid:6) (cid:16)(cid:22)(cid:5) (cid:16)(cid:22)(cid:5) (cid:14)(cid:13)(cid:23)(cid:23)(cid:27) (cid:19)(cid:22)(cid:6) (cid:19)(cid:22)(cid:6) (cid:26)(cid:19)(cid:17)(cid:22)(cid:12)(cid:20) (cid:29)(cid:13)(cid:23)(cid:23)(cid:27) (cid:17)(cid:25)(cid:23)(cid:28)(cid:22)(cid:15) (cid:25)(cid:26)(cid:16)(cid:22)(cid:26)(cid:16) (cid:16)(cid:22)(cid:6) (cid:16)(cid:22)(cid:6) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:5) (cid:19)(cid:22)(cid:7) (cid:19)(cid:22)(cid:7) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:6) (cid:25)(cid:6) (cid:16)(cid:22)(cid:7) (cid:16)(cid:22)(cid:7) (cid:26)(cid:16)(cid:22)(cid:26)(cid:16)(cid:7) (cid:25)(cid:6) (cid:14)(cid:24)(cid:2) (cid:25)(cid:6) (cid:14)(cid:24)(cid:3) (cid:25)(cid:7) (cid:25)(cid:6) (cid:25)(cid:5) (cid:7)(cid:25)(cid:5) (cid:7)(cid:25)(cid:5) (cid:7)(cid:25)(cid:5) (cid:14)(cid:24)(cid:23)(cid:28)(cid:27) (cid:31)(cid:34)(cid:40)(cid:39)(cid:41)(cid:1)(cid:36)(cid:33)(cid:35)(cid:38)(cid:40)(cid:39)(cid:32)(cid:41)(cid:37)(cid:41)(cid:36)(cid:38)(cid:35) (cid:23)(cid:28)(cid:27)(cid:5) (cid:27)(cid:18)(cid:25)(cid:16)(cid:16)(cid:3)(cid:24)(cid:18)(cid:12)(cid:26)(cid:16)(cid:1) (cid:21) (cid:23)(cid:28)(cid:27)(cid:6) (cid:21)(cid:23)(cid:27)(cid:23)(cid:25) (cid:23)(cid:28)(cid:27)(cid:7) (cid:17)(cid:22)(cid:15) (cid:12)(cid:21)(cid:4)(cid:7)(cid:11)(cid:11)(cid:8)(cid:11) 18/25 DocID18094 Rev 3

L6230 Application information 6.4 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat-sinking can be achieved using copper on the PCB with a proper area and thickness. For instance, using a VFQFPN32L 5 x 5 package the typical R is about 42 °C/W when th(JA) mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top side plus the 6 cm2 ground layer connected through 18 via holes (9 below the IC). Otherwise, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 µm), the R is about 35°C/W. th(jA) Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W. DocID18094 Rev 3 19/25 25

Package information L6230 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 VFQFPN32 package information Figure 17. VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50 package outline 20/25 DocID18094 Rev 3

L6230 Package information Table 9. VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 0.80 0.85 0.95 b 0.18 0.25 0.30 b1 0.165 0.175 0.185 D 4.85 5.00 5.15 D2 3.00 3.10 3.20 D3 1.10 1.20 1.30 E 4.85 5.00 5.15 E2 4.20 4.30 4.40 E3 0.60 0.70 0.80 e 0.50 L 0.30 0.40 0.50 ddd 0.08 Note: “VFQFPN” stands for the thermally enhanced very thin profile fine pitch quad flat package no lead. Very thin profile: 0.80 < A < 1.00 mm. Details of the terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. DocID18094 Rev 3 21/25 25

Package information L6230 7.2 PowerSO36 package information Figure 18. PowerSO36 package outline (cid:49) (cid:49) (cid:68)(cid:21) (cid:36) (cid:70) (cid:36) (cid:72) (cid:68)(cid:20) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:37) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:36) (cid:40) (cid:72)(cid:22) (cid:43) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:36) (cid:79)(cid:72)(cid:68)(cid:71) (cid:39) (cid:86)(cid:79)(cid:88)(cid:74) (cid:68)(cid:22) (cid:22)(cid:25) (cid:20)(cid:28) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:40)(cid:22) (cid:37) (cid:40)(cid:20) (cid:40)(cid:21) (cid:39)(cid:20) (cid:39)(cid:40)(cid:55)(cid:36)(cid:44)(cid:47)(cid:3)(cid:37) (cid:19)(cid:17)(cid:22)(cid:24) (cid:42)(cid:68)(cid:74)(cid:72)(cid:3)(cid:51)(cid:79)(cid:68)(cid:81)(cid:72) (cid:20) (cid:20) (cid:27) (cid:16)(cid:3)(cid:38)(cid:3)(cid:16) (cid:54) (cid:47) (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:42) (cid:38) (cid:75)(cid:3)(cid:91)(cid:3)(cid:23)(cid:24)(cid:219) (cid:69) (cid:134)(cid:19)(cid:17)(cid:20)(cid:21)(cid:48) (cid:36)(cid:37) (cid:51)(cid:54)(cid:50)(cid:22)(cid:25)(cid:48)(cid:40)(cid:38) (cid:11)(cid:38)(cid:50)(cid:51)(cid:47)(cid:36)(cid:49)(cid:36)(cid:53)(cid:44)(cid:55)(cid:60)(cid:12) 22/25 DocID18094 Rev 3

L6230 Package information Table 10. PowerSO36 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 3.6 a1 0.1 0.3 a2 3.3 a3 0 0.1 b 0.22 0.38 c 0.23 0.32 D(1) 15.8 16 D1 9.4 9.8 E 13.9 14.5 e 0.65 e3 11.05 E1(1) 10.9 11.1 E2 2.9 E3 5.8 6.2 E4 2.9 3.2 G 0 0.1 H 15.5 15.9 h 1.1 L 0.8 1.1 N 10°(max.) S 8 °(max.) 1. “D” and “E1” do not include mold flash or protrusions: - Mold flash or protrusions shall not exceed 0.15 mm - Critical dimensions are “a3”, “E” and “G”. DocID18094 Rev 3 23/25 25

Revision history L6230 8 Revision history Table 11. Document revision history Date Revision Changes 14-Oct-2010 1 First release 07-Jun-2011 2 Updated maturity status from preliminary data to final datasheet. Updated Figure1 on page3 (replaced by new figure). Updated Table2 on page4 and Table3 on page4 (corrected SENSE pin labels). Updated Figure2 on page6, Figure3 on page6, Figure10 on page13, Section5.3 on page 13, and Figure14 on page16 to Figure16 on page18 (replaced “DIAG/EN” by “DIAG-EN”). 01-Aug-2016 3 Added cross-reference to Table5 on page7 in Section6 on page 15, to Section5.3 on page 13 in Section5.2 on page 12 and in Section6 on page 15. Updated Section6.2 on page 17 (several updates). Replaced “DIAG/EN” by “DIAG-EN” in whole document. Minor modifications throughout document. 24/25 DocID18094 Rev 3

L6230 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID18094 Rev 3 25/25 25

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