L5991 L5991A ® PRIMARY CONTROLLER WITH STANDBY CURRENT-MODE CONTROL PWM MULTIPOWER BCD TECHNOLOGY SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT (< 120m A) HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOU- BLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100% AND 50% MAXIMUM DUTY CYCLE LIMIT DIP16 SO16 STANDBY FUNCTION PROGRAMMABLE SOFT START ORDERING NUMBERS: L5991/L5991A (DIP16) PRIMARY OVERCURRENT FAULT DETEC- L5991D/L5991AD (SO16) TION WITH RE-START DELAY line or DC-DC power supply applications using a PWM UVLO WITH HYSTERESIS fixed frequency current mode control. IN/OUT SYNCHRONIZATION Based on a standard current mode PWM control- LATCHED DISABLE ler this device includes some features such as INTERNAL 100ns LEADING EDGE BLANK- programmable soft start, IN/OUT synchronization, ING OF CURRENT SENSE disable (to be used for over voltage protection and PACKAGE: DIP16 AND SO16 for power management), precise maximum Duty Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, over- DESCRIPTION current protection with soft start intervention, and This primary controller I.C., developed in BCD60II Standby function for oscillator frequency reduction technology, has been designed to implement off when the converter is lightly loaded. BLOCK DIAGRAM SYNC DC-LIM VCC VREF 1 15 8 4 2 TIMING RCT 25V Vref + 3 + DC - T 15V/10V - PWM UVLO 14 9 DIS - DIS VC + 2.5V 13V 10 OUT BLANKING S Q R PWM OVER CURRENT VREF OK VREF 11 ISEN 13 + FAULT CDLISK PGND SOFT-START 16 - STAND-BY ST-BY 1.2V SS 7 + 2.5V E/A 5 2R - VFB 1V R 12 6 SGND COMP D97IN725A August 2001 1/23

L5991 - L5991A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage (ICC < 50mA) (*) selflimit V IOUT Output Peak Pulse Current 1.5 A Analog Inputs & Outputs (6,7) -0.3 to 8 V Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) -0.3 to 6 V Ptot Power Dissipation @ Tamb = 70(cid:176) C (DIP16) 1 W @ Tamb = 50(cid:176) C (SO16) 0.83 W Tj Junction Temperature, Operating Range -40 to 150 (cid:176) C Tstg Storage Temperature, Operating Range -55 to 150 (cid:176) C (*) maximum package power dissipation limits must be observed PIN CONNECTION SYNC 1 16 ST-BY RCT 2 15 DC-LIM DC 3 14 DIS VREF 4 13 ISEN VFB 5 12 SGND COMP 6 11 PGND SS 7 10 OUT VCC 8 9 VC THERMAL DATA Symbol Parameter Value Unit Rth j-amb Thermal Resistance Junction -Ambient (DIP16) 80 (cid:176) C/W Thermal Resistance Junction -Ambient (SO16) 120 (cid:176) C/W PIN FUNCTIONS N. Name Function 1 SYNC Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct 2 RCT Oscillator pin for external CT, RA, RB components 3 DC Duty Cycle control 4 VREF 5.0V +/-1.5% reference voltage @ 25°C 5 VFB Error Amplifier Inverting input 6 COMP Error Amplifier Output 7 SS Soft start pin for external capacitor Css 8 VCC Supply for internal "Signal" circuitry 9 VC Supply for Power section 10 OUT High current totem pole output 11 PGND Power ground 12 SGND Signal ground 13 ISEN Current sense 14 DIS Disable. It must never be left floating. TIE to SGND if not used. 15 DC-LIM Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed 16 ST-BY Standby. Connect a resistor to RCT. Connect to VREF or floating if not used. 2/23

L5991 - L5991A ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105(cid:176) C; RT = 13.3kW (*) CT = 1nF; unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit REFERENCE SECTION VREF Output Voltage Tj = 25(cid:176) C; IO = 1mA 4.925 5.0 5.075 V Line Regulation VCC = 12 to 20V; Tj = 25°C 2.0 10 mV Load Regulation IO = 1 to 10mA; Tj = 25°C 2.0 10 mV TS Temperature Stability 0.4 mV/(cid:176) C Total Variation Line, Load, Temperature 4.80 5.0 5.130 V IOS Short Circuit Current Vref = 0V 30 150 mA Power Down/UVLO VCC = 6V; Isink = 0.5mA 0.2 0.5 V OSCILLATOR SECTION Initial Accuracy pin 15 = Vref; Tj = 25°C; Vcomp = 4.5V 95 100 105 kHz pin 15 = Vref; VCC = 12 to 20V 93 100 107 kHz Vcomp = 4.5V pin 15 = Vref; VCC = 12 to 20V 46.5 50 53.5 kHz Vcomp = 2V Duty Cycle pin 3 = 0,7V, pin 15 = VREF 0 % pin 3 = 0.7V, pin 15 = OPEN 0 % pin 3 = 3.2V, pin 15 = VREF 47 % pin 3 = 3.2V, pin 15 = OPEN 93 % Duty Cycle Accuracy pin 3 = 2.79V, pin 15 = OPEN 75 80 85 % Oscillator Ramp Peak 2.8 3.0 3.2 V Oscillator Ramp Valley 0.75 0.9 1.05 V ERROR AMPLIFIER SECTION Input Bias Current VFB to GND 0.2 3.0 m A VI Input Voltage VCOMP = VFB 2.42 2.5 2.58 V GOPL Open Loop Gain VCOMP = 2 to 4V 60 90 dB SVR Supply Voltage Rejection VCC = 12 to 20V 85 dB VOL Output Low Voltage Isink = 2mA 1.1 V VOH Output High Voltage Isource = 0.5mA, VFB = 2.3V 5 6 V IO Output Source Current VCOMP > 4V, VFB = 2.3V 0.5 1.3 2.5 mA Output Sink Current VCOMP = 1.1V, VFB = 2.7V 2 6 mA Unit Gain Bandwidth 1.7 4 MHz SR Slew Rate 8 V/m s PWM CURRENT SENSE SECTION Ib Input Bias Current Isen = 0 3 15 m A IS Maximum Input Signal VCOMP = 5V 0.92 1.0 1.08 V Delay to Output 70 100 ns Gain 2.85 3 3.15 V/V Vt Fault Threshold Voltage 1.1 1.2 1.3 V SOFT START SECTION ISSC SS Charge Current Tj = 25(cid:176) C 14 20 26 m A ISSD SS Discharge Current VSS = 0.6V Tj = 25(cid:176) C 5 10 15 m A VSSSAT SS Saturation Voltage DC = 0% 0.6 V VSSCLAMP SS Clamp Voltage 7 V LEADING EDGE BLANKING Internal Masking Time 100 ns OUTPUT SECTION VOL Output Low Voltage IO = 250mA 1.0 V VOH Output High Voltage IO = 20mA; VCC = 12V 10 10.5 V IO = 200mA; VCC = 12V 9 10 V VOUT CLAMP Output Clamp Voltage IO = 5mA; VCC = 20V 13 V Collector Leakage VCC = 20V VC = 24V 2 20 m A (*) RT = RA//RB, RA = RB = 27kW , see Fig. 23. 3/23

L5991 - L5991A ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter Test Condition Min. Typ. Max. Unit OUTPUT SECTION Fall Time CO = 1nF 20 60 ns CO = 2.5nF 35 ns Rise Time CO = 1nF 50 100 ns CO = 2.5nF 70 ns UVLO Saturation VCC = VC = 0 to VCCON; Isink = 10mA 1.0 V SUPPLY SECTION VCCON Startup voltage L5991 14 15 16 V L5991A 7.8 8.4 9 V VCCOFF Minimum Operating L5991 9 10 11 V Voltage L5991A 7 7.6 8.2 V Vhys UVLO Hysteresis L5991 4.5 5 V L5991A 0.5 0.8 V IS Start Up Current Before Turn-on at: 40 75 120 m A VCC = VC = VCCON -0.5V Iop Operating Current CT = 1nF, RT = 13.3kW , CO =1nF 9 13 mA Iq Quiescent Current (After turn on), CT = 1nF, 7.0 10 mA RT = 13.3kW , CO =0nF VZ Zener Voltage I8 = 20mA 21 25 30 V STANDBY FUNCTION VREF-VST-BY IST-BY = 2mA 45 mV VT1 Standby Threshold Vcomp Falling 2.5 V Vcomp Rising 4.0 V SYNCHRONIZATION SECTION Master Operation V1 Clock Amplitude ISOURCE = 0.8mA 4 V I1 Clock Source Current Vclock = 3.5V 3 7 mA Slave Operation V1 Sync Pulse Low Level 1 V High Level 3.5 V I1 Sync Pulse Current VSYNC = 3.5V 0.5 mA OVER CURRENT PROTECTION Vt Fault Threshold Voltage 1.1 1.2 1.3 V DISABLE SECTION Shutdown threshold 2.4 2.5 2.6 V Input Bias Current Vpin14 = 0 to 3V -1 1 m A IqSH Quiescent current After VCC = 15V 330 m A Disable Figure 1. L5991 - Quiescent current vs. input Figure 2. L5991 - Quiescent current vs. input voltage. voltage (after disable). (X = 7.6V and Y= 8.4V for L5991A) (X = 7.6V and Y= 8.4V for L5991A) Iq [mA] 30 Iq [µA] 350 20 V14 = 0, Pin2 = open Tj = 25°C 300 8 250 6 200 4 150 V14 = Vref 0.2 Tj = 25 °C 0.15 100 0.1 50 X Y 0.05 X Y 0 0 0 4 8 12 16 20 24 0 4 8 12 16 20 24 28 Vcc [V] Vcc [V] 4/23

L5991 - L5991A Figure 3. Quiescent current vs. input voltage. Figure 4. Quiescent current vs. input voltage and switching frequency. Iq [mA] Iq [mA] 9.0 36 V14 = 0, V5 = Vref 30 Co = 1nF, Tj = 25°C Rt = 4.5Kohm,Tj = 25°C 8.5 DC = 0% 1Mhz 24 500Khz 1MHz 300Khz 8.0 18 100Khz 500KHz 12 300KHz 7.5 100KHz 6 7.0 0 8 10 12 14 16 18 20 22 24 8 10 12 14 16 18 20 22 Vcc [V] Vcc [V] Figure 5. Quiescent current vs. input voltage Figure 6. IC Consumption vs. Temperature. and switching frequency. Iq [mA] 36 [mA] Co = 1nF, Tj = 25°C 100 Operating current 30 Vcc =15V, after turn-on DC = 100% RT=13.3kW , CT=1nF DC=75%, Co=1nF 1MHz 10 24 Quiescent current Vcc =15V, after turn-on 18 500KHz RT=13.3 kW , CT=1nF 1 DC = 0 300KHz 12 100KHz 0.1 6 Start-up current Vc=Vcc= Vccon-0.5V, before turn-on 0 0.01 8 10 12 14 16 18 20 22 -50 -25 0 25 50 75 100 125 150 Vcc [V] Junction temperature [˚C] Figure 7. Reference voltage vs. load current. Figure 8. Vref vs. junction temperature. Vref [V] Vref [V]) 5.1 5.1 Vcc=15V Vcc = 15V 5.05 5.05 Tj = 25°C Iref = 1mA 5 5 4.95 4.95 4.9 4.9 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 150 Iref [mA] Tj (°C) 5/23

L5991 - L5991A Figure 9. Vref vs. junction temperature. Figure 10. Vref SVRR vs. switching frequency. Vref [V] SVRR (dB) 5.1 Vcc = 15V 120 Vcc=15V 5.05 Vp-p=1V Iref= 20mA 80 5 40 4.95 4.9 0 -50 -25 0 25 50 75 100 125 150 1 10 100 1000 10000 Tj (°C) fsw (Hz) Figure 11. Output saturation. Figure 12. Output saturation. Vsat = V [V] Vsat = V [V] 10 10 16 2.5 Vcc = Vc = 15V 14 Tj = 25°C 2 Vcc = Vc = 15V Tj = 25°C 12 1.5 10 1 8 0.5 6 0 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 Isource [A] Isink [A] Figure 13. UVLO Saturation Figure 14. Timing resistor vs. switching frequency. Ipin10 [mA] fsw (KHz) 50 5000 Vcc = 15V, V15 =0V Vcc < Vccon 2000 40 Tj = 25°C before turn-on 1000 30 500 100pF 200 20 220pF 100 470pF 50 10 5.6nF 2.2nF 1nF 20 0 10 0 200 400 600 800 1,000 1,200 1,400 10 20 30 40 Vpin10 [mV] Rt (kohm) 6/23

L5991 - L5991A Figure 16. Switching frequency vs. temperature. Figure 15. Switching frequency vs. tempera- ture. fsw (KHz) fsw (KHz) 320 320 Rt= 4.5Kohm, Ct = 1nF Rt= 4.5Kohm, Ct = 1nF 310 Vcc = 15V, V15= 0 310 Vcc = 15V, V15=Vref 300 300 290 290 280 280 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 Tj (°C) Tj (°C) Figure 18. Maximum Duty Cycle vs Vpin3. Figure 17. Dead time vs Ct. DC Control Voltage Vpin3 [V] Dead time [ns] 3.5 V15 = Vref V15 = 0V 1,500 Rt =4.5Kohm 3 V15 = 0V 1,200 2.5 900 V15 = Vref 2 600 Rt = 4.5Kohm, 1.5 Ct = 1nF 300 1 0 10 20 30 40 50 60 70 80 90 100 2 4 6 8 10 Timing capacitor Ct [nF] Duty Cycle [%] Figure 19. Delay to output vs junction temperature. Figure 20. E/A frequency response. Delay to output (ns) G [dB] Phase 140 42 150 40 120 38 100 100 36 80 34 50 60 32 PIN10 = OPEN 1V pulse 0 30 on PIN13 40 28 20 -50 -25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 1000 10000 100000 Tj (°C) f (KHz) 7/23

L5991 - L5991A Figure 21. Standby dynamic operation. STANDBY FUNCTION The standby function, optimized for flyback topol- Pin ogy, automatically detects a light load condition for the converter and decreases the oscillator fre- quency on that occurrence. The normal oscillation frequency is automatically resumed when the out- fosc put load builds up and exceeds a defined thresh- Normal operation old. This function allows to minimize power losses re- lated to switching frequency, which represent the PNO fSB majority of losses in a lightly loaded flyback, with- out giving up the advantages of a higher switching frequency at heavy load. PSB Stand-by This is accomplished by monitoring the output of the Error Amplifier (VCOMP) that depends linearly 1 2 VT1 3 VT2 4 on the peak primary current, except for an offset. VCOMP If the the peak primary current decreases (as a re- sult of a decrease of the power demanded by the matically the master. load) and VCOMP falls below a fixed threshold During the ramp-up of the oscillator the pin is (VT1), the oscillator frequency will be set to a pulled low by a 600m A internal sink current gener- lower value (fSB). When the peak primary current ator. During the falling edge, that is when the increases and VCOMP exceeds a second threshold pulse is released, the 600m A pull-down is discon- (VT2) the oscillator frequency is set to the normal nected. The pin becomes a generator whose value (fosc). An appropriate hysteresis (VT2-VT1) source capability is typically 7mA (with a voltage prevents undesired frequency change when still higher than 3.5V). power is such that VCOMP moves close to the In fig. 22, some practical examples of synchroniz- threshold. This operation is shown in fig. 21. ing the L5991 are given. Both the normal and the standby frequency are Since the device automatically diminishes its op- externally programmable. VT1 and VT2 are inter- erating frequency under light load conditions, it is nally fixed but it is possible to adjust the thresh- reasonable to suppose that synchronization will olds in terms of input power level. refer to normal operation and not to standby. APPLICATION INFORMATION Pin 2. RCT (Oscillator). Two resistors (RA and RB) Detailed Pin Function Description and one capacitor (CT), connected as shown in fig. 23, allow to set separately the operating fre- Pin 1. SYNC (In/Out Synchronization). This func- quency of the oscillator in normal operation (fosc) tion allows the IC’s oscillator either to synchronize and in standby mode (fSB). other controllers (master) or to be synchronized to an external frequency (slave). CT is charged from Vref through RA and RB in nor- mal operation (STANDBY = HIGH), through RA As a master, the pin delivers positive pulses dur- only in standby ( STANDBY = LOW). See pin 16 ing the falling edge of the oscillator (see pin 2). In description to see how the STANDBY signal is gen- slave operation the circuit is edge triggered. Refer erated. to fig. 23 to see how it works. When several IC work in parallel no master-slave designation is When the voltage on CT reaches 3V, the capaci- tor is quickly internally discharged. As the voltage needed because the fastest one becomes auto- has dropped to 1V it starts being charged again. Figure 22. Synchronizing the L5991. RB RA SYNC ST-BY SYNC ST-BY VREF 1L5991 416 VREF L51991 (MLA49S8T1EAR1)6 SYNC 1(SLL5A99V1E)416 VREF RB RCT 2(MLA5S9T94E1R)1 SYNC SYNC (LS4L9A8V1EA) RCT 2 RA 2 RCT 17 18 RCT 2 RA RB 16ST-BY 16 17 18 CT ROSC COSC CT CT ROSC COSC (a) (b) D97IN728A (c) 8/23

L5991 - L5991A Figure 23. Oscillator and synchronization internal schematic. SYNC 1 VREF 4 R1 D Q CLAMP R 600m A RA R3 R2 + RCT 2 CLK - D1 RB CT 50W ST-BY 16 STANDBY D97IN729A from fig. 14 or resulting from (1) and (2). The oscillation frequency can be established with the aid of the diagrams of fig. 14, where RT will be To prevent the oscillator frequency from switching intended as the parallel of RA and RB in normal back and forth from fosc to fSB, the ratio fosc / fSB operation and RT = RA in standby, or considering must not exceed 5.5. the following approximate relationships: If during normal operation the IC is to be synchro- nized to an external oscillator, RA, RB and CT f @ 1 (1), should be selected for a fosc lower than the master osc CT (cid:215) (0.693 (cid:215) (RA // RB) + KT frequency in any condition (typically, 10-20% ), depending also on the tolerance of the parts. which gives the normal operating frequency, and: Pin 3. DC (Duty Cycle Control). By biasing this fSB @ CT (cid:215) (0.6931 (cid:215) RA + KT) (2), ptoin s weti tthh ea mvoaltxaimgeu mbe dtwuetye ncy 1c laen bde 3tw Ve eitn i s0 paonsds itbhlee upper extreme Dx (see pin 15). which gives the standby frequency, that is the one If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: the converter will operate at when lightly loaded. In the above expressions, RA // RB means: R //R = RA (cid:215) RB, V3 = 5 - 2(2-Dmax) (5) A B RA + RB while KT is defined as: Dmax is determined by internal comparison be- tween V3 and the oscillator ramp (see fig. 24), (cid:236) 90 V = VREF thus in case the device is synchronized to an ex- KT = (cid:237)(cid:238) 160 V1155 = GND/OPEN (3), atemrnpalilt ufdreeq iuse rnecdyu cfeexdt )(,a (n5d) cthhaenregfeosr ein tthoe: oscillator athned s ias wretolaottehd: to the duration of the falling-edge of V3 = 5 - 4 (cid:215) exp (cid:230)(cid:231)Ł - RT (cid:215)D CmTa x(cid:215) fext(cid:246)(cid:247)ł (6) Td » 30 (cid:215) 10- 9 + KT (cid:215) CT (4). A voltage below 1V will inhibit the driver output Td is also the duration of the sync pulses deliv- stage. This could be used for a not-latched device ered at pin 1 and defines the upper extreme of the disable, for example in case of overvoltage pro- duty cycle range, Dx (see pin 15 for DX definition tection (see application ideas). and calculation) since the output is held low dur- If no limitation on the maximum duty cycle is re- ing the falling edge. quired (i.e. DMAX = DX), the pin has to be left float- In case V15 is connected to VREF, however, the ing. An internal pull-up (see fig. 24) holds the volt- switching frequency will be a half the values taken age above 3V. Should the pin pick up noise (e.g. 9/23

L5991 - L5991A during ESD tests), it can be connected to VREF duce the oscillator frequency when the converter through a 4.7kW resistor. is lightly loaded (standby). Figure 24. Duty cycle control. Pin 7. SS (Soft-Start). At device start-up, a ca- pacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage VREF 4 across Css itself and allowed to rise linearly, start- ing from zero, up to the steady-state value im- R1 3m A posed by the control loop. The maximum time in- terval during which the E/A is clamped, referred to DC 3 23K as soft-start time, is approximately: RA R2 28K 3 (cid:215) R (cid:215) I T @ sense Qpk (cid:215) C (7) ss ss ST-BY 16 ISSC RB RCT 2 + TO PWM LOGIC where Rsense is the current sense resistor (see pin - 13) and IQpk is the switch peak current (flowing CT through Rsense), which depends on the output D97IN727A load. Usually, CSS is selected for a TSS in the or- der of milliseconds. Pin 4. VREF (Reference Voltage). The device is As mentioned before, the soft-start intervenes provided with an accurate voltage reference also in case of severe overload or short circuit on (5V– 1.5%) able to deliver some mA to an external the output. Referring to fig. 25, pulse-by-pulse circuit. current limitation is somehow effective as long as A small film capacitor (0.1 m F typ.), connected Figure 25. Regulation characteristic and re- between this pin and SGND, is recommended to lated quantities. ensure the stability of the generator and to prevent noise from affecting the reference. Before device turn-on, this pin has a sink current ca- VOUT A IQpk pability of 0.5mA. D.C.M. C.C.M. 1-2 ·IQpk Pin 5. VFB (Error Amplifier Inverting Input). The IQpk(max) feedback signal is applied to this pin and is com- C B pared to the E/A internal reference (2.5V). The E/A output generates the control voltage which TON D fixes the duty cycle. The E/A features high gain-bandwidth product, TON(min) which allows to broaden the bandwidth of the D97IN495 ISHORT IOUT(max) IOUT overall control loop, high slew-rate and current ca- pability, which improves its large signal behavior. the ON-time of the power switch can be reduced Usually the compensation network, which stabi- (from A to B). After the minimum ON-time is lizes the overall control loop, is connected be- reached (from B onwards) the current is out of tween this pin and COMP (pin 6). control. To prevent this risk, a comparator trips an over- Pin 6. COMP (Error Amplifier Output). Usually, current handling procedure, named ’hiccup’ mode this pin is used for frequency compensation and operation, when a voltage above 1.2V (point C) is the relevant network is connected between this detected on current sense input (ISEN, pin 13). pin and VFB (pin 5). Compensation networks to- Basically, the IC is turned off and then soft-started wards ground are not possible since the L5991 as long as the fault condition is detected. As a re- E/A is a voltage mode amplifier (low output im- sult, the operating point is moved abruptly to D, pedance). See application ideas for some exam- creating a foldback effect. Fig. 26 illustrates the ple of compensation techniques. operation. It is worth mentioning that the calculation of the The oscillation frequency appearing on the soft- part values of the compensation network must start capacitor in case of permanent fault, referred take the standby frequency operation into ac- to as ’hiccup" period, is approximately given by: count. In particular, this means that the open-loop crossover frequency must not exceed fSB/4 ‚ fTShBe/5 .voltage on pin 6 is monitored in order to re- Thic @ 4.5 (cid:215) (cid:230)(cid:231)Ł IS1SC + IS1SD(cid:246)(cid:247)ł (cid:215) Css (8) 10/23

L5991 - L5991A Since the system tries restarting each hiccup cy- MOS. At turn-on the gate resistance is Rg + Rg’, at cle, there is not any latchoff risk. turn-off is Rg only. "Hiccup" keeps the system in control in case of Figure 27. Turn-on and turn-off speeds adjust- short circuits but does not eliminate power com- ment. ponents overstress during pulse-by-pulse limita- tion (from A to C). Other external protection cir- Rg' cuits are needed if a better control of overloads is required. VCC VC Rg(ON)=Rg+Rg' Rg(OFF)=Rg 8 9 Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as 13V VCC voltage exceeds the start threshold and DRIVE & 10 works as long as the voltage is above the UVLO CONTROL OUT Rg threshold. Otherwise the device is shut down and the current consumption is extremely low (<150m A). This is particularly useful for reducing L5991 11 D97IN726 PGND the consumption of the start-up circuit (in the sim- plest case, just one resistor), which is one of the most significant contributions to power losses in Pin 10. OUT (Driver Output). This pin is the out- standby. put of the driver stage of the external power An internal Zener limits the voltage on VCC to switch. Usually, this will be a PowerMOS, al- 25V. The IC current consumption increases con- though the driver is powerful enough to drive siderably if this limit is exceeded. BJT’s (1.6A source, 2A sink, peak). A small film capacitor between this pin and SGND The driver is made up of a totem pole with a high- (pin 12), placed as close as possible to the IC, is side NPN Darlington and a low-side VDMOS, thus recommended to filter high frequency noise. there is no need of an external diode clamp to prevent voltage from going below ground. An in- ternal clamp limits the voltage delivered to the Pin 9. VC (Supply of the Power Stage). It supplies gate at 13V. Thus it is possible to supply the the driver of the external switch and therefore ab- driver (Pin 9) with higher voltages without any risk sorbs a pulsed current. Thus it is recommended to of damage for the gate oxide of the external MOS. place a buffer capacitor (towards PGND, pin 11, The clamp does not cause any additional in- as close as possible to the IC) able to sustain crease of power dissipation inside the chip since these current pulses and in order to avoid them the current peak of the gate charge occurs when inducing disturbances. the gate voltage is few volts and the clamp is not This pin can be connected to the buffer capacitor active. Besides, no current flows when the gate directly or through a resistor, as shown in fig. 27, voltage is 13V, steady state. to control separately the turn-on and turn-off Under UVLO conditions an internal circuit (shown speed of the external switch, typically a Power- Figure 26. Hiccup mode operation. I OUT SHORT I SEN FAULT SS 5V 7V 0.5V time Thic D98IN986 11/23

L5991 - L5991A in fig.28) holds the pin low in order to ensure that Pin 13. ISEN (Current Sense). This pin is to be the external MOS cannot be turned on acciden- connected to the "hot" lead of the current sense tally. The peculiarity of this circuit is its ability to resistor Rsense (being the other one grounded), to mantain the same sink capability (typically, 20mA get a voltage ramp which is an image of the cur- @ 1V) from VCC = 0V up to the start-up threshold. rent of the switch (IQ). When this voltage is equal When the threshold is exceeded and the L5991 to: starts operating, VREFOK is pulled high (refer to fig. 28) and the circuit is disabled. It is then possible to omit the "bleeder" resistor V13pk = IQpk (cid:215) Rsense = VCOMP - 1.4 (9) (connected between the gate and the source of 3 the MOS) ordinarily used to prevent undesired switching-on of the external MOS because of some leakage current. the conduction of the switch is terminated. To increase the noise immunity, a "Leading Edge Figure 28. Pull-Down of the output in UVLO. Blanking" of about 100ns is internally realized as shown in fig. 29. Because of that, the smoothing RC filter between this pin and Rsense could be re- moved or, at least, considerably reduced. OUT 10 Pin 14. DIS (Device Disable). When the voltage on pin 14 rises above 2.5V the IC is shut down VREFOK and it is necessary to pull VCC (IC supply voltage, pin 8) below the UVLO threshold to allow the de- vice to restart. The pin can be driven by an external logic signal 12 SGND in case of power management, as shown in fig. 30. It is also possible to realize an overvoltage D97IN538 protection, as shown in the section " Application Ideas".If used, bypass this pin to ground with a fil- Pin 11. PGND (Power Ground). The current loop ter capacitor to avoid spurious activation due to during the discharge of the gate of the external noise spikes. If not, it must be connected to MOS is closed through this pin. This loop should SGND. be as short as possible to reduce EMI and run separately from signal currents return. Pin 15. DC-LIM (Maximum Duty Cycle Limit). The upper extreme, Dx, of the duty cycle range de- Pin 12. SGND (Signal Ground). This ground refer- pends on the voltage applied to this pin. Approxi- ences the control circuitry of the IC, so all the mately, ground connections of the external parts related to control functions must lead to this pin. In laying R out the PCB, care must be taken in preventing Dx @ R + T230 (10) switched high currents from flowing through the T SGND path. if DC-LIM is grounded or left floating. Instead, Figure 29. Internal LEB. 2V I 3V + 0 - CLK PWM ISEN 13 + COMPARATOR TO PWM LOGIC FROM E/A - + TO FAULT LOGIC 1.2V - OVERCURRENT COMPARATOR D97IN503 12/23

L5991 - L5991A Figure 30. Disable (Latched). and the output switching frequency will be halved with respect to the oscillator one because an in- ternal T flip-flop (see block diagram) is activated. Fig. 31 shows the operation. DISABLE The half duty cycle option speeds up the dis- SIGNAL charge of the timing capacitor CT (in order to get duty cycles as close to 50% as possible) so the oscillator frequency - with the same timing compo- DIS 14 + D DISABLE nents will be slightly higher. Q - R C 2.5V Pin 16. S-BY (Standby Function). The resistor RB, along with RA, sets the operating frequency of the UVLO D97IN502 oscillator in normal operation (fosc). In fact, as long as the STANDBY signal is high, the pin is inter- connecting DC-LIM to VREF (half duty cycle op- nally connected to the reference voltage VREF by tion), Dx will be set approximately at: a N-channel FET (see fig. 32), so the timing ca- pacitor CT is charged through RA and RB. When R the STANDBY signal goes low the N-channel FET Dx @ 2 (cid:215) RT T+ 260 (11) is turned off and the pin becomes floating. RB is Figure 31. Half duty cycle option. td V15=GND V5=V13=GND V2 tc DX = tc + td V10 tc td V15=VREF V5=V13=GND V2 tc DX = 2 ·tc + td V10 tc D97IN498 Figure 32. Standby function internal schematic and operation. COMP ISEN 6 13 + 2R R DRIVER OUT - R STANDBY 10V 4 5 FB - VREF + STANDBY + HIGH 2.5 - 2.5/4 ST-BY LEVEL SHIFT 16 STANDBY BLOCK LOW RB RA VT1 VT2 VCOMP 2.5V 4V 2 RCT CT D97IN752B 13/23

L5991 - L5991A now disconnected and CT is charged through RA Layout hints only. In this way the oscillator frequency (fSB) will Generally speaking a proper circuitboard layout is be lower. Refer to pin 2 description to see how to vital for correct operation but is not an easy task. calculate the timing components. Careful component placing, correct traces routing, Typical values for VT1 and VT2 are 2.5 V and 4V appropriate traces widths and, in case of high respectively. This 1.5V hysteresis is enough to voltages, compliance with isolation distances are prevent undesired frequency change up to a 5.5 the major issues. The L5991 eases this task by to 1 fosc/ fSB ratio. putting two pins at disposal for separate current The value of VT1 is such that in a discontinuous returns of bias (SGND) and switch drive currents flyback the standby frequency is activated when (PGND) The matter is complex and only few im- the input power is about 13% of the maximum. If portant points will be here reminded. necessary, it is possible to decrease the power 1) All current returns (signal ground, power threshold below 13% by adding a DC offset (Vo) ground, shielding, etc.) should be routed sepa- on the current sense pin (13, ISEN). This will also rately and should be connected only at a single allow a frequency change greater than 5.5 to 1. ground point. The following equations, useful for design, apply: 2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This 2 PinSB = 12 (cid:215) LP (cid:215) ƒosc (cid:215) (cid:230)(cid:231)Ł 0.3R6s7en -se Vo(cid:246)(cid:247)ł (12), acuprprleiensts p falorwtic.ularly to loops where high pulsed 3) For high current paths, the traces should be doubled on the other side of the PCB whenever PinNO = 1 (cid:215) LP (cid:215) ƒSB (cid:215) (cid:230)(cid:231) 0.867 - Vo(cid:246)(cid:247) 2 (13), paonsds tihbele i:n dthuicst awniclle roefd tuhcee w birointhg .the resistance 2 Ł Rsense ł 4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying ƒ (cid:230) 0.867 - V (cid:246) 2 switched currents as short as possible. osc < (cid:231) o(cid:247) (14), ƒSB Ł 0.367 - Voł 5) In general, traces carrying signal currents should run far from traces carrying pulsed cur- rents or with quickly swinging voltages. From where PinSB is the input power below which the this viewpoint, particular care should be taken L5991 recognizes a light load and switches the of the high impedance points (current sense in- oscillator frequency from ƒosc to fSB, PinNO is the put, feedback input, ...). It could be a good idea input power above which the L5991 switches to route signal traces on one PCB side and back from ƒSB to ƒosc and Lp the primary induc- power traces on the other side. tance of the flyback transformer. 6) Provide adequate filtering of some crucial Connect to Vref or leave open this pin when points of the circuit, such as voltage references, stand-by function is not used. IC’s supply pins, etc. 14/23

L5991 - L5991A either improving performance or solving common APPLICATION IDEAS application problems of L5991 based supplies. Here follows a series of ideas/suggestions aimed at Figure 33. Typical application circuit for computer monitors (90W). 180V65W 80V10W GND 6.3V5W +15V5W -15V5W V 0 0 21 C6F m0 10 0A 3 7 N 7I 9 D C52m100F250V C59m0.01F R564.3K F V C55m100016V R5247 C58F 25V VR51100K R55300K 0 m7 F 4KV C12 R20 4.7M18D52 BYT13-800 17D53 BYT11-600 16C54m220F 10 1514D54 BYW100-100 13D55 BYW100-10012 C56m470F 25VC5711m470F 25V 10D56 BYW100-100 R5344.7K C61m0.056F R584.7K p 0 M C11 470 R19 4.71 C1010nF100V 37 07 47 8 Q01STP6NA60FI R541K 4N35 Q51TL431 R R18R1647K750K3W D05R171N4937750K D04 1N4148 mC04 47F R08 22 R11 1K C05100pFR100.22 R21 100 C083.3nF BD01R01 3.32FmC03 220F400V R03 47KR04 47K C112.2nFR12 330K R13 47KR06 27 914168 10 L599113 12 11 6 88110220270 2.953.103.904.40 2 C0m0.1 4 2 16 7 5 V) W) W) 1 D06N4148 VAC( Pin( Pout( 0 1 LF R512K R924K 250V T3.15A C01m0.1F mC07 1F C06 6800pF C09 8.2nF C 1 A 270C F0 8 to VA 8 15/23

L5991 - L5991A Figure 34. Typical application circuit for inkjet printers (40W). A A 7 5 A 28V / 0. 12V / 1. GND 5V / 0.5 K 0 7 2 F m30V 35 x 3 K 2 5.1 K F V 3.9 0 m06 0 71 2 F 4 BYW100- W98-100 m2 x 47016V W100-50 m0.022F V BY BY K 00pF 4 7M N2 N3 N4 1K 2.7K 47 4. V 0 4700pF 4K 4.7M N1 Naux STP4NA6 0.471/2 W 220 4N35 TL431 4 7 5 3 1 9 6- N4 W0 1 V BZ10K BAT46 m33F/25 22 1K 470pF 470 470pF 97IN618 D 0 5 2.2 mF100400V STK2N 33K 22 98 10 13 12 11 6 1 BD0 14 91 K 9 4.7 5 L5 5 265 1.57 1 C02 m0.1F M M 22V 5.6K 4 3 2 16 1 7 110220 0.931.14 0.55 LF01 1.1 1.1 37 5.6K 5.6K 85 0.90 3 C AC 250V T1A C01 m0.1F B 47K 100nF 22K 3.3nF 330nF VAC(V) Pin(W) Pout(W) 1 c F0 OVa 5 T65 82 16/23

L5991 - L5991A Figure 35. Standby thresholds adjustment. SGND L5991 10 12 4 13 VREF ISEN R RA RSENSE OPTIONAL D97IN751A Figure 36. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies. VIN ISOLATION BOUNDARY VC 9 10 OUT L5991 ISEN 13 12 11 PGND SGND D97IN761 Figure 37. Low consumption start-up. VIN 2.2MW 33KW STD1NB50-1 T VCC 20V VREF 4 8 SEWLFIN-SDUINPGPLY 47KW L5991 12 11 D97IN762B Figure 38. Bipolar transistor driver. VIN VCC VC 8 9 10 OUT ISEN 13 L5991 11 PGND D97IN763 17/23

L5991 - L5991A Figure 39. Typical E/A compensation networks. + From VO 2.5V 1.3mA Ri + 2R VFB 5 - EA Rd Cf Rf R COMP 6 12 SGND Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. + From VO 2.5V 1.3mA RP + 2R Ri VFB 5 - EA CP Rd Cf Rf R COMP 6 12 SGND D97IN507 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. Figure 40. Feedback with optocoupler. VOUT COMP 6 L5991 5 TL431 VFB D97IN759 Figure 41. Slope compensation techniques. ST-BY ST-BY 16 VREF 16 VREF 4 10 OUT 4 RB RA RB RA R RCT RCT 2 2 I RSLOPE CT L5991 I RSLOPE CT L5991 L5991 RSLOPE CSLOPE ISEN ISEN ISEN 13 13 13 12 12 12 RSENSE SGND RSENSE SGND SGND RSENSE OPTIONAL OPTIONAL OPTIONAL D97IN760A 18/23

L5991 - L5991A Figure 42. Protection against overvoltage/feedback disconnection (latched) RSTART RSTART VCC VZ VCC 8 8 DIS DIS 14 L5991 14 L5991 12 11 2.2K 12 11 SGND PGND SGND PGND D97IN754 D98IN905 Figure 43 Protection against overvoltage/feed- Figure 44. Device shutdown on overcurrent back disconnection (not latched) RSTART 4 VREF Ipk max @ RS2E.N5SE • 1- RR21 R1 I Ipk DIS VREF VCC 14 4 8 L5991 R2 DC L5991 ISEN 3 13 11 12 12 11 PGND SGND RSENSE OPTIONAL D97IN755A D97IN756A Figure 45. Constant power in pulse-by-pulse current limitation (flyback discontinuous) V IN 80 ‚ 400VDC Lp R FF OUT R = 6·106 R·Lp FF RSENSE 10 L5991 ISEN 13 11 12 R RSENSE PGND SGND D97IN757 Figure 46. Voltage mode operation. DC 3 10K L5991 6 COMP 12 13 SGND ISEN D97IN758A 19/23

L5991 - L5991A Figure 47. Device shutdown on mains undervoltage. V IN 80÷400V DC R1 VREF 4 4.7K L5991 3 12 11 5.1 R2 10KW SGND PGND D97IN750B Figure 48. Synchronization to flyback pulses (for monitors). SYNC 1 L5991 1KW 12 5.1V SGND D97IN753A 20/23

L5991 - L5991A mm inch OUTLINE AND DIM. MECHANICAL DATA MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 DIP16 Z 1.27 0.050 21/23

L5991 - L5991A mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45˚ (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M 0.62 0.024 SO16 Narrow S 8˚(max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 22/23

L5991 - L5991A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 23/23

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