KSZ8993M/ML Integrated 3-Port 10/100 Managed Switch with PHYs Rev 1.06 General Description The KSZ8993M, a highly integrated Layer 2 The KSZ8993M contains two 10/100 transceivers managed switch, is designed for low port count, with patented mixed-signal low-power technology, cost-sensitive 10/100 Mbps switch systems. It offers three media access control (MAC) units, a high- an extensive feature set that includes tag/port-based speed non-blocking switch fabric, a dedicated VLAN, quality of service (QoS) priority, address lookup engine, and an on-chip frame buffer management, management information base (MIB) memory. counters, MII/SNI, and CPU control/data interfaces Both PHY units support 10BASE-T and 100BASE- to effectively address both current and emerging TX. In addition, one of the PHY unit supports Fast Ethernet applications. 100BASE-FX. The KSZ8993ML is the single supply version with all the identical rich features of the KSZ8993M. ___________________________________________________________________________________________________ Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com October 2008 1 M9999-020606

Micrel, Inc. KSZ8993M/ML 1KLook-Up Engine 10/100 AUTO 10/100 T/TX/FX MDI/MDI-X PHY 1 MAC1 Queue FIFO Management MDI/MADUTI-OX 1PT0H//T1YX0 20 1M0A/1C020 ,Flow C o n Buffer tro Management , Vl 10/100 L MII/SNI A MAC3 N T a g Frame g in Buffers g SNI ,Prio rity MIB SPI SPI Counters MIIM Control EEPROM Registers Interface SMI I2C P1 LED[3:0] LED Strap-In Drivers ConfigurationPins P2 LED[3:0] – Control registers configurable on the fly (port- Features priority, 802.1p/d/q, AN…) • QoS/CoS Packet Prioritization Support • Proven Integrated 3-Port 10/100 Ethernet Switch – Per port, 802.1p and DiffServ-based – 2nd generation switch with three MACs and two – Re-mapping of 802.1p priority field per port basis PHYs fully compliant to IEEE 802.3u standard • Advanced Switch Features – Non-blocking switch fabric assures fast packet – IEEE 802.1q VLAN support for up to 16 groups delivery by utilizing a 1K MAC address lookup table (full-range of VLAN ID) and a store-and-forward architecture – VLAN ID tag/untag options, per port basis – Full duplex IEEE 802.3x flow control (pause) with – IEEE 802.1p/q tag insertion or removal on a per force mode option port basis (egress) – Half-duplex back pressure flow control – Programmable rate limiting from 0Mbps to – Automatic MDI/MDI-X crossover with disable and 100Mbps at the ingress and egress port, rate options enable option for high and low priority per port basis – 100BASE-FX support on port 1 – Broadcast storm protection with % control (global – MII interface supports both MAC mode and PHY and per port basis) mode – IEEE 802.1d spanning tree protocol support – 7-wire serial network interface (SNI) support for – Upstream special tagging mode to inform the legacy MAC processor which ingress port receives the packet – Comprehensive LED Indicator support for link, – IGMP v1/v2 snooping support for multicast packet activity, full/half duplex and 10/100 speed filtering • Comprehensive Configuration Register Access – Double-tagging support – Serial management interface (SMI) to all internal registers – MII management (MIIM) interface to PHY registers – SPI and I2C Interface to all internal registers – I/0 Pins strapping and EEPROM to program selective registers in unmanaged switch mode October 2008 2 M9999-020606

Micrel, Inc. KSZ8993M/ML • Switch Management Features – Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII – MIB counters for fully compliant statistics gathering, 34 MIB counters per port – Loopback modes for remote diagnostic of failure • Low Power Dissipation: <0.8 Watts (includes PHY transmit drivers) – Full-chip hardware power-down (register configuration not saved) – Per port based software power-save on PHY (idle link detection, register configuration preserved) – 0.18um CMOS technology – Voltages: Core 1.8V I/O and Transceiver 3.3V Use K8993ML for 3.3V only operation • Available in128-Pin PQFP Applications • Universal Solutions – Broadband gateway / Firewall / VPN – Integrated DSL or cable modem multi-port router – Wireless LAN access point + gateway – Residential and enterprise VoIP gateway/phone – Set-top/game box – Home networking expansion – Standalone 10/100 switch – FTTx customer premises equipment – Fiber broadband gateway • Upgradeable Solutions(1) – Unmanaged switch with future option to migrate to a managed solution – Single PHY alternative with future expansion option for two ports • Industrial Solutions – Applications requiring port redundancy and port monitoring – Sensor devices in redundant ring topology Note: 1. The cost and time of PCB re-spin. October 2008 3 M9999-020606

Micrel, Inc. KSZ8993M/ML Ordering Information Part Number Temperature Range Package Pb-Free Standard KSZ8993M KS8993M 0oC to 70oC 128-Pin PQFP, Lead-free KSZ8993ML KS8993ML 0oC to 70oC 128-Pin PQFP, Lead-free KSZ8993MI KS8993MI –40oC to +85oC 128-Pin PQFP, Lead-free KSZ8993MLI KS8993MLI –40oC to +85oC 128-Pin PQFP, Lead-free October 2008 4 M9999-020606

Micrel, Inc. KSZ8993M/ML Revision History Revision Date Summary of Changes 1.00 5/14/03 Created. 1.01 5/28/03 Added KS8993MI availability in Q4 2003. 1.02 12/8/03 Changed V , V and V supply voltages DDIO DDATX DDARX from 3.3V to (3.3V or 2.5V). Changed [PS1,PS0] = [1,1] setting from Reserved to SMI mode. Changed Special Tagging Mode to Upstream Special Tagging Mode (Switch port 3 to processor support only). Updated recommended magnetic manufacturer list. Added 25MHz crystal/oscillator clock’s ppm spec. in Pin Description. Updated I2C Slave Serial Bus Configuration section. Updated KSZ8993MI availability to from Q1 2004. 1.03 9/22/04 Added KS8993ML to General Description (page 1) and to the Functional Description. Updated Part Ordering Information table. Updated pin description for pin 22 to the following: V : For KS8993M, this is an input power pin for the 1.8V digital DDC core V . DD V _1V8: For KS8993ML, this is an 1.8V output power pin to OUT supply the KS8993ML’s input power pins: V DDAP (pin 63), V (pins 91, 123), and V (pins 38, DDC DDA 43, 57). Updated pin description for P1LED3 (pin 25) to indicate that an external 1K pull-down is needed if a LED is connected. Updated pin description for MDIO (pin 95) to indicate that an external 4.7K pull-up is needed if this pin is in used. Changed the aging period from 300 +/–75 seconds to about 200 seconds. Updated Electrical Characteristics (V , V , V , V ). IH IL OH OL Transferred to new format. 1.04 4/12/05 Removed references to 2.5V operation Added reset circuit recommendation 1.05 2/14/05 Updated to add Pb-Free spwcifications 1.06 2/13/07 Add the P/N KSZ8993I into the Ordering information table 1.06a 10/28/08 Add the P/N KSZ8993MLI into the Ordering information table Modify the current consumption table from board to device. October 2008 5 M9999-020606

Micrel, Inc. KSZ8993M/ML Contents List of Figures.........................................................................................................................................9 List of Tables...........................................................................................................................................9 Pin Description and I/O Assignment...................................................................................................10 Pin Configuration..................................................................................................................................20 Functional Description.........................................................................................................................21 Functional Overview: Physical Layer Transceiver............................................................................21 100BASE-TX Transmit.........................................................................................................................................................21 100BASE-TX Receive..........................................................................................................................................................21 PLL Clock Synthesizer........................................................................................................................................................22 Scrambler/De-scrambler (100BASE-TX Only)...................................................................................................................22 100BASE-FX Operation.......................................................................................................................................................22 100BASE-FX Signal Detection............................................................................................................................................22 100BASE-FX Far End Fault.................................................................................................................................................22 10BASE-T Transmit.............................................................................................................................................................23 10BASE-T Receive..............................................................................................................................................................23 Power Management.............................................................................................................................................................23 MDI /MDI-X Auto Crossover................................................................................................................................................23 Straight Cable................................................................................................................................................................23 Crossover Cable............................................................................................................................................................25 Auto Negotiation.................................................................................................................................................................25 Functional Overview: MAC and Switch..............................................................................................27 Address Lookup..................................................................................................................................................................27 Learning...............................................................................................................................................................................27 Migration..............................................................................................................................................................................27 Aging....................................................................................................................................................................................27 Forwarding...........................................................................................................................................................................27 Switching Engine................................................................................................................................................................30 MAC Operation....................................................................................................................................................................30 Inter Packet Gap (IPG)..................................................................................................................................................30 Back-Off Algorithm.........................................................................................................................................................30 Late Collision.................................................................................................................................................................30 Illegal Frames................................................................................................................................................................30 Flow Control...................................................................................................................................................................30 Half-Duplex Backpressure.............................................................................................................................................30 Broadcast Storm Protection...........................................................................................................................................31 MII Interface Operation........................................................................................................................................................31 SNI (7-Wire) Operation........................................................................................................................................................32 MII Management Interface (MIIM).......................................................................................................................................32 Serial Management Interface (SMI)....................................................................................................................................33 Advanced Switch Functions................................................................................................................34 Spanning Tree Support.......................................................................................................................................................34 Upstream Special Tagging Mode.......................................................................................................................................35 IGMP Support......................................................................................................................................................................36 “IGMP” Snooping...........................................................................................................................................................36 “Multicast Address Insertion” in the Static MAC Table...................................................................................................36 Port Mirroring Support........................................................................................................................................................36 IEEE 802.1Q VLAN Support................................................................................................................................................36 QoS Priority Support...........................................................................................................................................................37 Rate Limiting Support.........................................................................................................................................................39 Configuration Interface.......................................................................................................................................................39 I2C Master Serial Bus Configuration..............................................................................................................................39 I2C Slave Serial Bus Configuration................................................................................................................................40 SPI Slave Serial Bus Configuration...............................................................................................................................40 Loopback Support...............................................................................................................................................................44 MII Management (MIIM) Registers.......................................................................................................45 October 2008 6 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 0: MII Basic Control..........................................................................................................................................46 Register 1: MII Basic Status...........................................................................................................................................46 Register 2: PHYID HIGH................................................................................................................................................46 Register 3: PHYID LOW.................................................................................................................................................46 Register 4: Auto-Negotiation Advertisement Ability........................................................................................................47 Register 5: Auto-Negotiation Link Partner Ability...........................................................................................................47 Register Map: Switch & PHY (8 bit registers).....................................................................................48 Global Registers.............................................................................................................................................................48 Port Registers................................................................................................................................................................48 Advanced Control Registers...........................................................................................................................................48 Global Registers..................................................................................................................................................................48 Register 0 (0x00): Chip ID0............................................................................................................................................48 Register 1 (0x01): Chip ID1 / Start Switch......................................................................................................................49 Register 2 (0x02): Global Control 0................................................................................................................................49 Register 3 (0x03): Global Control 1................................................................................................................................50 Register 4 (0x04): Global Control 2................................................................................................................................50 Register 5 (0x05): Global Control 3................................................................................................................................51 Register 6 (0x06): Global Control 4................................................................................................................................52 Register 7 (0x07): Global Control 5................................................................................................................................53 Register 8 (0x08): Global Control 6................................................................................................................................53 Register 9 (0x09): Global Control 7................................................................................................................................53 Register 10 (0x0A): Global Control 8..............................................................................................................................53 Register 11 (0x0B): Global Control 9..............................................................................................................................53 Register 12 (0x0C): Reserved Register..........................................................................................................................54 Register 13 (0x0D): User Defined Register 1.................................................................................................................54 Register 14 (0x0E): User Defined Register 2.................................................................................................................54 Register 15 (0x0F): User Defined Register 3.................................................................................................................54 Port Registers......................................................................................................................................................................55 Register 16 (0x10): Port 1 Control 0...............................................................................................................................55 Register 32 (0x20): Port 2 Control 0...............................................................................................................................55 Register 48 (0x30): Port 3 Control 0...............................................................................................................................55 Register 17 (0x11): Port 1 Control 1...............................................................................................................................56 Register 33 (0x21): Port 2 Control 1...............................................................................................................................56 Register 49 (0x31): Port 3 Control 1...............................................................................................................................56 Register 18 (0x12): Port 1 Control 2...............................................................................................................................57 Register 34 (0x22): Port 2 Control 2...............................................................................................................................57 Register 50 (0x32): Port 3 Control 2...............................................................................................................................57 Register 19 (0x13): Port 1 Control 3...............................................................................................................................57 Register 35 (0x23): Port 2 Control 3...............................................................................................................................57 Register 51 (0x33): Port 3 Control 3...............................................................................................................................57 Register 20 (0x14): Port 1 Control 4...............................................................................................................................58 Register 36 (0x24): Port 2 Control 4...............................................................................................................................58 Register 52 (0x34): Port 3 Control 4...............................................................................................................................58 Register 21 (0x15): Port 1 Control 5...............................................................................................................................58 Register 37 (0x25): Port 2 Control 5...............................................................................................................................58 Register 53 (0x35): Port 3 Control 5...............................................................................................................................58 Register 22 (0x16): Port 1 Control 6...............................................................................................................................58 Register 38 (0x26): Port 2 Control 6...............................................................................................................................58 Register 54 (0x36): Port 3 Control 6...............................................................................................................................58 Register 23 (0x17): Port 1 Control 7...............................................................................................................................58 Register 39 (0x27): Port 2 Control 7...............................................................................................................................58 Register 55 (0x37): Port 3 Control 7...............................................................................................................................58 Register 24 (0x18): Port 1 Control 8...............................................................................................................................58 Register 40 (0x28): Port 2 Control 8...............................................................................................................................58 Register 56 (0x38): Port 3 Control 8...............................................................................................................................58 Register 25 (0x19): Port 1 Control 9...............................................................................................................................59 Register 41 (0x29): Port 2 Control 9...............................................................................................................................59 Register 57 (0x39): Port 3 Control 9...............................................................................................................................59 Register 26 (0x1A): Port 1 Control 10............................................................................................................................59 Register 42 (0x2A): Port 2 Control 10............................................................................................................................59 Register 58 (0x3A): Port 3 Control 10............................................................................................................................59 Register 27 (0x1B): Port 1 Control 11............................................................................................................................59 October 2008 7 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 43 (0x2B): Port 2 Control 11............................................................................................................................59 Register 59 (0x3B): Port 3 Control 11............................................................................................................................59 Register 28 (0x1C): Port 1 Control 12............................................................................................................................60 Register 44 (0x2C): Port 2 Control 12............................................................................................................................60 Register 60 (0x3C): Reserved, not applied to port 3......................................................................................................60 Register 29 (0x1D): Port 1 Control 13............................................................................................................................61 Register 45 (0x2D): Port 2 Control 13............................................................................................................................61 Register 61 (0x3D): Reserved, not applied to port 3......................................................................................................61 Register 30 (0x1E): Port 1 Status 0................................................................................................................................62 Register 46 (0x2E): Port 2 Status 0................................................................................................................................62 Register 62 (0x3E): Reserved, not applied to port 3......................................................................................................62 Register 31 (0x1F): Port 1 Status 1................................................................................................................................63 Register 47 (0x2F): Port 2 Status 1................................................................................................................................63 Register 63 (0x3F): Port 3 Status 1................................................................................................................................63 Advanced Control Registers..............................................................................................................................................64 Register 96 (0x60): TOS Priority Control Register 0.......................................................................................................64 Register 97 (0x61): TOS Priority Control Register 1.......................................................................................................64 Register 98 (0x62): TOS Priority Control Register 2.......................................................................................................64 Register 99 (0x63): TOS Priority Control Register 3.......................................................................................................64 Register 100 (0x64): TOS Priority Control Register 4.....................................................................................................64 Register 101 (0x65): TOS Priority Control Register 5.....................................................................................................64 Register 102 (0x66): TOS Priority Control Register 6.....................................................................................................64 Register 103 (0x67): TOS Priority Control Register 7.....................................................................................................64 Register 104 (0x68): MAC Address Register 0..............................................................................................................65 Register 105 (0x69): MAC Address Register 1..............................................................................................................65 Register 106 (0x6A): MAC Address Register 2..............................................................................................................65 Register 107 (0x6B): MAC Address Register 3..............................................................................................................65 Register 108 (0x6C): MAC Address Register 4..............................................................................................................65 Register 109 (0X6D): MAC Address Register 5.............................................................................................................65 Register 110 (0x6E): Indirect Access Control 0..............................................................................................................66 Register 111 (0x6F): Indirect Access Control 1..............................................................................................................66 Register 112 (0x70): Indirect Data Register 8................................................................................................................66 Register 113 (0x71): Indirect Data Register 7................................................................................................................66 Register 114 (0x72): Indirect Data Register 6................................................................................................................66 Register 115 (0x73): Indirect Data Register 5................................................................................................................66 Register 116 (0x74): Indirect Data Register 4................................................................................................................66 Register 117 (0x75): Indirect Data Register 3................................................................................................................67 Register 118 (0x76): Indirect Data Register 2................................................................................................................67 Register 119 (0x77): Indirect Data Register 1................................................................................................................67 Register 120 (0x78): Indirect Data Register 0................................................................................................................67 Registers 121 to 127......................................................................................................................................................67 Static MAC Address Table.............................................................................................................................................67 VLAN Table....................................................................................................................................................................68 Dynamic MAC Address Table........................................................................................................................................69 MIB (Management Information Base) Counters.............................................................................................................70 Additional Information.....................................................................................................................................................73 Absolute Maximum Ratings.................................................................................................................74 Operating Ratings.................................................................................................................................74 Electrical Characteristics.....................................................................................................................75 Timing Specifications...........................................................................................................................77 EEPROM Timing..................................................................................................................................................................77 SNI Timing............................................................................................................................................................................78 MII Timing….……………………………………………………………………………………………………………………………78 MAC Mode MII Timing....................................................................................................................................................79 PHY-Mode MII Timing....................................................................................................................................................80 SPI Timing….…………………………………………………………………………………………………………………………...78 Input Timing...................................................................................................................................................................81 Output Timing.................................................................................................................................................................82 Reset Timing........................................................................................................................................................................83 Selection of Isolation Transformers....................................................................................................85 Selection of Reference Crystal............................................................................................................85 October 2008 8 M9999-020606

Micrel, Inc. KSZ8993M/ML Package Information.............................................................................................................................86 List of Figures Figure 1. Typical Straight Cable Connection.......................................................................................................................................25 Figure 2. Typical Crossover Cable Connection...................................................................................................................................25 Figure 3. Auto Negotiation and Parallel Operation.............................................................................................................................26 Figure 4. Destination Address Lookup Flow Chart, Stage 1..............................................................................................................27 Figure 5. Destination Address Resolution Flow Chart, Stage 2........................................................................................................28 Figure 6. 802.1p Priority Field Format..................................................................................................................................................37 Figure 7. KSZ8993M EEPROM Configuration Timing Diagram..........................................................................................................38 Figure 8. SPI Write Data Cycle...............................................................................................................................................................42 Figure 9. SPI Read Data Cycle...............................................................................................................................................................42 Figure 10. SPI Multiple Write..................................................................................................................................................................42 Figure 11. SPI Multiple Read..................................................................................................................................................................43 Figure 12. Loopback Path......................................................................................................................................................................44 Figure 13. EEPROM Interface Input Timing Diagram..........................................................................................................................76 Figure 14. EEPROM Interface Output Timing Diagram.......................................................................................................................76 Figure 15. SNI Input Timing Diagram....................................................................................................................................................77 Figure 16. SNI Output Timing Diagram.................................................................................................................................................77 Figure 17. MAC-Mode MII Timing – Data Received from MII..............................................................................................................79 Figure 18. MAC-Mode MII Timing – Data Input to MII..........................................................................................................................78 Figure 19. PHY-Mode MII Timing – Data Received from MII...............................................................................................................79 Figure 20. PHY-Mode MII Timing – Data Input to MII...........................................................................................................................79 Figure 21. SPI Input Timing....................................................................................................................................................................81 Figure 22. SPI Output Timing.................................................................................................................................................................82 Figure 23. Reset Timing.........................................................................................................................................................................83 128-Pin PQFP Package...........................................................................................................................................................................86 List of Tables Table 1. FX and TX Mode Selection......................................................................................................................................................22 Table 2. MDI/MDI-X Pin Definitions........................................................................................................................................................23 Table 3. MII Signals.................................................................................................................................................................................31 Table 4. SNI Signals................................................................................................................................................................................32 Table 5. MII Management Interface Frame Format..............................................................................................................................33 Table 6. Serial Management Interface (SMI) Frame Format................................................................................................................33 Table 7. Upstream Special Tagging Mode Format..............................................................................................................................35 Table 8. STPID Egress Rules (Switch Port 3 to Processor)................................................................................................................35 Table 9. FID+DA Lookup in VLAN Mode...............................................................................................................................................37 Table 10. FID+SA Lookup in VLAN Mode.............................................................................................................................................37 Table 11. KSZ8993M SPI Connections..................................................................................................................................................41 Table 12. Format of Static MAC Table (8 Entries)................................................................................................................................67 Table 13. Format of Static VLAN Table (16 Entries)............................................................................................................................69 Table 14. Format of Dynamic MAC Address Table (1K Entries)........................................................................................................69 Table 15. Format of “Per Port” MIB Counters......................................................................................................................................70 Table 16. Port 1s “Per Port” MIB Counters Indirect Memory Offsets................................................................................................71 Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets...............................................................................................72 Table 18. Format of “All Port Dropped Packet” MIB Counters..........................................................................................................72 Table 19. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets.................................................................................72 Table 20. EEPROM Timing Parameters................................................................................................................................................77 Table 21. SNI Timing Parameters..........................................................................................................................................................78 Table 22. MAC-Mode MII Timing Parameters.......................................................................................................................................79 Table 23. PHY-Mode MII Timing Parameters........................................................................................................................................80 Table 24. SPI Input Timing Parameters................................................................................................................................................81 Table 25. SPI Output Timing Parameters.............................................................................................................................................82 Table 26. Reset Timing Parameters......................................................................................................................................................83 Table 27. Transformer Selection Criteria..............................................................................................................................................85 Table 28. Qualified Single Port Magnetics...........................................................................................................................................85 Table 29. Typical Reference Crystal Characteristics..........................................................................................................................85 October 2008 9 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Description and I/O Assignment Pin Number Pin Name Type (1) Description 1 P1LED2 Ipu/O Port 1 LED indicators 2 P1LED1 Ipu/O [LEDSEL1, LEDSEL0] 3 P1LED0 Ipu/O [0, 0] [0, 1] P1LED3 — — P1LED2 Link/Act 100Link/Act P1LED1 Full duplex/Col 10Link/Act P1LED0 Speed Full duplex [LEDSEL1, LEDSEL0] [1, 0] [1, 1] P1LED3 Act — P1LED2 Link — P1LED1 Full duplex/Col — P1LED0 Speed — Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. 4 P2LED2 Ipu/O Port 2 LED indicators 5 P2LED1 Ipu/O [LEDSEL1, LEDSEL0] 6 P2LED0 Ipu/O [0, 0] [0, 1] P2LED3 — — P2LED2 Link/Act 100Link/Act P2LED1 Full duplex/Col 10Link/Act P2LED0 Speed Full duplex [LEDSEL1, LEDSEL0] [1, 0] [1, 1] P2LED3 Act — P2LED2 Link — P2LED1 Full duplex/Col — P2LED0 Speed — Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing. 7 DGND Gnd Digital ground Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. Gnd = Ground. October 2008 10 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 8 VDDIO P 3.3V digital V DD 9 NC Ipd No connect 10 NC Ipd No connect 11 NC Ipu No connect 12 ADVFC Ipu 1 = advertise the switch’s flow control capability via auto negotiation. 0 = will not advertise the switch’s flow control capability via auto negotiation. 13 P2ANEN Ipu 1 = enable auto negotiation on port 2 0 = disable auto negotiation on port 2 14 P2SPD Ipd 1 = force port 2 to 100BT if P2ANEN = 0 0 = force port 2 to 10BT if P2ANEN = 0 15 P2DPX Ipd 1 = port 2 default to full duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0. 0 = port 2 default to half duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0. 16 P2FFC Ipd 1 = always enable (force) port 2 flow control feature 0 = port 2 flow control feature enable is determined by auto negotiation result. 17 NC Opu No connect 18 NC Ipd No connect 19 NC Ipd No connect 20 P2LED3 Opd Port 2 LED indicator Note: Internal pull-down is weak; it will not turn ON the LED. See description in pin 4. 21 DGND Gnd Digital ground 22 VDDC/VOUT_1 P V : For KSZ8993M, this is an input power pin for the 1.8V DDC V8 digital core V . DD V : For KSZ8993ML, this is a 1.8V output power pin to OUT_1V8 supply the KSZ8993ML’s input power pins: V (pin 63), DDAP V (pins 91 and 123), and V (pins 38, 43, and 57). DDC DDA 23 LEDSEL1 Ipd LED display mode select See description in pins 1 and 4. 24 NC O No connect 25 P1LED3 Opd Port 1 LED indicator Note: An external 1K pull-down is needed on this pin if it is connected to a LED. The 1K resistor will not turn ON the LED. See description in pin 1. Note: 1. P = Power supply. Gnd = Ground. O = Output. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Opu = Output with internal pull-up. Opd = Output internal pull-down. October 2008 11 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 26 NC O No connect 27 HWPOVR Ipd Hardware pin overwrite 0 = Disable. All strap-in pins configurations are overwritten by the EEPROM configuration data 1 = Enable. All strap-in pins configurations are overwritten by the EEPROM configuration data, except for register 0x2C bits [7:5], (port 2: auto-negotiation enable, force speed, force duplex). 28 P2MDIXDIS Ipd Port 2 Auto MDI/MDI-X PD (default) = enable PU = disable 29 P2MDIX Ipd Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled. PD (default) = MDI-X (transmit on TXP2 / TXM2 pins) PU = MDI, (transmit on RXP2 / RXM2 pins) 30 P1ANEN Ipu 1 = enable auto negotiation on port 1 0 = disable auto negotiation on port 1 31 P1SPD Ipd 1 = force port 1 to 100BT if P1ANEN = 0 0 = force port 1 to 10BT if P1ANEN = 0 32 P1DPX Ipd 1 = port 1 default to full duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0. 0 = port 1 default to half duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0. 33 P1FFC Ipd 1 = always enable (force) port 1 flow control feature 0 = port 1 flow control feature enable is determined by auto negotiation result. 34 NC Ipd No connect 35 NC Ipd No connect 36 PWRDN Ipu Chip power-down input (active low) 37 AGND Gnd Analog ground 38 VDDA P 1.8V analog V DD 39 AGND Gnd Analog ground 40 MUX1 I Factory test pin - float for normal operation 41 MUX2 I Factory test pin - float for normal operation 42 AGND Gnd Analog ground 43 VDDA P 1.8V analog V DD 44 FXSD1 I Fiber signal detect/factory test pin Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. October 2008 12 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 45 RXP1 I/O Physical receive or transmit signal (+ differential) 46 RXM1 I/O Physical receive or transmit signal (– differential) 47 AGND Gnd Analog ground 48 TXP1 I/O Physical transmit or receive signal (+ differential) 49 TXM1 I/O Physical transmit or receive signal (– differential) 50 VDDATX P 3.3V analog V DD 51 VDDARX P 3.3V analog V DD 52 RXM2 I/O Physical receive or transmit signal (– differential) 53 RXP2 I/O Physical receive or transmit signal (+ differential) 54 AGND Gnd Analog ground. 55 TXM2 I/O Physical transmit or receive signal (– differential) 56 TXP2 I/O Physical transmit or receive signal (+ differential) 57 VDDA P 1.8 analog V DD 58 AGND Gnd Analog ground 59 TEST1 I Factory test pin - float for normal operation 60 TEST2 Ipu Factory test pin - float or pull-up for normal operation 61 ISET O Set physical transmit output current. Pull-down this pin with a 3.01K 1% resistor to ground. 62 AGND Gnd Analog ground 63 VDDAP P 1.8V analog V for PLL DD 64 AGND Gnd Analog ground. 65 X1 I 25MHz crystal/oscillator clock connections 66 X2 O Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock is +/- 50ppm for both crystal and oscillator. 67 RST_N Ipu Hardware reset pin (active low) 68 BPEN Ipd Half-duplex backpressure 1 = enable 0 = disable 69 SMAC Ipd Special Mac-mode In this mode, the switch will do faster back-offs than normal. 1 = enable 0 = disable Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. October 2008 13 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 70 LEDSEL0 Ipd LED display mode select See description in pins 1 and 4. 71 SMTXEN Ipd Switch MII transmit enable 72 SMTXD3 Ipd Switch MII transmit data bit 3 73 SMTXD2 Ipd Switch MII transmit data bit 2 74 SMTXD1 Ipd Switch MII transmit data bit 1 75 SMTXD0 Ipd Switch MII transmit data bit 0 76 SMTXER Ipd Switch MII transmit error 77 SMTXC Ipd/O Switch MII transmit clock Output in PHY MII mode Input in MAC MII mode 78 DGND Gnd Digital ground 79 VDDIO P 3.3V digital V DD 80 SMRXC Ipd/O Switch MII receive clock. Output in PHY MII mode Input in MAC MII mode 81 SMRXDV O Switch MII receive data valid 82 SMRXD3 Ipd/O Switch MII receive data bit 3 Strap option: switch MII full-duplex flow control PD (default) = disable PU = enable 83 SMRXD2 Ipd/O Switch MII receive bit 2 Strap option: switch MII is in PD (default) = full-duplex mode PU = half-duplex mode 84 SMRXD1 Ipd/O Switch MII receive bit 1 Strap option: Switch MII is in PD (default) = 100Mbps mode PU = 10Mbps mode 85 SMRXD0 Ipd/O Switch MII receive bit 0 Strap option: switch will accept packet size up to PD (default) = 1536 bytes (inclusive) PU = 1522 bytes (tagged), 1518 bytes (untagged) 86 SCOL Ipd/O Switch MII collision detect 87 SCRS Ipd/O Switch MII carrier sense Note: 1. P = Power supply. Gnd = Ground. O = Output. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. October 2008 14 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 88 SCONF1 Ipd Switch MII interface configuration 89 SCONF0 Ipd (SCONF1, SCONF0) Description (0,0) disable, outputs tri-stated (0,1) PHY mode MII (1,0) MAC mode MII (1,1) PHY mode SNI 90 DGND Gnd Digital ground 91 VDDC P 1.8V digital VDD 92 PRSEL1 Ipd Priority select. Select queue servicing if using split queues. Use the table below to select the desired servicing. Note that 93 PRSEL0 Ipd this selection effects all split transmit queue ports in the same way. (PRSEL1, PRSEL0) Description Transmit all high priority before low (0,0) priority Transmit high priority and low priority at (0,1) 10:1 ratio. Transmit high priority and low priority at (1,0) 5:1 ratio. Transmit high priority and low priority at (1,1) 2:1 ratio. 94 MDC Ipu MII management interface: clock input 95 MDIO Ipu/O MII management interface: data input/output Note: an external 4.7K pull-up is needed on this pin when it is in use. 96 SPIQ Opu SPI slave mode: serial data output See description in pins 100 and 101. 97 SCL Ipu/O SPI slave mode / I2C slave mode: clock input I2C master mode: clock output See description in pins 100 and 101. 98 SDA Ipu/O SPI slave mode: serial data input I2C master/slave mode: serial data input/output See description in pins 100 and 101. 99 SPIS_N Ipu SPI slave mode: chip select (active low) When SPIS_N is high, the KSZ8993M is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pins 100 and 101. Note: 1. P = Power supply. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. Opu = Output w/ internal pull-up. October 2008 15 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 100 PS1 Ipd Serial bus configuration pins to select mode of access to KSZ8993M internal registers. 101 PS0 Ipd [PS1, PS0] = [0, 0] — I2C master (EEPROM) mode (If EEPROM is not detected, the power-up default values of the KSZ8993M internal registers will be used.) Interface Signals Type Description SPIQ O Not used (tri-stated) SCL O I2C clock SDA I/O I2C data I/O SPIS_N Ipu Not used [PS1, PS0] = [0, 1] — I2C slave mode The external I2C master will drive the SCL clock. The KSZ8993M device addresses are: 1011_1111 <read> 1011_1110 <write> Interface Signals Type Description SPIQ O Not used (tri-stated) SCL I I2C clock SDA I/O I2C data I/O SPIS_N Ipu Not used [PS1, PS0] = [1, 0] — SPI slave mode Interface Signals Type Description SPIQ O SPI data out SCL I SPI clock SDA I SPI data In SPIS_N Ipu SPI chip select [PS1, PS0] = [1, 1] – SMI-mode In this mode, the KSZ8993M provides access to all its internal 8 bit registers through its MDC and MDIO pins. Note: When (PS1, PS0) ≠ (1,1), the KSZ8993M provides access to its 16 bit MIIM registers through its MDC and MDIO pins. 102 PV31 Ipu Port 3 port-based VLAN mask bits – Use to select which ports may transmit packets received on port 3. 103 PV32 Ipu PV31 = 1, port 1 may transmit packets received on port 3 PV31 = 0, port 1 will not transmit any packets received on port 3 PV32 = 1, port 2 may transmit packets received on port 3 PV32 = 0, port 2 will not transmit any packets received on port 3 Note: 1. I = Input. Ipu = Input w/ internal pull-up. I/O = Bi-directional. O= Output. Ipd = Input w/ internal pull-down. October 2008 16 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 104 PV21 Ipu Port 2 port-based VLAN mask bits – Use to select which ports may transmit packets received on port 2. 105 PV23 Ipu PV21 = 1, port 1 may transmit packets received on port 2 PV21 = 0, port 1 will not transmit any packets received on port 2 PV23 = 1, port 3 may transmit packets received on port 2 PV23 = 0, port 3 will not transmit any packets received on port 2 106 DGND Gnd Digital ground 107 VDDIO P 3.3V digital V DD 108 PV12 Ipu Port 1 port-based VLAN mask bits – Use to select which ports may transmit packets received on port 1. 109 PV13 Ipu PV12 = 1, port 2 may transmit packets received on port 1 PV12 = 0, port 2 will not transmit any packets received on port 1 PV13 = 1, port 3 may transmit packets received on port 1 PV13 = 0, port 3 will not transmit any packets received on port 1 110 P3_1PEN Ipd Enable 802.1p priority classification on port 3 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P3_PP pin. 111 P2_1PEN Ipd Enable 802.1p priority classification on port 2 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P2_PP pin. 112 P1_1PEN Ipd Enable 802.1p priority classification on port 1 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P1_PP pin. 113 P3_TXQ2 Ipd Select transmit queue split on port 3 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 3 is set by P3_TXQ2. Note: 1. P = Power supply. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. October 2008 17 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 114 P2_TXQ2 Ipd Select transmit queue split on port 2 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 2 is set by P2_TXQ2. 115 P1_TXQ2 Ipd Select transmit queue split on port 1 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 1 is set by P1_TXQ2. 116 P3_PP Ipd Select port-based priority on port 3 ingress 1 = high 0 = low <default> 802.1p and DiffServ, if applicable, takes precedence. 117 P2_PP Ipd Select port-based priority on port 2 ingress 1 = high 0 = low <default> 802.1p and DiffServ, if applicable, takes precedence. 118 P1_PP Ipd Select port-based priority on port 1 ingress 1 = high 0 = low <default> 802.1p and DiffServ, if applicable, takes precedence. 119 P3_TAGINS Ipd Enable tag insertion on port 3 egress 1 = enable 0 = disable All packets transmitted from port 3 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. 120 P2_TAGINS Ipd Enable tag insertion on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. Note: 1. Ipd = Input w/ internal pull-down. October 2008 18 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Number Pin Name Type (1) Description 121 P1_TAGINS Ipd Enable tag insertion on port 1 egress 1 = enable 0 = disable All packets transmitted from port 1 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. 122 DGND Gnd Digital ground 123 VDDC P 1.8V digital V DD 124 P3_TAGRM Ipd Enable tag removal on port 3 egress 1 = enable 0 = disable All packets transmitted from port 3 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. 125 P2_TAGRM Ipd Enable tag removal on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. 126 P1_TAGRM Ipd Enable tag removal on port 1 egress 1 = enable 0 = disable All packets transmitted from port 1 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. 127 TESTEN Ipd Scan Test Enable For normal operation, pull-down this pin to ground. 128 SCANEN Ipd Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. Note: 1. P = Power supply. Gnd = Ground. Ipd = Input w/ internal pull-down. October 2008 19 M9999-020606

Micrel, Inc. KSZ8993M/ML Pin Configuration PV31PS0PS1SPIS_NSDASCLSPIQMDIOMDCPRSEL0PRSEL1VDDCDGNDSCONF0SCONF1SCRSSCOLSMRXD0SMRXD1SMRXD2SMRXD3SMRXDVSMRXCVDDIODGNDSMTXCSMTXERSMTXD0SMTXD1SMTXD2SMTXD3SMTXENLEDSEL0SMACBPENRST_NX2X1 PV32 AGND PV21 VDDAP PV23 AGND DGND ISET VDDIO TEST2 PV12 TEST1 PV13 AGND P3_1PEN VDDA P2_1PEN TXP2 P1_1PEN TXM2 P3_TXQ2 AGND P2_TXQ2 RXP2 P1_TXQ2 RXM2 P3_PP VDDARX P2_PP VDDATX P1_PP TXM1 P3_TAGINS TXP1 P2_TAGINS AGND P1_TAGINS RXM1 DGND RXP1 VDDC FXSD1 P3_TAGRM VDDA P2_TAGRM AGND P1_TAGRM MUX2 TESTEN MUX1 SCANEN AGND 210210DOCCCCNDXCCCC3DC1C3CRSXNDXCCCNDA P1LEDP1LEDP1LEDP2LEDP2LEDP2LEDDGNVDDINNNADVFP2ANEP2SPP2DPP3FFNNNP2LEDDGNVDDEDSELNP1LEDNWPOVMDIXDIP2MDIP1ANEP1SPP1DPP1FFNNPWRDAGNVDD L H2 P 128-Pin PQFP (Top View) October 2008 20 M9999-020606

Micrel, Inc. KSZ8993M/ML Functional Description The KSZ8993M contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8993M has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of the KSZ8993M via the SMI interface, MIIM interface, SPI bus, or I2C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time. On the media side, the KSZ8993M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and 100BASE-FX on PHY port 1. The KSZ8993M can be used as a media converter. The KSZ8993ML is the single supply version with all the identical rich features of the KSZ8993M. In the KSZ8993ML version, pin number 22 provides 1.8V output power to the KSZ8993ML’s V , V , and V DDC DDA DDAP power pins. Refer to the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment). Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01 KΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. October 2008 21 M9999-020606

Micrel, Inc. KSZ8993M/ML PLL Clock Synthesizer The KSZ8993M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler / de-scrambler and MLT3 encoder / decoder are bypassed on transmission and reception. In 100BASE-FX mode, the auto negotiation feature is bypassed since there is no standard that supports fiber auto negotiation. The auto- MDI/MDI-X feature is also disabled. 100BASE-FX Signal Detection In fiber operation, the KSZ8993M’s FXSD1 (fiber signal detect) input pin is usually connected to the fiber transceiver’s SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V. When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far end fault (FEF) is generated. When FXSD1 is over 2.2V, the fiber signal is detected. Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied high to force 100BASE-FX mode. 100BASE-FX signal detection is summarized in the following table: Part Number Mode Less than 0.2V TX mode Greater than 1V, but less than 1.8V FX mode No signal detected. Far-end fault generated Greater than 2.2V I FX mode Signal detected Table 1. FX and TX Mode Selection To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver’s SD output voltage swing to match the KSZ8993M’s FXSD1 input voltage threshold. 100BASE-FX Far End Fault An FEF occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8993M detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When an FEF occurs, the transmission side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between frames. Upon receiving an FEF, the LINK will go down (even when a fiber signal is detected) to indicate a fault condition. The transmitting side is not affected when an FEF is received, and will continue to send out its normal transmit pattern from the MAC. By default, FEF is enabled. The FEF feature can be disabled through register setting. October 2008 22 M9999-020606

Micrel, Inc. KSZ8993M/ML 10BASE-T Transmit The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8993M decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. Power Management The KSZ8993M features a per-port power down mode. To save power, the user can power down ports that are not in use by setting the port control registers, or MII control registers. In addition, there is a full chip power down mode. When activated, the entire chip will be shut down. MDI /MDI-X Auto Crossover The KSZ8993M supports MDI/ DI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the KSZ8993M device. This feature can be extremely useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers. Based on the IEEE 802.3 standard, the MDI and MDI-X definitions are as follows: MDI MDI-X RJ45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD- 2 RD- 3 RD+ 3 TD+ 6 RD- 6 TD- Table 2. MDI/MDI-X Pin Definitions October 2008 23 M9999-020606

Micrel, Inc. KSZ8993M/ML Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). 10/100 Ethernet 10/100 Ethernet Media Dependent Interface Media Dependent Interface 1 1 Transmit Pair Receive Pair 2 2 Straight 3 3 Cable 4 4 Receive Pair Transmit Pair 5 5 6 6 7 7 8 8 Modular Connector Modular Connector (RJ-45) (RJ-45) NIC HUB (Repeater or Switch) Figure 1. Typical Straight Cable Connection October 2008 24 M9999-020606

Micrel, Inc. KSZ8993M/ML Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). 10/100 Ethernet 10/100 Ethernet Media Dependent Interface Media Dependent Interface 1 Crossover 1 Receive Pair Cable Receive Pair 2 2 3 3 4 4 Transmit Pair Transmit Pair 5 5 6 6 7 7 8 8 Modular Connector (RJ-45) Modular Connector (RJ-45) HUB HUB (Repeater or Switch) (Repeater or Switch) Figure 2. Typical Crossover Cable Connection Auto Negotiation The KSZ8993M conforms to the auto negotiation protocol as described by the 802.3 committee. Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported or the link partner to the KSZ8993M is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The link setup is shown in the following flow diagram. October 2008 25 M9999-020606

Micrel, Inc. KSZ8993M/ML Start Auto Negotiation N Parallel Force Link Setting o Operation Ye s Bypass Auto Negotiation Attempt Auto Listen for 100BASE-TX Listen for 10BASE-T Link and Set Link Mode Negotiation Idles Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 3. Auto Negotiation and Parallel Operation October 2008 26 M9999-020606

Micrel, Inc. KSZ8993M/ML Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K uni-cast address table plus switching information. The KSZ8993M is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses that can be learned. Learning The internal lookup engine will update its table with a new entry if the following conditions are met: 1. The received packet's SA does not exist in the lookup table. 2. The received packet is good; the packet has no receiving errors, and is of legal length. The lookup engine will insert the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table will be deleted to make room for the new entry. Migration The internal lookup engine also monitors whether a station has moved. If so, it will update the table accordingly. Migration happens when the following conditions are met: 1. The received packet's SA is in the table but the associated source port information is different. 2. The received packet is good; the packet has no receiving errors, and is of legal length. The lookup engine will update the existing record in the table with the new source port information. Aging The lookup engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine will remove the record from the table. The lookup engine constantly performs the aging process and will continuously remove aging records. The aging period is about 200 seconds. This feature can be enabled or disabled through Global Register 3 (0x03). Forwarding The KSZ8993M will forward packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLA processes to come up with “port to forward 2” (PTF2), as shown in Figure 5. The packet is sent to PTF2. October 2008 27 M9999-020606

Micrel, Inc. KSZ8993M/ML Start - Search VLAN table NO PTF1= NULL VLAN ID - Ingress VLAN filtering Valid? - Discard NPVID check YES Search complete. FOUND Get PTF1 from Search Static This search is based on Static MAC Table Table DA or DA+FID NOT FOUND Search complete. FOUND Get PTF1 from Dynamic Table This search is based on Dynamic MAC Search DA+FID Table NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 Figure 4. Destination Address Lookup Flow Chart, Stage 1 October 2008 28 M9999-020606

Micrel, Inc. KSZ8993M/ML PTF1 - Check receiving port's receive enable bit Spanning Tree - Check destination port's transmit enable bit Process - Check whether packets are special (BPDU or specified) - Applied to MAC #1 and MAC #2 - MAC #3 is reserved for IGMP Process microprocessor - IGMP will be forwarded to port 3 - RX Mirror Port Mirror - TX Mirror Process - RX or TX Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KSZ8993M will not forward the following packets: 1. Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KSZ8993M will intercept these packets and perform the appropriate actions. 3. "Local" packets. Based on destination address (DA) lookup. If the destination port from the lookup table matches the port where the packet was from, the packet is defined as "local." October 2008 29 M9999-020606

Micrel, Inc. KSZ8993M/ML Switching Engine The KSZ8993M features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8993M has a 32kB internal frame buffer. This resource is shared between all three ports. The buffer- sharing mode can be programmed through Global Register 2 (0x02). In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use one third of the total buffer pool. There are a total of 250 buffers available. Each buffer is sized at 128B. MAC Operation The KSZ8993M strictly abides by IEEE 802.3 standards to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN. Back-Off Algorithm The KSZ8993M implements the IEEE standard 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Global Register 3 (0x03) Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. Illegal Frames The KSZ8993M discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Global Register 4 (0x04). For special applications, the KSZ8993M can also be programmed to accept frames up to 1916 bytes in the same global register. Since the KSZ8993M supports VLAN tags, the maximum sizing is adjusted when these tags are present. See the EEPROM section for programming options. Flow Control The KSZ8993M supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8993M receives a pause control frame, the KSZ8993M will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KSZ8993M will be transmitted. On the transmit side, the KSZ8993M has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8993M will flow control a port, which just received a packet, if the destination port resource is being used up. The KSZ8993M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8993M will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. The KSZ8993M will flow control all ports if the receive queue becomes full. Half-Duplex Backpressure A half-duplex backpressure option (Note: not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full duplex mode. If backpressure is required, the KSZ8993M will send preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from October 2008 30 M9999-020606

Micrel, Inc. KSZ8993M/ML sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type backpressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following: 1. Aggressive back off (Global Register 3 (0x03), bit 0 or external strap-in pin SMAC = high) 2. No excessive collision drop (Global Register 4 (0x04), bit 3 or external strap-in pin SMAC = high) These bits are not set as defaults because this is not the IEEE standard. Broadcast Storm Protection The KSZ8993M has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KSZ8993M has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Global Register 6 (0x06) and 7 (0x07). The default setting for registers 6 and 7 is 0x63, which is 99 decimal. This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63 MII Interface Operation The MII is specified by the IEEE 802.3 standards committee and provides a common interface between physical layer and MAC layer devices. The MII Interface provided by the KSZ8993M is connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used in the MII interface. KSZ8993M PHY-Mode Connections KSZ8993M MAC-Mode Connections External MAC KSZ8993M Pin External KSZ8993M Controller Signals PHY Signals Descriptions PHY Signals MAC Signals MTXEN SMTXEN Transmit enable MTXEN SMRXDV MTXER SMTXER Transmit error MTXER (not used) MTXD3 SMTXD[3] Transmit data bit 3 MTXD3 SMRXD[3] MTXD2 SMTXD[2] Transmit data bit 2 MTXD2 SMRXD[2] MTXD1 SMTXD[1] Transmit data bit 1 MTXD1 SMRXD[1] MTXD0 SMTXD[0] Transmit data bit 0 MTXD0 SMRXD[0] MTXC SMTXC Transmit clock MTXC SMRXC MCOL SCOL Collision detection MCOL SCOL MCRS SCRS Carrier sense MCRS SCRS MRXDV SMRXDV Receive data valid MRXDV SMTXEN MRXER (not used) Receive error MRXER SMTXER MRXD3 SMRXD[3] Receive data bit 3 MRXD3 SMTXD[3] MRXD2 SMRXD[2] Receive data bit 2 MRXD2 SMTXD[2] MRXD1 SMRXD[1] Receive data bit 1 MRXD1 SMTXD[1] MRXD0 SMRXD[0] Receive data bit 0 MRXD0 SMTXD[0] MRXC SMRXC Receive clock MRXC SMTXC Table 3. MII Signals October 2008 31 M9999-020606

Micrel, Inc. KSZ8993M/ML The MII interface operates in either PHY mode or MAC mode. The interface is a nibble wide data interfaces and therefore run at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half duplex operation there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the interface for PHY mode operation and the signal MTXER is not provided on the interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KSZ8993M has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KSZ8993M has an MTXER pin, it should be tied low. SNI (7-Wire) Operation The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol processing. In SNI mode, the KSZ8993M acts like a PHY and the external controller functions as the MAC. The KSZ8993M can interface directly with external controllers using the 7-wire interface. These signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the following table. Pin Descriptions External MAC KSZ8993M Controller Signals PHY Signals Transmit enable TXEN SMTXEN Serial transmit data TXD SMTXD[0] Transmit clock TXC SMTXC Collision detection COL SCOL Carrier sense CRS SMRXDV Serial receive data RXD SMRXD[0] Receive clock RXC SMRXC Table 4. SNI Signals The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when the data is valid. For half duplex operation, the KSZ8993M’s SCOL signal is used to indicate that a collision has occurred during transmission. MII Management Interface (MIIM) The KSZ8993M supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8993M. An external device with MDC/MDIO capability can be used to read the PHY status or configure the PHY settings. Further details on the MIIM interface can be found in section 22.2.4.5 of the IEEE 802.3 specification. October 2008 32 M9999-020606

Micrel, Inc. KSZ8993M/ML The MIIM interface consists of the following: (cid:131) A physical connection that incorporates the data line (MDIO) and the clock line (MDC). (cid:131) A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8993M device. (cid:131) Access to a set of six 16-bits registers, consisting of standard MIIM registers [0:5]. The following table depicts the MII Management Interface frame format. Preamble Start of Read/Write PHY REG TA Data Idle Frame OP Code Address Address Bits [15:0] Bits [4:0] Bits [4:0] Read 32 1’s 01 10 xx0AA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 xx0AA RRRRR 10 DDDDDDDD_DDDDDDDD Z Table 5. MII Management Interface Frame Format For the KSZ8993M, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits [4:3] are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation. Serial Management Interface (SMI) The SMI is the KSZ8993M non-standard MIIM interface that provides access to all KSZ8993M configuration registers. This interface allows an external device to completely monitor and control the states of the KSZ8993M. The SMI interface consists of the following: (cid:131) A physical connection that incorporates the data line (MDIO) and the clock line (MDC). (cid:131) A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8993M device. (cid:131) Access to all KSZ8993M configuration registers. Registers access includes the Global, Port and Advanced Control Registers 0-127 (0x00 – 0x7F), and indirect access to the standard MIIM registers [0:5]. The following table depicts the SMI frame format. Preamble Start of Read/Write PHY REG TA Data Idle Frame OP Code Address Address Bits [15:0] Bits [4:0] Bits [4:0] Read 32 1’s 01 10 RR1xx RRRRR Z0 0000_0000_DDDD_DDDD Z Write 32 1’s 01 01 RR1xx RRRRR 10 xxxx_xxxx_DDDD_DDDD Z Table 6. Serial Management Interface (SMI) Frame Format For the KSZ8993M, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation. To access the KSZ8993M registers 0-127 (0x00 – 0x7F), the following applies: (cid:131) PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address; that is, {PHYAD[4:3], REGAD[4:0]} = bits [6:0] of the 7-bits address. October 2008 33 M9999-020606

Micrel, Inc. KSZ8993M/ML (cid:131) Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data bits [15:8] are not defined, and hence can be set to either 0’s or 1’s. SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section. Advanced Switch Functions Spanning Tree Support To support spanning tree, port 3 is the designated port for the processor. The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following description shows the port setting and software actions taken for each of the five spanning tree states. Disable state: The port should not forward or receive any packets. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable =1” Software action: The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “static MAC table” with “overriding bit” set) and the processor should discard those packets. Note: processor is connected to port 3 via MII interface. Address learning is disabled on the port in this state. Blocking state: Only packets to the processor are forwarded. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable =1” Software action: The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC table” with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening state: Only packets to and from the processor are forwarded. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable =1” Software action: The processor should program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” for details. Address learning is disabled on the port in this state. Learning state: Only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0” October 2008 34 M9999-020606

Micrel, Inc. KSZ8993M/ML Software action: The processor should program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” for details. Address learning is enabled on the port in this state. Forwarding state: Packets are forwarded and received normally. Learning is enabled. Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0” Software action: The processor should program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” for details. Address learning is enabled on the port in this state. Upstream Special Tagging Mode Upstream Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. The Upstream Special Tagging Mode, similar to 802.1Q, requires software to change network drivers to modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit 0 and register 48 bit 2 to “1”. 802.1Q Tag Format Special Tag Format STPID (special tag identifier, 0x810 + TPID (tag protocol identifier, 0x8100) + TCI. 4 bit for “port mask”) + TCI Table 7. Upstream Special Tagging Mode Format The STPID is only seen and used by the port 3 interface, which should be connected to a processor. The KSZ8993M uses a non-zero “port mask” to bypass the lookup result and override any port setting, regardless of port states (disable, blocking, listening, learning). For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows: “0001” from port 1 “0010” from port 2 No port mask values, other than the previous two defined ones, should be received in Upstream Special Tagging Mode. The egress rules are defined as follows: Ingress Packets Egress Action to Tag Field - Modify TPID to 0x810 + “port mask”, which indicates source port. - No change to TCI if VID is not null Tagged with 0x8100 + TCI - Replace null VID with ingress port VID - Recalculate CRC - Insert TPID to 0x810 + “port mask”, which indicates source port Not tagged. – Insert TCI with ingress port VID - Recalculate CRC Table 8. STPID Egress Rules (Switch Port 3 to Processor) October 2008 35 M9999-020606

Micrel, Inc. KSZ8993M/ML IGMP Support For IGMP support in layer 2, the KSZ8993M provides two components: “IGMP” Snooping The KSZ8993M will trap IGMP packets and forward them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. “Multicast Address Insertion” in the Static MAC Table Once the multicast address is programmed in the Static MAC Table, the multicast session will be trimmed to the subscribed ports, instead of broadcasting to all ports. To enable IGMP support, set register 5 bit 6 to “1”. Also, “Special Tagging Mode” needs to be enabled, so that the processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit 0 and register 48 bit 2 to “1.” Port Mirroring Support KSZ8993M supports “Port Mirroring” comprehensively as: 1. “receive only” mirror on a port All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8993M will forward the packet to both port 2 and port 3. The KSZ8993M can optionally forward even “bad” received packets to the “sniffer port”. 2. “transmit only” mirror on a port All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal lookup. The KSZ8993M will forward the packet to both port 1 and port 3. 3. “receive and transmit” mirror on two ports All the packets received on port A and transmitted on port B will be mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit 0 to “1”. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8993M will forward the packet to both port 2 and port 3. Multiple ports can be selected to be “receive sniff” or “transmit sniff”. And any port can be selected to be the “sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively. IEEE 802.1Q VLAN Support The KSZ8993M supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8993M provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4- bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source Address (FID+SA) are used for address learning. October 2008 36 M9999-020606

Micrel, Inc. KSZ8993M/ML DA+FID DA found in found in Static MAC Use FID flag? FID match? Action Dynamic Table? MAC Table? Broadcast to the membership ports No Don’t care Don’t care No defined in the VLAN Table bits [18:16] Send to the destination port defined in the No Don’t care Don’t care Yes Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in Yes 0 Don’t care Don’t care the Static MAC Address Table bits [50:48] Broadcast to the membership ports Yes 1 No No defined in the VLAN Table bits [18:16] Send to the destination port defined in the Yes 1 No Yes Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in Yes 1 Yes Don’t care the Static MAC Address Table bits [50:48] Table 9. FID+DA Lookup in VLAN Mode FID+SA found in Dynamic Action MAC Table? No Learn and add FID+SA to the Dynamic MAC Address Table Yes Update time stamp Table 10. FID+SA Lookup in VLAN Mode Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KSZ8993M. These features can be set on a per port basis, and are defined in register 18, bit 6 and bit 5, respectively for port 1. QoS Priority Support This feature provides Quality of Service (QoS) for applications, such as VoIP and video conferencing. The KSZ8993M per port transmit queue could be split into two priority queues: a high priority queue and a low priority queue. Bit 0 of registers 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. Optionally, the Px_TXQ2 strap-in pins can be used to enable this feature. With split transmit queues, high priority packets will be placed in the high priority queue and low priority packets will be placed in the low priority queue. For split transmit queues, the KSZ8993M provides four priority schemes: 1. “Transmit all high priority packets before low priority packets;” i.e. a low priority packet could be transmitted only when the high priority queue is empty 2. “Transmit high priority packets and low priority packets at 10:1 ratio;” i.e. transmit a low priority packet after every 10 high priority packets are transmitted, if both queues are busy 3. “Transmit high priority packets and low priority packets at 5:1 ratio” 4. “Transmit high priority packets and low priority packets at 2:1 ratio” If a port's transmit queue is not split, both high priority packets and low priority packets have equal priority in the transmit queue. Register 5 bits [3:2] are used to select the desired priority scheme. Optionally, the PRSEL1 and PRSEL0 strap-in pins can be used. October 2008 37 M9999-020606

Micrel, Inc. KSZ8993M/ML Port-Based Priority With port based priority, each ingress port can be individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority, and will be sent to the high priority transmit queue if the corresponding transmit queue is split. Bit 4 of registers 16, 32 and 48 is used to enable port based priority for ports 1, 2 and 3, respectively. Optionally, the Px_PP strap-in pins can be used to enable this feature. 802.1p-Based Priority For 802.1p based priority, the KSZ8993M will examine the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bits priority field in the VLAN tag is retrieved and compared against the “priority base” value, specified by register 2 bits [6:4]. The “priority base” value is programmable; its default value is 0x4. The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Bytes 8 6 6 2 2 2 46-1500 4 Preamble DA SA VPID TCI length LLC Data FCS Bits 16 3 1 12 802.1q VLAN Tag T(a8g1g0e0d f oPra Ectkheet rTneypt)e 802.1p CFI VLAN ID Figure 6. 802.1p Priority Field Format If an ingress packet has an equal or higher priority value than the "priority base" value, the packet will be placed in the high priority transmit queue if the corresponding transmit queue is split. 802.1p based priority is enabled by bit 5 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_1PEN strap-in pins can be used to enable this feature. The KSZ8993M provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2 bytes Tag Control Information field (TCI), is also refer to as the 802.1Q VLAN Tag. Tag Insertion is enabled by bit 2 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_TAGINS strap-in pins can be used to enable this feature. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KSZ8993M will not add tags to already tagged packets. Tag Removal is enabled by bit 1 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_TAGRM strap-in pins can be used to enable this feature. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8993M will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8993M to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled by bit 3 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. DiffServ-Based Priority DiffServ-based priority uses registers 96 to 103. More details are provided at the beginning of the Advanced Control Registers section. October 2008 38 M9999-020606

Micrel, Inc. KSZ8993M/ML Rate Limiting Support The KSZ8993M supports hardware rate limiting independently on the “receive side” and on the “transmit side” on a per port basis. Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KSZ8993M uses “one second” as the rate limiting interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. On the “receive side”, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the “one second” interval expires. Flow control can be enabled to prevent packet loss. If the rate limit is programmed greater than or equal to 128 kbps and the byte counter is 8 Kbytes below the limit, flow control will be triggered. If the rate limit is programmed lower than 128 kbps and the byte counter is 2 Kbytes below the limit, flow control will also be triggered. On the “transmit side”, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the “one second” interval expires. If priority is enabled, the KSZ8993M can be programmed to support different rate limits for high priority packets and low priority packets. Configuration Interface The KSZ8993M can operate as both a managed switch and an unmanaged switch. In unmanaged mode, the KSZ8993M is typically programmed using an EEPROM. If no EEPROM is present, the KSZ8993M is configured using its default register settings. Some defaults settings are configured via strap-in pin options. The strap-in pins are indicated in the “KSZ8993M Pin Description and I/O Assignment” table. I2C Master Serial Bus Configuration With an additional I2C (“2-wire”) EEPROM, the KSZ8993M can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor. For KSZ8993M I2C Master configuration, the EEPROM stores the configuration data for register 0 to register 109 (as defined in the KSZ8993M register map) with the exception of the “Read Only” status registers. After the de- assertion of reset, the KSZ8993M will sequentially read in the configuration data for all 110 registers, starting from register 0. The configuration access time (t ) is less than 15 ms, as depicted in the following figure. prgm .... RST_N .... SCL .... SDA t <15 ms prgm Figure 7. KSZ8993M EEPROM Configuration Timing Diagram The following is a sample procedure for programming the KSZ8993M with a pre-configured EEPROM: 1. Connect the KSZ8993M to the EEPROM by joining the SCL and SDA signals of the respective devices. For the KSZ8993M, SCL is pin 97 and SDA is pin 98. October 2008 39 M9999-020606

Micrel, Inc. KSZ8993M/ML 2. Enable I2C master mode by setting the KSZ8993M strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “00”. 3. Check to ensure that the KSZ8993M reset signal input, RST_N (pin 67), is properly connected to the external reset source at the board level. 4. Program the desired configuration data into the EEPROM. 5. Place the EEPROM on the board and power up the board. 6. Assert an active-low reset to the RST_N pin of the KSZ8993M. After reset is de-asserted, the KSZ8993M will begin reading the configuration data from the EEPROM. The KSZ8993M will check that the first byte read from the EEPROM is “93”. If this value is correct, EEPROM configuration will continue. If not, EEPROM configuration access is denied and all other data sent from the EEPROM will be ignored by the KSZ8993M. The configuration access time (t ) is less than 15ms. prgm Note: For proper operation, check to ensure that the KSZ8993M PWRDN input signal (pin 36) is not asserted during the reset operation. The PWRDN input is active low. I2C Slave Serial Bus Configuration In managed mode, the KSZ8993M can be configured as an I2C slave device. In this mode, an I2C master device (external controller/CPU) has complete programming access to the KSZ8993M’s 128 registers. Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly accessed via registers 110 thru 120. In I2C slave mode, the KSZ8993M operates like other I2C slave devices. Addressing the KSZ8993M’s 8 bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of I2C read/write operations and related timing information can be found in the AT24C02 Datasheet. Two fixed 8 bits device addresses are used to address the KSZ8993M in I2C slave mode. One is for read; the other is for write. The addresses are as follow: 1011_1111 <read> 1011_1110 <write> The following is a sample procedure for programming the KSZ8993M using the I2C slave serial bus: 1. Enable I2C slave mode by setting the KSZ8993M strap-in pins PS[1:0] (pins 100 and 101, respectively) to “01”. 2. Power up the board and assert reset to the KSZ8993M. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 3. Configure the desired register settings in the KSZ8993M, using the I2C write operation. 4. Read back and verify the register settings in the KSZ8993M, using the I2C read operation. 5. Write a ‘1’ to the “Start Switch” bit to start the KSZ8993M with the programmed settings. Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’. Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started. SPI Slave Serial Bus Configuration In managed mode, the KSZ8993M can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8993M’s 128 registers. Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via registers 110 thru 120. The KSZ8993M supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI multiple read and multiple write are also supported by the KSZ8993M to expedite register read back and register configuration, respectively. October 2008 40 M9999-020606

Micrel, Inc. KSZ8993M/ML SPI multiple read is initiated when the master device continues to drive the KSZ8993M SPIS_N input pin (SPI Slave Select signal) low after a byte (a register) is read. The KSZ8993M internal address counter will increment automatically to the next byte (next register) after the read. The next byte at the next register address will be shifted out onto the KSZ8993M SPIQ output pin. SPI multiple read will continue until the SPI master device terminates it by de-asserting the SPIS_N signal to the KSZ8993M. Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8993M SPIS_N input pin low after a byte (a register) is written. The KSZ8993M internal address counter will increment automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8993M SDA input pin will be written to the next register address. SPI multiple write will continue until the SPI master device terminates it by de-asserting the SPIS_N signal to the KSZ8993M. For both SPI multiple read and multiple write, the KSZ8993M internal address counter will wrap back to register address zero once the highest register address is reached. This feature allows all 128 KSZ8993M registers to be read, or written with a single SPI command and any initial register address. The KSZ8993M is capable of supporting a 5MHz SPI bus. The following is a sample procedure for programming the KSZ8993M using the SPI bus: 1. At the board level, connect the KSZ8993M pins as follows: KSZ8993M Pin # KSZ8993M Signal Name External Processor Signal Description 99 SPIS_N SPI Slave Select SCL 97 SPI Clock (SPIC) SDA SPI Data 98 (SPID) (Master output; Slave input) SPI Data 96 SPIQ (Master input; Slave output) Table 11. KSZ8993M SPI Connections 2. Enable SPI slave mode by setting the KSZ8993M strap-in pins PS[1:0] (pins 100 and 101, respectively) to “10”. 3. Power up the board and assert reset to the KSZ8993M. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 4. Configure the desired register settings in the KSZ8993M, using the SPI write or multiple write command. 5. Read back and verify the register settings in the KSZ8993M, using the SPI read or multiple read command. 6. Write a ‘1’ to the “Start Switch” bit to start the KSZ8993M with the programmed settings. Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’. Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started. The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC. October 2008 41 M9999-020606

Micrel, Inc. KSZ8993M/ML SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS WRITE DATA Figure 8. SPI Write Data Cycle SPIS_N SPIC SPID X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 SPIQ D7 D6 D5 D4 D3 D2 D1 D0 READ COMMAND READ ADDRESS READ DATA Figure 9. SPI Read Data Cycle SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS Byte 1 SPIS_N SPIC SPID D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SPIQ Byte 2 Byte 3 ... Byte N Figure 10. SPI Multiple Write October 2008 42 M9999-020606

Micrel, Inc. KSZ8993M/ML SPIS_N SPIC SPID X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X SPIQ D7 D6 D5 D4 D3 D2 D1 D0 READ COMMAND READ ADDRESS Byte 1 SPIS_N SPIC SPID X X X X X X X X X X X X X X X X X X X X X X X X SPIQ D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Byte 2 Byte 3 Byte N Figure 11. SPI Multiple Read October 2008 43 M9999-020606

Micrel, Inc. KSZ8993M/ML Loopback Support The KSZ8993M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX, and the “Priority Buffer reserve” bit needs to be set to 48 pre- allocated buffers per output queue. The latter is required to prevent loopback packet drops and is achieved by setting register 4 bit 0 to ‘1’. Bit 0 of registers 29 and 45 is used to enable loopback for ports 1 and 2, respectively. Alternatively, the MII Management register 0, bit 14 can be used to enable loopback. Loopback is conducted between the KSZ8993M’s two PHY ports. The loopback path starts at the “Originating.” PHY ports receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM). The KSZ8993M loopback path is illustrated in the following figure. Figure 12. Loopback Path October 2008 44 M9999-020606

Micrel, Inc. KSZ8993M/ML MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C, and SMI interfaces can also be used to access these registers. The latter three interfaces use a different mapping mechanism than the MIIM interface. As defined in the IEEE 802.3 specification, the “PHYAD” are assigned as “0x1” for PHY port 1 and “0x2” for PHY port 2. The “REGAD” supported are 0,1,2,3,4, and 5. Register Number Description 0x0 Basic Control Register 0x1 Basic Status Register 0x2 Physical Identifier I 0x3 Physical Identifier II 0x4 Auto-Negotiation Advertisement Register 0x5 Auto-Negotiation Link Partner Ability Register 0x6 – 0x1F Not supported Register 0: MII Basic Control Bit Name R/W Description Default Reference 15 Soft reset RO NOT SUPPORTED 0 14 Loopback R/W =1, Loopback mode 0 Reg. 29, bit 0 =0, Normal operation Reg. 45, bit 0 13 Force 100 R/W =1, 100 Mbps 0 Reg. 28, bit 6 =0, 10 Mbps Reg. 44, bit 6 12 AN enable R/W =1, Auto-negotiation enabled 1 =0, Auto-negotiation disabled 11 Power down R/W =1, Power down 0 Reg. 29, bit 3 =0, Normal operation Reg. 45, bit 3 10 Isolate RO NOT SUPPORTED 0 9 Restart AN R/W =1, Restart auto-negotiation 0 Reg. 29, bit 5 =0, Normal operation Reg. 45, bit 5 8 Force full R/W =1, Full duplex 0 Reg. 28, bit 5 duplex =0, Half duplex Reg. 44, bit 5 7 Collision test RO NOT SUPPORTED 0 6 Reserved RO 0 5 Reserved RO 0 4 Force MDI R/W =1, Force MDI (transmit on RXP / RXM pins) 0 Reg. 29, bit 1 =0, Normal operation (transmit on TXP / TXM Reg. 45, bit 1 pins) October 2008 45 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 0: MII Basic Control (continued) Bit Name R/W Description Default Reference 3 Disable MDIX R/W =1, Disable auto MDI-X 0 Reg. 29, bit 2 =0, Normal operation Reg. 45, bit 2 2 Disable far end R/W =1, Disable far end fault detection 0 Reg. 29, bit 4 fault =0, Normal operation 1 Disable R/W =1, Disable transmit 0 Reg. 29, bit 6 transmit =0, Normal operation Reg. 45, bit 6 0 Disable LED R/W =1, Disable LED 0 Reg. 29, bit 7 =0, Normal operation Reg. 45, bit 7 Register 1: MII Basic Status Bit Name R/W Description Default Reference 15 T4 capable RO =0, Not 100 BASE-T4 capable 0 14 100 Full RO =1, 100BASE-TX full duplex capable 1 Always 1 capable =0, Not capable of 100BASE-TX full duplex 13 100 Half RO =1, 100BASE-TX half duplex capable 1 Always 1 capable =0, Not 100BASE-TX half duplex capable 12 10 Full RO =1, 10BASE-T full duplex capable 1 Always 1 capable =0, Not 10BASE-T full duplex capable 11 10 Half RO =1, 10BASE-T half duplex capable 1 Always 1 capable =0, Not 10BASE-T half duplex capable 10-7 Reserved RO 0 6 Preamble RO NOT SUPPORTED 0 suppressed 5 AN complete RO =1, Auto-negotiation complete 0 Reg. 30, bit 6 =0, Auto-negotiation not completed Reg. 46, bit 6 4 Far end fault RO =1, Far end fault detected 0 Reg. 31, bit 0 =0, No far end fault detected 3 AN capable RO =1, Auto-negotiation capable 1 Reg. 28, bit 7 =0, Not auto-negotiation capable Reg. 44, bit 7 2 Link status RO =1, Link is up 0 Reg. 30, bit 5 =0, Link is down Reg. 46, bit 5 1 Jabber test RO NOT SUPPORTED 0 0 Extended RO =0, Not extended register capable 0 capable Register 2: PHYID HIGH Bit Name R/W Description Default 15-0 PHYID high RO High order PHYID bits 0x0022 Register 3: PHYID LOW Bit Name R/W Description Default 15-0 PHYID low RO Low order PHYID bits 0x1430 October 2008 46 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 4: Auto-Negotiation Advertisement Ability Bit Name R/W Description Default Reference 15 Next page RO NOT SUPPORTED 0 14 Reserved RO 0 13 Remote fault RO NOT SUPPORTED 0 12-11 Reserved RO 0 10 Pause R/W =1, Advertise pause ability 1 Reg. 28, bit 4 =0, Do not advertise pause ability Reg. 44, bit 4 9 Reserved R/W 0 8 Adv 100 Full R/W =1, Advertise 100 full duplex ability 1 Reg. 28, bit 3 =0, Do not advertise 100 full duplex ability Reg. 44, bit 3 7 Adv 100 Half R/W =1, Advertise 100 half duplex ability 1 Reg. 28, bit 2 =0, Do not advertise 100 half duplex Reg. 44, bit 2 ability 6 Adv 10 Full R/W =1, Advertise 10 full duplex ability 1 Reg. 28, bit 1 =0, Do not advertise 10 full duplex ability Reg. 44, bit 1 5 Adv 10 Half R/W =1, Advertise 10 half duplex ability 1 Reg. 28, bit 0 =0, Do not advertise 10 half duplex ability Reg. 44, bit 0 4-0 Selector field RO 802.3 00001 Register 5: Auto-Negotiation Link Partner Ability Bit Name R/W Description Default Reference 15 Next page RO NOT SUPPORTED 0 14 LP ACK RO NOT SUPPORTED 0 13 Remote fault RO NOT SUPPORTED 0 12-11 Reserved RO 0 10 Pause RO Link partner pause capability 0 Reg. 30, bit 4 Reg. 46, bit 4 9 Reserved RO 0 8 Adv 100 Full RO Link partner 100 full capability 0 Reg. 30, bit 3 Reg. 46, bit 3 7 Adv 100 Half RO Link partner 100 half capability 0 Reg. 30, bit 2 Reg. 46, bit 2 6 Adv 10 Full RO Link partner 10 full capability 0 Reg. 30, bit 1 Reg. 46, bit 1 5 Adv 10 Half RO Link partner 10 half capability 0 Reg. 30, bit 0 Reg. 46, bit 0 4-0 Reserved RO 00000 October 2008 47 M9999-020606

Micrel, Inc. KSZ8993M/ML Register Map: Switch & PHY (8 bit registers) Global Registers Register (Decimal) Register (Hex0 Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12 0x0C Reserved Register 13-15 0x0D-0x0F User Defined Registers Port Registers Register (Decimal) Register (Hex0 Description 16-29 0x10-0x1D Port 1 Control Registers, including MII PHY Registers 30-31 0x1E-0x1F Port 1 Status Registers, including MII PHY Registers 32-45 0x20-0x2D Port 2 Control Registers, including MII PHY Registers 46-47 0x2E-0x2F Port 2 Status Registers, including MII PHY Registers 48-61 0x30-0x3D Port 3 Control Registers, including MII PHY Registers 62-63 0x3E-0x3F Port 3 Status Registers, including MII PHY Registers 64-95 0x40-0x5F Reserved Advanced Control Registers Register (Decimal) Register (Hex0 Description 96-103 0x60-0x67 TOS Priority Control Registers 104-109 0x68-0x6D Switch Engine’s MAC Address Registers 110-111 0x6E-0x6F Indirect Access Control Registers 112-120 0x70-0x78 Indirect Data Registers 121-122 0x79-0x7A Digital Testing Status Registers 123-124 0x7B-0x7C Digital Testing Control Registers 125-126 0x7D-0x7E Analog Testing Control Registers 127 0x7F Analog Testing Status Register Global Registers Register 0 (0x00): Chip ID0 Bit Name R/W Description Default 7-0 Family ID RO Chip family 0x93 October 2008 48 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W Description Default 7-4 Chip ID RO 0x0 is assigned to M series. (93M) 0x0 3-1 Revision ID RO Revision ID - 0 Start switch RW = 1, start the chip when external pins - (PS1, PS0) = (0,1) or (1,0) or (1,1). Note: In (PS1, PS0) = (0, 0) mode, the chip will start automatically after trying to read the external EEPROM. If EEPROM does not exist, the chip will use pin strapping and default values for all internal registers. If EEPROM is present, the contents in the EEPROM will be checked. The switch will check: (1) Register 0 = 0x93, (2) Register 1 bits [7:4] = 0x0. If this check is OK, the contents in the EEPROM will override chip registers’ default values. = 0, chip will not start when external pins (PS1, PS0) = (0,1) or (1,0) or (1,1). Register 2 (0x02): Global Control 0 Bit Name R/W Description Default 7 New back-off R/W New back-off algorithm designed for UNH 0x0 Enable 1 = Enable 0 = Disable 6-4 802.1p base R/W Used to classify priority for incoming 802.1Q packets. 0x4 priority “user priority” is compared against this value. >= : classified as high priority < : classified as low priority 3 Pass flow R/W = 1, switch will not filter 802.1x “flow control” packets 0x0 control packet 2 Buffer share R/W = 1, buffer pool is shared by all ports. A port can use 0x1 mode more buffers when other ports are not busy. = 0, a port is only allowed to use 1/3 of the buffer pool. 1 Reserved R/W Reserved 0 0 Link change R/W = 1, link change from “link” to “no link” will cause fast 0 age aging (<800us) to age address table faster. After an age cycle is complete, the age logic will return to normal aging (about 200 sec). Note: If any port is unplugged, all addresses will be automatically aged out. October 2008 49 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 3 (0x03): Global Control 1 Bit Name R/W Description Default 7 Pass all frames R/W = 1, switch all packets including bad ones. Used 0 solely for debugging purposes. Works in conjunction with sniffer mode only. 6 Repeater R/W 0 = normal mode 0 mode 1 = repeater mode (half duplex Hub mode) 5 IEEE 802.3x R/W = 1, will enable transmit direction flow control feature. 1 Transmit = 0, will not enable transmit direction flow control direction flow feature. control enable 4 IEEE 802.3x R/W = 1, will enable receive direction flow control feature. 1 Receive = 0, will not enable receive direction flow control direction flow feature. control enable 3 Frame Length R/W 1 = will check frame length field in the IEEE packets. 0 field check If the actual length does not match, the packet will be dropped (for Length/Type field < 1500). 2 Aging enable R/W 1 = enable age function in the chip 1 0 = disable age function in the chip 1 Fast age R/W 1 = turn on fast age (800us) 0 enable 0 Aggressive R/W 1 = enable more aggressive back off algorithm in half SMAC (pin back off enable duplex mode to enhance performance. This is not an 69) value IEEE standard. during reset. Register 4 (0x04): Global Control 2 Bit Name R/W Description Default 7 Unicast port- R/W This feature is used for port-VLAN (described in reg. 1 VLAN 17, reg. 33, …) mismatch = 1, all packets can not cross VLAN discard boundary = 0, unicast packets (excluding unkown/multicast/broadcast) can cross VLAN boundary Note: Port mirroring is not supported if this bit is set to “0”. 6 Multicast storm R/W = 1, “Broadcast Storm Protection” does not include 1 protection multicast packets. Only disable DA = FFFFFFFFFFFF packets will be regulated. = 0, “Broadcast Storm Protection” includes DA = FFFFFFFFFFFF and DA[40] = 1 packets. 5 Back pressure R/W = 1, carrier sense based backpressure is selected 1 Mode = 0, collision based backpressure is selected October 2008 50 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 4 (0x04): Global Control 2 (continued) Bit Name R/W Description Default 4 Flow control R/W = 1, fair mode is selected. In this mode, if a flow 1 and back control port and a non-flow control port talk to the pressure fair same destination port, packets from the non-flow mode control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time. = 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be “fair” to the flow control port. 3 No excessive R/W = 1, the switch will not drop packets when 16 or more SMAC (pin collision drop collisions occur. 69) value during = 0, the switch will drop packets when 16 or more reset. collisions occur. 2 Huge packet R/W = 1, will accept packet sizes up to 1916 bytes 0 support (inclusive). This bit setting will override setting from bit 1 of the same register. = 0, the max packet size will be determined by bit 1 of this register. 1 Legal R/W = 0, will accept packet sizes up to 1536 bytes SMRXD0 Maximum (inclusive). (pin 85) Packet size value = 1, 1522 bytes for tagged packets, 1518 bytes for check enable during untagged packets. Any packets larger than the reset. specified value will be dropped. 0 Priority Buffer R/W = 1, each output queue is pre-allocated 48 buffers, 1 reserve used exclusively for high priority packets. It is recommended to enable this when priority queue feature is turned on. = 0, no reserved buffers for high priority packets. Register 5 (0x05): Global Control 3 Bit Name R/W Description Default 7 802.1Q VLAN R/W = 1, 802.1Q VLAN mode is turned on. VLAN table 0 enable needs to set up before the operation. = 0, 802.1Q VLAN is disabled. 6 IGMP snoop R/W =1, IGMP snoop is enabled. 0 enable on All the IGMP packets will be forwarded to the Switch Switch MII MII port. interface =0, IGMP snoop is disabled. 5 Reserved R/W 0 4 Reserved R/W 0 3-2 Priority R/W 00 = always deliver high priority packets first 00 Scheme select 01 = deliver high/low packets at ratio 10/1 10 = deliver high/low packets at ratio 5/1 11 = deliver high/low packets at ratio 2/1 1 Reserved R/W 0 October 2008 51 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 5 (0x05): Global Control 3 (continued) Bit Name R/W Description Default 0 Sniff mode R./W = 1, will do rx AND tx sniff (both source port and 0 select destination port need to match) = 0, will do rx OR tx sniff (Either source port or destination port needs to match). This is the mode used to implement rx only sniff. Register 6 (0x06): Global Control 4 Bit Name R/W Description Default 7 Reserved R/W 0 6 Switch MII half- R/W = 1, enable MII interface half-duplex mode. Pin SMRXD2 duplex mode strap option. = 0, enable MII interface full-duplex mode. Pull-down(0): Full-duplex mode Pull-up(1): Half-duplex mode Note: SMRXD2 has internal pull- down. 5 Switch MII flow R/W = 1, enable full-duplex flow control on Switch MII Pin SMRXD3 control enable interface. strap option. = 0, disable full-duplex flow control on Switch MII Pull-down(0): interface. Disable flow control Pull- up(1): Enable flow control Note: SMRXD3 has internal pull- down. 4 Switch MII R/W = 1, the switch interface is in 10Mbps mode Pin SMRXD1 10BT strap option. = 0, the switch interface is in 100Mbps mode Pull – down(0): Enable 100Mbps Pull-up(1): Enable 10Mpbs Note: SMRXD1 has internal pull- down. October 2008 52 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 6 (0x06): Global Control 4 (continued) Bit Name R/W Description Default 3 Null VID R/W = 1, will replace NULL VID with port VID(12 bits) 0 replacement = 0, no replacement for NULL VID 2-0 Broadcast R/W This register along with the next register determines 000 storm how many “64 byte blocks” of packet data allowed on protection rate an input port in a preset period. The period is 50ms Bit [10:8] for 100BT or 500ms for 10BT. The default is 1%. Register 7 (0x07): Global Control 5 Bit Name R/W Description Default 7-0 Broadcast R/W This register along with the previous register 0x63 storm determines how many “64 byte blocks” of packet data protection are allowed on an input port in a preset period. The rate(1) period is 67ms for 100BT or 500ms for 10BT. The default is 1%. Bit [7:0] Note: Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63 Register 8 (0x08): Global Control 6 Bit Name R/W Description Default 7-0 Factory testing R/W Reserved 0x4E Register 9 (0x09): Global Control 7 Bit Name R/W Description Default 7-0 Factory testing R/W Reserved 0x24 Register 10 (0x0A): Global Control 8 Bit Name R/W Description Default 7-0 Factory testing R/W Reserved 0x24 Register 11 (0x0B): Global Control 9 Bit Name R/W Description Default 7 Reserved Reserved 0 6 PHY R/W = 1, enable PHY power save mode 0 power = 0, disable PHY power save mode save 5 Reserved R/W Reserved 0 4 Reserved RW Testing mode, must be 0 0 3 Reserved R/W Reserved 1 October 2008 53 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 11 (0x0B): Global Control 9 (continued) Bit Name R/W Description Default 2 Reserved R/W Reserved 0 1 LED mode R/W This register bit sets the LEDSEL0 selection only. LEDSEL0 LEDSEL1 is set via strap-in pin. pin value during Port x LED indicators, defined as below: reset. [LEDSEL1, LEDSEL0] [0, 0] [0, 1] PxLED3 ------ ------ PxLED2 LINK/ACT 100LINK/ACT PxLED1 FULL_DPX/COL 10LINK/ACT PxLED0 SPEED FULL_DPX [LEDSEL1, LEDSEL0] [1, 0] [1, 1] PxLED3 ACT ------ PxLED2 LINK ------ PxLED1 FULL_DPX/COL ------ PxLED0 SPEED ------ Notes: LEDSEL0 is external strap-in pin #70. LEDSEL1 is external strap-in pin #23. 0 Special R/W Used for direct mode forwarding from port 3. See 0 TPID description in “spanning tree” functional description. mode 0 = disable 1 = enable Register 12 (0x0C): Reserved Register Bit Name R/W Description Default 7-0 Reserved Reserved 0x00 Register 13 (0x0D): User Defined Register 1 Bit Name R/W Description Default 7-0 UDR1 R/W 0x00 Register 14 (0x0E): User Defined Register 2 Bit Name R/W Description Default 7-0 UDR2 R/W 0x00 Register 15 (0x0F): User Defined Register 3 Bit Name R/W Description Default 7-0 UDR3 R/W 0x00 October 2008 54 M9999-020606

Micrel, Inc. KSZ8993M/ML Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Bit Name R/W Description Default 7 Broadcast R/W = 1, enable broadcast storm protection for 0 storm ingress packets on the port protection = 0, disable broadcast storm protection enable 6 DiffServ priority R/W = 1, enable DiffServ priority classification for 0 classification ingress packets on port enable = 0, disable DiffServ function 5 802.1p priority R/W = 1, enable 802.1p priority classification for Pin value during classification ingress packets on port reset: enable = 0, disable 802.1p P1_1PEN (port 1) P2_1PEN (port 2) P3_1PEN (port 3) 4 Port-based R/W = 1, ingress packets on the port will be classified Pin value during priority as high priority if “DiffServ” or “802.1p” reset: classification classification is not enabled or fails to classify. P1_PP (port 1) enable = 0, ingress packets on port will be classified as P2_PP (port 2) low priority if “DiffServ” or “802.1p” classification is not enabled or fails to classify. P3_PP (port 3) Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of 802.1p and DSCP overwrites the port priority. 3 User priority R/W = 1, if the packet’s “user priority field” is greater 0 ceiling than the “user priority field” in the port default tag register, replace the packet’s “user priority field” with the “user priority field” in the port default tag register. = 0, do not compare and replace the packet’s ‘user priority field” 2 Tag insertion R/W = 1, when packets are output on the port, the Pin value during switch will add 802.1p/q tags to packets without reset: 802.1p/q tags when received. The switch will not P1_TAGINS add tags to packets already tagged. The tag (port 1) inserted is the ingress port’s “port VID”. P2_TAGINS = 0, disable tag insertion (port 2) P3_TAGINS (port 3) October 2008 55 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 (continued) Bit Name R/W Description Default 1 Tag removal R/W = 1, when packets are output on the port, the Pin value during switch will remove 802.1p/q tags from packets reset: with 802.1p/q tags when received. The switch will P1_TAGRM not modify packets received without tags. (port 1) = 0, disable tag removal P2_TAGRM (port 2) P3_TAGRM (port 3) 0 Priority enable R/W = 1, the port output queue is split into high and Pin value during low priority queues. reset: = 0, single output queue on the port. There is no P1_TXQ2 (port priority differentiation even though packets are 1) classified into high or low priority. P2_TXQ2 (port 2) P3_TXQ2 (port 3) Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W Description Default 7 Sniffer port R/W = 1, Port is designated as sniffer port and will 0 transmit packets that are monitored. = 0, Port is a normal port 6 Receive sniff R/W = 1, All the packets received on the port will be 0 marked as “monitored packets” and forwarded to the designated “sniffer port” = 0, no receive monitoring 5 Transmit sniff R/W = 1, All the packets transmitted on the port will be 0 marked as “monitored packets” and forwarded to the designated “sniffer port” = 0, no transmit monitoring 4 Double tag R/W = 1, All packets will be tagged with port default 0x0 tag of ingress port regardless of the original packets are tagged or not = 0, do not double tagged on all packets 3 Reserved R/W 0x0 2-0 Port VLAN R/W Define the port’s “ egress port VLAN Pin value during membership membership. Bit 2 stands for port 3, bit 1 for port reset: 2 bit 0 for port 1. The Port can only communicate For port 1, within the membership. A ‘1’ includes a port in (PV13, PV12, 1) the membership, a ‘0’ excludes a port from For port 2, membership. (PV23, 1, PV21) For port 3, (1, PV32, PV31) October 2008 56 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Bit Name R/W Description Default 7 Reserved Reserved 0 6 Ingress VLAN R/W = 1, the switch will discard packets whose VID 0 filtering port membership in VLAN table bits [18:16] does not include the ingress port. = 0, no ingress VLAN filtering. 5 Discard non R/W = 1, the switch will discard packets whose VID 0 PVID packets does not match ingress port default VID. = 0, no packets will be discarded 4 Force flow R/W = 1, will always enable flow control on the port, Pin value during control regardless of AN result. reset: = 0, the flow control is enabled based on AN For port 1, result. P1FFC pin For port 2, P2FFC pin For port 3, this bit has no meaning. Flow control is controlled by Reg. 6, bit 5. 3 Back pressure R/W = 1, enable port’s half duplex back pressure Pin value during enable reset: = 0, disable port’s half duplex back pressure. BPEN pin 2 Transmit R/W = 1, enable packet transmission on the port 1 enable = 0, disable packet transmission on the port 1 Receive R/W = 1, enable packet reception on the port 1 enable = 0, disable packet reception on the port 0 Learning R/W = 1, disable switch address learning capability 0 disable = 0, enable switch address learning Note: Bits [2:0] are used for spanning tree support (see page 33). Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Bit Name R/W Description Default 7-0 Default tag R/W Port’s default tag, containing 0x00 [15:8] 7-5 : User priority bits 4 : CFI bit 3-0 : VID[11:8] October 2008 57 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Bit Name R/W Description Default 7-0 Default tag R/W Port’s default tag, containing 0x01 [7:0] 7-0: VID[7:0] Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes: 1. Associated with the ingress untagged packets, and used for egress tagging. 2. Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup. Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Bit Name R/W Description Default 7-0 Transmit high R/W This register along with port control 7, bits [3:0] 0x00 priority rate form a 12-bits field to determine how many control [7:0] “32Kbps” high priority blocks can be transmitted in a unit of 4Kbytes in a one second period). Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Bit Name R/W Description Default 7-0 Transmit low R/W This register along with port control 7, bits [7:4] 0x00 priority rate form a 12-bits field to determine how many control [7:0] “32Kbps” low priority blocks can be transmitted in a unit of 4 Kbytes in a one second period). Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Bit Name R/W Description Default 7-4 Transmit low R/W These bits along with port control 6, bits [7:0] 0x0 priority rate form a 12-bits field to determine how many control [11:8] “32Kbps” low priority blocks can be transmitted in a unit of 4Kbytes in a one second period). 3-0 Transmit high R/W These bits along with port control 5, bits [7:0] 0x0 priority rate form a 12-bits field to determine how many control [11:8] “32Kbps” high priority blocks can be transmitted (in a unit of 4Kbytes in a one second period). Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Bit Name R/W Description Default 7-0 Receive high R/W This register along with port control 10, bits [3:0] 0x00 priority rate form a 12-bits field to determine how many control [7:0] “32Kbps” high priority blocks can be received in a unit of 4Kbytes in a one second period). October 2008 58 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Bit Name R/W Description Default 7-0 Receive low R/W This register along with port control 10, bits [7:4] 0x00 priority rate form a 12-bits field to determine how many control [7:0] “32Kbps” low priority blocks can be received (in a unit of 4Kbytes in a one second period). Register 26 (0x1A): Port 1 Control 10 Register 42 (0x2A): Port 2 Control 10 Register 58 (0x3A): Port 3 Control 10 Bit Name R/W Description Default 7-4 Receive low R/W These bits along with port control 9, bits [7:0] 0x0 priority rate form a 12-bits field to determine how many control [11:8] “32Kbps” low priority blocks can be received (in a unit of 4Kbytes in a one second period). 3-0 Receive high R/W These bits along with port control 8, bits [7:0] 0x0 priority rate form a 12-bits field to determine how many control [11:8] “32Kbps” high priority blocks can be received (in a unit of 4Kbytes in a one second period). Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Bit Name R/W Description Default 7 Receive R/W = 1, If bit 6 is also ‘1’ this will enable receive rate 0 differential control for this port on low priority packets at the priority rate low priority rate. If bit 5 is also ‘1’, this will enable control receive rate control on high priority packets at the high priority rate. = 0, receive rate control will be based on the low priority rate for all packets on this port. 6 Low priority R/W = 1, enable port’s low priority receive rate control 0 receive rate feature control enable = 0, disable port’s low priority receive rate control 5 High priority R/W = 1, If bit 7 is also ‘1’ this will enable the port’s 0 receive rate high priority receive rate control feature. If bit 7 is control enable a ‘0’ and bit 6 is a ‘1’, all receive packets on this port will be rate controlled at the low priority rate. = 0, disable port’s high priority receive rate control feature 4 Low priority R/W = 1, flow control may be asserted if the port’s low 0 receive rate priority receive rate is exceeded. flow control = 0, flow control is not asserted if the port’s low enable priority receive rate is exceeded. October 2008 59 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 (continued Bit Name R/W Description Default 3 High priority R/W = 1, flow control may be asserted if the port’s 0 receive rate high priority receive rate is exceeded. flow control (To use this, differential receive rate control must enable be on.) = 0, flow control is not asserted if the port’s high priority receive rate is exceeded. 2 Transmit R/W = 1, will do transmit rate control on both high and 0 differential low priority packets based on the rate counters priority rate defined by the high and low priority packets control respectively. = 0, will do transmit rate control on any packets. The rate counters defined in low priority will be used. 1 Low priority R/W 1, enable the port’s low priority transmit rate 0 transmit rate control feature control enable = 0, disable the port’s low priority transmit rate control feature 0 High priority R/W = 1, enable the port’s high priority transmit rate 0 transmit rate control feature control enable = 0, disable the port’s high priority transmit rate control feature Note: Port Control 12 and 13, and Port Status 0 contents can also be accessed with the MIIM (MDC/MDIO) interface via the Standard MIIM registers. Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 Bit Name R/W Description Default 7 Auto R/W = 0, disable auto negotiation, speed and duplex For port 1, negotiation are decided by bit 6 and 5 of the same register. P1ANEN pin enable value during = 1, auto negotiation is on reset. For port 2, P2ANEN pin value during reset 6 Force speed R/W = 1, forced 100BT if AN is disabled (bit 7) For port 1, P1SPD pin = 0, forced 10BT if AN is disabled (bit 7) value during reset. For port 2, P2SPD pin value during reset. October 2008 60 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 (continued) Bit Name R/W Description Default 5 Force duplex R/W = 1, forced full duplex if (1) AN is disabled or (2) For port 1, AN is enabled but failed. P1DPX pin value during = 0, forced half duplex if (1) AN is disabled or (2) reset. AN is enabled but failed. For port 2, P2DPX pin value during reset. 4 Advertised flow R/W = 1, advertise flow control (pause) capability ADVFC pin control value during = 0, suppress flow control (pause) capability from capability reset. transmission to link partner 3 Advertised R/W = 1, advertise 100BT full-duplex capability 1 100BT full- = 0, suppress 100BT full-duplex capability from duplex transmission to link partner capability 2 Advertised R/W = 1, advertise 100BT half-duplex capability 1 100BT half- = 0, suppress 100BT half-duplex capability from duplex transmission to link partner capability 1 Advertised R/W = 1, advertise 10BT full-duplex capability 1 10BT full- = 0, suppress 10BT full-duplex capability from duplex transmission to link partner capability 0 Advertised R/W = 1, advertise 10BT half-duplex capability 1 10BT half- = 0, suppress 10BT half-duplex capability from duplex transmission to link partner capability Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Reserved, not applied to port 3 Bit Name R/W Description Default 7 LED off R/W = 1, Turn off all port’s LEDs (LEDx_3, LEDx_2, 0 LEDx_1, LEDx_0, where “x” is the port number). These pins will be driven high if this bit is set to one. = 0, normal operation 6 Txids R/W = 1, disable port’s transmitter 0 = 0, normal operation 5 Restart AN R/W = 1, restart auto-negotiation 0 = 0, normal operation October 2008 61 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Reserved, not applied to port 3 (continued) Bit Name R/W Description Default 4 Disable far end R/W = 1, disable far end fault detection and pattern 0 fault transmission. Note: Only port = 0, enable far end fault detection and pattern 1 supports fiber. transmission This bit is applicable to port 1 only. 3 Power-down R/W = 1, power-down 0 = 0, normal operation 2 Disable auto R/W = 1, disable auto MDI/MDI-X function 0 MDI/MDI-X = 0, enable auto MDI/MDI-X function For port 2, P2MDIX disable pin value during reset. 1 Force MDI-X R/W If auto MDI/MDI-X is disabled, 0 = 1, force PHY into MDI mode (transmit on For port 2, RXP/RXM pins) P2MDIX pin = 0, force PHY into MDI-X mode (transmit on value during reset. TXP/TXM pins) 0 Loopback R/W = 1, perform loopback, as indicated: 0 Port 1 Loopback (reg. 29, bit 0 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) Port 2 Loopback (reg. 45, bit 0 ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port 1) = 0, normal operation Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 Bit Name R/W Description Default 7 MDI-X status RO = 1, MDI-X 0 = 0, MDI 6 AN done RO = 1, AN done 0 = 0, AN not done 5 Link good RO = 1, link good = 0, link not good 4 Partner flow RO = 1, link partner flow control (pause) capable control = 0, link partner not flow control (pause) capable capability October 2008 62 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 (continued) Bit Name R/W Description Default 3 Partner 100BT RO = 1, link partner 100BT full-duplex capable 0 full-duplex = 0, link partner not 100BT full-duplex capable capability 2 Partner 100BT RO = 1, link partner 100BT half-duplex capable 0 half-duplex = 0, link partner not 100BT half-duplex capable capability 1 Partner 10BT RO = 1, link partner 10BT full-duplex capable 0 full-duplex = 0, link partner not 10BT full-duplex capable capability 0 Partner 10BT RO = 1, link partner 10BT half-duplex capable 0 half-duplex = 0, link partner not 10BT half-duplex capable capability Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W Description Default 7 Reserved RO 0 6-5 Reserved RO 00 4 Receive flow RO 1 = receive flow control feature is active 0 control enable 0 = receive flow control feature is inactive 3 Transmit flow RO 1 = transmit flow control feature is active 0 control enable 0 = transmit flow control feature is inactive 2 Operation RO 1 = link speed is 100Mbps 0 speed 0 = link speed is 10Mbps 1 Operation RO 1 = link duplex is full 0 duplex 0 = link duplex is half 0 Far end fault RO = 1, far end fault status detected 0 = 0, no far end fault status detected Note: only port 1 supports fiber; this bit is applicable to port 1 only. October 2008 63 M9999-020606

Micrel, Inc. KSZ8993M/ML Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. f the register bit is a 1, the priority is high; if it is a 0, the priority is low. Register 96 (0x60): TOS Priority Control Register 0 Bit Name R/W Description Default 7-0 DSCP[63:56] R/W 0000_0000 Register 97 (0x61): TOS Priority Control Register 1 Bit Name R/W Description Default 7-0 DSCP[55:48] R/W 0000_0000 Register 98 (0x62): TOS Priority Control Register 2 Bit Name R/W Description Default 7-0 DSCP[47:40] R/W 0000_0000 Register 99 (0x63): TOS Priority Control Register 3 Bit Name R/W Description Default 7-0 DSCP[39:32] R/W 0000_0000 Register 100 (0x64): TOS Priority Control Register 4 Bit Name R/W Description Default 7-0 DSCP[31:24] R/W 0000_0000 Register 101 (0x65): TOS Priority Control Register 5 Bit Name R/W Description Default 7-0 DSCP[23:16] R/W 0000_0000 Register 102 (0x66): TOS Priority Control Register 6 Bit Name R/W Description Default 7-0 DSCP[15:8] R/W 0000_0000 Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W Description Default 7-0 DSCP[7:0] R/W 0000_0000 October 2008 64 M9999-020606

Micrel, Inc. KSZ8993M/ML Registers 104 to 109 Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the SA for MAC pause control frames. Register 104 (0x68): MAC Address Register 0 Bit Name R/W Description Default 7-0 MACA[47:40] R/W 0x00 Register 105 (0x69): MAC Address Register 1 Bit Name R/W Description Default 7-0 MACA[39:32] R/W 0x10 Register 106 (0x6A): MAC Address Register 2 Bit Name R/W Description Default 7-0 MACA[31:24] R/W 0xA1 Register 107 (0x6B): MAC Address Register 3 Bit Name R/W Description Default 7-0 MACA[23:16] R/W 0xFF Register 108 (0x6C): MAC Address Register 4 Bit Name R/W Description Default 7-0 MACA[15:8] R/W 0xFF Register 109 (0X6D): MAC Address Register 5 Bit Name R/W Description Default 7-0 MACA[7:0] R/W 0xFF October 2008 65 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 110 and 111 Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. Register 110 (0x6E): Indirect Access Control 0 Bit Name R/W Description Default 7-5 Reserved R/W Reserved 000 4 Read high R/W = 1, read cycle 0 Write low = 0, write cycle 3-2 Table select R/W 00 = static MAC address table selected 00 01 = VLAN table selected 10 = dynamic address table selected 11 = MIB counter selected 1-0 Indirect R/W Bit 9-8 of indirect address 00 address high Register 111 (0x6F): Indirect Access Control 1 Bit Name R/W Description Default 7-0 Indirect R/W Bit 7-0 of indirect address 0000_0000 address low Note: Write to register 111 will actually trigger a command. Read or write access is determined by Register 110 bit 4. Register 112 (0x70): Indirect Data Register 8 Bit Name R/W Description Default 68-64 Indirect data R/W Bit 68-64 of indirect data 0_0000 Register 113 (0x71): Indirect Data Register 7 Bit Name R/W Description Default 63-56 Indirect data R/W Bit 63-56 of indirect data 0000_0000 Register 114 (0x72): Indirect Data Register 6 Bit Name R/W Description Default 55-48 Indirect data R/W Bit 55-48 of indirect data 0000_0000 Register 115 (0x73): Indirect Data Register 5 Bit Name R/W Description Default 47-40 Indirect data R/W Bit 47-40 of indirect data 0000_0000 Register 116 (0x74): Indirect Data Register 4 Bit Name R/W Description Default 39-32 Indirect data R/W Bit 39-32 of indirect data 0000_0000 October 2008 66 M9999-020606

Micrel, Inc. KSZ8993M/ML Register 117 (0x75): Indirect Data Register 3 Bit Name R/W Description Default 31-24 Indirect data R/W Bit of 31-24 of indirect data 0000_0000 Register 118 (0x76): Indirect Data Register 2 Bit Name R/W Description Default 23-16 Indirect data R/W Bit 23-16 of indirect data 0000_0000 Register 119 (0x77): Indirect Data Register 1 Bit Name R/W Description Default 15-8 Indirect data R/W Bit 15-8 of indirect data 0000_0000 Register 120 (0x78): Indirect Data Register 0 Bit Name R/W Description Default 7-0 Indirect data R/W Bit 7-0 of indirect data 0000_0000 Registers 121 to 127 Registers 121 to 127 are Reserved. Static MAC Address Table The KSZ8993M has both a static and a dynamic MAC address table. When a destination address (DA) lookup is requested, both tables are searched to make a packet forwarding decision. When a SA lookup is requested, only the dynamic table is searched for aging, migration and learning purposes. The static DA lookup result will have precedence over the dynamic DA lookup result. If there is a DA match in both tables, the result from the static table will be used. The static table can be accessed and controlled by an external processor via the SMI, SPI and I2C interfaces. The external processor performs all addition, modification and deletion of static table entries. These entries in the static table will not be aged out by the KSZ8993M. Bit Name R/W Description Default 57-54 FID R/W Filter VLAN ID, representing one of the 16 active 0000 VLANs 53 Use FID R/W = 1, use (FID+MAC) to look up in static table 0 = 0, use MAC only to look up in static table 52 Override R/W = 1, override port setting “transmit enable=0” or 0 “receive enable=0” setting = 0, no override 51 Valid R/W = 1, this entry is valid, the lookup result will be 0 used = 0, this entry is not valid Table 12. Format of Static MAC Table (8 Entries) October 2008 67 M9999-020606

Micrel, Inc. KSZ8993M/ML Bit Name R/W Description Default 50-48 Forwarding R/W These 3 bits control the forwarding port(s): 000 ports 001, forward to port 1 010, forward to port 2 100, forward to port 3 011, forward to port 1 and port 2 110, forward to port 2 and port 3 101, forward to port 1 and port 3 111, broadcasting (excluding the ingress port) 47-0 MAC address R/W 48 bits MAC address 0x0000_0000_0000 Table 12. Format of Static MAC Table (8 Entries) (continued) Examples: 1. Static Address Table Read (Read the 2nd Entry) Write to reg. 110 with 0x10 (read static table selected) Write to reg. 111 with 0x01 (trigger the read operation) Then, Read reg. 113 (57-56) Read reg. 114 (55-48) Read reg. 115 (47-40) Read reg. 116 (39-32) Read reg. 117 (31-24) Read reg. 118 (23-16) Read reg. 119 (15-8) Read reg. 120 (7-0) 2. Static Address Table Write (Write the 8th Entry) Write reg. 113 (57-56) Write reg. 114 (55-48) Write reg. 115 (47-40) Write reg. 116 (39-32) Write reg. 117 (31-24) Write reg. 118 (23-16) Write reg. 119 (15-8) Write reg. 120 (7-0) Write to reg. 110 with 0x00 (write static table selected) Write to reg. 111 with 0x07 (trigger the write operation) VLAN Table VLAN table is used to do VLAN table lookup. If 802.1Q VLAN mode is enabled (Register 5, Bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID), VID (VLAN ID), and VLAN membership as described in the following table. October 2008 68 M9999-020606

Micrel, Inc. KSZ8993M/ML Bit Name R/W Description Default 19 Valid R/W = 1, the entry is valid 1 = 0, entry is invalid 18-16 Membership R/W Specify which ports are members of the VLAN. If 111 a DA lookup fails (no match in both static and dynamic tables), then the packet associated with this VLAN will be forwarded to ports specified in this field. For example, 101 means port 3 and 1 are in this VLAN. 15-12 FID R/W Filter ID. KSZ8993M supports 16 active VLANs 0x0 represented by these four bit fields. FID is the mapped ID. If 802.1Q VLAN is enabled, the lookup will be based on FID+DA and FID+SA. 11-0 VID R/W IEEE 802.1Q 12 bits VLAN ID 0x001 Table 13. Format of Static VLAN Table (16 Entries) If 802.1Q VLAN mode is enabled, KSZ8993M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The lookup process will start from the VLAN table lookup. If the VID is not valid, the packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and FID+SA lookups are performed. The FID+DA lookup determines the forwarding ports. If FID+DA fails, the packet will be broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned. Examples: 1. VLAN Table Read (read the 3rd entry) Write to reg. 110 with 0x14 (read VLAN table selected) Write to reg. 111 with 0x02 (trigger the read operation) Then Read reg. 118 (VLAN table bits 19-16) Read reg. 119 (VLAN table bits 15-8) Read reg. 120 (VLAN table bits 7-0) 2. VLAN Table Write (write the 7th entry) Write to reg. 118 (VLAN table bits 19-16) Write to reg. 119 (VLAN table bits 15-8) Write to reg. 120 (VLAN table bits 7-0) Write to reg. 110 with 0x04 (write VLAN table selected) Write to reg. 111 with 0x06 (trigger the write operation) Dynamic MAC Address Table This table is read only. The table contents are maintained by KSZ8993M only. Bit Name R/W Description Default 71 Data not ready RO = 1, entry is not ready, retry until this bit is set to 0 = 0, entry is ready 70-67 Reserved RO Reserved Table 14. Format of Dynamic MAC Address Table (1K Entries) October 2008 69 M9999-020606

Micrel, Inc. KSZ8993M/ML Bit Name R/W Description Default 66 MAC empty RO = 1, there is no valid entry in the table 1 = 0, there are valid entries in the table 65-56 No of valid RO Indicates how many valid entries in the table 00_0000_0000 entries 0x3ff means 1 K entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry 55-54 Time stamp RO 2 bits counter for internal aging 53-52 Source port RO The source port where FID+MAC is learned 00 00, port 1 01, port 2 10, port 3 51-48 FID RO Filter ID 0x0 47-0 MAC address RO 48 bits MAC address 0x0000_0000_0000 Table 14. Format of Dynamic MAC Address Table (1K Entries) (continued) Example: Dynamic MAC Address Table Read (read the 1st entry and retrieve the MAC table size) Write to reg. 110 with 0x18 (read dynamic table selected) Write to reg. 111 with 0x00 (trigger the read operation) Then Read reg. 112 (71-64) // if bit 71 = 1, restart (reread) from this register Read reg. 113 (63-56) Read reg. 114 (55-48) Read reg. 115 (47-40) Read reg. 116 (39-32) Read reg. 117 (31-24) Read reg. 118 (23-16) Read reg. 119 (15-8) Read reg. 120 (7-0) MIB (Management Information Base) Counters The KSZ8993M provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” Bit Name R/W Description Default 31 Reserve RO Reserve 0 30 Count valid RO = 1, counter value is valid 0 = 0, counter value is not valid 29-0 Counter values RO Counter value 0 Table 15. Format of “Per Port” MIB Counters “Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for all three ports are: Port 1, base is 0x00 and range is (0x00-0x1f) Port 2, base is 0x20 and range is (0x20-0x3f) Port 3, base is 0x40 and range is (0x40-0x5f) October 2008 70 M9999-020606

Micrel, Inc. KSZ8993M/ML Port 1’s “Per Port” MIB Counters Indirect Memory Offsets are shown in the following table. Offset Counter Name Description 0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets 0x1 RxHiPriorityByte Rx hi-priority octet count including bad packets 0x2 RxUndersizePkt Rx undersize packets w/ good CRC 0x3 RxFragments Rx fragment packets w/ bad CRC, symbol errors or alignment errors 0x4 RxOversize Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes) 0x5 RxJabbers Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol errors (depends on max packet size setting) 0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size. 0x7 RxCRCError Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit depends on max packet size setting) 0x8 RxAlignmentError Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting) 0x9 RxControl8808Pkts Number of MAC control frames received by a port with 88-08h in EtherType field 0xA RxPausePkts Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC 0xB RxBroadcast Rx good broadcast packets (not including error broadcast packets or valid multicast packets) 0xC RxMulticast Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets) 0xD RxUnicast Rx good unicast packets 0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length 0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets 0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets 0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet 0x17 TxPausePkts Number of PAUSE frames transmitted by a port 0x18 TxBroadcastPkts Tx good broadcast packets (not including error broadcast or valid multicast packets) 0x19 TxMulticastPkts Tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1A TxUnicastPkts Tx good unicast packets Table 16. Port 1s “Per Port” MIB Counters Indirect Memory Offsets October 2008 71 M9999-020606

Micrel, Inc. KSZ8993M/ML Offset Counter Name Description 0x1B TxDeferred Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium 0x1C TxTotalCollision Tx total collision, half duplex only 0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions 0x1E TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision 0x1F TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets Bit Name R/W Description Default 30-16 Reserved N/A Reserved N/A 15-0 Counter values RO Counter value 0 Table 18. Format of “All Port Dropped Packet” MIB Counters “All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in the following table: Offset Counter Name Description 0x100 Port1 TX Drop Packets TX packets dropped due to lack of resources 0x101 Port2 TX Drop Packets TX packets dropped due to lack of resources 0x102 Port3 TX Drop Packets TX packets dropped due to lack of resources 0x103 Port1 RX Drop Packets RX packets dropped due to lack of resources 0x104 Port2 RX Drop Packets RX packets dropped due to lack of resources 0x105 Port3 RX Drop Packets RX packets dropped due to lack of resources Table 19. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets Examples: 1. MIB Counter Read (Read port 1 “Rx64Octets” Counter) Write to reg. 110 with 0x1c (read MIB counters selected) Write to reg. 111 with 0x0e (trigger the read operation) Then Read reg. 117 (counter value 30-24) // If bit 30 = 0, restart (reread) from this register Read reg. 118 (counter value 23-16) Read reg. 119 (counter value 15-8) Read reg. 120 (counter value 7-0) 2. MIB Counter Read (Read Port 2 “Rx64Octets” Counter) Write to reg. 110 with 0x1c (read MIB counter selected) Write to reg. 111 with 0x2e (trigger the read operation) October 2008 72 M9999-020606

Micrel, Inc. KSZ8993M/ML Then, Read reg. 117 (counter value 30-24) // If bit 30 = 0, restart (reread) from this register Read reg. 118 (counter value 23-16) Read reg. 119 (counter value 15-8) Read reg. 120 (counter value 7-0) 3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter) Write to reg. 110 with 0x1d (read MIB counter selected) Write to reg. 111 with 0x00 (trigger the read operation) Then Read reg. 119 (counter value 15-8) Read reg. 120 (counter value 7-0) Additional Information Both “Per Port” and “All Port Dropped Packet” MIB counters do not indicate overflow. The application must keep track of overflow conditions for these counters. “All Port Dropped Packet” MIB counters do not indicate if count is valid. The application must keep track of valid conditions for these counters. To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. A high performance SPI master is also recommended to prevent counters overflow. Per Port MIB counters are designed as “read clear.” That is, these counters will be cleared after they are read. “All Port Dropped Packet” MIB counters are not cleared after they are read. October 2008 73 M9999-020606

Micrel, Inc. KSZ8993M/ML Absolute Maximum Ratings(1) Description Pins Value Supply Storage N/A -55°C to 150°C Supply Voltage V , V , V –0.5V to 2.4V DDA DDAP DDC V , V , V –0.5V to 4.0V DDATX DDARX DDIO Input Voltage (all inputs) All Inputs –0.5V to 4.0V Output Voltage (all outputs All Outputs –0.5V to 4.0V Lead Temperature (soldering, 10 sec) N/A Storage Temperature (T ) N/A -55°C to 150°C s Note: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level. Operating Ratings(1) Parameter Symbol Min Typ Max Supply Voltages V ,V ,V 1.710V 1.8V 1.890V DDA DDAP DDC V ,V , V 3.135V 3.3V 3.465V DDATX DDARX DDIO Ambient Operating T 0°C 70°C Temperature (M, ML) A Ambient Operating T -40°C 85°C Temperature (MI, MLI) A Maximum Junction T 125°C J Temperature Thermal Resistance Junction to Ambient(2) θJA 32°C/W Notes: 1. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). 2. No (HS) heat spreader in this package. October 2008 74 M9999-020606

Micrel, Inc. KSZ8993M/ML Electrical Characteristics(1) V = xx; R =xx; T = 25°C, bold values indicate –40°C< T < +85°C; unless noted. IN L A A Parameter Symbol Condition Min Typ Max Supply Current (including TX output driver current, KSZ8993M device only) 100BASE-TX Operation (All Ports@100% Utilization) 100BASE-TX (analog core + PLL + I VDDA, VDDAP, VDDC = 1.8V 92mA digital core) ddc 100BASE-TX (transceiver + digital I VDDATX, VDDARX, VDDIO = 3.3V 33mA ddxio I/O) 10BASE-T Operation (All Ports@100% Utilization) 10BASE-T I VDDA, VDDAP, VDDC = 1.8V 66mA (analog core + PLL + digital core) ddc 10BASE-T I VDDATX, VDDARX, VDDIO = 3.3V 35mA (transceiver + digital I/O) ddxio TTL Inputs Input High Voltage V 2.0V ih Input Low Voltage V 0.8V il Input Current I V = GND ~ VDDIO -10µA 10µA in in TTL Outputs Output High Voltage V I = -8 mA 2.4V oh oh Output Low Voltage V I = 8 mA 0.4V ol ol Output Tri-State Leakage |I | 10µA oz 100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage V 100Ω termination on the differential 0.95V 1.05V o output. Output Voltage Imbalance V 100Ω termination on the differential 2% imb output Rise/Fall Time T/T 3ns 5ns r f Rise/Fall Time Imbalance 0ns 0.5ns 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion + 0.5ns Overshoot 5% Reference Voltage of ISET V 0.5V set Output Jitters Peak-to-peak 0.7ns 1.4ns Note: 1. Specification for packaged product only. October 2008 75 M9999-020606

Micrel, Inc. KSZ8993M/ML Electrical Characteristics (continued)(1) Parameter Symbol Condition Min Typ Max 10BaseT Receive Squelch Threshold Vsq 5MHz square wave 400mV 10BaseT Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only Peak Differential Output Voltage Vp 100Ω termination on the differential 2.3V output. Jitters Added 100Ω termination on the differential + 3.5ns output. Rise/Fall Time 25ns Note: 1. Specification for packaged product only. October 2008 76 M9999-020606

Micrel, Inc. KSZ8993M/ML Timing Specifications EEPROM Timing Figure 13. EEPROM Interface Input Timing Diagram Figure 14. EEPROM Interface Output Timing Diagram Timing Parameter Description Min Typ Max Unit t Clock cycle 16384 ns cyc1 t Setup time 20 ns s1 t Hold time 20 ns h1 t Output valid 4096 4112 4128 ns ov1 Table 20. EEPROM Timing Parameters October 2008 77 M9999-020606

Micrel, Inc. KSZ8993M/ML SNI Timing Figure 15. SNI Input Timing Diagram Figure 16. SNI Output Timing Diagram Timing Parameter Description Min Typ Max Unit t Clock cycle 100 ns cyc2 t Setup time 10 ns s2 t Hold time 0 ns h2 t Output valid 0 3 6 ns ov2 Table 21. SNI Timing Parameters October 2008 78 M9999-020606

Micrel, Inc. KSZ8993M/ML MII Timing MAC Mode MII Timing Figure 17. MAC-Mode MII Timing – Data Received from MII Figure 18. MAC-Mode MII Timing – Data Input to MII Timing Parameter Description Min Typ Max Unit t (100BASE-T) Clock cycle 40 ns cyc3 100BASE-T tcyc3 (10BASE-T) Clock cycle 400 ns 10BASE-T t Setup time 10 ns s3 t Hold time 10 ns h3 t Output valid 0 25 ns ov3 Table 22. MAC-Mode MII Timing Parameters October 2008 79 M9999-020606

Micrel, Inc. KSZ8993M/ML PHY-Mode MII Timing Figure 19. PHY-Mode MII Timing – Data Received from MII Figure 20. PHY-Mode MII Timing – Data Input to MII Timing Parameter Description Min Typ Max Unit tcyc4 Clock cycle 40 ns (100BASE-T) 100BASE-T tcyc4 (10BASE-T) Clock cycle 400 ns 10BASE-T ts4 Setup time 10 ns th4 Hold time 10 ns tov4 Output valid 0 25 ns Table 23. PHY-Mode MII Timing Parameters October 2008 80 M9999-020606

Micrel, Inc. KSZ8993M/ML SPI Timing Input Timing Figure 21. SPI Input Timing Timing Parameter Description Min Max Units fC Clock frequency 5 MHz tCHSL SPIS_N inactive hold time 90 ns tSLCH SPIS_N active setup time 90 ns tCHSH SPIS_N active old time 90 ns tSHCH SPIS_N inactive setup time 90 ns tSHSL SPIS_N deselect time 100 ns tDVCH Data input setup time 20 ns tCHDX Data input hold time 30 ns tCLCH Clock rise time 1 us tCHCL Clock fall time 1 us tDLDH Data input rise time 1 us tDHDL Data input fall time 1 us Table 24. SPI Input Timing Parameters October 2008 81 M9999-020606

Micrel, Inc. KSZ8993M/ML Output Timing Figure 22. SPI Output Timing Timing Parameter Description Min Max Units fC Clock frequency 5 MHz tCLQX SPIQ hold time 0 0 ns tCLQV Clock low to SPIQ valid 60 ns tCH Clock high time 90 ns tCL Clock low time 90 tQLQH SPIQ rise time 50 ns tQHQL SPIQ fall time 50 ns tSHQZ SPIQ disable time 100 ns Table 25. SPI Output Timing Parameters October 2008 82 M9999-020606

Micrel, Inc. KSZ8993M/ML Reset Timing As long as the stable supply voltages to reset high timing (minimum of10ms) are met, there is no power sequencing requirement for the KSZ8993M supply voltages (1.8V, 3.3). It is recommended to wait 100µsec after the de-assertion of reset before starting programming on the managed interface. The reset timing requirement is summarized in the following figure and table. Figure 23. Reset Timing Parameter Description Min Max Units t Stable supply voltages to reset high 10 ms sr t Configuration setup time 50 ns cs t Configuration hold time 50 ns ch t Reset to strap-in pin output 50 us rc Table 26. Reset Timing Parameters Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 24 when powering up the KSZ8893M/ML/MI device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 25. October 2008 83 M9999-020606

Micrel, Inc. KSZ8993M/ML Figure 24. Recommended Reset Circuit Figure 25. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. October 2008 84 M9999-020606

Micrel, Inc. KSZ8993M/ML Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Value Test Condition Turns ratio 1 CT : 1 CT Open-circuit inductance (min.) 350µH 100mV, 100kHz, 8mA Leakage inductance (max.) 0.4µH 1MHz (min.) Inter-winding capacitance (max.) 12pF D.C. resistance (max.) 0.9Ω Insertion loss (max.) 1.0dB 0MHz – 65MHz HIPOT (min.) 1500Vrms Table 27. Transformer Selection Criteria Magnetic Manufacturer Part Number Auto MDI-X Number of Port Bel Fuse S558-5999-U7 Yes 1 Bel Fuse SI-46001 Yes 1 Bel Fuse SI-50170 Yes 1 Delta LF8505 Yes 1 LanKom LF-H41S Yes 1 Pulse H1102 Yes 1 Pulse (low cost) H1260 Yes 1 Transpower HB726 Yes 1 YCL LF-H41S Yes 1 Table 28. Qualified Single Port Magnetics Selection of Reference Crystal Chacteristics Value Units Frequency 25.00000 MHz Frequency tolerance (max) ±50 ppm Load capacitance (max) 20 pF Series resistance 25 Ω Table 29. Typical Reference Crystal Characteristics October 2008 85 M9999-020606

Micrel, Inc. KSZ8993M/ML Package Information 128-Pin PQFP Package MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL: +1 (408) 944-0800 FAX: +1 (408) 474 1000 WEB: http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. October 2008 86 M9999-020606