KSZ8841-16M/-32M Single-Port Ethernet MAC Controller with Non-PCI Interface Features Additional Features • Single Chip Ethernet Controller with IEEE 802.3u In addition to offering all of the features of a Layer 2 Support controller, the KSZ8841-16M/-32M offers: • Supports 10BASE-T/100BASE-TX • Dynamic Buffer Memory Scheme • Supports IEEE 802.3x Full-Duplex Flow Control - Essential for Applications such as Video over and Half-Duplex Backpressure Collision Flow IP where Image Jitter is Unacceptable Control • Flexible 8-bit, 16-bit, and 32-bit Generic Host Pro- • Supports Burst Data Transfers cessor Interfaces • 8 KB Internal Memory for RX/TX FIFO Buffers • Microchip LinkMD® Cable Diagnostic Capabilities • Early TX/RX Functions to Minimize Latency to Determine Cable Length, Diagnose Faulty Through the Device Cables, and Determine Distance to Fault • Optional to Use External Serial EEPROM Config- • Wake-on-LAN Functionality uration for Both KSZ8841-16MQL and KSZ8841- - Incorporates Magic Packet™, Network Link 32MQL State, and Wake-Up Frame Technology • S ingle 25MHz Reference Clock for Both PHY • HP Auto MDI-X™ Crossover with Disable/Enable and MAC Option Network Features • Ability to Transmit and Receive Frames up to • Fully Integrated to Comply with IEEE 802.3u 1916 bytes Standards Applications • 10BASE-T and 100BASE-TX Physical Layer Sup- port • Video Distribution Systems • A uto-Negotiation: 10/100Mbps Full- and Half- • High-End Cable, Satellite, and IP Set-Top Boxes Duplex • Video over IP • Adaptive Equalizer • Voice over IP (VoIP) and Analog Telephone • Baseline Wander Correction Adapters (ATA) Power Modes, Power Supplies, and Packaging • Industrial Control in Latency-Critical Applications • Motion Control • Single Power Supply (3.3V) with 5V Tolerant I/O Buffers • Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves) • Enhanced Power Management Feature with Power-Down Feature to Ensure Low Power Dissi- • Security and Surveillance Cameras pation During Device Idle Periods Markets • Comprehensive LED Indicator Support for Link, Activity, Full-/Half-Duplex, and 10/100 Speed (4 • Fast Ethernet LEDs) • Embedded Ethernet - User Programmable • Industrial Ethernet • Low-Power CMOS Design • Commercial Temperature Range: 0°C to +70°C • Industrial Temperature Range: –40°C to +85°C • Available in 128-Pin PQFP and 100-Ball LFBGA (128-Pin LQFP Optional)  2019 Microchip Technology Inc. D S00003147A-page 1

KSZ8841-16M/-32M TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. D S00003147A-page 2  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Table of Contents 1.0 Introduction .....................................................................................................................................................................................4 2.0 Pin Description and Configuration ...................................................................................................................................................5 3.0 Functional Description ..................................................................................................................................................................22 4.0 Register Descriptions ....................................................................................................................................................................37 5.0 Operational Characteristics ...........................................................................................................................................................75 6.0 Electrical Characteristics ...............................................................................................................................................................76 7.0 Timing Specifications ....................................................................................................................................................................77 8.0 Selection of Isolation Transformers ...............................................................................................................................................88 9.0 Package Outline ............................................................................................................................................................................89 Appendix A: Data Sheet Revision History ...........................................................................................................................................93 The Microchip Web Site ......................................................................................................................................................................94 Customer Change Notification Service ...............................................................................................................................................94 Customer Support ...............................................................................................................................................................................94 Product Identification System .............................................................................................................................................................95  2019 Microchip Technology Inc. D S00003147A-page 3

KSZ8841-16M/-32M 1.0 INTRODUCTION 1.1 General Description The KSZ8841-series single-port chip includes PCI and non-PCI CPU interfaces, and are available in 8-bit, 16-bit, and 32-bit bus designs. This data sheet describes the KSZ8841M-series of non-PCI CPU interface chips. For information on the KSZ8841 PCI CPU interface chips, refer to the KSZ8841P data sheet. The KSZ8841M is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, an 8-bit, 16-bit, and 32-bit generic host pro- cessor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 8 KB for both TX and RX directions in host buffer interface. The KSZ8841M is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature grade version of the KSZ8841M, the KSZ8841MVLI, also can be ordered. Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower power consumption. The KSZ8841M is designed using a low-power CMOS process that features a single 3.3V power supply with 5V tolerant I/O. It has an extensive feature set that offers management infor- mation base (MIB) counters and CPU control/data interfaces. The KSZ8841M includes a unique cable diagnostics feature called LinkMD®. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8841M supports Hewlett Packard (HP) Auto-MDIX, thereby eliminating the need to differentiate between straight or crossover cables in applications. FIGURE 1-1: SYSTEM BLOCK DIAGRAM 10/100 P1 HP Auto Base-T/TX Host MAC MDI/MDI-X PHY RXQ QMU 4KB DMA Non-PCI Channel TXQ CPU 4KB Embedded Processor Bus Interface Interface Unit Control Registers 8,16, or 32-bit Generic Host Interface MIB Counters LED P1 LED[3:0] Driver EEPROM Interface EEPROM I/F D S00003147A-page 4  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: PIN CONFIGURATION FOR KSZ8841-16 CHIP (8-/16-BIT) NCNCNCNCNCNCNCNCNCNCVDDIOVDDCDGNDNCBE0NBE1NNCNCA1A2A3A4A5VDDIODGNDA6A7A8A9A10A11A12A13A14A15RSTNX2X1 NC 1031021011009998979695949392919089888786858483828180797877767574737271706968676665 64 AGND NC 104 63 VDDAP NC 105 62 AGND NC 106 61 ISET DGND 107 60 NC VDDIO 108 59 NC NC 109 58 AGND D15 110 57 VDDA D14 111 56 NC D13 112 55 NC D12 113 54 AGND DD1101 111145 KSZ8841-16MQL 5532 NNCC D9 116 51 VDDARX D8 117 50 VDDATX D7 118 (Top View) 49 TXM1 D6 119 48 TXP1 D5 120 47 AGND D4 121 46 RXM1 D3 122 45 RXP1 DGND 123 44 NC DGND 124 43 VDDA VDDIO 125 42 AGND D2 126 41 NC D1 127 40 NC D0 128 39 AGND 1234567891011121314151617181920212223242526272829303132333435363738 TESTENSCANENP1LED2P1LED1P1LED0NCNCNCDGNDVDDIODYRTNNBCLKNCPMENSRDYNINTRNLDEVNRDNEECSARDYCYCLENNCDGNDVDDCOVLBUSNEEENP1LED3EEDOEESKEEDISWRAENWRNDGNDADSNPWRDNAGNDVDDA R NCNCNCNCVDDIOVDDCDGNDNCBE0NBE1NNCNCA1A2A3A4A5VDDIODGNDA6A7A8A9A10A11A12A13A14A15RSTNX2X1 9695949392919089888786858483828180797877767574737271706968676665 NC 97 64 AGND VVDDDDDGGGDDDDDDDDNNDDDNNNNNNNNNNNDDDDDDD1111I11IDCOD345DCCCCCCOCCC0012678941523 1111111111111111111111111111199000000000011111111112222222229821034567890123456789012345678 KSZ(T8o8p4 1V-i1e6wM)VL 66665555555555444444443333333443210987654321098753210934567864 RRATTVVNNANNVANNAVAVIANNDAANVPWSXXDGGDGGDDGGDXXCCCCCCCCGDGCDWERPMDPMDDDDSNNNNNNNNDTRN11NAAAA1ADDDDDD1DDADTPRNXX 1234567891011121314151617181920212223242526272829303132 TESTENSCANENP1LED2P1LED1P1LED0NCNCNCDGNDVDDIORDYRTNNBCLKNCPMENSRDYNINTRNLDEVNRDNEECSARDYCYCLENNCDGNDVDDCOVLBUSNEEENP1LED3EEDOEESKEEDISWRAEN  2019 Microchip Technology Inc. D S00003147A-page 5

KSZ8841-16M/-32M TABLE 2-1: S IGNALS Pin Pin Name Type Description Number Test Enable 1 TEST_EN I For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable 2 SCAN_EN I For normal operation, pull-down this pin to ground. Port 1 LED Indicators, defined as follows Chip Global Control Register: CGCR bit [15,9] [0, 0] Default [0, 1] P1LED3 — — P1LED2 Link/Activity 100Link/Activity P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex 3 P1LED2 4 P1LED1 OPU Reg. CGCR bit [15,9] 5 P1LED0 [1, 0] [1, 1] P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed — Note: Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- duplex); Speed = On (100BASE-T); Off (10BASE-T) Note: P1LED3 is pin 27. 6 NC OPU No connect. 7 NC OPU No connect. 8 NC OPU No connect. 9 DGND GND Digital ground. 3.3V digital V input power supply for IO with well decoupling capaci- 10 VDDIO P DDIO tors. Ready Return Not: For VLBus-like mode: Asserted by the host to complete synchronous 11 RDYRTNN IPD read cycles. If the host doesn’t connect to this pin, assert this pin. For burst mode (32-bit interface only): Host drives this pin low to signal waiting states. Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is 12 BCLK IPD 5 0MHz. This pin should be tied Low or unconnected if it is in asynchronous mode. 13 NC IPU No connect. Power Management Event Not When asserted (Low), this signal indicates that a power management 14 PMEN OPU event has occurred in the system when a wake-up signal is detected by KSZ8841M. D S00003147A-page 6  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. 15 SRDYN OPU For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8841M drives this pin low to signal wait states. Interrupt 16 INTRN OPD Active Low signal to host CPU to indicate an interrupt status bit is set, t his pin need an external 4.7kΩ pull-up resistor. Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 17 LDEVN OPD decode to the KSZ8841M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not 18 RDN IPD Asynchronous read strobe, active-low. EEPROM Chip Select 19 EECS OPU This signal is used to select an external EEPROM device. Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus 20 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. this pin n eed an external 4.7kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this pin follows the addressing cycle 21 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write cycles. 22 NC OPD No connect. 23 DGND GND Digital IO ground. 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. It is recommended this pin should be connected to 3.3V power rail by a 24 VDDCO P 100Ω resistor for the internal LDO application Note: Internally generated power voltage. Do not connect an external power supply to this pin. This pin is used for connecting external filter (Ferrite bead and capacitors). VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. 25 VLBUSN IPD Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like burst mode. EEPROM Enable 26 EEEN IPD EEPROM is enabled and connected when this pin is pull-up. EEPROM is disabled when this pin is pull-down or no connect. Port 1 LED indicator 27 P1LED3 OPD See the description in pins 3, 4, and 5. EEPROM Data Out 28 EEDO OPD This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25M Hz) or 800ns 29 EESK OPD (OBCR[1:0]=00 on-chip bus speed @ 1 25MHz) serial output clock cycle to load configuration data from the serial EEPROM.  2019 Microchip Technology Inc. D S00003147A-page 7

KSZ8841-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number EEPROM Data In This pin is connected to DO output of the serial EEPROM when EEEN is pull-up. 30 EEDI IPD This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM). Synchronous Write/Read 31 SWR IPD Write/Read signal for synchronous bus accesses. Write cycles when high and Read cycles when low. Address Enable 32 AEN IPU Address qualifier for the address decoding, active-low. Write Strobe Not 33 WRN IPD Asynchronous write strobe, active-low. 34 DGND GND Digital IO ground Address Strobe Not 35 ADSN IPD For systems that require address latching, the rising edge of ADSN indi- cates the latching moment of A15-A1 and AEN. Full-chip power-down. Active-Low 36 PWRDN IPU (Low = Power down; High or floating = Normal operation). 37 AGND GND Analog ground 1.2V analog V input power supply from VDDCO (pin 24) through 38 VDDA P DD external Ferrite bead and capacitor. 39 AGND GND Analog ground 40 NC — No Connect 41 NC — No Connect 42 AGND GND Analog ground 1.2V analog V input power supply from VDDCO (pin 24) through 43 VDDA P DD external Ferrite bead and capacitor. 44 NC — No Connect 45 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential) 46 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential) 47 AGND GND Analog ground 48 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential) 49 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential) 50 VDDATX P 3.3V analog V input power supply with well decoupling capacitors. DD 51 VDDARX P 3.3V analog V input power supply with well decoupling capacitors. DD 52 NC — No Connect 53 NC — No Connect 54 AGND GND Analog ground 55 NC — No Connect 56 NC — No Connect 1.2 analog V input power supply from VDDCO (pin 24) through exter- 57 VDDA P DD nal Ferrite bead and capacitor. 58 AGND GND Analog ground 59 NC IPU No connect 60 NC IPU No connect D S00003147A-page 8  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number Set physical transmits output current. 61 ISET O P ull-down this pin with a 3.01kΩ 1% resistor to ground. 62 AGND GND Analog ground 1.2V analog V for PLL input power supply from VDDCO (pin 24) 63 VDDAP P DD through external Ferrite bead and capacitor. 64 AGND GND Analog ground 65 X1 I 2 5MHz crystal or oscillator clock connection. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to 66 X2 O a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock requirement is ±5 0ppm for either crystal or oscillator. Reset Not 67 RSTN IPU Hardware reset pin (active-low). This reset input is required minimum of 1 0ms low after stable supply voltage 3.3V. 68 A15 I Address 15 69 A14 I Address 14 70 A13 I Address 13 71 A12 I Address 12 72 A11 I Address 11 73 A10 I Address 10 74 A9 I Address 9 75 A8 I Address 8 76 A7 I Address 7 77 A6 I Address 6 78 DGND GND Digital IO ground 3.3V digital V input power supply for IO with well decoupling capaci- 79 VDDIO P DDIO tors. 80 A5 I Address 5 81 A4 I Address 4 82 A3 I Address 3 83 A2 I Address 2 84 A1 I Address 1 85 NC I No Connect 86 NC I No Connect Byte Enable 1 Not, Active-low for Data byte 1 enable (don’t care in 8-bit 87 BE1N I bus mode). Byte Enable 0 Not, Active-low for Data byte 0 enable (there is an internal 88 BE0N I inverter enabled and connected to the BE1N for 8-bit bus mode). 89 NC I No Connect 90 DGND GND Digital core ground 1.2V digital core V input power supply from VDDCO (pin 24) through 91 VDDC P DD external Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capaci- 92 VDDIO P DDIO tors. 93 NC I No Connect 94 NC I No Connect 95 NC I No Connect  2019 Microchip Technology Inc. D S00003147A-page 9

KSZ8841-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number 96 NC I No Connect 97 NC I No Connect 98 NC I No Connect 99 NC I No Connect 100 NC I No Connect 101 NC I No Connect 102 NC I No Connect 103 NC I No Connect 104 NC I No Connect 105 NC I No Connect 106 NC I No Connect 107 DGND GND Digital IO ground 3.3V digital V input power supply for IO with well decoupling capac- 108 VDDIO P DDIO itors. 109 NC I No Connect 110 D15 I/O Data 15 111 D14 I/O Data 14 112 D13 I/O Data 13 113 D12 I/O Data 12 114 D11 I/O Data 11 115 D10 I/O Data 10 116 D9 I/O Data 9 117 D8 I/O Data 8 118 D7 I/O Data 7 119 D6 I/O Data 6 120 D5 I/O Data 5 121 D4 I/O Data 4 122 D3 I/O Data 3 123 DGND GND Digital IO ground 124 DGND GND Digital core ground 3.3V digital V input power supply for IO with well decoupling capaci- 125 VDDIO P DDIO tors. 126 D2 I/O Data 2 127 D1 I/O Data 1 128 D0 I/O Data 0 Note 2-1 P = power supply; GND = ground; I = input; O = output I/O = bi-directional IPU/O = Input with internal pull-up during reset; output pin otherwise. IPU = Input with internal pull-up. IPD = Input with internal pull-down. OPU = Output with internal pull-up. OPD = Output with internal pull-down. D S00003147A-page 10  2019 Microchip Technology Inc.

KSZ8841-16M/-32M FIGURE 2-2: BALL CONFIGURATION FOR KSZ8841-16 CHIP (8/16-BIT) TABLE 2-2: BALL DESCRIPTION FOR KSZ8841-16 CHIP ( 8/16-BIT) Ball Ball Name Type Description Number Test Enable E8 TEST_EN I For normal operation, pull-down this ball to ground. Scan Test Scan Mux Enable D10 SCAN_EN I For normal operation, pull-down this ball to ground.  2019 Microchip Technology Inc. D S00003147A-page 11

KSZ8841-16M/-32M TABLE 2-2: BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED) Ball Ball Name Type Description Number Port 1 LED Indicators, defined as follows Switch Global Control Register 5: SGCR bit [15,9] [0, 0] Default [0, 1] P1LED3 — — P1LED2 Link/Activity 100Link/Activity P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex A10 P1LED2 B10 P1LED1 OPU Reg. SGCR bit [15,9] C10 P1LED0 [1, 0] [1, 1] P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed — Note: Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- duplex); Speed = On (100BASE-T); Off (10BASE-T) Note: P1LED3 is ball A4. Ready Return Not: D9 RDYRTNN IPD For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the host doesn’t connect to this ball, assert this ball. Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is A8 BCLK IPD 5 0MHz. This ball should be tied Low or unconnected if it is in asynchronous mode. Power Management Event Not When asserted (Low), this signal indicates that a power management D8 PMEN OPU event has occurred in the system when a wake-up signal is detected by KSZ8841M. Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and B8 SRDYN OPU VLBus-like extend accesses. For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. Interrupt C8 INTRN OPD Active-low signal to host CPU to indicate an interrupt status bit is set, t his ball need an external 4.7kΩ pull-up resistor. Local Device Not Active-low output signal, asserted when AEN is Low and A15-A4 decode A7 LDEVN OPD to the KSZ8841M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not B7 RDN IPD Asynchronous read strobe, active-low. C7 EECS OPU EEPROM Chip Select D S00003147A-page 12  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-2: BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED) Ball Ball Name Type Description Number Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus A6 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. This ball n eeds an external 4.7kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this ball follows the addressing cycle B6 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this ball stays High for read cycles and Low for write cycles. VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. A5 VLBUSN IPD Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like burst mode. EEPROM Enable B5 EEEN IPD EEPROM is enabled and connected when this ball is pull-up. EEPROM is disabled when this ball is pull-down or no connect. Port 1 LED indicator A4 P1LED3 OPD See the description in balls A10, B10, and C10. EEPROM Data Out B4 EEDO OPD This ball is connected to DI input of the serial EEPROM. EEPROM Serial Clock A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25M Hz) or 800ns A3 EESK OPD (OBCR[1:0]=00 on-chip bus speed @ 1 25MHz) serial output clock cycle to load configuration data from the serial EEPROM. EEPROM Data In This ball is connected to DO output of the serial EEPROM when EEEN is pull-up. B3 EEDI IPD This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don’t care for 32-bit bus mode when EEEN is pull-down (with- out EEPROM). Synchronous Write/Read C3 SWR IPD Write/Read signal for synchronous bus accesses. Write cycles when high and Read cycles when low. Address Enable A2 AEN IPU Address qualifier for the address decoding, active-low. Write Strobe Not B2 WRN IPD Asynchronous write strobe, active-low. Address Strobe Not A1 ADSN IPD For systems that require address latching, the rising edge of ADSN indi- cates the latching moment of A15-A1 and AEN. Full-chip power-down. Low = Power down; High or floating = Normal B1 PWRDN IPU operation. C1 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential) C2 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential) D1 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential) D2 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential) Test input 2 H2 TEST2 IPU For normal operation, left this ball open. Set physical transmits output current. G3 ISET O P ull-down this ball with a 3.01kΩ 1% resistor to ground.  2019 Microchip Technology Inc. D S00003147A-page 13

KSZ8841-16M/-32M TABLE 2-2: BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED) Ball Ball Name Type Description Number J1 X1 I 2 5MHz crystal or oscillator clock connection. Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects K1 X2 O to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock requirement is  50ppm for either crystal or oscillator. Hardware reset ball (active Low). This reset input is required minimum of J2 RSTN IPU 1 0ms low after stable supply voltage 3.3V. K2 A15 I Address 15 K3 A14 I Address 14 J3 A13 I Address 13 H3 A12 I Address 12 K4 A11 I Address 11 J4 A10 I Address 10 H4 A9 I Address 9 K5 A8 I Address 8 J5 A7 I Address 7 H5 A6 I Address 6 K6 A5 I Address 5 J6 A4 I Address 4 H6 A3 I Address 3 K7 A2 I Address 2 J7 A1 I Address 1 Byte Enable 1 Not, Active-low for Data byte 1 enable (don’t care in 8-bit H7 BE1N I bus mode). Byte Enable 0 Not, Active-low for Data byte 0 enable (there is an internal K8 BE0N I inverter enabled and connected to the BE1N for 8-bit bus mode). K9 D15 I/O Data 15 K10 D14 I/O Data 14 J9 D13 I/O Data 13 J10 D12 I/O Data 12 J8 D11 I/O Data 11 H9 D10 I/O Data 10 H10 D9 I/O Data 9 H8 D8 I/O Data 8 G9 D7 I/O Data 7 G10 D6 I/O Data 6 G8 D5 I/O Data 5 F9 D4 I/O Data 4 F10 D3 I/O Data 3 F8 D2 I/O Data 2 E9 D1 I/O Data 1 E10 D0 I/O Data 0 D S00003147A-page 14  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-2: BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED) Ball Ball Name Type Description Number 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output ball provides power to all VDDC/VDDA balls. It is rec- ommended this ball should be connected to 3.3V power rail by a 100Ω C4 VDDCO P resistor for the internal LDO application. Note: Internally generated power voltage. Do not connect an external power supply to this ball. This ball is used for connecting external filter (Ferrite bead and capacitors). 1.2V digital core V input power supply from VDDCO (ball C4) through C5 VDDC P DD external Ferrite bead and capacitor. 1.2V analog V input power supply from VDDCO (ball C4) through D3, E3, F3 VDDA P DD external Ferrite bead and capacitor. E1 VDDATX P 3.3V analog V input power supply with well decoupling capacitors. DD E2 VDDARX P 3.3V analog V input power supply with well decoupling capacitors. DD D7, E7, F7, 3.3V digital V input power supply for IO with well decoupling capac- G4, G5, VDDIO P DDIO itors. G6, G7 D4, D5, D6, E4, E5, E6, GND GND All digital and analog grounds F4, F5, F6 H1, A9, B9, C9, C6, F2, NC I/O No Connect F1, G2, G1  2019 Microchip Technology Inc. D S00003147A-page 15

KSZ8841-16M/-32M FIGURE 2-3: PIN CONFIGURATION FOR KSZ8841-32 CHIP (32-BIT) D21D22D23D24D25D26D27D28D29D30VDDIOVDDCDGNDD31BE0NBE1NBE2NBE3NA1A2A3A4A5VDDIODGNDA6A7A8A9A10A11A12A13A14A15RSTNX2X1 D20 1031021011009998979695949392919089888786858483828180797877767574737271706968676665 64 AGND D19 104 63 VDDAP D18 105 62 AGND D17 106 61 ISET DGND 107 60 NC VDDIO 108 59 NC D16 109 58 AGND D15 110 57 VDDA D14 111 56 NC D13 112 55 NC DD1112 111134 KSZ8841-32MQL 5543 NAGCND D10 115 52 NC D9 116 51 VDDARX D8 117 (Top View) 50 VDDATX D7 118 49 TXM1 D6 119 48 TXP1 D5 120 47 AGND D4 121 46 RXM1 D3 122 45 RXP1 DGND 123 44 NC DGND 124 43 VDDA VDDIO 125 42 AGND D2 126 41 NC D1 127 40 NC D0 128 39 AGND 1234567891011121314151617181920212223242526272829303132333435363738 TESTENSCANENP1LED2P1LED1P1LED0NCNCNCDGNDVDDIORDYRTNNBCLKDATACSNPMENSRDYNINTRNLDEVNRDNEECSARDYCYCLENNCDGNDVDDCOVLBUSNEEENP1LED3EEDOEESKEEDISWRAENWRNDGNDADSNPWRDNAGNDVDDA D27D28D29D30VDDIOVDDCDGNDD31BE0NBE1NBE2NBE3NA1A2A3A4A5VDDIODGNDA6A7A8A9A10A11A12A13A14A15RSTNX2X1 9695949392919089888786858483828180797877767574737271706968676665 D26 97 64 AGND D25 98 63 VDDAP D24 99 62 AGND D23 100 61 ISET D22 101 60 NC D21 102 59 NC D20 103 58 AGND D19 104 57 VDDA D18 105 56 NC D17 106 55 NC DGND 107 54 AGND VDDIO 108 53 NC D16 109 52 NC D15 110 KSZ8841-32MVL 51 VDDARX D14 111 50 VDDATX D13 112 49 TXM1 D12 113 48 TXP1 D11 114 (Top View) 47 AGND D10 115 46 RXM1 D9 116 45 RXP1 D8 117 44 NC D7 118 43 VDDA D6 119 42 AGND D5 120 41 NC D4 121 40 NC D3 122 39 AGND DGND 123 38 VDDA DGND 124 37 AGND VDDIO 125 36 PWRDN D2 126 35 ADSN D1 127 34 DGND D0 128 33 WRN 1234567891011121314151617181920212223242526272829303132 TESTENSCANENP1LED2P1LED1P1LED0NCNCNCDGNDVDDIORDYRTNNBCLKDATACSNPMENSRDYNINTRNLDEVNRDNEECSARDYCYCLENNCDGNDVDDCOVLBUSNEEENP1LED3EEDOEESKEEDISWRAEN D S00003147A-page 16  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-3: PIN DESCRIPTION FOR KSZ8841-32 CHIP ( 32-BIT) Pin Pin Name Type Description Number Test Enable 1 TEST_EN I For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable 2 SCAN_EN I For normal operation, pull-down this pin to ground. Port 1 LED Indicators, defined as follows Chip Global Control Register: CGCR bit [15,9] [0, 0] Default [0, 1] P1LED3 — — P1LED2 Link/Activity 100Link/Activity P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex 3 P1LED2 4 P1LED1 OPU Reg. CGCR bit [15,9] 5 P1LED0 [1, 0] [1, 1] P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed — Note: Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- duplex); Speed = On (100BASE-T); Off (10BASE-T) Note: P1LED3 is pin 27. 6 NC OPU No connect. 7 NC OPU No connect. 8 NC OPU No connect. 9 DGND GND Digital ground. 3.3V digital V input power supply for IO with well decoupling capaci- 10 VDDIO P DDIO tors. Ready Return Not: For VLBus-like mode: Asserted by the host to complete synchronous 11 RDYRTNN IPD read cycles. If the host doesn’t connect to this pin, assert this pin. For burst mode (32-bit interface only): Host drives this pin low to signal waiting states. Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is 12 BCLK IPD 5 0MHz. This pin should be tied Low or unconnected if it is in asynchronous mode. DATA Chip Select Not (For KSZ8841-32 Mode only) Chip select signal for QMU data register (QDRH, QDRL), active Low. 13 DATACSN IPU When DATACSN is Low, the data path can be accessed regardless of the value of AEN, A15-A1, and the content of the BANK select register. Power Management Event Not When asserted (Low), this signal indicates that a power management 14 PMEN OPU event has occurred in the system when a wake-up signal is detected by KSZ8841M.  2019 Microchip Technology Inc. D S00003147A-page 17

KSZ8841-16M/-32M TABLE 2-3: PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED) Pin Pin Name Type Description Number Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. 15 SRDYN OPU For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8841M drives this pin low to signal wait states. Interrupt 16 INTRN OPD Active-low signal to host CPU to indicate an interrupt status bit is set, t his pin need an external 4.7kΩ pull-up resistor Local Device Not Active-low output signal, asserted when AEN is Low and A15-A4 decode 17 LDEVN OPD to the KSZ8841M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not 18 RDN IPD Asynchronous read strobe, active-low. EEPROM Chip Select 19 EECS OPU This signal is used to select an external EEPROM device. Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus 20 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. this pin n eed an external 4.7kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this pin follows the addressing cycle 21 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write cycles. 22 NC OPD No Connect 23 DGND GND Digital IO ground 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. It is recommended this ball should be connected to 3.3V power rail by a 24 VDDCO P 100Ω resistor for the internal LDO application. Note: Internally generated power voltage. Do not connect an external power supply to this pin. This pin is used for connecting external filter (Ferrite bead and capacitors). VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. 25 VLBUSN IPD Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like burst mode. EEPROM Enable 26 EEEN IPD EEPROM is enabled and connected when this pin is pull-up. EEPROM is disabled when this pin is pull-down or no connect. Port 1 LED indicator 27 P1LED3 OPD See the description in pins 3, 4, and 5. EEPROM Data Out 28 EEDO OPD This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25M Hz) or 800ns 29 EESK OPD (OBCR[1:0]=00 on-chip bus speed @ 1 25MHz) serial output clock cycle to load configuration data from the serial EEPROM. D S00003147A-page 18  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-3: PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED) Pin Pin Name Type Description Number EEPROM Data In This pin is connected to DO output of the serial EEPROM when EEEN is pull-up. 30 EEDI IPD This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM). Synchronous Write/Read 31 SWR IPD Write/Read signal for synchronous bus accesses. Write cycles when high and Read cycles when low. Address Enable 32 AEN IPU Address qualifier for the address decoding, active-low. Write Strobe Not 33 WRN IPD Asynchronous write strobe, active-low. 34 DGND GND Digital IO ground Address Strobe Not 35 ADSN IPD For systems that require address latching, the rising edge of ADSN indi- cates the latching moment of A15-A1 and AEN. Full-chip power-down. Active-low 36 PWRDN IPU (Low = Power down; High or floating = Normal operation). 37 AGND GND Analog ground 1.2V analog V input power supply from VDDCO (pin 24) through 38 VDDA P DD external Ferrite bead and capacitor. 39 AGND GND Analog ground 40 NC — No Connect 41 NC — No Connect 42 AGND GND Analog ground 1.2V analog V input power supply from VDDCO (pin 24) through 43 VDDA P DD external Ferrite bead and capacitor. 44 NC — No Connect 45 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential) 46 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential) 47 AGND GND Analog ground 48 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential) 49 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential) 50 VDDATX P 3.3V analog V input power supply with well decoupling capacitors. DD 51 VDDARX P 3.3V analog V input power supply with well decoupling capacitors. DD 52 NC — No Connect 53 NC — No Connect 54 AGND GND Analog ground 55 NC — No Connect 56 NC — No Connect 1.2 analog V input power supply from VDDCO (pin 24) through exter- 57 VDDA P DD nal Ferrite bead and capacitor. 58 AGND GND Analog ground 59 NC IPU No connect 60 NC IPU No connect  2019 Microchip Technology Inc. D S00003147A-page 19

KSZ8841-16M/-32M TABLE 2-3: PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED) Pin Pin Name Type Description Number Set physical transmits output current. 61 ISET O P ull-down this pin with a 3.01kΩ 1% resistor to ground. 62 AGND GND Analog ground 1.2V analog V for PLL input power supply from VDDCO (pin 24) 63 VDDAP P DD through external Ferrite bead and capacitor. 64 AGND GND Analog ground 65 X1 I 2 5MHz crystal or oscillator clock connection. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to 66 X2 O a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock requirement is ±5 0ppm for either crystal or oscillator. Reset Not 67 RSTN IPU Hardware reset pin (active-low). This reset input is required minimum of 1 0ms low after stable supply voltage 3.3V. 68 A15 I Address 15 69 A14 I Address 14 70 A13 I Address 13 71 A12 I Address 12 72 A11 I Address 11 73 A10 I Address 10 74 A9 I Address 9 75 A8 I Address 8 76 A7 I Address 7 77 A6 I Address 6 78 DGND GND Digital IO ground 3.3V digital V input power supply for IO with well decoupling capaci- 79 VDDIO P DDIO tors. 80 A5 I Address 5 81 A4 I Address 4 82 A3 I Address 3 83 A2 I Address 2 84 A1 I Address 1 85 BE3N I Byte Enable 3 Not, Active-low for Data byte 3 enable 86 BE2N I Byte Enable 2 Not, Active-low for Data byte 2 enable 87 BE1N I Byte Enable 1 Not, Active-low for Data byte 1 enable 88 BE0N I Byte Enable 0 Not, Active-low for Data byte 0 enable 89 D31 I/O Data 31 90 DGND GND Digital core ground 1.2V digital core V input power supply from VDDCO (pin 24) through 91 VDDC P DD external Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capaci- 92 VDDIO P DDIO tors. 93 D30 I/O Data 30 94 D29 I/O Data 29 95 D28 I/O Data 28 96 D27 I/O Data 27 97 D26 I/O Data 26 D S00003147A-page 20  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 2-3: PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED) Pin Pin Name Type Description Number 98 D25 I/O Data 25 99 D24 I/O Data 24 100 D23 I/O Data 23 101 D22 I/O Data 22 102 D21 I/O Data 21 103 D20 I/O Data 20 104 D19 I/O Data 19 105 D18 I/O Data 18 106 D17 I/O Data 17 107 DGND GND Digital IO ground 3.3V digital V input power supply for IO with well decoupling capac- 108 VDDIO P DDIO itors. 109 D16 I/O Data 16 110 D15 I/O Data 15 111 D14 I/O Data 14 112 D13 I/O Data 13 113 D12 I/O Data 12 114 D11 I/O Data 11 115 D10 I/O Data 10 116 D9 I/O Data 9 117 D8 I/O Data 8 118 D7 I/O Data 7 119 D6 I/O Data 6 120 D5 I/O Data 5 121 D4 I/O Data 4 122 D3 I/O Data 3 123 DGND GND Digital IO ground 124 DGND GND Digital core ground 3.3V digital V input power supply for IO with well decoupling capaci- 125 VDDIO P DDIO tors. 126 D2 I/O Data 2 127 D1 I/O Data 1 128 D0 I/O Data 0 Legend: P = Power supply, GND = Ground I/O = Bi-directional, I = Input, O = Output. IPD = Input with internal pull-down. IPU = Input with internal pull-up. OPD = Output with internal pull-down. OPU = Output with internal pull-up.  2019 Microchip Technology Inc. D S00003147A-page 21

KSZ8841-16M/-32M 3.0 FUNCTIONAL DESCRIPTION The KSZ8841M is a single-chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8841M via an 8-bit, 16-bit, or 32-bit host bus interface. The KSZ8841M is fully compliant to IEEE802.3u standards. 3.1 Power Management 3.1.1 POWER DOWN The KSZ8841M features a port power-down mode. To save power, the user can power-down the port that is not in use by setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these regis- ters. In addition, there is a full chip power-down mode PWRDN (pin 36). When this pin is pulled-down, the entire chip powers down. Transitioning this pin from pull-down to pull-up results in a power up and chip reset. 3.1.2 WAKE-ON-LAN Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. A wake-up event is a request for hardware and/or software external to the network device to put the system into a pow- ered state (working). A wake-up signal is caused by: • Detection of a change in the network link state • Receipt of a network wake-up frame • Receipt of a Magic Packet There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own way. 3.1.3 LINK CHANGE Link status wake events are useful to indicate a change in the network’s availability, especially when this change may impact the level at which the system should re-enter the sleeping state. For example, a change from link off to link on may trigger the system to re-enter sleep at a higher level (D2 versus D3) so that wake frames can be detected. Con- versely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2) since the network is not currently available. References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI. For more information, refer to the PCI specification. 3.1.4 WAKE-UP PACKET Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame. The KSZ8841M supports up to four users defined wake-up frames as below: 1. Wake-up frame 0 is defined in registers 0x00 - 0x0A of Bank 4 and is enabled by bit 0 in wakeup frame control register. 2. Wake-up frame 1 is defined in registers 0x00 - 0x0A of Bank 5 and is enabled by bit 1 in wakeup frame control register. 3. Wake-up frame 2 is defined in registers 0x00 - 0x0A of Bank 6 and is enabled by bit 2 in wakeup frame control register. 4. Wake-up frame 4 is defined in registers 0x00 - 0x0A of Bank 7 and is enabled by bit 3 in wakeup frame control register. D S00003147A-page 22  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 3.1.5 MAGIC PACKET Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the LAN controller receives a Magic Packet frame, it will alert the system to wake up. Magic Packet is a standard feature integrated into the KSZ8841M. The controller implements multiple advanced power- down modes including Magic Packet to conserve power and operate more efficiently. Once the KSZ8841M has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address (SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address and CRC. The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchro- nization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened. Example: If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scan- ning for the data sequence (assuming an Ethernet frame): DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - MISC - CRC. There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the frame’s destination. If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8841M controller detects the data sequence, however, it then alerts the PC’s power management circuitry (assert the PMEN pin) to wake up the system. 3.2 Physical Layer Transceiver 3.2.1 100BASE-TX TRANSMIT The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 1% 3 .01kΩ resistor for the 1:1 transformer ratio sets the output current. The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE- TX driver. 3.2.2 100BASE-TX RECEIVE The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on com- parisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.  2019 Microchip Technology Inc. D S00003147A-page 23

KSZ8841-16M/-32M Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/ 5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC. 3.2.3 PLL CLOCK SYNTHESIZER (RECOVERY) The internal PLL clock synthesizer generates 1 25MHz, 62.5MHz, 41.66MHz, and 2 5MHz clocks by setting the on- chip bus speed control register for KSZ8841M system timing. These internal clocks are generated from an external 2 5MHz crystal or oscillator. 3.2.4 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter. 3.2.5 10BASE-T TRANSMIT The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.4V amplitude. The harmonic contents a re at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 3.2.6 10BASE-T RECEIVE On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 4 00mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8841M decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. 3.2.7 MDI/MDI-X AUTO CROSSOVER To eliminate the need for crossover cables between similar devices, the KSZ8841M supports HP-Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the KSZ8841M device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers. The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in T able3-1. TABLE 3-1: MDI/MDI-X PIN DEFINITIONS MDI MDI-X RJ-45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD– 2 RD– 3 RD+ 3 TD+ 6 RD– 6 TD– D S00003147A-page 24  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 3.2.7.1 Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. F igure3-1 depicts a typical straight cable connection between a NIC card (MDI) and a switch or hub (MDI-X). FIGURE 3-1: TYPICAL STRAIGHT CABLE CONNECTION 10/100 Ethernet 10/100 Ethernet Media Dependent Interface Media Dependent Interface 1 1 Transmit Pair Receive Pair 2 2 Straight 3 3 Cable 4 4 Receive Pair Transmit Pair 5 5 6 6 7 7 8 8 Modular Connector Modular Connector (RJ-45) (RJ-45) NIC HUB (Repeater or Switch) 3.2.7.2 Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. F igure3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). FIGURE 3-2: TYPICAL CROSSOVER CABLE CONNECTION 10/100 Ethernet 10/100 Ethernet Media Dependent Interface Media Dependent Interface 1 Crossover 1 Receive Pair Cable Receive Pair 2 2 3 3 4 4 Transmit Pair Transmit Pair 5 5 6 6 7 7 8 8 Modular Connector (RJ-45) Modular Connector (RJ-45) HUB HUB (Repeater or Switch) (Repeater or Switch)  2019 Microchip Technology Inc. D S00003147A-page 25

KSZ8841-16M/-32M 3.2.8 AUTO-NEGOTIATION The KSZ8841M conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port to oper- ate at either 10BASE-T or 100BASE-TX. Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported or the link partner to the KSZ8841M is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The link up process is shown in F igure3-3. FIGURE 3-3: AUTO-NEGOTIATION AND PARALLEL OPERATION START AUTO-NEGOTIATION PARALLEL FORCE LINK SETTING NO OPERATION YES BYPASS AUTO-NEGOTIATION ATTEMPT AUTO- LISTEN FOR 100BASE-TX LISTEN FOR 10BASE-T AND SET LINK MODE NEGOTIATION IDLES LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET D S00003147A-page 26  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 3.2.9 LINKMD® CABLE DIAGNOSTICS The KSZ8841M LinkMD® uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling prob- lems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable digital format in register P1VCT[8:0]. Note that cable diagnostics are only valid for copper connections. Fiber-optic operation is not supported. 3.2.9.1 Access LinkMD is initiated by accessing register P1VCT, the LinkMD Control/Status register, in conjunction with register P1CR4, the 100BASE-TX PHY Controller register. 3.2.9.2 Usage LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to P1CR4[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic test enable bit, P1VCT[15], is set to ‘1’ to start the test on this pair. When bit P1VCT[15] returns to ‘0’, the test is complete. The test result is returned in bits P1VCT[14:13] and the distance is returned in bits P1VCT[8:0]. The cable diagnostic test results are as follows: 00 = Valid test, normal condition 01 = Valid test, open circuit in cable 10 = Valid test, short circuit in cable 11 = Invalid test, LinkMD failed If P1VCT[14:13]=11, this indicates an invalid test, and occurs when the KSZ8841M is unable to shut down the link part- ner. In this instance, the test is not run, as it is not possible for the KSZ8841M to determine if the detected signal is a reflection of the signal generated or a signal from another source. Cable distance can be approximated by the following formula: P1VCT[8:0] x 0.4m for port 1 cable distance This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that var- ies significantly from the norm. 3.2.10 MEDIA ACCESS CONTROL (MAC) OPERATION The KSZ8841M strictly abides by IEEE 802.3 standards to maximize compatibility. 3.2.10.1 Inter Packet Gap (IPG) If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive pack- ets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense (CRS) to the next transmit packet. 3.2.10.2 Back-Off Algorithm The KSZ8841M implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16 collisions, the packet is dropped. 3.2.10.3 Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. 3.2.10.4 Flow Control The KSZ8841M supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8841M receives a pause control frame, the KSZ8841M will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow controlled), only flow control packets from the KSZ8841M are transmitted.  2019 Microchip Technology Inc. D S00003147A-page 27

KSZ8841-16M/-32M On the transmit side, the KSZ8841M has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources. The KSZ8841M issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8841M sends out the another flow control frame (Xon, or transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. 3.2.10.5 Half-Duplex Backpressure A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation condi- tions are the same as in full-duplex mode. If backpressure is required, the KSZ8841M sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8841M dis- continues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other sta- tions from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are trans- mitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is gener- ated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet recep- tion. 3.2.10.6 Clock Generator The X1 and X2 pins are connected to a 2 5MHz crystal. X1 can also serve as the connector to a 3.3V, 2 5MHz oscillator (as described in the pin description). The bus interface unit (BIU) uses BCLK (Bus Clock) for synchronous accesses. The maximum frequency is 5 0MHz for VLBus-like and EISA-like slave direct memory access (DMA). 3.2.11 BUSINESS INTERFACE UNIT (BIU) The BIU host interface is a generic bus interface, designed to communicate with embedded processors. The use of glue logic may be required when it talks to various standard buses and processors. 3.2.11.1 Supported Transfers In terms of transfer type, the BIU can support two transfers: asynchronous transfer and synchronous transfer. To support these transfers (asynchronous and synchronous), the BIU provides three groups of signals: • Synchronous signals • Asynchronous signals • Common signals are used for both synchronous and asynchronous transfers. Because both synchronous and asynchronous signals are independent of each other, synchronous transfer and asyn- chronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of common signals). 3.2.11.2 Physical Data Bus Size The BIU supports an 8-bit, 16-bit, or 32-bit host standard data bus. Depending on the size of the physical data bus, the KSZ8841M supports 8-bit, 16-bit, or 32-bit data transfers For example, For a 32-bit system/host data bus, the KSZ8841M allows an 8-bit, 16-bit, and 32-bit data transfer (KSZ8841-32MQL). For a 16-bit system/host data bus, the KSZ8841M allows an 8-bit and 16-bit data transfer (KSZ8841-16MQL). For an 8-bit system/host data bus, the KSZ8841M only allows an 8-bit data transfer (KSZ8841-16MQL). The KSZ8841M does not support internal data byte-swap but it does support internal data word-swap. This means that the system/host data bus HD[7:0] must connect to both D[7:0] and D[15:8] for an 8-bit data bus interface. For a 16-bit data bus, the system/host data bus HD[15:8] and HD[7:0] only need to connect to D[15:8] and D[7:0] respectively, and there is no need to connect HD[15:8] and HD[7:0] to D[31:24] and D[23:16]. T able3-2 describes the BIU signal grouping. D S00003147A-page 28  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 3-2: BUS INTERFACE UNIT SIGNAL GROUPING Signal Type Function Common Signals A[15:1] I Address Address Enable AEN I Address Enable asserted indicates memory address on the bus for DMA access and because the device is an I/O device, address decoding is only enabled when AEN is Low. Byte Enable BE0N BE1N BE2N BE3N Description 0 0 0 0 32-bit access 0 0 1 1 Lower 16-bit (D[15:0]) access 1 1 0 0 Higher 16-bit (D[31:16]) access BE3N, 0 1 1 1 Byte 0 (D[7:0]) access BE2N, I BE1N, 1 0 1 1 Byte 1 (D[15:8]) access BE0N 1 1 0 1 Byte 2 (D[23:16]) access 1 1 1 0 Byte 3 (D[31:24]) access Note 1: BE3N, BE2N, BE1N, and BE0N are ignored when DATACSN is low because 32-bit transfers are assumed. Note 2: BE2N and BE3N are valid only for the KSZ8841-32 mode, and are No Connect for the KSZ8841-16 mode. Data D[31:16] I/O For KSZ8841M-32 mode only. Data D[15:0] I/O For both KSZ8841-32 and KSZ8841-16 modes Address Strobe ADSN I The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N. Local Device LDEVN O This signal is a combinatorial decode of AEN and A[15:4]. This A[15:4] is used to compare against the Base Address Register. Data Register Chip Select (For KSZ8841-32MQL Mode only) This signal is used for central decoding architecture (mostly for embedded application). When DATACSN I asserted, the device’s local decoding logic is ignored and the 32-bit access to QMU Data Register is assumed. INTR O Interrupt Synchronous Transfer Signals VLBUS VLBUSN I VLBUSN = 0, VLBus-like cycle. VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait state) CYCLEN CYCLEN I For VLBus-like access: used to sample SWR when asserted. For burst access: used to connect to IOWC# bus signal to indicate burst write. Write/Read SWR I For VLBus-like access: used to indicate write (High) or read (Low) transfer. For burst access: used to connect to IORC# bus signal to indicate burst read. Synchronous Ready For VLBus-like access: exactly the same signal definition of nSRDY in VLBus. SRDYN O For burst access: insert wait state by KSZ8841M whenever necessary during the Data Regis- ter access.  2019 Microchip Technology Inc. D S00003147A-page 29

KSZ8841-16M/-32M TABLE 3-2: BUS INTERFACE UNIT SIGNAL GROUPING (CONTINUED) Signal Type Function Ready Return For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle. RDYRTNN I For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that the wait states are inserted by system logic (memory) not by KSZ8841M. BCLK I Bus Clock Asynchronous Transfer Signals RDN I Asynchronous Read WRN I Asynchronous Write Asynchronous Ready ARDY O This signal is asserted (Low) to insert wait states. Note 3-1 I = Input. O = Output. I/O = Bi-directional. Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N. Note that if the local device decoder is used in either synchronous or asynchronous transfers, LDEVN will be asserted to indicate that the KSZ8841M is successfully targeted. The signal LDEVN is a combinatorial decode of AEN and A[15:4]. 3.2.11.3 Asynchronous Interface For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the syn- chronous dedicated signals CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level through- out the entire asynchronous transfer. There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU, however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three major ways of interfacing with the system (host) are. • Interfacing with the system/host relying on local device decoding and having stable address throughout the whole transfer: The typical example for this application is ISA-like bus interface using latched address signals as shown in Figure 13. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. The host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data. • Interfacing with the system/host relying on local device decoding but not having stable address throughout the entire transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in Figure 14. This type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies with AEN to determine if the KSZ8841M device is the intended target. The data transfer is the same as the first case. • Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only): The typical example for this application is for an embedded processor having a central decoder on the system board or within the processor. Connecting the chip select (CS) from system/host to DATACSN bypasses the local device decoder. When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N, BE1N, and BE0N are ignored as shown in Figure 15. No other registers can be accessed by asserting DATACSN. The data transfer is the same as in the first case. Independent of the type of asynchronous interface used. To insert a wait state, the BIU will assert ARDY to prolong the cycle. 3.2.11.4 Synchronous Interface For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the asyn- chronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire syn- chronous transfer. The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C) burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a VLBus-like or EISA-like burst transfer. If VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the interface is for EISA-like burst transfer. For VLBus-like transfer interface (VLBUSN = 0): D S00003147A-page 30  2019 Microchip Technology Inc.

KSZ8841-16M/-32M This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. No burst is supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a hand- shaking process to end the cycle of VLBus-like transfers. When the KSZ8841M is ready to finish the cycle, it asserts SRDYN. The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched the read data. The KSZ8841M holds the read data until RDYRTNN is asserted. The timing waveform is shown in Figures 19 and 20. For EISA-like burst transfer interface (VLBUSN = 1): The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to indicate the burst write. Note that in this application, both the system/host/memory and KSZ8841M are capable of insert- ing wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8841M to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 17 and 18. 3.2.11.5 BIU Summation F igure3-4 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the chip’s BIU. F igure3-5 shows the connection for different data bus sizes. Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so an even address will enable the BE0N and an odd address will enable the BE1N. FIGURE 3-4: MAPPING FROM THE ISA, EISA, AND VLBUS TO THE KSZ8841M BUS INTERFACE KSZ8841M BIU ISA Host Interface No Addr Latch (ADSN = 0) Local decode Asynchronous Non-burst Host Interface Address Latch Interface Central decode EISA Central decode Burst Host Interface (VLBUSN = 1) Synchronous Interface Local VLBus Host Interface Address Latch decode (VLBUSN = 0) Note: To use DATACSN & 32-bit only for Central decode  2019 Microchip Technology Inc. D S00003147A-page 31

KSZ8841-16M/-32M FIGURE 3-5: KSZ8841M 8-BIT, 16-BIT, AND 32-BIT DATA BUS CONNECTIONS KSZ8841-16 KSZ8841-16 KSZ8841-32 HA[1] A[1] HA[1] A[1] GND A[1] HA[15:2] A[15:2] HA[15:2] A[15:2] HA[15:2] A[15:2] HD[7:0] D[7:0] HD[7:0] D[7:0] HD[7:0] D[7:0] D[15:8] HD[15:8] D[15:8] HD[15:8] D[15:8] HD[23:16] D[23:16] HD[31:24] D[31:24] HA[0] BE0N HA[0] BE0N nHBE[0] BE0N VDD BE1N nSBHE BE1N nHBE[1] BE1N nHBE[2] BE2N nHBE[3] BE3N 8-bit Data Bus 16-bit Data Bus 32-bit Data Bus (for example: ISA-like) (for example: EISA-like) 3.2.11.6 BIU Implementation Principles Because KSZ8841M is an I/O device with 16 addressable locations, address decoding is based on the values of A15- A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is assumed (BE3N – BE0N are ignored). If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN = 0. • Byte, word, and double word data buses and accesses (transfers) are supported. • Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 11 for the appropriate 8-bit, 16-bit, and 32-bit data bus connection. • Because independent sets of synchronous and asynchronous signals are provided, synchronous and asynchro- nous cycles can be mixed or interleaved as long as they are not active simultaneously. • The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de- asserted on the leading edge of the strobe. • The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must be held until RDYRTNN is asserted. The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal VLBUSN = 1. Both the system/host/memory and KSZ8841M are capable of inserting wait states. To set the system/host/memory to insert a wait state, assert RDYRTNN signal. To set the KSZ8841M to insert a wait state, assert SRDYN signal. 3.2.12 QUEUE MANAGEMENT UNIT (QMU) The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each queue contains 4 KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the host of the real time TX/RX status. 3.2.12.1 Transmit Queue (TXQ) Frame Format The frame format for the transmit queue is shown in T able3-3. The first word contains the control information for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon whether hardware CRC checksum generation is enabled. D S00003147A-page 32  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue mem- ory, thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR register. TABLE 3-3: FRAME FORMAT FOR TRANSMIT QUEUE Bit 15 Bit 0 Packet Memory Address Offset 2nd Byte 1st Byte 0 Control Word 2 Byte Count Transmit Packet Data 4 and up (maximum size is 1916) Because multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the TX queue. The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word aligned. Each control word corresponds to one TX packet. T able3-4 gives the transmit control word bit fields. TABLE 3-4: TRANSMIT CONTROL WORD BIT FIELDS Bit Description 15 TXIC Transmit Interrupt on Completion When this bit is set, the KSZ8841M sets the transmit interrupt after the present frame has been transmitted. 14 - 6 Reserved. 5 - 0 TXFID Transmit Frame ID This field specifies the frame ID that is used to identify the frame and its associated status infor- mation in the transmit status register. TABLE 3-5: TRANSMIT BYTE COUNT FORMA T Bit Description 15 - 11 Reserved. 10 - 0 TXBC Transmit Byte Count Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer mem- ory for better utilization of the packet memory. Note: The hardware behavior is unknown if an incorrect byte count information is written to this field. Writing a 0 value to this field is not permitted. The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The KSZ8841M does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8841M. It is treated transparently as data both for transmit operations. 3.2.12.2 Receive Queue (RXQ) Frame Format The frame format for the receive queue is shown in T able3-6. The first word contains the status information for the frame received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether hard- ware CRC stripping is enabled. TABLE 3-6: FRAME FORMAT FOR RECEIVE QUEUE Packet Memory Bit 15 Bit 0 Address Offset 2nd Byte 1st Byte 0 Status Word 2 Byte Count 4 and up Receive Packet Data (maximum size is 1916)  2019 Microchip Technology Inc. D S00003147A-page 33

KSZ8841-16M/-32M For receive, the packet receive status always reflects the receive status of the packet received in the current RX packet memory (see T able3-7). The RXSR register indicates the status of the current received frame. TABLE 3-7: RXQ RECEIVE PACKET STATUS WORD Bit Description RXFV Receive Frame Valid When set, this field indicates that the present frame in the receive packet memory is valid. The 15 status information currently in this location is also valid. When clear, it indicates that there is either no pending receive frame or that the current frame is still in the process of receiving. 14 - 8 Reserved. RXBF Receive Broadcast Frame 7 When set, it indicates that this frame has a broadcast address. RXMF Receive Multicast Frame 6 When set, it indicates that this frame has a multicast address (including the broadcast address). RXUF Receive Unicast Frame 5 When set, it indicates that this frame has a unicast address. 4 Reserved. RXFT Receive Frame Type When set, it indicates that the frame is an Ethernet-type frame (frame length is greater than 1500 3 bytes). When clear, it indicates that the frame is an IEEE 802.3 frame. This bit is not valid for runt frames. RXTL Receive Frame Too Long When set, it indicates that the frame length exceeds the maximum size of 1518 bytes. Frames that 2 are too long are passed to the host only if the pass bad frame bit is set. Note: Frame too long is only a frame length indication and does not cause any frame truncation. RXRF Receive Runt Frame When set, it indicates that a frame was damaged by a collision or had a premature termination 1 before the collision window passed. Runt frames are passed to the host only if the pass bad frame bit is set. RXCE Receive CRC Error 0 When set, it indicates that a CRC error has occurred on the current received frame. CRC error frames are passed to the host only if the pass bad frame bit is set. T able3-8 gives the format of the RX byte count field. TABLE 3-8: RXQ RECEIVE PACKET BYTE COUNT WORD Bit Description 15 - 11 Reserved. RXBC Receive Byte Count 10 - 0 Receive Byte Count up to 1916 bytes 3.2.13 EEPROM INTERFACE It is optional in the KSZ8841M to use an external EEPROM. In the case that an EEPROM is not used, the EEEN pin must be tied Low or floating. An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address, base address, and default configuration settings. The KSZ8841M can detect if the EEPROM is a 1KB (93C46) or 4 KB (93C66) EEPROM device (the 93C46 and the 93C66 are typical EEPROM devices). The EEPROM is organized as 16-bit mode. If the EEEN pin is pulled high, then the KSZ8841M performs an automatic read of the external EEPROM words 0H to 6H after the deassertion of Reset. The EEPROM values are placed in certain host-accessible registers. EEPROM read/ write functions can also be performed by software read/writes to the EEPCR registers. The KSZ8841M EEPROM format is given in T able3-9. D S00003147A-page 34  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 3-9: KSZ8841M EEPROM FORMAT Word 15 - 8 7 - 0 0H Base Address 1H Host MAC Address Byte 2 Host MAC Address Byte 1 2H Host MAC Address Byte 4 Host MAC Address Byte 3 3H Host MAC Address Byte 6 Host MAC Address Byte 5 4H Reserved 5H Reserved 6H ConfigParam (see T able3-10) 7H - 3FH Not used for KSZ8841M (available for user to use) The format for ConfigParam is shown in T able3-10. TABLE 3-10: CONFIGPARAM WORD IN EEPROM FORMA T Bit Bit Name Description 15 Reserved Reserved. No Soft Reset When this bit is set, indicates that KSZ8841M transitioning from D3_hot to D0 because of PowerState commands do not perform an internal reset. Configura- tion Context is preserved. Upon transition from the D3_hot to the D0 Initialized state, no additional operating system intervention is required to preserve Con- figuration Context beyond writing the PowerState bits. When this bit is clear, KSZ8841M performs an internal reset upon transitioning 14 NO_SRST from D3_hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3_hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled. This bit is loaded to bit 3 of PMCS register 13 Reserved Reserved. PME Support D2 When this bit is set, the KSZ8841M asserts PME event (pin 14) when the 12 PME_D2 KSZ8841M is in D2 state and PME_EN is set. Otherwise, the KSZ8841M does not assert PME event when the KSZ8841M is in D2 state. This bit is loaded to bit 13 of PMCR register PME Support D1 When this bit is set, the KSZ8841M asserts PME event (pin 14) when the 11 PME_D1 KSZ8841M is in D1 state and PME_EN is set. Otherwise, the KSZ8841M does not assert PME event when the KSZ8841M is in D1 state. This bit is loaded to bit 12 of PMCR register. D2 Support 10 D2_SUP When this bit is set, the KSZ8841M supports D2 power state. This bit is loaded to bit 10 of PMCR register. D1 Support 9 D1_SUP When this bit is set, the KSZ8841M supports D1 power state. This bit is loaded to bit 9 of PMCR register. 8 - 2 Reserved Reserved. Internal clock rate selection 0 = 125MHz 1 Clock_Rate 1 = 25MHz Note: At power up, this chip operates on 125MHz clock. The internal fre- q uency can be dropped to 25MHz via the external EEPROM.  2019 Microchip Technology Inc. D S00003147A-page 35

KSZ8841-16M/-32M TABLE 3-10: CONFIGPARAM WORD IN EEPROM FORMAT (CONTINUED) Bit Bit Name Description Async 8-bit bus select 1 = Bus is configured for 16-bit width 0 ASYN_8bit 0 = Bus is configured for 8-bit width This bit is loaded to bit 0 of PMCR register (32-bit width, KSZ8841-32MQL, don’t care this bit setting) 3.2.14 LOOPBACK SUPPORT The KSZ8841M provides Near-end (Remote) loopback support for remote diagnostic of failure. In loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode. 3.2.14.1 Near-End (Remote) Loopback Near-end (Remote) loopback is conducted at PHY port 1of the KSZ8841M. The loopback path starts at the PHY port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1). Bit [1] of register P1PHYCTRL is used to enable near-end loopback for port 1. Alternatively, Bit [9] of register P1SCSLMD can also be used to enable near-end loopback. The ports 1 near-end loopback path is illustrated in F igure3-6. FIGURE 3-6: PHY PORT 1 NEAR-END (REMOTE) LOOPBACK PATH RXP1 / TXP1 / PHY Port 1 RXM1 TXM1 Near-end (remote) Loopback PMD1/PMA1 PCS1 MAC1 RXQ/TXQ QMU/DMA Bus I/F Unit D S00003147A-page 36  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 4.0 REGISTER DESCRIPTIONS 4.1 CPU Interface I/O Registers The KSZ8841M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O reg- isters. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets by read- ing and writing through the packet data registers. 4.1.1 I/O REGISTERS Input/Output (I/O) registers are limited to 16 locations as required by most ISA bus-based systems; therefore, registers are assigned to different banks. The last word of the I/O register locations (0xE - 0xF) is shared by all banks and can be used to change the bank in use. The following I/O Space Mapping Tables apply to 8-, 16-, or 32-bit bus products. Depending upon the bus interface used and byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit operation. The KSZ8841M is not limited to 8/16-bit performance and 32-bit read/write are also supported. TABLE 4-1: INTERNAL I/O SPACE MAPPING - BANK 0 T O BANK 7 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Base Host MAC On-Chip Wakeup Wakeup Wakeup Wakeup 0x0 Address Address Bus Control Frame0 Frame1 Frame2 Frame3 [7:0] Low [7:0] [7:0] CRC0 [7:0] CRC0 [7:0] CRC0 [7:0] CRC0 [7:0] 0x0 to 0x1 Reserved Wakeup Wakeup Wakeup Wakeup Base Host MAC On-Chip Frame0 Frame1 Frame2 Frame3 0x1 Address Address Bus Control CRC0 CRC0 CRC0 CRC0 [15:8] Low [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] 0x0 to 0x3 Host MAC EEPROM Wakeup Wakeup Wakeup Wakeup 0x2 Address Control Frame0 Frame1 Frame2 Frame3 Mid [7:0] [7:0] CRC1 [7:0] CRC1 [7:0] CRC1 [7:0] CRC1 [7:0] 0x2 to 0x3 Reserved Reserved Wakeup Wakeup Wakeup Wakeup Host MAC EEPROM Frame0 Frame1 Frame2 Frame3 0x3 Address Control CRC1 CRC1 CRC1 CRC1 Mid [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] QMU RX Wakeup Wakeup Wakeup Wakeup Flow Con- Host MAC Memory Frame0 Frame1 Frame2 Frame3 0x4 trol Water- Address BIST Info Byte Mask0 Byte Mask0 Byte Mask0 Byte Mask0 mark High [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x4 to 0x5 Reserved QMU RX Wakeup Wakeup Wakeup Wakeup Flow Con- Host MAC Memory Frame0 Frame1 Frame2 Frame3 0x5 trol Water- Address BIST Info Byte Mask0 Byte Mask0 Byte Mask0 Byte Mask0 mark High [15:8] [15:8] 0x4 to 0x7 [15:8] [15:8] [15:8] [15:8] [15:8] Wakeup Wakeup Wakeup Wakeup Bus Error Global Frame0 Frame1 Frame2 Frame3 0x6 Status Reset Byte Mask1 Byte Mask1 Byte Mask1 Byte Mask1 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x6 to 0x7 Reserved Reserved Wakeup Wakeup Wakeup Wakeup Bus Error Global Frame0 Frame1 Frame2 Frame3 0x7 Status Reset Byte Mask1 Byte Mask1 Byte Mask1 Byte Mask1 [15:8] [15:8] [15:8] [15:8] [15:8] [15:8]  2019 Microchip Technology Inc. D S00003147A-page 37

KSZ8841-16M/-32M TABLE 4-1: INTERNAL I/O SPACE MAPPING - BANK 0 TO BANK 7 (CONTINUED) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Power Wakeup Wakeup Wakeup Wakeup Bus Burst Manage- Frame0 Frame1 Frame2 Frame3 0x8 Length ment Capa- Byte Mask2 Byte Mask2 Byte Mask2 Byte Mask2 [7:0] bilities [7:0] [7:0] [7:0] [7:0] [7:0] 0x8 to 0x9 Reserved Reserved Power Wakeup Wakeup Wakeup Wakeup Bus Burst Manage- Frame0 Frame1 Frame2 Frame3 0x9 Length ment Capa- Byte Mask2 Byte Mask2 Byte Mask2 Byte Mask2 [15:8] bilities [15:8] [15:8] [15:8] [15:8] 0x8 to 0xB [15:8] Wakeup Wakeup Wakeup Wakeup Wakeup Frame Frame0 Frame1 Frame2 Frame3 0xA Control Byte Mask3 Byte Mask3 Byte Mask3 Byte Mask3 [7:0] [7:0] [7:0] [7:0] [7:0] 0xA to 0xB Reserved Wakeup Wakeup Wakeup Wakeup Wakeup Frame Frame0 Frame1 Frame2 Frame3 0xB Control Byte Mask3 Byte Mask3 Byte Mask3 Byte Mask3 [15:8] [15:8] [15:8] [15:8] [15:8] 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8] TABLE 4-2: INTERNAL I/O SPACE MAPPING - BANK 8 T O BANK 15 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 Bank 14 Bank 15 0x0 0x0 to 0x1 Reserved 0x1 0x0 to 0x3 0x2 0x2 to 0x3 Reserved 0x3 0x4 0x4 to 0x5 Reserved 0x5 0x4 to 0x7 0x6 0x6 to 0x7 Reserved 0x7 0x8 0x8 to 0x9 Reserved 0x9 0x8 to 0xB 0xA 0xA to 0xB Reserved 0xB 0xC 0xC to 0xD Bank Select [7:0] 0xD 0xC to 0xF 0xE 0xE to 0xF Bank Select [15:8] 0xF D S00003147A-page 38  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-3: INTERNAL I/O SPACE MAPPING - BANK 16 T O BANK 23 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 16 Bank 17 Bank 18 Bank 19 Bank 20 Bank 21 Bank 22 Bank 23 Transmit Interrupt Multicast TXQ Com- 0x0 Control Enable Table 0 mand [7:0] [7:0] [7:0] [7:0] 0x0 to 0x1 Reserved Transmit TXQ Com- Interrupt Multicast 0x1 Control mand Enable Table 0 [15:8] [15:8] [15:8] [15:8] 0x0 to 0x3 Transmit Interrupt Multicast RXQ Com- 0x2 Status Status Table 1 mand [7:0] [7:0] [7:0] [7:0] 0x2 to 0x3 Reserved Transmit RXQ Com- Interrupt Multicast 0x3 Status mand Status Table 1 [15:8] [15:8] [15:8] [15:8] TX Frame Receive Receive Multicast Data 0x4 Control Status Table 2 Pointer [7:0] [7:0] [7:0] [7:0] 0x4 to 0x5 Reserved TX Frame Receive Receive Multicast Data 0x5 Control Status Table 2 Pointer [15:8] [15:8] [15:8] [15:8] 0x4 to 0x7 RX Frame Receive Multicast Data Byte 0x6 Table 3 Pointer Counter [7:0] [7:0] [7:0] 0x6 to 0x7 Reserved Reserved RX Frame Receive Multicast Data Byte 0x7 Table 3 Pointer Counter [15:8] [15:8] [15:8] Power TXQ Mem- QMU Data Early Manage- ory Infor- 0x8 Low Transmit ment Con- mation [7:0] [7:0] trol/Status [7:0] [7:0] 0x8 to 0x9 Reserved Power TXQ Mem- QMU Data Early Manage- ory Infor- 0x9 Low Transmit ment Con- mation 0x8 to 0xB [15:8] [15:8] [15:8] trol/Status [15:8] RXQ Mem- QMU Data Early 0xA ory Infor- High Receive mation [7:0] [7:0] [7:0] 0xA to 0xB RXQ Mem- Reserved QMU Data Early ory Infor- 0xB High Receive mation [15:8] [15:8] [15:8] 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8]  2019 Microchip Technology Inc. D S00003147A-page 39

KSZ8841-16M/-32M TABLE 4-4: INTERNAL I/O SPACE MAPPING - BANK 24 T O BANK 31 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 24 Bank 25 Bank 26 Bank 27 Bank 28 Bank 29 Bank 30 Bank 31 0x0 0x0 to 0x1 Reserved 0x1 0x0 to 0x3 0x2 0x2 to 0x3 Reserved 0x3 0x4 0x4 to 0x5 Reserved 0x5 0x4 to 0x7 0x6 0x6 to 0x7 Reserved 0x7 0x8 0x8 to 0x9 Reserved 0x9 0x8 to 0xB 0xA 0xA to 0xB Reserved 0xB 0xC 0xC to 0xD Bank Select [7:0] 0xD 0xC to 0xF 0xE 0xE to 0xF Bank Select [15:8] 0xF TABLE 4-5: INTERNAL I/O SPACE MAPPING - BANK 32 T O BANK 39 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 32 Bank 33 Bank 34 Bank 35 Bank 36 Bank 37 Bank 38 Bank 39 Chip ID 0x0 and Enable [7:0] 0x0 to 0x1 Reserved Chip ID 0x0 to 0x3 0x1 and Enable [15:8] 0x2 0x2 to 0x3 Reserved 0x3 0x4 0x4 to 0x5 Reserved 0x5 0x4 to 0x7 0x6 0x6 to 0x7 Reserved 0x7 0x8 0x8 to 0x9 Reserved 0x9 Chip Global 0x8 to 0xB 0xA Control [7:0] 0xA to 0xB Reserved Chip Global 0xB Control [15:8] 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8] D S00003147A-page 40  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-6: INTERNAL I/O SPACE MAPPING - BANK 40 T O BANK 47 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 40 Bank 41 Bank 42 Bank 43 Bank 44 Bank 45 Bank 46 Bank 47 PHY1 MII- PHY1 Indirect Register LinkMD Access 0x0 Basic Con- Control/ Control. trol Status [7:0] [7:0] [7:0] 0x0 to 0x1 Reserved Reserved Reserved PHY1 Indirect PHY1 MII- LinkMD Access Register 0x1 Control/ Control. Basic Con- Status [15:8] trol [15:8] [15:8] 0x0 to 0x3 PHY1 MII- PHY1 Indirect Register Special Access 0x2 Basic Sta- Control/ Data 1 tus Status [7:0] [7:0] [7:0] 0x2 to 0x3 Reserved Reserved Reserved PHY1 Indirect PHY1 MII- Special Access Register 0x3 Control/ Data 1 Basic Sta- Status [15:8] tus [15:8] [15:8] Indirect PHY1 0x4 Access PHYID Low Data 2 [7:0] [7:0] 0x4 to 0x5 Reserved Indirect Reserved Reserved PHY1 Access 0x5 PHYID Low Data 2 [15:8] [15:8] 0x4 to 0x7 PHY1 Indirect PHYID 0x6 Access High Data 3 [7:0] [7:0] 0x6 to 0x7 Reserved Reserved Reserved Indirect PHY1 Access PHYID 0x7 Data 3 High [15:8] [15:8] PHY1 A.N. Indirect Advertise- 0x8 Access ment Data 4 [7:0] [7:0] 0x8 to 0x9 Reserved Reserved Reserved Indirect PHY1 A.N. Access Advertise- 0x9 Data 4 ment [15:8] [15:8] 0x8 to 0xB PHY1 A.N. Indirect Link Part- 0xA Access ner Ability Data 5 [7:0] [7:0] 0xA to 0xB Reserved Reserved Reserved Indirect PHY1 A.N. Access Link Part- 0xB Data 5 ner Ability [15:8] [15:8] 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8]  2019 Microchip Technology Inc. D S00003147A-page 41

KSZ8841-16M/-32M TABLE 4-7: INTERNAL I/O SPACE MAPPING - BANK 48 T O BANK 55 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 48 Bank 49 Bank 50 Bank 51 Bank 52 Bank 53 Bank 54 Bank 55 Port 1 PHY Special Control/ 0x0 Status, LinkMD [7:0] 0x0 to 0x1 Reserved Reserved Port 1 PHY Special Control/ 0x0 to 0x3 0x1 Status, LinkMD [15:8] Port 1 0x2 Control 4 [7:0] 0x2 to 0x3 Reserved Reserved Port 1 0x3 Control 4 [15:8] Port 1 0x4 Status [7:0] 0x4 to 0x5 Reserved Reserved Port 1 0x4 to 0x7 0x5 Status [15:8] 0x6 0x6 to 0x7 Reserved 0x7 0x8 0x8 to 0x9 Reserved 0x9 0x8 to 0xB 0xA 0xA to 0xB Reserved 0xB 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8] TABLE 4-8: INTERNAL I/O SPACE MAPPING - BANK 56 T O BANK 63 I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 56 Bank 57 Bank 58 Bank 59 Bank 60 Bank 61 Bank 62 Bank 63 0x0 0x0 to 0x1 Reserved 0x1 0x0 to 0x3 0x2 0x2 to 0x3 Reserved 0x3 0x4 0x4 to 0x5 Reserved 0x5 0x4 to 0x7 0x6 0x6 to 0x7 Reserved 0x7 0x8 0x8 to 0x9 Reserved 0x9 0x8 to 0xB 0xA 0xA to 0xB Reserved 0xB 0xC 0xC to 0xD Reserved 0xD 0xC to 0xF 0xE Bank Select [7:0] 0xE to 0xF 0xF Bank Select [15:8] D S00003147A-page 42  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 4.2 Register Map: MAC and PHY Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes unpredict- able and often fatal results. If the user wants to write to these reserved bits, the user has to read back these reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits. Bit Type Definitions • RO = Read only. • RW = Read/Write. • W1C = Write 1 to Clear (writing a one to this bit clears it). Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) The bank select register is used to select or to switch between different sets of register banks for I/O access. There are a total of 64 banks available to select, including the built-in switch engine registers. TABLE 4-9: B ANK 0-63 BANK SELECT REGISTER (0X0E) Bit Default Value R/W Description 15 - 6 0x000 RO Reserved BSA Bank Select Address Bits BSA bits select the I/O register bank in use. This register is always accessible regardless of the register bank currently selected. Notes: 5 - 0 0x00 R/W The bank select register can be accessed as a doubleword (32-bit) at offset 0xC, as a word (16-bit) at offset 0xE, or as a byte (8-bit) at offset 0xE. A doubleword write to offset 0xC writes to the BANK Select Regis- ter but does not write to registers 0xC and 0xD; it only writes to reg- ister 0xE. Bank 0 Base Address Register (0x00): BAR This register holds the base address for decoding a device access. Its value is loaded from the external EEPROM (0x0H) upon a power-on reset if the EEPROM Enable (EEEN) pin is tied to High. Its value can also be modified after reset. Writing to this register does not store the value into the EEPROM. When the EEEN pin is tied to Low, the default base address is 0x300. TABLE 4-10: BANK 0 BASE A DDRESS REGISTER (0X00) Bit Default Value R/W Description 0x03 if EEEN is Low or BARH Base Address High 15 - 8 the value from EEPROM R/W These bits are compared against the address on the bus if EEEN is High ADDR[15:8] to determine the BASE for the KSZ8841M registers. 0x00 if EEEN is Low or BARL Base Address Low 7 - 5 the value from EEPROM R/W These bits are compared against the address on the bus if EEEN is High ADDR[7:5] to determine the BASE for the KSZ8841M registers. 4 - 0 0x00 RO Reserved Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR This register contains the user defined QMU RX Queue high watermark configuration bit as below. TABLE 4-11: Bit Default Value R/W Description 15 - 13 0x0 RO Reserved 12 0 R/W QMU RX Flow Control High Watermark Configuration 0 = 3KBytes 1 = 2KBytes 11 - 0 0x000 RO Reserved  2019 Microchip Technology Inc. D S00003147A-page 43

KSZ8841-16M/-32M Bank 0 Bus Error Status Register (0x06): BESR This register flags the different kinds of errors on the host bus. TABLE 4-12: BANK 0 BUS ERROR STAT US REGISTER (0X06) Bit Default Value R/W Description 15 0 RO IBEC Illegal Byte Enable Combination 1 = Illegal byte enable combination occurs. The illegal combination value can be found from bit 14 to bit 11. 0 = Legal byte enable combination. Write 1 to clear. 14 - 11 — RO IBECV Illegal Byte Enable Combination Value Bit 14 = Byte enable 3. Bit 13 = Byte enable 2. Bit 12 = Byte enable 1. Bit 11 = Byte enable 0. This value is valid only when bit 15 is set to 1. 10 0 RO SSAXFER Simultaneous Synchronous and Asnychronous Trans- fers 1 = Synchronous and Asnychronous Transfers occur simultane- ously. 0 = Normal. Write 1 to clear. 9 - 0 0x000 RO Reserved Bank 0 Bus Burst Length Register (0x08): BBLR Before the burst can be sent, the burst length needs to be programmed. TABLE 4-13: B ANK 0 BUS BURST LENGTH REGISTER (0X08) Bit Default Value R/W Description 15 0 RO Reserved BRL Burst Length (for burst read and write) 000: single. 14 - 12 0x0 R/W 011: fixed burst read length of 4. 101: fixed burst read length of 8. 111: fixed burst read length of 16. 11 - 0 0x000 RO Reserved Bank 1: Reserved Except Bank Select Register (0xE). Bank 2 Host MAC Address Register Low (0x00): MARL This register along with the other two Host MAC address registers are loaded starting at word location 0x1 of the EEPROM upon hardware reset. The software driver can modify the register, but it will not modify the original Host MAC address value in the EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three registers as mapping below: • MARL[15:0] = EEPROM 0x1(MAC Byte 2 and 1) • MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) • MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The Host MAC address is used to define the individual destination address that the KSZ8841M responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101. These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below: • MARL[15:0] = 0x89AB • MARM[15:0] = 0x4567 D S00003147A-page 44  2019 Microchip Technology Inc.

KSZ8841-16M/-32M • MARH[15:0] = 0x0123 The following table shows the register bit fields for Low word of Host MAC address. TABLE 4-14: BANK 2 HOST MAC A DDRESS REGISTER LOW (0X00) Bit Default Value R/W Description MARL MAC Address Low 15 - 0 — R/W The least significant word of the MAC address. Bank 2 Host MAC Address Register Middle (0x02): MARM The following table shows the register bit fields for middle word of Host MAC address. TABLE 4-15: BANK 2 HOST MAC A DDRESS REGISTER MIDDLE (0X02) Bit Default Value R/W Description MARM MAC Address Middle 15 - 0 — R/W The middle word of the MAC address. Bank 2 Host MAC Address Register High (0x04): MARH The following table shows the register bit fields for high word of Host MAC address. TABLE 4-16: BANK 2 HOST MAC A DDRESS REGISTER HIGH (0X04) Bit Default Value R/W Description MARH MAC Address High 15 - 0 — R/W The Most significant word of the MAC address. Bank 3 On-Chip Bus Control Register (0x00): OBCR This register controls the on-chip bus speed for the KSZ8841M. It is used for power management when the external host CPU is running at a slow frequency. The default of the on-chip bus speed is 1 25MHz without EEPROM. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance. TABLE 4-17: BANK 3 ON-CHIP BUS CONTROL R EGISTER (0X00) Bit Default Value R/W Description 15 - 2 — RO Reserved OBSC On-Chip Bus Speed Control 0 0 = 125MHz. 0 1 = 62.5MHz. 1 0 = 41.66MHz. 1 1 = 25MHz. 1 - 0 0x0 R/W Note: When external EEPROM is enabled, the bit 1 in Configparm word (0x6H) is used to control this speed as below: B it 1 = 0, this value will be 00 for 125MHz. Bit 1 = 1, this value will be 11 for 25MHz. (User still can write these two bits to change speed after EEPROM data loaded)  2019 Microchip Technology Inc. D S00003147A-page 45

KSZ8841-16M/-32M Bank 3 EEPROM Control Register (0x02): EEPCR To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded from the EEPROM immediately after reset. The KSZ8841M allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is set. TABLE 4-18: BANK 3 EEPROM CONTROL R EGISTER (0X02) Bit Default Value R/W Description 15 - 5 — RO Reserved EESA EEPROM Software Access 4 0 R/W 1 = Enable software to access EEPROM through bit 3 to bit 0. 0 = Disable software to access EEPROM. EECB EEPROM Status Bit 3 — RO Data Receive from EEPROM. This bit directly reads the EEDI pin. EECB EEPROM Control Bits Bit 2 = Data Transmit to EEPROM. This bit directly controls the device’s EEDO pin. 2 - 0 0x0 R/W Bit 1 = Serial Clock. This bit directly controls the device’s EESK pin. Bit 0 = Chip Select for EEPROM. This bit directly controls the device’s EECS pin. Bank 3 Memory BIST Info Register (0x04): MBIR TABLE 4-19: BANK 3 MEMORY B IST INFO REGISTER (0X04) Bit Default Value R/W Description 15 - 13 0x0 RO Reserved TXMBF TX Memory BIST Finish 12 — RO When set, it indicates the Memory Built In Self Test completion for the TX Memory. TXMBFA TX Memory BIST Fail 11 — RO When set, it indicates the Memory Built In Self Test has failed. 10 - 5 — RO Reserved RXMBF RX Memory BIST Finish 4 — RO When set, it indicates the Memory Built In Self Test completion for the RX Memory. RXMBFA RX Memory BIST Fail 3 — RO When set, it indicates the Memory Built In Self Test has failed. 2 - 0 — RO Reserved Bank 3 Global Reset Register (0x06): GRR This register controls the global reset function with information programmed by the CPU. TABLE 4-20: BANK 3 GLOBAL R ESET REGISTER (0X06) Bit Default Value R/W Description 15 - 1 0x0000 RO Reserved Global Soft Reset 1 = Software reset is active. 0 = Software reset is inactive. 0 0 R/W Software reset will affect PHY, MAC, QMU, DMA, and the switch core, only the BIU (base address registers) remains unaffected by a software reset. D S00003147A-page 46  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 3 Power Management Capabilities Register (0x08): PMCR This register is a read-only register that provides information on the K8841M power management capabilities. These bits are automatically downloaded from Configparam word of EEPROM if pin EEEN is high (enabled EEPROM). TABLE 4-21: BANK 3 POWER MANAGEMENT CAPA BILITIES REGISTER (0X08) Bit Default Value R/W Description PME Support D3 (cold) 15 0 RO This bit defaults to 0, so the KSZ8841M does not support D3(cold) PME Support D3 (hot) This bit is 1 only. It indicates that the KSZ8841M can assert PME 14 1 RO event (PMEN pin 14) in D3(hot) power state.(see bit1:0 in PMCS register) PME Support D2 If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the KSZ8841M is in D2 power state and PME_EN (see bit8 in PMCS register) is set. Otherwise, the KSZ8841M does 13 0 RO not assert PME event (PMEN pin 14) when the KSZ8841M is in D2 power state. The value of this bit is loaded from the PME_D2 bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). PME Support D1 If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the KSZ8841M is in D1 power state and PME_EN (see bit8 in PMCS register) is set. Otherwise, the KSZ8841M does 12 0 RO not assert PME event (PMEN pin 14) when the KSZ8841M is in D1 power state. The value of this bit loaded from the PME_D1 bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). PME Support D0 11 0 RO This bit defaults to 0, it is indicating that the KSZ8841M does not assert PME event (PMEN pin 14) in D0 power state. D2 Support If this bit is set, it indicates that the KSZ8841M support D2 power 10 0 RO state. The value of this bit is loaded from the D2_SUP bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). D1 Support If this bit is set, it indicates that the KSZ8841M support D1 power 9 0 RO state. The value of this bit is loaded from the D1_SUP bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). 8 - 1 — RO Reserved Bus Configuration (only for KSZ8841-16MQL device) 1 = Bus width is 16 bits. 0 — RO 0 = Bus width is 8 bits. (this bit, ASYN_8bit, is only available when EEPROM is enabled) Bank 3 Wakeup Frame Control Register (0x0A): WFCR This register holds control information programmed by the CPU to control the wake up frame function. TABLE 4-22: BANK 3 WAKEUP FRAME CONTROL R EGISTER (0X0A) Bit Default Value R/W Description 15 - 8 0x00 RO Reserved MPRXE Magic Packet RX Enable 7 0 R/W When set, it enables the magic packet pattern detection. When reset, the magic packet pattern detection is disabled.  2019 Microchip Technology Inc. D S00003147A-page 47

KSZ8841-16M/-32M TABLE 4-22: BANK 3 WAKEUP FRAME CONTROL REGISTER (0X0A) (CONTINUED) Bit Default Value R/W Description 6 - 4 0x0 RO Reserved WF3E Wake up Frame 3 Enable 3 0 R/W When set, it enables the Wake up frame 3 pattern detection. When reset, the Wake up frame 3 pattern detection is disabled. WF2E Wake up Frame 2 Enable 2 0 R/W When set, it enables the Wake up frame 2 pattern detection. When reset, the Wake up frame 2 pattern detection is disabled. WF1E Wake up Frame 1 Enable 1 0 R/W When set, it enables the Wake up frame 1 pattern detection. When reset, the Wake up frame 1 pattern detection is disabled. WF0E Wake up Frame 0 Enable 0 0 R/W When set, it enables the Wake up frame 0 pattern detection. When reset, the Wake up frame 0 pattern detection is disabled. Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0 This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-23: BANK 4 WAKEUP F RAME 0 CRC0 REGISTER (0X00) Bit Default Value R/W Description WF0CRC0 15 - 0 0x0000 R/W Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1 This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-24: BANK 4 WAKEUP F RAME 0 CRC1 REGISTER (0X02) Bit Default Value R/W Description WF0CRC1 15 - 0 0 R/W Wake up Frame 0 CRC (upper 16 bits). The expected CRC value of a Wake up frame 0 pattern. Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0 This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte of the Wake up frame 0, setting bit 15 selects the 16th byte of the Wake up frame 0. TABLE 4-25: BANK 4 WAKEUP F RAME 0 BYTE MASK 0 REGISTER (0X04) Bit Default Value R/W Description WF0BM0 15 - 0 0 R/W Wake up Frame 0 Byte Mask 0 The first 16 bytes mask of a Wake up frame 0 pattern. D S00003147A-page 48  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1 This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 0. Setting bit 15 selects the 32nd byte of the Wake up frame 0. TABLE 4-26: BANK 4 WAKEUP F RAME 0 BYTE MASK 1 REGISTER (0X06) Bit Default Value R/W Description WF0BM1 Wake up Frame 0 Byte Mask 1. 15 - 0 0 R/W The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 0 pattern. Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2 This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 0. Setting bit 15 selects the 48th byte of the Wake up frame 0. TABLE 4-27: BANK 4 WAKEUP F RAME 0 BYTE MASK 2 REGISTER (0X08) Bit Default Value R/W Description WF0BM2 Wake-up Frame 0 Byte Mask 2. 15 - 0 0 R/W The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 0 pattern. Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3 This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 0. Setting bit 15 selects the 64th byte of the Wake up frame 0. TABLE 4-28: BANK 4 WAKEUP F RAME 0 BYTE MASK 3 REGISTER (0X0A) Bit Default Value R/W Description WF0BM3 Wake-up Frame 0 Byte Mask 3. 15 - 0 0 R/W The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 0 pattern. Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0 This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-29: BANK 5 WAKEUP F RAME 1 CRC0 REGISTER (0X00) Bit Default Value R/W Description WF1CRC0 15 - 0 0 R/W Wake-up frame 1 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 1 pattern. Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1 This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-30: BANK 5 WAKEUP F RAME 1 CRC1 REGISTER (0X02) Bit Default Value R/W Description WF1CRC1 15 - 0 0 R/W Wake-up frame 1 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 1 pattern.  2019 Microchip Technology Inc. D S00003147A-page 49

KSZ8841-16M/-32M Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0 This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1. TABLE 4-31: BANK 5 WAKEUP F RAME 1 BYTE MASK 0 REGISTER (0X04) Bit Default Value R/W Description WF1BM0 15 - 0 0 R/W Wake-up frame 1 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 1 pattern. Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1 This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1. TABLE 4-32: BANK 5 WAKEUP F RAME 1 BYTE MASK 1 REGISTER (0X06) Bit Default Value R/W Description WF1BM1 Wake-up frame 1 Byte Mask 1. 15 - 0 0 R/W The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 1 pattern. Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2 This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 1. Setting bit 15 selects the 48th byte of the Wake up frame 1. TABLE 4-33: BANK 5 WAKEUP F RAME 1 BYTE MASK 2 REGISTER (0X08) Bit Default Value R/W Description WF1BM2 Wake-up frame 1 Byte Mask 2. 15 - 0 0 R/W The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 1 pattern. Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3 This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 1. Setting bit 15 selects the 64th byte of the Wake up frame 1. TABLE 4-34: BANK 5 WAKEUP F RAME 1 BYTE MASK 3 REGISTER (0X0A) Bit Default Value R/W Description WF1BM3 Wake-up frame 1 Byte Mask 3. 15 - 0 0 R/W The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 1 pattern. Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0 This register contains the expected CRC values of the Wake up frame 2 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-35: BANK 6 WAKEUP F RAME 2 CRC0 REGISTER (0X00) Bit Default Value R/W Description WF2CRC0 15 - 0 0 R/W Wake-up frame 2 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 2 pattern. D S00003147A-page 50  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1 This register contains the expected CRC values of the wake-up frame 2 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-36: BANK 6 WAKEUP F RAME 2 CRC1 REGISTER (0X02) Bit Default Value R/W Description WF2CRC1 15 - 0 0 R/W Wake-up frame 2 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 2 pattern. Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0 This register contains the first 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the first byte of the Wake up frame 2, setting bit 15 selects the 16th byte of the Wake up frame 2. TABLE 4-37: BANK 6 WAKEUP F RAME 2 BYTE MASK 0 REGISTER (0X04) Bit Default Value R/W Description WF2BM0 15 - 0 0 R/W Wake-up frame 2 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 2 pattern. Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1 This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 2. Setting bit 15 selects the 32nd byte of the Wake up frame 2. TABLE 4-38: BANK 6 WAKEUP F RAME 2 BYTE MASK 1 REGISTER (0X06) Bit Default Value R/W Description WF2BM1 Wake-up frame 2 Byte Mask 1. 15 - 0 0 R/W The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 2 pattern. Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2 This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 2. Setting bit 15 selects the 48th byte of the Wake up frame 2. TABLE 4-39: BANK 6 WAKEUP F RAME 2 BYTE MASK 2 REGISTER (0X08) Bit Default Value R/W Description WF2BM2 Wake-up frame 2 Byte Mask 2. 15 - 0 0 R/W The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 2 pattern. Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3 This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 2. Setting bit 15 selects the 64th byte of the Wake up frame 2. TABLE 4-40: BANK 6 WAKEUP F RAME 2 BYTE MASK 3 REGISTER (0X0A) Bit Default Value R/W Description WF2BM3 Wake-up frame 2 Byte Mask 3. 15 - 0 0 R/W The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 2 pattern.  2019 Microchip Technology Inc. D S00003147A-page 51

KSZ8841-16M/-32M Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0 This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake-up byte mask registers. TABLE 4-41: BANK 7 WAKEUP F RAME 3 CRC0 REGISTER (0X00) Bit Default Value R/W Description WF3CRC0 15 - 0 0 R/W Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3 pattern. Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1 This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. TABLE 4-42: BANK 7 WAKEUP F RAME 3 CRC1 REGISTER (0X02) Bit Default Value R/W Description WF3CRC1 15 - 0 0 R/W Wake-up frame 3 CRC (upper 16 bits). The expected CRC value of a Wake up frame 3 pattern. Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0 This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte of the Wake up frame 3, setting bit 15 selects the 16th byte of the Wake up frame 3. TABLE 4-43: BANK 7 WAKEUP F RAME 3 BYTE MASK 0 REGISTER (0X04) Bit Default Value R/W Description WF3BM0 15 - 0 0 R/W Wake up Frame 3 Byte Mask 0 The first 16 byte mask of a Wake up frame 3 pattern. Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1 This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 3. Setting bit 15 selects the 32nd byte of the Wake up frame 3. TABLE 4-44: BANK 7 WAKEUP F RAME 3 BYTE MASK 1 REGISTER (0X06) Bit Default Value R/W Description WF3BM1 Wake up Frame 3 Byte Mask 1 15 - 0 0 R/W The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 3 pattern. Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2 This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 3. Setting bit 15 selects the 48th byte of the Wake up frame 3. TABLE 4-45: BANK 7 WAKEUP F RAME 3 BYTE MASK 2 REGISTER (0X08) Bit Default Value R/W Description WF3BM2 Wake up Frame 3 Byte Mask 2 15 - 0 0 R/W The next 16 bytes mask covering bytes 33 to 48 of a Wake up frame 3 pattern. D S00003147A-page 52  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3 This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3. TABLE 4-46: BANK 7 WAKEUP F RAME 3 BYTE MASK 3 REGISTER (0X0A) Bit Default Value R/W Description WF3BM3 Wake up Frame 3 Byte Mask 3. 15 - 0 0 R/W The last 16 bytes mask covering bytes 49 to 64 of a Wake up frame 3 pattern. Bank 8 - 15: Reserved Except Bank Select Register (0xE). Bank 16 Transmit Control Register (0x00): TXCR This register holds control information programmed by the CPU to control the QMU transmit module function. TABLE 4-47: BANK 16 TRANSMIT CONTROL R EGISTER (0X00) Bit Default Value R/W Description 15 — RO Reserved 14 - 13 0x0 R/W Reserved 12 - 4 — RO Reserved TXFCE Transmit Flow Control Enable When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled. The KSZ8841M transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold level that will 3 0x0 R/W cause the buffer to overflow. When this bit is set and the KSZ8841M is in half-duplex mode, back-pressure flow control is enabled. When this bit is cleared, no transmit flow control is enabled. TXPE Transmit Padding Enable When this bit is set, the KSZ8841M automatically adds a padding 2 0x0 R/W field to a packet shorter than 64 bytes. Note: Setting this bit requires enabling the add CRC feature to avoid CRC errors for the transmit packet. TXCE Transmit CRC Enable 1 0x0 R/W When this bit is set, the KSZ8841M automatically adds a CRC checksum field to the end of a transmit frame. TXE Transmit Enable When this bit is set, the transmit module is enabled and placed in a 0 0x0 R/W running state. When reset, the transmit process is placed in the stopped state after the transmission of the current frame is com- pleted.  2019 Microchip Technology Inc. D S00003147A-page 53

KSZ8841-16M/-32M Bank 16 Transmit Status Register (0x02): TXSR This register keeps the status of the last transmitted frame. TABLE 4-48: BANK 16 TRANSMIT STAT US REGISTER (0X02) Bit Default Value R/W Description 15 0x0 RO Reserved TXUR Transmit Underrun This bit is set when underrun occurs. Note: This is a fatal status. Software should guarantee that no underrun condition occurred when enabling the early transmit func- 14 0x0 RO tion. The system or the QMU requires a reset or restart to recover from an underrun condition. To aviod transmit underun condition, the user has to make sure that the host interface speed (bandwidth) is faster than the ethernet port. TXLC Transmit Late Collision 13 0x0 RO This bit is set when a transmit Late Collision occurs. TXMC Transmit Maximum Collision 12 0x0 RO This bit is set when a transmit Maximum Collision is reached. 11 - 6 — RO Reserved TXFID Transmit Frame ID 5 - 0 — RO This field identifies the transmitted frame. All of the transmit status information in this register belongs to the frame with this ID. Bank 16 Receive Control Register (0x04): RXCR This register holds control information programmed by the CPU to control the receive function. TABLE 4-49: BANK 16 RECEIVE CONTROL R EGISTER (0X04) Bit Default Value R/W Description 15 - 11 — RO Reserved RXFCE Receive Flow Control Enable When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled, and the KSZ8841M will acknowledge a PAUSE frame from the receive interface; i.e., the outgoing packets are 10 0x0 R/W pending in the transmit buffer until the PAUSE frame control timer expires. This field has no meaning in half-duplex mode and should be programmed to 0. When this bit is cleared, flow control is not enabled. RXEFE Receive Error Frame Enable When this bit is set, CRC error frames are allowed to be received 9 0x0 R/W into the RX queue. When this bit is cleared, all CRC error frames are discarded. 8 — RO Reserved RXBE Receive Broadcast Enable 7 0x0 R/W When this bit is set, the RX module receives all the broadcast frames. RXME Receive Multicast Enable 6 0x0 R/W When this bit is set, the RX module receives all the multicast frames (including broadcast frames). RXUE Receive Unicast 5 0x0 R/W When this bit is set, the RX module receives unicast frames that match the 48-bit Station MAC address of the module. D S00003147A-page 54  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-49: BANK 16 RECEIVE CONTROL REGISTER (0X04) (CONTINUED) Bit Default Value R/W Description RXRA Receive All 4 0x0 R/W When this bit is set, the KSZ8841M receives all incoming frames, regardless of the frame’s destination address. RXSCE Receive Strip CRC When this bit is set, the KSZ8841M strips the CRC on the received 3 0x0 R/W frames. Once cleared, the CRC is stored in memory following the packet. QMU Receive Multicast Hash-Table Enable 2 0x0 R/W When this bit is set, this bit enables the RX function to receive mul- ticast frames that pass the CRC Hash filtering mechanism. 1 — RO Reserved RXE Receive Enable When this bit is set, the RX block is enabled and placed in a run- 0 0x0 R/W ning state. When this bit is cleared, the receive process is placed in the stopped state upon completing reception of the current frame. Bank 16 TXQ Memory Information Register (0x08): TXMIR This register indicates the amount of free memory available in the TXQ of the QMU module. TABLE 4-50: BANK 16 TXQ MEMORY INFORMAT ION REGISTER (0X08) Bit Default Value R/W Description 15 - 13 — RO Reserved TXMA Transmit Memory Available The amount of memory available is represented in units of byte. The TXQ memory is used for both frame payload, control word. 12 - 0 — RO Note: Software must be written to ensure that there is enough memory for the next transmit frame including control information before transmit data is written to the TXQ. Bank 16 RXQ Memory Information Register (0x0A): RXMIR This register indicates the amount of receive data available in the RXQ of the QMU module. TABLE 4-51: BANK 16 RXQ MEMORY INFORMAT ION REGISTER (0X0A) Bit Default Value R/W Description 15 - 13 — RO Reserved RXMA Receive Packet Data Available The amount of Receive packet data available is represented in units of byte. The RXQ memory is used for both frame payload, sta- tus word. There is total 4096 bytes in RXQ. This counter will update 12 - 0 — RO after a complete packet is received and also issues an interrupt when receive interrupt enable IER[13] in Bank 18 is set. Note: Software must be written to empty the RXQ memory to allow for the new RX frame. If this is not done, the frame may be dis- carded as a result of insufficient RXQ memory.  2019 Microchip Technology Inc. D S00003147A-page 55

KSZ8841-16M/-32M Bank 17 TXQ Command Register (0x00): TXQCR This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in the TXQ memory is queued for transmit. TABLE 4-52: B ANK 17 TXQ COMMAND REGISTER (0X00) Bit Default Value R/W Description 15 - 1 — RO Reserved TXETF Enqueue TX Frame When this bit is written as 1, the current TX frame prepared in the TX buffer is queued for transmit. 0 0x0 R/W Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before setting up another new TX frame. Bank 17 RXQ Command Register (0x02): RXQCR This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ frame buffer is read only by the host and the memory space is released. TABLE 4-53: B ANK 17 RXQ COMMAND REGISTER (0X02) Bit Default Value R/W Description 15 - 1 — RO Reserved RXRRF Release RX Frame When this bit is written as 1, the current RX frame buffer is released. 0 0x0 R/W Note: This bit is self-clearing after the frame memory is released. The software should wait for the bit to be cleared before processing new RX frame. Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO incre- ment is set, It will automatically increment the pointer value on Write accesses to the data register. The counter is incremented by one for every byte access, by two for every word access, and by four for every double word access. TABLE 4-54: BANK 17 TX FRAME DATA P OINTER REGISTER (0X04) Bit Default Value R/W Description 15 — RO Reserved TXFPAI TX Frame Data Pointer Auto Increment When this bit is set, the TX Frame data pointer register increments automatically on accesses to the data register. The increment is by 14 0x0 R/W one for every byte access, by two for every word access, and by four for every doubleword access. When this bit is reset, the TX frame data pointer is manually con- trolled by user to access the TX frame location. 13 - 11 — RO Reserved TXFP TX Frame Pointer TX Frame Pointer index to the Frame Data register for access. 10 - 0 0x000 R/W This field reset to next available TX frame location when the TX Frame Data has been enqueued through the TXQ command regis- ter. D S00003147A-page 56  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment is set, it will automatically increment the RXQ Pointer on read accesses to the data register. The counter is incremented is by one for every byte access, by two for every word access, and by four for every double word access. TABLE 4-55: BANK 17 RX FRAME DATA P OINTER REGISTER (0X06) Bit Default Value R/W Description 15 — RO Reserved RXFPAI RX Frame Pointer Auto Increment When this bit is set, the RXQ Address register increments automat- ically on accesses to the data register. The increment is by one for 14 0x0 R/W every byte access, by two for every word access, and by four for every double word access. When this bit is reset, the RX frame data pointer is manually con- trolled by user to access the RX frame location. 13 - 11 — RO Reserved RXFP RX Frame Pointer RX Frame data pointer index to the Data register for access. 10 - 0 0x000 R/W This field reset to next available RX frame location when RX Frame release command is issued (through the RXQ command register). Bank 17 QMU Data Register Low (0x08): QDRL This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps from the RXQ, and writing maps to the TXQ. TABLE 4-56: BANK 17 QMU DATA R EGISTER LOW (0X08) Bit Default Value R/W Description QDRL Queue Data Register Low This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the 15 - 0 — R/W KSZ8841M regardless of whether the pointer is even, odd, or Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This register along with DQRH is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations. Bank 17 QMU Data Register High (0x0A): QDRH This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading maps from the RXQ, and writing maps to the TXQ. TABLE 4-57: BANK 17 QMU DATA R EGISTER HIGH (0X0A) Bit Default Value R/W Description QDRL Queue Data Register High This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the 15 - 0 — R/W KSZ8841M regardless of whether the pointer is even, odd, or Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This register along with DQRL is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations.  2019 Microchip Technology Inc. D S00003147A-page 57

KSZ8841-16M/-32M Bank 18 Interrupt Enable Register (0x00): IER This register enables the interrupts from the QMU and other sources. TABLE 4-58: B ANK 18 INTERRUPT ENABLE REGISTER (0X00) Bit Default Value R/W Description LCIE Link Change Interrupt Enable 15 0x0 R/W When this bit is set, the link change interrupt is enabled. When this bit is reset, the link change interrupt is disabled. TXIE Transmit Interrupt Enable 14 0x0 R/W When this bit is set, the transmit interrupt is enabled. When this bit is reset, the transmit interrupt is disabled. RXIE Receive Interrupt Enable 13 0x0 R/W When this bit is set, the receive interrupt is enabled. When this bit is reset, the receive interrupt is disabled. TXUIE Transmit Underrun Interrupt Enable 12 0x0 R/W When this bit is set, the transmit underrun interrupt is enabled. When this bit is reset, the transmit underrun interrupt is disabled. RXOIE Receive Overrun Interrupt Enable 11 0x0 R/W When this bit is set, the Receive Overrun interrupt is enabled. When this bit is reset, the Receive Overrun interrupt is disabled. RXEIE Receive Early Receive Interrupt Enable 10 0x0 R/W When this bit is set, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. TXPSIE Transmit Process Stopped Interrupt Enable When this bit is set, the Transmit Process Stopped interrupt is 9 0x0 R/W enabled. When this bit is reset, the Transmit Process Stopped interrupt is disabled. RXPSIE Receive Process Stopped Interrupt Enable When this bit is set, the Receive Process Stopped interrupt is 8 0x0 R/W enabled. When this bit is reset, the Receive Process Stopped interrupt is dis- abled. RXEFIE Receive Error Frame Interrupt Enable 7 0x0 R/W When this bit is set, the Receive error frame interrupt is enabled. When this bit is reset, the Receive error frame interrupt is disabled. 6 - 0 — RO Reserved Bank 18 Interrupt Status Register (0x02): ISR This register contains the status bits for all QMU and other interrupt sources. When the corresponding enable bit is set, it causes the interrupt pin to be asserted. This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits are not cleared when read. The user has to write “1” to clear. TABLE 4-59: BANK 18 INTERRUPT STAT US REGISTER (0X02) Bit Default Value R/W Description LCIS Link Change Interrupt Status RO When this bit is set, it indicates that the link status has changed 15 0x0 (W1C) from link up to link down, or link down to link up. This edge-triggered interrupt status is cleared by writing 1 to this bit. D S00003147A-page 58  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-59: BANK 18 INTERRUPT STATUS REGISTER (0X02) (CONTINUED) Bit Default Value R/W Description TXIS Transmit Status When this bit is set, it indicates that the TXQ MAC has transmitted RO 14 0x0 at least a frame on the MAC interface and the QMU TXQ is ready (W1C) for new frames from the host. This edge-triggered interrupt status is cleared by writing 1 to this bit. RXIS Receive Interrupt Status When this bit is set, it indicates that the QMU RXQ has received a RO 13 0x0 frame from the MAC interface and the frame is ready for the host (W1C) CPU to process. This edge-triggered interrupt status is cleared by writing 1 to this bit. TXUIS Transmit Underrun Interrupt Status RO When this bit is set, it indicates that the transmit underrun condition 12 0x0 (W1C) has occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. RXOIS Receive Overrun Interrupt Status RO When this bit is set, it indicates that the Receive Overrun status has 11 0x0 (W1C) occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. RXEIS Receive Early Receive Interrupt Status RO When this bit is set, it indicates that the Early Receive status has 10 0x0 (W1C) occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. TXPSIE Transmit Process Stopped Status RO When this bit is set, it indicates that the Transmit Process has 9 0x0 (W1C) stopped. This edge-triggered interrupt status is cleared by writing 1 to this bit. RXPSIE Receive Process Stopped Status RO When this bit is set, it indicates that the Receive Process has 8 0x0 (W1C) stopped. This edge-triggered interrupt status is cleared by writing 1 to this bit. RXEFIE Receive Error Frame Interrupt Status RO When this bit is set, it indicates that the Receive error frame status 7 0x0 (W1C) has occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. 6 - 0 — RO Reserved Bank 18 Receive Status Register (0x04): RXSR This register indicates the status of the current received frame and mirrors the Receive Status word of the Receive Frame in the RXQ. TABLE 4-60: BANK 18 RECEIVE STAT US REGISTER (0X04) Bit Default Value R/W Description RXFV Receive Frame Valid When set, it indicates that the present frame in the receive packet memory is valid. The status information currently in this location is 15 — RO also valid. When clear, it indicates that there is either no pending receive frame or that the current frame is still in the process of receiving. 14 - 8 — RO Reserved RXBF Receive Broadcast Frame 7 — RO When set, it indicates that this frame has a broadcast address.  2019 Microchip Technology Inc. D S00003147A-page 59

KSZ8841-16M/-32M TABLE 4-60: BANK 18 RECEIVE STATUS REGISTER (0X04) (CONTINUED) Bit Default Value R/W Description RXMF Receive Multicast Frame 6 — RO When set, it indicates that this frame has a multicast address (including the broadcast address). RXUF Receive Unicast Frame 5 — RO When set, it indicates that this frame has a unicast address. RXMR Receive MII Error 4 — RO When set, it indicates that there is an MII symbol error on the received frame. RXFT Receive Frame Type When set, it indicates that the frame is an Ethernet-type frame 3 — RO (frame length is greater than 1500 bytes). When clear, it indicate that the frame is an IEEE 802.3 frame. This bit is not valid for runt frames. RXTL Receive Frame Too Long When set, it indicates that the frame length exceeds the maximum size of 1916 bytes. Frames that are too long are passed to the host 2 — RO only if the pass bad frame bit is set (bit 9 in RXCR register). Note: Frame too long is only a frame length indication and does not cause any frame truncation. RXRF Receive Runt Frame When set, it indicates that a frame was damaged by a collision or 1 — RO premature termination before the collision window has passed. Runt frames are passed to the host only if the pass bad frame bit is set (bit 9 in RXCR register). RXCE Receive CRC Error When set, it indicates that a CRC error has occurred on the current 0 — RO received frame. A CRC error frame is passed to the host only if the pass bad frame bit is set (bit 9 in RXCR register) Bank 18 Receive Byte Count Register (0x06): RXBC This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive Frame in the RXQ. TABLE 4-61: B ANK 18 RECEIVE BYTE COUNT REGISTER (0X06) Bit Default Value R/W Description 15 - 11 — RO Reserved RXBX Receive Byte Count 10 - 0 — RO Receive byte count. Bank 18 Early Transmit Register (0x08): ETXR This register specifies the threshold for the early transmit. TABLE 4-62: BANK 18 EARLY T RANSMIT REGISTER (0X08): ETXR Bit Default Value R/W Description 15 - 8 — RO Reserved TXEE Early Transmit Enable 7 0x0 R/W When this bit is set, the Early Transmit function is enabled. When this bit is cleared, normal operation is assumed. 6- 5 — RO Reserved D S00003147A-page 60  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-62: BANK 18 EARLY TRANSMIT REGISTER (0X08): ETXR (CONTINUED) Bit Default Value R/W Description ETXTH Early Transmit Threshold The threshold for Early Transmit. Specified in unit of 64-byte. Whenever the number of bytes written in memory for the presently 4 - 0 0x00 R/W transmitting packet exceeds the threshold, Early Transmit will be started on the network interface. When early transmit is enabled, setting this field to 0 is invalid, and the hardware behavior is unknown. Bank 18 Early Receive Register (0x0A): ERXR This register specify the threshold for early receive and interrupt condition. TABLE 4-63: BANK 18 EARLY R ECEIVE REGISTER (0X0A) Bit Default Value R/W Description 15 - 8 — RO Reserved RXEE Early Receive Enable 7 0x0 R/W When this bit is set, the Early Receive function is enabled. When this bit is cleared, normal operation is assumed. 6 - 5 — RO Reserved ERXTH Early Receive Threshold The threshold for Early Receive and Interrupt. Specified in unit of 64-byte. Whenever the number of bytes written in memory for the presently received packet exceeds the threshold, early receive sta- 4 - 0 0x1F R/W tus will be set, and Early Receive interrupt will be asserted if its interrupt is enabled. When early receive is enabled, setting this field to 0 is invalid, and the hardware behavior is unknown. Bank 19 Multicast Table Register 0 (0x00): MTR0 The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while the others determine which bit within the register. TABLE 4-64: BANK 19 MULTICAST TA BLE REGISTER 0 (0X00) Bit Default Value R/W Description MTR0 Multicast Table 0 When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being fil- tered. 15 - 0 0x0 R/W When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value.  2019 Microchip Technology Inc. D S00003147A-page 61

KSZ8841-16M/-32M Bank 19 Multicast Table Register 1 (0x02): MTR1 TABLE 4-65: BANK 19 MULTICAST TA BLE REGISTER 1 (0X02) Bit Default Value R/W Description MTR0 Multicast Table 1 When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being fil- tered. 15 - 0 0x0 R/W When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. Bank 19 Multicast Table Register 2 (0x04): MTR2 TABLE 4-66: BANK 19 MULTICAST TA BLE REGISTER 2 (0X04) Bit Default Value R/W Description MTR0 Multicast Table 2 When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being fil- tered. 15 - 0 0x0 R/W When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. Bank 19 Multicast Table Register 3 (0x06): MTR3 TABLE 4-67: BANK 19 MULTICAST TA BLE REGISTER 3 (0X06) Bit Default Value R/W Description MTR0 Multicast Table 3 When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being fil- tered. 15 - 0 0x0 R/W When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. Bank 19 Power Management Control and Status Register (0x08): PMCS The following control and status register provides information on the KSZ8841M power management capabilities. The following table shows the register bit fields. TABLE 4-68: BANK 19 POWER MANAGEMENT CONTROL AND STAT US REGISTER (0X08) Bit Default Value R/W Description PME_Status This bit indicates that the KSZ8841M has detected a power-man- RO agement event. If bit PME_Enable is set, the KSZ8841M also 15 0 (W1C) asserts the PMEN pin. This bit is cleared on power-up reset or by write 1. It is not modified by either hardware or software reset. When this bit is cleared, the KSZ8841M deasserts the PMEN pin. 14 - 9 0x00 RO Reserved PME_Enable If this bit is set, the KSZ8841M can assert the PMEN pin. Other- 8 0 R/W wise, assertion of the PMEN pin is disabled. This bit is cleared on power-up reset and will be not modified by software reset. D S00003147A-page 62  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-68: BANK 19 POWER MANAGEMENT CONTROL AND STATUS REGISTER (0X08) Bit Default Value R/W Description 7 - 4 0x0 RO Reserved No Soft Reset If this bit is set (“1”), the KSZ8841M does not perform an internal reset when transitioning from D3_hot to D0 because of PowerState commands. Configuration context is preserved. Upon transition from D3_hot to the D0 Initialized state, no additional operating sys- tem intervention is required to preserve configuration context beyond writing the PowerState bits. If this bit is cleared (“0”), the KSZ8841M does perform an internal reset when transitioning from D3_hot to D0 via software control of 3 0 RO the PowerState bits. Configuration context is lost when performing the soft reset. Upon transition from D3_hot to the D0 state, full reini- tialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled. The value of this bit is loaded from the NO_SRST bit in the serial EEPROM. 2 0 RO Reserved Power State This field is used to set the new power state of the KSZ8841M as well as to determine its current power state. The definitions of the field values are: 1 - 0 0x0 R/W 00 = D0 -> System is on and running 01 = D1 -> Low-power state 10 = D2 -> Low-power state 11 = D3 (hot) -> System is off and not running Banks 20 – 31: Reserved Except Bank Select Register (0xE). Bank 32 Chip ID and Enable Register (0x00): CIDER This register contains the chip ID and the chip enable bit. TABLE 4-69: BANK 32 CHIP ID A ND ENABLE REGISTER (0X00) Bit Default Value R/W Description Family ID 15 - 8 0x88 RO Chip family ID Chip ID 7 - 4 0x1 RO 0x1 is assigned to KSZ8841M 3 - 1 0x1 RO Revision ID 0 0 RO Reserved  2019 Microchip Technology Inc. D S00003147A-page 63

KSZ8841-16M/-32M Bank 32 Chip Global Control Register (0x0A): CGCR This register contains the global control for the chip function. TABLE 4-70: BANK 32 CHIP GLOBAL CONTROL R EGISTER (0X0A) Bit Default Value R/W Description LEDSEL1 15 0 R/W See description for bit 9. 14 - 12 0 R/W Reserved 11 - 10 0x2 R/W Reserved LEDSEL0 This register bit sets the LEDSEL0 selection only. Port 1 LED indicators, defined as below: [LEDSEL1, LEDSEL0] [0, 0] [0, 1] P1LED3 — — P1LED2 Link/Activity 100Link/Activity 9 0 R/W P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex [LEDSEL1, LEDSEL0] [1, 0] [1, 1] P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed — 8 0 R/W Reserved 7 - 0 0x35 R/W Reserved Banks 33 – 41: Reserved Except Bank Select Register (0xE) Bank 42 Indirect Access Control Register (0x00): IACR This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read or write access is determined by register bit 12). TABLE 4-71: BANK 42 INDIRECT ACCESS CONTROL R EGISTER (0X00) Bit Default Value R/W Description 15 - 13 0x0 R/W Reserved 12 0 R/W Read High. Write Low 1 = Read cycle. 0 = Write cycle. 11 - 10 0x0 R/W Table Select 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = MIB counter selected. 9 - 0 0x000 R/W Indirect Address Bit 9-0 of indirect address. D S00003147A-page 64  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 42 Indirect Access Data Register 1 (0x02): IADR1 This register contains the indirect data for the chip function. TABLE 4-72: BANK 42 INDIRECT ACCESS DATA R EGISTER 1 (0X02) Bit Default Value R/W Description 15 - 0 0x0000 RO Reserved Bank 42 Indirect Access Data Register 2 (0x04): IADR2 This register contains the indirect data for the chip function. TABLE 4-73: BANK 42 INDIRECT ACCESS DATA R EGISTER 2 (0X04) Bit Default Value R/W Description 15 - 0 0x0000 RO Reserved Bank 42 Indirect Access Data Register 3 (0x06): IADR3 This register contains the indirect data for the chip function. TABLE 4-74: BANK 42 INDIRECT ACCESS DATA R EGISTER 3 (0X06) Bit Default Value R/W Description 15 - 0 0x0000 RO Reserved Bank 42 Indirect Access Data Register 4 (0x08): IADR4 This register contains the indirect data for the chip function. TABLE 4-75: BANK 42 INDIRECT ACCESS DATA R EGISTER 4 (0X08) Bit Default Value R/W Description Indirect Data 15 - 0 0x0000 R/W Bit 15-0 of indirect data. Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 This register contains the indirect data for the chip function. TABLE 4-76: BANK 42 INDIRECT ACCESS DATA R EGISTER 5 (0X0A) Bit Default Value R/W Description Indirect Data 15 - 0 0x0000 R/W Bit 31-16 of indirect data. Bank 43– 44: Reserved Except Bank Select Register (0xE) Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification. TABLE 4-77: BANK 45 PHY 1 MII-REGISTER BASIC CONTROL R EGISTER (0X00) Bit Default Value R/W Description Bit Same As Soft reset 15 0 RO — Not supported. 14 0 R/W Reserved — Force 100 13 0 R/W 1 = Force 100Mbps if AN is disabled (bit 12) Bank49 0x2 bit6 0 = Force 10Mbps if AN is disabled (bit 12) AN Enable 12 1 R/W 1 = Auto-negotiation enabled. Bank49 0x2 bit7 0 = Auto-negotiation disabled.  2019 Microchip Technology Inc. D S00003147A-page 65

KSZ8841-16M/-32M TABLE 4-77: BANK 45 PHY 1 MII-REGISTER BASIC CONTROL REGISTER (0X00) (CONTINUED) Bit Default Value R/W Description Bit Same As Power-Down Bank49 0x2 11 0 R/W 1 = Power-down. bit11 0 = Normal operation. Isolate 10 0 RO — Not supported. Restart AN Bank49 0x2 9 0 R/W 1 = Restart auto-negotiation. bit13 0 = Normal operation. Force Full Duplex 1 = Force full-duplex 8 0 R/W Bank49 0x2 bit5 0 = Force half-duplex. If AN is disabled (bit 12) or AN is enabled but failed. Collision test 7 0 RO — Not supported. 6 0 RO Reserved — HP_mdix Bank49 0x4 5 1 R/W 1 = HP Auto MDI-X mode. bit15 0 = Microchip Auto MDI-X mode. Force MDI-X 4 0 R/W 1 = Force MDI-X. Bank49 0x2 bit9 0 = Normal operation. Disable MDI-X Bank49 0x2 3 0 R/W 1 = Disable auto MDI-X. bit10 0 = Normal operation. Bank49 0x2 2 0 R/W Reserved bit12 Disable Transmit Bank49 0x2 1 0 R/W 1 = Disable transmit. bit14 0 = Normal operation. Disable LED Bank49 0x2 0 0 R/W 1 = Disable LED. bit15 0 = Normal operation. Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR This register contains the MII register status for the chip function. TABLE 4-78: BANK 45 PHY 1 MII-REGISTER BASIC STAT US REGISTER (0X02) Bit Default Value R/W Description Bit Same As T4 Capable 15 0 RO 1 = 100BASE-T4 capable. — 0 = not 100BASE-T4 capable. 100 Full Capable 14 1 RO 1 = 100BASE-TX full-duplex capable. — 0 = Not 100BASE-TX full-duplex.capable. 100 Half Capable 13 1 RO 1= 100BASE-TX half-duplex capable. — 0= Not 100BASE-TX half-duplex capable. 10 Full Capable 12 1 RO 1 = 10BASE-T full-duplex capable. — 0 = Not 10BASE-T full-duplex capable. D S00003147A-page 66  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-78: BANK 45 PHY 1 MII-REGISTER BASIC STATUS REGISTER (0X02) (CONTINUED) Bit Default Value R/W Description Bit Same As 10 Half Capable 11 1 RO 1 = 10BASE-T half-duplex capable. — 0 = Not 10BASE-T half-duplex capable. 10 - 7 0 RO Reserved — Preamble suppressed 6 0 RO — Not supported. AN Complete 5 0 RO 1 = Auto-negotiation complete. Bank49 0x4 bit6 0 = Auto-negotiation not completed. 4 0 RO Reserved Bank49 0x4 bit8 AN Capable 3 1 RO 1 = Auto-negotiation capable. — 0 = Not auto-negotiation capable. Link Status 2 0 RO 1 = Link is up. Bank49 0x4 bit5 0 = Link is down. Jabber test 1 0 RO — Not supported. Extended Capable 0 0 RO 1 = Extended register capable. — 0 = Not extended register capable. Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR This register contains the PHY ID (low) for the chip. TABLE 4-79: BANK 45 PHY 1 PHYID LOW REGISTER (0X04) Bit Default Value R/W Description PHYID Low 15 - 0 0x1430 RO Low order PHYID bits. Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR This register contains the PHY ID (high) for the chip. TABLE 4-80: BANK 45 PHY 1 PHYID HIGH REGISTER (0X06) Bit Default Value R/W Description PHYID High 15 - 0 0x0022 RO High order PHYID bits. Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR This register contains the auto-negotiation advertisement for the PHY function. TABLE 4-81: BANK 45 PHY 1 AUTO-NEGOTIATION A DVERTISEMENT REGISTER (0X08) Bit Default Value R/W Description Bit Same As Next page 15 0 RO — Not supported. 14 0 RO Reserved — Remote fault 13 0 RO — Not supported. 12 - 11 0 RO Reserved —  2019 Microchip Technology Inc. D S00003147A-page 67

KSZ8841-16M/-32M TABLE 4-81: BANK 45 PHY 1 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (0X08) Bit Default Value R/W Description Bit Same As Pause (flow control capability) 10 1 R/W 1 = Advertise pause capability. Bank49 0x2 bit4 0 = Do not advertise pause capability. 9 0 R/W Reserved — Adv 100 Full 8 1 R/W 1 = Advertise 100 full-duplex capability. Bank49 0x2 bit3 0 = Do not advertise 100 full-duplex capability Adv 100 Half 7 1 R/W 1= Advertise 100 half-duplex capability. Bank49 0x2 bit2 0 = Do not advertise 100 half-duplex capability. Adv 10 Full 6 1 R/W 1 = Advertise 10 full-duplex capability. Bank49 0x2 bit1 0 = Do not advertise 10 full-duplex capability. Adv 10 Half 5 1 R/W 1 = Advertise 10 half-duplex capability. Bank49 0x2 bit0 0 = Do not advertise 10 half-duplex capability. Selector Field 4 - 0 0x01 RO — 802.3 Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR This register contains the auto-negotiation link partner ability for the chip function. TABLE 4-82: BANK 45 PHY 1 AUTO-NEGOTIATION LINK PARTNER ABILITY R EGISTER (0X0A) Bit Default Value R/W Description Bit Same As Next page 15 0 RO — Not supported. LP ACK 14 0 RO — Not supported. Remote fault 13 0 RO — Not supported. 12 - 11 0 RO Reserved — Pause 10 0 RO Bank49 0x4 bit4 Link partner pause capability. 9 0 RO Reserved — Adv 100 Full 8 0 RO Bank49 0x4 bit3 Link partner 100 full capability. Adv 100 Half 7 0 RO Bank49 0x4 bit2 Link partner 100 half capability. Adv 10 Full 6 0 RO Bank49 0x4 bit1 Link partner 10 full capability. Adv 10 Half 5 0 RO Bank49 0x4 bit0 Link partner 10 half capability. 4 - 0 0x01 RO Reserved — Bank 46: Reserved Except Bank Select Register (0xE) D S00003147A-page 68  2019 Microchip Technology Inc.

KSZ8841-16M/-32M Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT This register contains the LinkMD control and status information of PHY 1. TABLE 4-83: BANK 47 PHY1 LINKMD CONTROL/STAT US (0X00): P1VCT Bit Default Value R/W Description Bit Same As Vct_enable R/W 1 = Cable diagnostic test is enabled. It is self-cleared after Bank49 0x0 15 0 (Self- the VCT test is done. bit 12 Clear) 0 = Indicates that the cable diagnostic test is completed and the status information is valid for read. Vct_result [00] = Normal condition. Bank49 0x0 14 - 13 0 RO [01] = Open condition detected in the cable. bit 14 - 13 [10] = Short condition detected in the cable. [11] = Cable diagnostic test failed. Vct 10M Short Bank49 0x0 12 — RO 1 = Less than 10m short. bit 15 11 - 9 0x0 RO Reserved — Vct_fault_count Bank49 0x0 8 - 0 0x000 RO Distance to the fault. The distance is approximately bit 8 - 0 0.4m*vct_fault_count. Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL This register contains the control and status information of PHY1. TABLE 4-84: BANK 47 PHY1 SPECIAL CONTROL/STATUS REGISTER (0X02): P1PHYCTRL Bit Default Value R/W Description Bit Same As 15 - 6 0x000 RO Reserved — Polarity Reverse (polrvs) Bank49 0x04 5 0 RO 1 = Polarity is reversed. bit 13 0 = Polarity is not reversed. MDIX Status (mdix_st) Bank49 0x04 4 0 RO 1 = MDI bit 7 0 = MDIX Force Link (force_lnk) Bank49 0x00 3 0 R/W 1 = Force link pass. b it11 0 = Normal operation. Power Saving (pwrsave) Bank49 0x00 2 1 R/W 1 = Disable power saving. b it10 0 = Enable power saving. Remote (Near-end) Loopback (rlb) 1 = Perform remote loopback at PHY (RXP1/RXM1 -> Bank49 0x00 1 0 R/W TXP1/TXM1, see Figure 12) b it9 0 = Normal operation 0 0 R/W Reserved — Bank 48: Reserved Except Bank Select Register (0xE)  2019 Microchip Technology Inc. D S00003147A-page 69

KSZ8841-16M/-32M Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD TABLE 4-85: BANK 49 PORT 1 PHY SPECIAL CONTROL/STAT US, LINKMD (0X00) Bit Default Value R/W Description Bit Same As Vct_10m_short Bank 47 0x00 15 0 RO 1 = Less than 10 meter short. bit 12 Vct_result VCT result. [00] = Normal condition. Bank 47 0x00 14 - 13 0 RO [01] = Open condition has been detected in cable. bit 14 - 13 [10] = Short condition has been detected in cable. [11] = Cable diagnostic test is failed. Vct_en Vct enable. R/W 1 = The cable diagnostic test is enabled. It is self-cleared Bank 47 0x00 12 0 (Self- after the VCT test is done. bit 15 Clear) 0 = Indicates the cable diagnostic test is completed and the status information is valid for read. Force_lnk Force link. Bank 47 0x02 11 0 R/W 1 = Force link pass. bit 3 0 = Normal operation. pwrsave Power-saving. Bank 47 0x02 10 1 R/W 1 = Disable power saving. bit 2 0 = Enable power saving. Remote (Near-end) loopback (rlb) 1 = Perform remote loopback at PHY Bank 47 0x02 9 0 R/W (RXP1/RXM1 -> TXP1/TXM1, see Figure 12) bit 1 0 = Normal operation Vct_fault_count VCT fault count. Bank 47 0x00 8 - 0 0x000 RO Distance to the fault. It’s approximately bit 8 - 0 0.4m*vct_fault_count. Bank 49 Port 1 Control Register 4 (0x02): P1CR4 This register contains the global per port control for the chip function. TABLE 4-86: BANK 49 PORT 1 CONTROL R EGISTER 4 (0X02) Bit Default Value R/W Description Bit Same As LED Off 1 = Turn off all of the port 1 LEDs (P1LED3, P1LED2, Bank 45 0x00 15 0 R/W P1LED1, P1LED0). These pins are driven high if this bit is bit 0 set to one. 0 = Normal operation. Txids Bank 45 0x00 14 0 R/W 1 = Disable the port’s transmitter. bit 1 0 = Normal operation. Restart AN Bank 45 0x00 13 0 R/W 1 = Restart auto-negotiation. bit 9 0 = Normal operation. Bank 45 0x00 12 0 R/W Reserved bit 2 D S00003147A-page 70  2019 Microchip Technology Inc.

KSZ8841-16M/-32M TABLE 4-86: BANK 49 PORT 1 CONTROL REGISTER 4 (0X02) (CONTINUED) Bit Default Value R/W Description Bit Same As Power Down Bank 45 0x00 11 0 R/W 1 = Power down. bit 11 0 = Normal operation. Disable auto MDI/MDI-X Bank 45 0x00 10 0 R/W 1 = Disable auto MDI/MDI-X function. bit 3 0 = Enable auto MDI/MDI-X function. Force MDI-X 1= If auto MDI/MDI-X is disabled, force PHY into MDI-X Bank 45 0x00 9 0 R/W mode. bit 4 0 = Do not force PHY into MDI-X mode. 8 0 R/W Reserved — Auto-Negotiation Enable 1 = Auto-negotiation is enabled. Bank 45 0x00 7 1 R/W 0 = Disable auto negotiation, speed, and duplex are bit 12 decided by bits 6 and 5 of the same register. Force Speed Bank 45 0x00 6 0 R/W 1 = Force 100BT if AN is disabled (bit 7). bit 13 0 = Force 10BT if AN is disabled (bit 7). Force Duplex 1 = Force full-duplex if (1) AN is disabled or (2) AN is Bank 45 0x00 5 0 R/W enabled but failed. bit 8 0 = Force half-duplex if (1) AN is disabled or (2) AN is enabled but failed. Advertised flow control capability. 1 = Advertise flow control (pause) capability. Bank 45 0x08 4 1 R/W 0 = Suppress flow control (pause) capability from trans- bit 10 mission to link partner. Advertised 100BT full-duplex capability. 1 = Advertise 100BT full-duplex capability. Bank 45 0x08 3 1 R/W 0 = Suppress 100BT full-duplex capability from transmis- bit 8 sion to link partner. Advertised 100BT half-duplex capability. 1 = Advertise 100BT half-duplex capability. Bank 45 0x08 2 1 R/W 0 = Suppress 100BT half-duplex capability from transmis- bit 7 sion to link partner. Advertised 10BT full-duplex capability. 1 = Advertise 10BT full-duplex capability. Bank 45 0x08 1 1 R/W 0 = Suppress 10BT full-duplex capability from transmis- bit 6 sion to link partner. Advertised 10BT half-duplex capability. 1 = Advertise 10BT half-duplex capability. Bank 45 0x08 0 1 R/W 0 = Suppress 10BT half-duplex capability from transmis- bit 5 sion to link partner.  2019 Microchip Technology Inc. D S00003147A-page 71

KSZ8841-16M/-32M Bank 49 Port 1 Status Register (0x04): P1SR This register contains the global per port status for the chip function. TABLE 4-87: BANK 49 PORT 1 STAT US REGISTER (0X04) Bit Default Value R/W Description Same Bit As HP_mdix Bank 45 0x00 15 1 R/W 1 = HP Auto MDI-X mode. bit 5 0 = Microchip Auto MDI-X mode. 14 0 RO Reserved — Polarity Reverse Bank 47 0x02 13 0 RO 1 = Polarity is reversed. bit 5 0 = Polarity is not reversed. Receive Flow Control Enable 12 0 RO 1 = Receive flow control feature is active. — 0 = Receive flow control feature is inactive. Transmit Flow Control Enable 11 0 RO 1 = Transmit flow control feature is active. — 0 = Transmit flow control feature is inactive. Operation Speed 10 0 RO 1 = Link speed is 100Mbps. — 0 = Link speed is 10Mbps. Operation Duplex 9 0 RO 1 = Link duplex is full. — 0 = Link duplex is half. Bank 45 0x02 8 0 RO Reserved bit 4 MDI-X status Bank 47 0x02 7 0 RO 1 = MDI. bit 4 0 = MDI-X. AN Done Bank 45 0x02 6 0 RO 1 = AN done. bit 5 0 = AN not done. Link Good Bank 45 0x02 5 0 RO 1 = Link good. bit 2 0 = Link not good. Partner flow control capability. Bank 45 0x0A 4 0 RO 1 = Link partner flow control (pause) capable. bit 10 0 = Link partner not flow control (pause) capable. Partner 100BT full-duplex capability. Bank 45 0x0A 3 0 RO 1 = Link partner 100BT full-duplex capable. bit 8 0 = Link partner not 100BT full-duplex capable. Partner 100BT half-duplex capability. Bank 45 0x0A 2 0 RO 1 = Link partner 100BT half-duplex capable. bit 7 0 = Link partner not 100BT half-duplex capable. Partner 10BT full-duplex capability. Bank 45 0x0A 1 0 RO 1 = Link partner 10BT full-duplex capable. bit 6 0 = Link partner not 10BT full-duplex capable. Partner 10BT half-duplex capability. Bank 45 0x0A 0 0 RO 1 = Link partner 10BT half-duplex capable. bit 5 0 = Link partner not 10BT half-duplex capable. Banks 50 – 63: Reserved Except Bank Select Register (0xE) D S00003147A-page 72  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 4.3 Management Information Base (MIB) Counters The KSZ8841M provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown below. TABLE 4-88: FORMAT OF MIB COUNTERS Bit Name R/W Description Default 31 Overflow RO 1 = Counter overflow. 0 0 = No counter overflow. 30 Count Valid RO 1 = Counter value is valid. 0 0 = Counter value is not valid. 29 - 0 Counter Values RO Counter value (read clear) 0x00000000 Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. TABLE 4-89: PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS Offset Counter Name Description 0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets 0x1 Reserved Reserved 0x2 RxUndersizePkt Rx undersize packets w/ good CRC 0x3 RxFragments Rx fragment packets w/ bad CRC, symbol errors or alignment errors 0x4 RxOversize Rx oversize packets w/ good CRC (max: 1536 bytes) Rx packets longer than 1536 bytes w/ either CRC errors, alignment 0x5 RxJabbers errors, or symbol errors 0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size. Rx packets within (64,1916) bytes w/ an integral number of bytes and 0x7 RxCRCError a bad CRC Rx packets within (64,1916) bytes w/ a non-integral number of bytes 0x8 RxAlignmentError and a bad CRC Number of MAC control frames received by a port with 88-08h in 0x9 RxControl8808Pkts EtherType field Number of PAUSE frames received by a port. PAUSE frame is quali- 0xA RxPausePkts fied with EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC Rx good broadcast packets (not including error broadcast packets or 0xB RxBroadcast valid multicast packets) Rx good multicast packets (not including MAC control frames, error 0xC RxMulticast multicast packets or valid broadcast packets) 0xD RxUnicast Rx good unicast packets 0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length Total Rx packets (bad packets included) that are between 65 and 127 0xF Rx65to127Octets octets in length Total Rx packets (bad packets included) that are between 128 and 0x10 Rx128to255Octets 255 octets in length Total Rx packets (bad packets included) that are between 256 and 0x11 Rx256to511Octets 511 octets in length Total Rx packets (bad packets included) that are between 512 and 0x12 Rx512to1023Octets 1023 octets in length Total Rx packets (bad packets included) that are between 1024 and 0x13 Rx1024to1522Octets 1916 octets in length 0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets 0x15 Reserved Reserved  2019 Microchip Technology Inc. D S00003147A-page 73

KSZ8841-16M/-32M TABLE 4-89: PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS (CONTINUED) Offset Counter Name Description The number of times a collision is detected later than 512 bit-times 0x16 TxLateCollision into the Tx of a packet 0x17 TxPausePkts Number of PAUSE frames transmitted by a port Tx good broadcast packets (not including error broadcast or valid 0x18 TxBroadcastPkts multicast packets) Tx good multicast packets (not including error multicast packets or 0x19 TxMulticastPkts valid broadcast packets) 0x1A TxUnicastPkts Tx good unicast packets Tx packets by a port for which the 1st Tx attempt is delayed due to 0x1B TxDeferred the busy medium 0x1C TxTotalCollision Tx total collision, half-duplex only 0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly 0x1E TxSingleCollision one collision Successfully Tx frames on a port for which Tx is inhibited by more 0x1F TxMultipleCollision than one collision Example: 1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E) Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow // If bit 30 = 0, restart (re-read) from this register Read reg. IADR4 (MIB counter value 15-0) 4.3.1 ADDITIONAL MIB INFORMATION In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read. D S00003147A-page 74  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (V , V , V )..........................................................................................................................–0.5V to +4.0V DDATX DDARX DDIO Input Voltage (all inputs)............................................................................................................................–0.5V to +5.0V Output Voltage (all outputs).......................................................................................................................–0.5V to +4.0V Lead Temperature (soldering, 10s).......................................................................................................................+270°C Storage Temperature (T )......................................................................................................................–55°C to +150°C S *Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level. 5.2 Operating Ratings** Supply Voltage (V , V , V )..........................................................................................................................+3.1V to +3.5V DDATX DDARX DDIO Ambient Operating Temperature for Commercial Options (T )....................................................................0°C to +70°C A Ambient Operating Temperature for Industrial Options (T )....................................................................–40°C to +85°C A Maximum Junction Temperature (T )....................................................................................................................+125°C J Thermal Resistance (N ote5-1) (Θ )...........................................................................................................+42.91°C/W JA Thermal Resistance (N ote5-1) (Θ ).............................................................................................................+19.6°C/W JC **The device is not guaranteed to function outside its operating ratings. Unused inputs must always be tied to an appro- priate logic voltage level (Ground to VDD). Note 5-1 No heat spreader (HS) in this package. The Θ /Θ is under air velocity 0 m/s. JC JA Note: Do not drive input signals without power supplied to the device.  2019 Microchip Technology Inc. D S00003147A-page 75

KSZ8841-16M/-32M 6.0 ELECTRICAL CHARACTERISTICS T = 25°C. Specification is for packaged product only. Single port’s transformer consumes an additional 4 5mA @ 3.3V A f or 100BASE-TX and 70mA @ 3.3V for 10BASE-T. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note Supply Current for 100BASE-TX Operation (Single Port @ 100% Utilization) 100BASE-TX (analog core + PLL + VDDATX, VDDARX, VDDIO = 3.3V; I — 100 — mA digital core + transceiver + DDXIO Chip only (no transformer) digital I/O) Supply Current for 10BASE-T Operation (Single Port @ 100% Utilization) 10BASE-T (analog core + PLL + VDDATX, VDDARX, VDDIO = 3.3V; I — 85 — mA digital core + transceiver + DDXIO Chip only (no transformer) digital I/O) CMOS Inputs Input High Voltage V 2.0 — — V — IH Input Low Voltage V — — 0.8 V — IL Input Current I –10 — 10 μA V = GND ~ V IN IN DDIO CMOS Outputs Output High Voltage V 2.4 — — V I = –8mA OH OH Output Low Voltage V — — 0.4 V I = 8mA OL OL Output Tri-State Leakage |I | — — 10 μA — OZ 100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output 100Ω termination across differential V ±0.95 — ±1.05 V Voltage O output. 100Ω termination across differential Output Voltage Imbalance V — — 2 % IMB output. Rise/Fall Time t/t 3 — 5 ns — r f Rise/Fall Time Imbalance — 0 — 0.5 ns — Duty Cycle Distortion — — — ±0.25 ns — Overshoot — — — 5 % — Reference Voltage of I V — 0.5 — V — SET SET Output Jitter — — 0.7 1.4 ns Peak-to-peak 10BASE-T Receive Squelch Threshold V — 400 — mV 5 MHz square wave SQ 10BASE-T Transmit (measured differentially after 1:1 transformer) Peak Differential Output 100Ω termination across differential V — 2.4 — V Voltage P output. Peak-to-peak, 100Ω termination Jitter Added — — 1.8 3.5 ns across differential output D S00003147A-page 76  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.0 TIMING SPECIFICATIONS 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) FIGURE 7-1: ASYNCHRONOUS CYCLE – ADSN = 0 t2 Addr, AEN, BExN valid ADSN t3 t4 Read Data valid t1 t5 RDN, WRN t6 Write Data valid t7 ARDY t9 (Read Cycle) t8 ARDY t10 (Write Cycle) TABLE 7-1: ASYNCHRONOUS CYCLE (ADSN = 0) TIMING PA RAMETERS Symbol Parameter Min. Typ. Max. Units t1 A1-A15, AEN, BExN[3:0] valid to RDN, WRN active 0 — — ns A1-A15, AEN, BExN[3:0] hold after RDN inactive (assume ADSN tied 0 — — Low) t2 ns A1-A15, AEN, BExN[3:0] hold after WRN inactive (assume ADSN 1 — — tied Low) t3 Read data valid to ARDY rising — — 0.8 ns t4 Read data to hold RDN inactive 4 — — ns t5 Write data setup to WRN inactive 4 — — ns t6 Write data hold after WRN inactive 2 — — ns t7 Read active to ARDY Low — — 8 ns t8 Write inactive to ARDY Low — — 8 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 40ns to read QMU data 0 40 — register in turbo mode) (N ote7-2) t9 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 80ns to read QMU data 0 80 — register in normal mode) ARDY low (wait time) in write cycle (N ote7-1) t10 ( It is 0ns to write bank select register) 0 50 — ns ( It is 36ns to write QMU data register) Note 7-1 When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/ WRN low until the ARDY returns to high. Note 7-2 In order to speed up the ARDY low time to 4 0ns, user has to use the turbo software driver which is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.  2019 Microchip Technology Inc. D S00003147A-page 77

KSZ8841-16M/-32M 7.2 Asynchronous Timing using Address Strobe (ADSN) FIGURE 7-2: ASYNCHRONOUS CYCLE – USING ADSN t8 Addr, AEN, BExN valid t6 ADSN Read Data valid t1 t4 t3 RDN, WRN t5 Write Data valid t7 t2 ARDY t10 (Read Cycle) t9 ARDY t11 (Write Cycle) TABLE 7-2: ASYNCHRONOUS CYCLE USING ADSN TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units t1 A1-A15, AEN, BExN[3:0] valid to RDN, WRN active 0 — — ns t2 Read data valid to ARDY rising — — 0.8 ns t3 Read data hold to RDN inactive 4 — — ns t4 Write data setup to WRN inactive 4 — — ns t5 Write data hold after WRN inactive 2 — — ns t6 A1-A15, AEN, nBE[3:0] setup to ADSN rising 4 — — ns t7 Read active to ARDY Low — — 8 ns t8 A1-A15, AEN, BExN[3:0] hold after ADSN rising 2 — — ns t9 Write inactive to ARDY Low — — 8 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 40ns to read QMU data 0 40 — register in turbo mode) (N ote7-2) t10 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 80ns to read QMU data 0 80 — register in normal mode) ARDY low (wait time) in write cycle (N ote7-1) t11 ( It is 0ns to write bank select register) 0 50 — ns ( It is 36ns to write QMU data register) Note 7-1 When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/ WRN low until the ARDY returns to high. Note 7-2 In order to speed up the ARDY low time to 4 0ns, user has to use the turbo software driver which is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail. D S00003147A-page 78  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.3 Asynchronous Timing using DATACSN FIGURE 7-3: ASYNCHRONOUS CYCLE – USING DATACSN t2 DATACSN Read Data valid t1 t5 t4 RDN, WRN t6 Write Data valid t7 t3 ARDY t9 (Read Cycle) t8 ARDY t10 (Write Cycle) TABLE 7-3: ASYNCHRONOUS CYCLE USING DATACSN TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units t1 DATACSN setup to RDN, WRN active 2 — — ns t2 DATACSN hold after RDN, WRN inactive (assume ADSN tied Low) 0 — — ns t3 Read data hold to ARDY rising — — 0.8 ns t4 Read data to RDN hold 4 — — ns t5 Write data setup to WRN inactive 4 — — ns t6 Write data hold after WRN inactive 2 — — ns t7 Read active to ARDY Low — — 8 ns t8 Write inactive to ARDY Low — — 8 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 40ns to read QMU data 0 40 — register in turbo mode) (N ote7-2) t9 ns ARDY low (wait time) in read cycle (N ote7-1) ( It is 0n s to read bank select register and 80ns to read QMU data 0 80 — register in normal mode) ARDY low (wait time) in write cycle (N ote7-1) t10 ( It is 0ns to write bank select register) 0 50 — ns ( It is 36ns to write QMU data register) Note 7-1 When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/ WRN low until the ARDY returns to high. Note 7-2 In order to speed up the ARDY low time to 4 0ns, user has to use the turbo software driver which is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.  2019 Microchip Technology Inc. D S00003147A-page 79

KSZ8841-16M/-32M 7.4 Address Latching Timing for All Modes FIGURE 7-4: ADDRESS LATCHING CYCLE FOR ALL MODES t1 ADSN t2 Address, AEN, BExN t3 LDEVN TABLE 7-4: ADDRESS LATCHING TIMING P ARAMETERS Symbol Parameter Min. Typ. Max. Units t1 A1-A15, AEN, BExN[3:0] setup to ADSN 4 — — ns t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising 2 — — ns t3 A4-A15, AEN to LDEVN delay — — 5 ns D S00003147A-page 80  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) FIGURE 7-5: SYNCHRONOUS BURST WRITE CYCLES – VLBUSN = 1 TABLE 7-5: SYNCHRONOUS BURST WRITE TIMING PARAMETERS Symbol Parameter Min. Max. Units t1 SWR setup to BCLK falling 4 — ns t2 DATDCSN setup to BCLK rising 4 — ns t3 CYCLEN setup to BCLK rising 4 — ns t4 Write data setup to BCLK rising 6 — ns t5 Write data hold to BCLK rising 2 — ns t6 RDYRTNN setup to BCLK falling 5 — ns t7 RDYRTNN hold to BCLK falling 3 — ns t8 SRDYN setup to BCLK rising 4 — ns t9 SRDYN hold to BCLK rising 3 — ns t10 DATACSN hold to BCLK rising 2 — ns t11 SWR hold to BCLK falling 2 — ns t12 CYCLEN hold to BCLK 2 — ns  2019 Microchip Technology Inc. D S00003147A-page 81

KSZ8841-16M/-32M 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) FIGURE 7-6: SYNCHRONOUS BURST READ CYCLES – VLBUSN = 1 BCLK t2 t10 DATACSN t1 t11 SWR t12 t3 CYCLEN t5 t4 Read Data data0 data1 data2 data3 t7 t6 RDYRTNN t8 t9 SRDYN TABLE 7-6: SYNCHRONOUS BURST READ TIMING PARAMETERS Symbol Parameter Min. Max. Units t1 SWR setup to BCLK falling 4 — ns t2 DATDCSN setup to BCLK rising 4 — ns t3 CYCLEN setup to BCLK rising 4 — ns t4 Read data setup to BCLK rising 6 — ns t5 Read data hold to BCLK rising 2 — ns t6 RDYRTNN setup to BCLK falling 5 — ns t7 RDYRTNN hold to BCLK falling 3 — ns t8 SRDYN setup to BCLK rising 4 — ns t9 SRDYN hold to BCLK rising 3 — ns t10 DATACSN hold to BCLK rising 2 — ns t11 SWR hold to BCLK falling 2 — ns t12 CYCLEN hold to BCLK 2 — ns D S00003147A-page 82  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.7 Synchronous Write Timing (VLBUSN = 0) FIGURE 7-7: SYNCHRONOUS WRITE CYCLE – VLBUSN = 0 BCLK t2 Address, AEN, BExN valid t1 ADSN t5 t6 SWR t4 t3 CYCLEN t7 t8 Write Data valid t9 t10 SRDYN t11 t12 RDYRTNN TABLE 7-7: SYNCHRONOUS WRITE (VLBUSN = 0) TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising 4 — — ns t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising 2 — — ns t3 CYCLEN setup to BCLK rising 4 — — ns t4 CYCLEN hold after BCLK rising (non-burst mode) 2 — — ns t5 SWR setup to BCLK 4 — — ns t6 SWR hold after BCLK rising with SRDYN active 0 — — ns t7 Write data setup to BCLK rising 5 — — ns t8 Write data hold from BCLK rising 1 — — ns t9 SRDYN setup to BCLK 8 — — ns t10 SRDYN hold to BCLK 1 — — ns t11 RDYRTNN setup to BCLK 4 — — ns t12 RDYRTNN hold to BCLK 1 — — ns  2019 Microchip Technology Inc. D S00003147A-page 83

KSZ8841-16M/-32M 7.8 Synchronous Read Timing (VLBUSN = 0) FIGURE 7-8: SYNCHRONOUS READ CYCLE – VLBUSN = 0 BCLK t2 Address, AEN, BExN valid t1 ADSN t5 SWR t4 t3 CYCLEN t7 t6 Read Data valid t8 t9 SRDYN t10 t11 RDYRTNN TABLE 7-8: SYNCHRONOUS READ (VLBUSN = 0) TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising 4 — — ns t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising 2 — — ns t3 CYCLEN setup to BCLK rising 4 — — ns t4 CYCLEN hold after BCLK rising (non-burst mode) 2 — — ns t5 SWR setup to BCLK 4 — — ns t6 Read data hold from BCLK rising 1 — — ns t7 Read data setup to BCLK 8 — — ns t8 SRDYN setup to BCLK 8 — — ns t9 SRDYN hold to BCLK 1 — — ns t10 RDYRTNN setup to BCLK rising 4 — — ns t11 RDYRTNN hold after BCLK rising 1 — — ns D S00003147A-page 84  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.9 Auto-Negotiation Timing FIGURE 7-9: AUTO-NEGOTIATION TIMING TABLE 7-9: AUTO-NEGOTIATION TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units t FLP burst to FLP burst 8 16 24 ms BTB t FLP burst width — 2 — ms FLPW t Clock/Data pulse width — 100 — ns PW t Clock pulse to data pulse 55.5 64 69.5 μs CTD t Clock pulse to clock pulse 111 128 139 μs CTC — Number of Clock/Data pulses per burst 17 — 33 —  2019 Microchip Technology Inc. D S00003147A-page 85

KSZ8841-16M/-32M 7.10 Reset Timing As long as the stable supply voltages to reset High timing (minimum of 1 0ms) are met, there is no power-sequencing requirement for the KSZ8841M supply voltages (3.3V). The reset timing requirement is summarized in F igure7-10 and T able7-10. FIGURE 7-10: RESET TIMING Supply Voltage tsr RST_N TABLE 7-10: RESET TIMING P ARAMETERS Parameter Description Min. Typ. Max. Units t Stable supply voltages to reset high 10 — — ms SR D S00003147A-page 86  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 7.11 EEPROM Timing FIGURE 7-11: EEPROM READ CYCLE TIMING DIAGRAM EECS *1 EESK 1 tcyc ts EEDO 11 0 An A0 th High-Z EEDI D15 D14 D13 D1 D0 *1 Start bit TABLE 7-11: EEPROM TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units 4 (OBCR[1:0]=11 on-chip b us speed @ 25MHz) or t Clock cycle — — μs CYC 0.8 (OBCR[1:0]=00 on-chip bus speed @ 1 25MHz) t Setup time 20 — — ns S t Hold time 20 — — ns h  2019 Microchip Technology Inc. D S00003147A-page 87

KSZ8841-16M/-32M 8.0 SELECTION OF ISOLATION TRANSFORMERS A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. T able8-1 lists recommended transformer characteristics. TABLE 8-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 3 50μH 1 00mV, 100k Hz, 8mA Leakage Inductance (max.) 0 .4μH 1 MHz (min.) Interwinding Capacitance (max.) 1 2pF — D.C. Resistance (max.) 0.9Ω — Insertion Loss (max.) 1 .0dB 0 M Hz to 65MHz HIPOT (min.) 1 500V — RMS TABLE 8-2: QUALIFIED SINGLE-PORT MAGNETICS Manufacturer Part Number Auto MDI-X Bel Fuse S558-5999-U7 Yes Delta LF8505 Yes LanKom LF-H41S Yes Pulse H1102 Yes Pulse (Low Cost) H1260 Yes Transpower HB726 Yes TDK (Mag Jack) TLA-6T718 Yes TABLE 8-3: TYPICAL REFERENCE CRYSTAL CHARACTERISTICS Characteristic Value Frequency 2 5MHz Frequency Tolerance (max.) ± 50ppm Load Capacitance (max.) 2 0pF Series Resistance 25Ω D S00003147A-page 88  2019 Microchip Technology Inc.

KSZ8841-16M/-32M 9.0 PACKAGE OUTLINE 9.1 Package Marking Information 128-Lead PQFP* 128-Lead LQFP* Example 100-Lead LFBGA* MICREL MICREL XXXXXXX-XX KSZ8841-16 YYWWA7 1912A5 XXXXXYYWWNNN G00001912710 YYWWNNN 1912710 Legend: XX...X Product code or customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e 3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. ●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.  2019 Microchip Technology Inc. D S00003147A-page 89

KSZ8841-16M/-32M FIGURE 9-1: 128-LEAD PQFP 1 4M M X 20MM PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. D S00003147A-page 90  2019 Microchip Technology Inc.

KSZ8841-16M/-32M FIGURE 9-2: 128-LEAD LQFP 14M M X 14MM PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.  2019 Microchip Technology Inc. D S00003147A-page 91

KSZ8841-16M/-32M FIGURE 9-3: 100-LEAD LFBGA 1 0M M X 10MM PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. D S00003147A-page 92  2019 Microchip Technology Inc.

KSZ8841-16M/-32M APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction Converted Micrel data sheet KSZ8841-16M/-32M to DS00003147A (07-22-19) — Microchip DS00003147A. Minor text changes throughout.  2019 Microchip Technology Inc. D S00003147A-page 93

KSZ8841-16M/-32M THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi- cation” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu- ment. Technical support is available through the web site at: http://microchip.com/support D S00003147A-page 94  2019 Microchip Technology Inc.

KSZ8841-16M/-32M PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. -XX X X X [X] [-XX] a) KSZ8841-16MQL 8-Bit or 16-Bit Bus Design, Non-PCI Interface Device Bus Interface Package Supply Temperature Media 128-lead PQFP, Single 3.3V Power Supply Design Voltage Type Commercial Temperature Range 66/Tray b) KSZ8841-16MBL Device: KSZ8841: Single-Port Ethernet MAC Controller with Non-PCI 8-Bit or 16-Bit Bus Design, Non-PCI Interface Interface 100-lead LFBGA, Single 3.3V Power Supply Commercial Temperature Range 240/Tray Bus Design: -16 = 8-bit or 16-bit c) KSZ8841-16MBLI -32 = 32-bit (Not available for LFBGA option) 8-Bit or 16-Bit Bus Design, Non-PCI Interface 100-lead LFBGA, Single 3.3V Power Supply Industrial Temperature Range Interface: M = Management Interface 240/Tray d) KSZ8841-16MVL 8-Bit or 16-Bit Bus Design, Non-PCI Interface Package: Q = 128-lead PQFP 128-lead LQFP, Single 3.3V Power Supply B = 100-lead LFBGA Commercial Temperature Range V = 128-lead LQFP 90/Tray e) KSZ8841-16MVLI 8-Bit or 16-Bit Bus Design, Non-PCI Interface Supply Voltage: L = Single 3.3V Power Supply Supported with Internal 1.8V 128-lead LQFP, Single 3.3V Power Supply LDO Industrial Temperature Range 90/Tray f) KSZ8841-16MVL-TR Temperature: <blank> = 0C to +70C (Commercial) 8-Bit or 16-Bit Bus Design, Non-PCI Interface I = –40C to +85C (Industrial) 128-lead LQFP, Single 3.3V Power Supply Commercial Temperature Range 1,000/Reel Media Type: <blank> = 66/Tray (PQFP option) <blank> = 240/Tray (LFBGA option) g) KSZ8841-16MVLI-TR <blank> = 90/Tray (LQFP option) 8-Bit or 16-Bit Bus Design, Non-PCI Interface TR = 1,000/Reel 128-lead LQFP, Single 3.3V Power Supply Industrial Temperature Range 1,000/Reel h) KSZ8841-32MQL 32-Bit Bus Design, Non-PCI Interface 128-lead PQFP, Single 3.3V Power Supply Commercial Temperature Range 66/Tray i) KSZ8841-32MVL 32-Bit Bus Design, Non-PCI Interface 128-lead LQFP, Single 3.3V Power Supply Commercial Temperature Range 90/Tray j) KSZ8841-32MVLI 32-Bit Bus Design, Non-PCI Interface 128-lead LQFP, Single 3.3V Power Supply Industrial Temperature Range 90/Tray Note1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2019 Microchip Technology Inc. D S00003147A-page 95

KSZ8841-16M/-32M NOTES: D S00003147A-page 96  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic- itly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4832-7 For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2019 Microchip Technology Inc. D S00003147A-page 97

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