Not Recommended for New Designs ISO7240A ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 1-Mbps QUAD DIGITAL ISOLATORS CheckforSamples:ISO7240A,ISO7241A,ISO7242A FEATURES 1 • 4000-V Isolation,560-V V APPLICATIONS peak peak IORM – UL1577,IEC60747-5-2(VDE0884,Rev2), • IndustrialFieldbus IEC61010-1,IEC60950-1andCSA • ComputerPeripheralInterface Approved • ServoControlInterface • 4kVESDProtection • DataAcquisition • OperateWith3.3-Vor5-VSupplies • Typical25-YearLifeatRatedWorkingVoltage (SeeApplicationNote(SLLA197)and Figure10) • HighElectromagneticImmunity (SeeApplicationReport(SLLA181)) • –40°Cto125°COperatingRange DESCRIPTION See the Product Notificationsection. The ISO7240A, ISO7241A and ISO7242A are quad-channel digital isolators with multiple channel configurations and output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide (SiO ) isolation barrier. Used in conjunction with isolated power supplies, 2 these devices block high voltage, isolate grounds, and prevent noise currents from entering the local ground and interferingwithordamagingsensitivecircuitry. The ISO7240A has all four channels in the same direction while the ISO7241A has three channels the same directionandonechannelinopposition.TheISO7242Ahastwochannelsineachdirection. The devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passedtotheoutputofthedevice. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drivestheoutputtoalogichighstate.(SeeISO7240CF(SLLS869)orcontactTIforalogiclowfailsafeoption). These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V, 5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supplylevelbeingused. Thesedevicesarecharacterizedforoperationovertheambienttemperaturerangeof–40°Cto125°C. ISO7240A ISO7241A ISO7242A VCC1 1 16 VCC2 VCC1 1 16 VCC2 VCC1 1 16 VCC2 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 INA 3 14 OUTA INA 3 14 OUTA INA 3 14 OUTA INB 4 13 OUTB INB 4 13 OUTB INB 4 13 OUTB INC 5 12 OUTC INC 5 12 OUTC OUTC 5 12 INC IND 6 11 OUTD OUTD 6 11 IND OUTD 6 11 IND NC 7 10 EN EN1 7 10 EN2 EN1 7 10 EN2 GND1 8 9 GND2 GND1 8 9 GND2 GND1 8 9 GND2 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008–2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + Vref Pulse Width Demodulation PWM Carrier Detect EN Input Data MUX AC Detect IN + Vref OUT Filter Output Buffer AC Channel Table1.DeviceFunctionTableISO724x (1) INPUT OUTPUTENABLE OUTPUT INPUTV OUTPUTV CC CC (IN) (EN) (OUT) H HorOpen H L HorOpen L PU PU X L Z Open HorOpen H PD PU X HorOpen H PD PU X L Z (1) PU=PoweredUp;PD=PoweredDown;X=Irrelevant;H=HighLevel;L=LowLevel AVAILABLEOPTIONS SIGNALING INPUT CHANNEL MARKED ORDERING PRODUCT RATE THRESHOLD CONFIGURATION AS NUMBER(1) ~1.5V(TTL) ISO7240ADW(rail) ISO7240ADW 1Mbps 4/0 ISO7240A (CMOScompatible) ISO7240ADWR(reel) ~1.5V(TTL) ISO7241ADW(rail) ISO7241ADW 1Mbps 3/1 ISO7241A (CMOScompatible) ISO7241ADWR(reel) ~1.5V(TTL) ISO7242ADW(rail) ISO7242ADW 1Mbps 2/2 ISO7242A (CMOScompatible) ISO7242ADWR(reel) (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. 2 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT V Supplyvoltage(2),V ,V –0.5to6 V CC CC1 CC2 V VoltageatIN,OUT,EN –0.5to6 V I I Outputcurrent ±15 mA O HumanBodyModel JEDECStandard22,TestMethodA114-C.01 ±4 Electrostatic Field-Induced-ChargedDevice kV ESD JEDECStandard22,TestMethodC101 Allpins ±1 discharge Model MachineModel ANSI/ESDS5.2-1996 ±200 V T Maximumjunctiontemperature 170 °C J (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttonetworkgroundterminalandarepeakvoltagevalues. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT V Supplyvoltage(1),V ,V 3.15 5.5 V CC CC1 CC2 I High-leveloutputcurrent 4 mA OH I Low-leveloutputcurrent –4 mA OL t Inputpulsewidth ISO724xA 1 ms ui 1/t Signalingrate ISO724xA 0 1000 kbps ui V High-levelinputvoltage(IN)(ENonalldevices) 2 V V IH CC ISO724xA V Low-levelinputvoltage(IN)(ENonalldevices) 0 0.8 V IL T Junctiontemperature 150 °C J Externalmagneticfield-strengthimmunityperIEC61000-4-8andIEC61000-4-9 H 1000 A/m certification (1) Forthe5-Voperation,V orV isspecifiedfrom4.5Vto5.5V. CC1 CC2 Forthe3-Voperation,V orV isspecifiedfrom3.15Vto3.6V. CC1 CC2 IEC 60747-5-2 INSULATION CHARACTERISTICS(1) overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS SPECIFICATIONS UNIT V Maximumworkinginsulationvoltage 560 V IORM AfterInput/OutputSafetyTestSubgroup2/3 V =V ×1.2,t=10s, 672 V PR IORM Partialdischarge<5pC Methoda,V =V ×1.6, PR IORM V Inputtooutputtestvoltage Typeandsampletestwitht=10s, 896 V PR Partialdischarge<5pC Methodb1,V =V ×1.875, PR IORM 100%Productiontestwitht=1s, 1050 V Partialdischarge<5pC V Transientovervoltage t=60s 4000 V IOTM R Insulationresistance V =500VatT >109 Ω S IO S Pollutiondegree 2 (1) ClimaticClassification40/125/21 Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com ELECTRICAL CHARACTERISTICS: V and V at 5-V(1) OPERATION CC1 CC2 ,overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT Quiescent 1 3 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 1 3 Quiescent V =V or0V,Allchannels,noload,EN at3V, I ISO7241A I CC 1 6.5 11 mA CC1 1Mbps EN2at3V Quiescent V =V or0V,Allchannels,noload,EN at3V, 10 16 ISO7242A I CC 1 mA 1Mbps EN2at3V 10 16 Quiescent 15 22 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 16 22 Quiescent V =V or0V,Allchannels,noload,EN at3V, 13 20 I ISO7241A I CC 1 mA CC2 1Mbps EN2at3V 13 20 Quiescent V =V or0V,Allchannels,noload,EN at3V, 10 16 ISO7242A I CC 1 mA 1Mbps EN2at3V 10 16 ELECTRICALCHARACTERISTICS I Sleepmodeoutputcurrent ENat0V,Singlechannel 0 mA OFF I =–4mA,SeeFigure1 V –0.8 OH CC V High-leveloutputvoltage V OH I =–20mA,SeeFigure1 V –0.1 OH CC I =4mA,SeeFigure1 0.4 OL V Low-leveloutputvoltage V OL I =20mA,SeeFigure1 0.1 OL V Inputvoltagehysteresis 150 mV I(HYS) I High-levelinputcurrent 10 IH INfrom0VtoV mA CC I Low-levelinputcurrent –10 IL C Inputcapacitancetoground INatV ,V =0.4sin(4E6pt) 2 pF I CC I CMTI Common-modetransientimmunity V =V or0V,SeeFigure4 25 50 kV/ms I CC (1) Forthe5-Voperation,V orV isspecifiedfrom4.5Vto5.5V. CC1 CC2 Forthe3-Voperation,V orV isspecifiedfrom3.15Vto3.6V. CC1 CC2 SWITCHING CHARACTERISTICS: V and V at 5-V OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelay 40 95 PLH PHL SeeFigure1 ns PWD Pulse-widthdistortion(1)|t –t | 10 PHL PLH t Channel-to-channeloutputskew (2) 2 ns sk(o) t Outputsignalrisetime 2 r SeeFigure1 ns t Outputsignalfalltime 2 f t Propagationdelay,high-level-to-high-impedanceoutput 15 20 PHZ t Propagationdelay,high-impedance-to-high-leveloutput 15 20 PZH SeeFigure2 ns t Propagationdelay,low-level-to-high-impedanceoutput 15 20 PLZ t Propagationdelay,high-impedance-to-low-leveloutput 15 20 PZL t Failsafeoutputdelaytimefrominputpowerloss SeeFigure3 12 ms fs (1) Alsoreferredtoaspulseskew. (2) t istheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthe sk(o) samedirectionwhiledrivingidenticalspecifiedloads. 4 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 ELECTRICAL CHARACTERISTICS: V at 5-V, V at 3.3-V(1) OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT Quiescent 1 3 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 1 3 Quiescent V =V or0V,Allchannels,noload,EN at3V, I ISO7241A I CC 1 6.5 11 mA CC1 1Mbps EN2at3V Quiescent V =V or0V,Allchannels,noload,EN at3V, 10 16 ISO7242A I CC 1 mA 1Mbps EN2at3V 10 16 Quiescent 9.5 15 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 10 15 Quiescent V =V or0V,Allchannels,noload,EN at3V, 8 13 I ISO7241A I CC 1 mA CC2 1Mbps EN2at3V 8 13 Quiescent V =V or0V,Allchannels,noload,EN at3V, 6 10 ISO7242A I CC 1 mA 1Mbps EN2at3V 6 10 ELECTRICALCHARACTERISTICS I Sleepmodeoutputcurrent ENat0V,Singlechannel 0 mA OFF ISO7240A V –0.4 CC I =–4mA,SeeFigure1 OH V High-leveloutputvoltage ISO724x(5-Vside) V –0.8 V OH CC I =–20mA,SeeFigure1 V –0.1 OH CC I =4mA,SeeFigure1 0.4 OL V Low-leveloutputvoltage V OL I =20mA,SeeFigure1 0.1 OL V Inputvoltagehysteresis 150 mV I(HYS) I High-levelinputcurrent 10 IH INfrom0VtoV mA CC I Low-levelinputcurrent –10 IL C Inputcapacitancetoground INatV ,V =0.4sin(4E6pt) 2 pF I CC I CMTI Common-modetransientimmunity V =V or0V,SeeFigure4 25 50 kV/ms I CC (1) Forthe5-Voperation,V orV isspecifiedfrom4.5Vto5.5V. CC1 CC2 Forthe3-Voperation,V orV isspecifiedfrom3.15Vto3.6V. CC1 CC2 SWITCHING CHARACTERISTICS: V at 5-V, V at 3.3-V OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelay 40 100 PLH PHL SeeFigure1 ns PWD Pulse-widthdistortion(1)|t –t | 11 PHL PLH 3 t Channel-to-channeloutputskew (2) ns sk(o) 0 1 t Outputsignalrisetime 2 r SeeFigure1 ns t Outputsignalfalltime 2 f t Propagationdelay,high-level-to-high-impedanceoutput 15 20 PHZ t Propagationdelay,high-impedance-to-high-leveloutput 15 20 PZH SeeFigure2 ns t Propagationdelay,low-level-to-high-impedanceoutput 15 20 PLZ t Propagationdelay,high-impedance-to-low-leveloutput 15 20 PZL t Failsafeoutputdelaytimefrominputpowerloss SeeFigure3 18 ms fs (1) Alsoknownaspulseskew (2) t istheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthe sk(o) samedirectionwhiledrivingidenticalspecifiedloads. Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com ELECTRICAL CHARACTERISTICS: V at 3.3-V, V at 5-V(1) OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT Quiescent 0.5 1 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 1 2 Quiescent 4 7 I ISO7241A V =V or0V,Allchannels,noload,EN at3V,EN at3V mA CC1 I CC 1 2 1Mbps 4 7 Quiescent 6 10 ISO7242A V =V or0V,Allchannels,noload,EN at3V,EN at3V mA I CC 1 2 1Mbps 6 10 Quiescent 15 22 ISO7240A V =V or0V,Allchannels,noload,EN at3V mA I CC 2 1Mbps 16 22 Quiescent 13 20 I ISO7241A V =V or0V,Allchannels,noload,EN at3V,EN at3V mA CC2 I CC 1 2 1Mbps 13 20 Quiescent 10 16 ISO7242A V =V or0V,Allchannels,noload,EN at3V,EN at3V mA I CC 1 2 1Mbps 10 16 ELECTRICALCHARACTERISTICS I Sleepmodeoutputcurrent ENatV ,Singlechannel 0 mA OFF CC ISO7240A V –0.4 CC I =–4mA,SeeFigure1 OH V High-leveloutputvoltage ISO724x(5-Vside) V –0.8 V OH CC I =–20mA,SeeFigure1 V –0.1 OH CC I =4mA,SeeFigure1 0.4 OL V Low-leveloutputvoltage V OL I =20mA,SeeFigure1 0.1 OL V Inputvoltagehysteresis 150 mV I(HYS) I High-levelinputcurrent 10 IH INfrom0VtoV mA CC I Low-levelinputcurrent –10 IL C Inputcapacitanceto INatV ,V =0.4sin(4E6pt) 2 I CC I pF ground Common-modetransient V =V or0V,SeeFigure4 CMTI I CC 25 50 kV/ms immunity (1) Forthe5-Voperation,V orV isspecifiedfrom4.5Vto5.5V. CC1 CC2 Forthe3-Voperation,V orV isspecifiedfrom3.15Vto3.6V. CC1 CC2 SWITCHING CHARACTERISTICS: V at 3.3-V and V at 5-V OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelay 40 100 PLH PHL SeeFigure1 ns PWD Pulse-widthdistortion(1)|t –t | 11 PHL PLH 2.5 t Channel-to-channeloutputskew (2) ns sk(o) 0 1 t Outputsignalrisetime 2 r SeeFigure1 ns t Outputsignalfalltime 2 f t Propagationdelay,high-level-to-high-impedanceoutput 15 20 PHZ t Propagationdelay,high-impedance-to-high-leveloutput 15 20 PZH SeeFigure2 ns t Propagationdelay,low-level-to-high-impedanceoutput 15 20 PLZ t Propagationdelay,high-impedance-to-low-leveloutput 15 20 PZL t Failsafeoutputdelaytimefrominputpowerloss SeeFigure3 12 ms fs (1) Alsoknownaspulseskew (2) t istheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthe sk(o) samedirectionwhiledrivingidenticalspecifiedloads. 6 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 ELECTRICAL CHARACTERISTICS: V and V at 3.3 V(1) OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT Quiescent 0.5 1 ISO7240A V =V or0V,allchannels,noload,EN at3V mA I CC 2 1Mbps 1 2 Quiescent V =V or0V,allchannels,noload,EN at3V, 4 7 I ISO7241A I CC 1 CC1 1Mbps EN2at3V 4 7 mA Quiescent V =V or0V,allchannels,noload,EN at3V, 6 10 ISO7242A I CC 1 1Mbps EN2at3V 6 10 Quiescent 9.5 15 ISO7240A V =V or0V,allchannels,noload,EN at3V mA I CC 2 1Mbps 10 15 Quiescent V =V or0V,allchannels,noload,EN at3V, 8 13 I ISO7241A I CC 1 CC2 1Mbps EN2at3V 8 13 mA Quiescent V =V or0V,allchannels,noload,EN at3V, 6 10 ISO7242A I CC 1 1Mbps EN2at3V 6 10 ELECTRICALCHARACTERISTICS I Sleepmodeoutputcurrent ENat0V,singlechannel 0 mA OFF I =–4mA,SeeFigure1 V –0.4 OH CC V High-leveloutputvoltage V OH I =–20mA,SeeFigure1 V –0.1 OH CC I =4mA,SeeFigure1 0.4 OL V Low-leveloutputvoltage V OL I =20mA,SeeFigure1 0.1 OL V Inputvoltagehysteresis 150 mV I(HYS) I High-levelinputcurrent 10 IH INfrom0VorV mA CC I Low-levelinputcurrent –10 IL C Inputcapacitancetoground INatV ,V =0.4sin(4E6pt) 2 pF I CC I CMTI Common-modetransientimmunity V =V or0V,SeeFigure4 25 50 kV/ms I CC (1) Forthe5-Voperation,V orV isspecifiedfrom4.5Vto5.5V. CC1 CC2 Forthe3-Voperation,V orV isspecifiedfrom3.15Vto3.6V. CC1 CC2 SWITCHING CHARACTERISTICS: V and V at 3.3-V OPERATION CC1 CC2 overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelay 45 110 PLH PHL SeeFigure1 ns PWD Pulse-widthdistortion|t –t |(1) 12 PHL PLH 3.5 t Channel-to-channeloutputskew (2) sk(o) 0 1 ns t Outputsignalrisetime 2 r SeeFigure1 t Outputsignalfalltime 2 f t Propagationdelay,high-level-to-high-impedanceoutput 15 20 PHZ t Propagationdelay,high-impedance-to-high-leveloutput 15 20 PZH SeeFigure2 ns t Propagationdelay,low-level-to-high-impedanceoutput 15 20 PLZ t Propagationdelay,high-impedance-to-low-leveloutput 15 20 PZL t Failsafeoutputdelaytimefrominputpowerloss SeeFigure3 18 ms fs (1) Alsoreferredtoaspulseskew. (2) t istheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthe sk(o) samedirectionwhiledrivingidenticalspecifiedloads. Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com PARAMETER MEASUREMENT INFORMATION ER VCC1 RRI VI VCC1/2 VCC1/2 A IN B OUT 0 V Input TION tPLH tPHL GNeOneTrEatAor VI 50W SOLA VO NCOLTE B VO 50% 90% 50%VOH I tr 10% tf VOL A. Theinputpulseissuppliedbyageneratorhavingthefollowingcharacteristics:PRR≤50kHz,50%dutycycle,t ≤3 r ns,t ≤3ns,Z =50Ω. f O B. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L Figure1. SwitchingCharacteristicTestCircuitandVoltageWaveforms V cc Vcc R = 1 kW±1% RIER L VI Vcc/2 Vcc/2 0V IN ATIONBAR OUT VO tPZL tPLZ 0VcVc ISOL EN CL VO 50% 0.5V Input NOTE V OL Generator VI 50W B NOTEA R E Vcc RRI V 3V IN NBA OUT O VI Vcc/2 Vcc/2 O 0V TI OLA EN tPZH V IS CL RL= 1 kW±1% OH Input NOTE VO 50% 0.5V Generator VI 50W B t 0V PHZ NOTEA A. Theinputpulseissuppliedbyageneratorhavingthefollowingcharacteristics:PRR≤50kHz,50%dutycycle,t ≤3 r ns,t ≤3ns,Z =50Ω. f O B. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L Figure2. Enable/DisablePropagationDelayTimeTestCircuitandWaveform 8 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 PARAMETER MEASUREMENT INFORMATION (continued) V I VCC1 R VCC1 E RI 2.7 V V0Co CVr1 IN TION BAR OUT VO VI tfs 0 V A V ISOL NCOLTE B VO 50% OH fs low V OL A. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L B. Theinputpulseissuppliedbyageneratorhavingthefollowingcharacteristics:PRR≤50kHz,50%dutycycle,t ≤3 r ns,t ≤3ns,Z =50Ω. f O Figure3. FailsafeDelayTimeTestCircuitandVoltageWaveforms VCC1 VCC2 C = 0.1mF± 1% C = 0.1mF± 1% R E Pass-fail criteria: RRI Output must IN BA OUT remain stable S1 N O TI A OL NOTE B VOHor VOL S I GND1 GND2 VCM A. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L B. Theinputpulseissuppliedbyageneratorhavingthefollowingcharacteristics:PRR≤50kHz,50%dutycycle,t ≤3 r ns,t ≤3ns,Z =50Ω. f O Figure4. Common-ModeTransientImmunityTestCircuitandVoltageWaveform Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER TESTCONDITIONS MIN TYP MAX UNIT L(I01) Minimumairgap(Clearance) Shortestterminal-to-terminaldistancethroughair 8.34 mm Shortestterminal-to-terminaldistanceacrossthe L(I02) Minimumexternaltracking(Creepage) 8.1 mm packagesurface Trackingresistance(comparative C DINIEC60112/VDE0303Part1 ≥175 V TI trackingindex) MinimumInternalGap(Internal Distancethroughtheinsulation 0.008 mm Clearance) R Isolationresistance Inputtooutput,VIO=500V,allpinsoneachsideofthe >1012 Ω IO barriertiedtogethercreatingatwo-terminaldevice C BarriercapacitanceInputtooutput V =0.4sin(4E6pt) 2 pF IO I C Inputcapacitancetoground V =0.4sin(4E6pt) 2 pF I I IEC60664-1RATINGSTABLE PARAMETER TESTCONDITIONS SPECIFICATION Basicisolationgroup Materialgroup IIIa Ratedmainsvoltage≤150VRMS I-IV Installationclassification Ratedmainsvoltage≤300VRMS I-III REGULATORYINFORMATION VDE CSA UL CertifiedaccordingtoIEC ApprovedunderCSAComponentAcceptance Recognizedunder1577ComponentRecognition 60747-5-2 Notice Program(1) FileNumber:40016131 FileNumber:1698195 FileNumber:E181974 (1) Productiontested≥3000Vrmsfor1secondinaccordancewithUL1577. DEVICE I/O SCHEMATICS Enable Input Output V VCC VCC VCC VCC VCC VCC CC 1 MW 1 MW 500W 500W 8W EN IN OUT 13W 10 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 THERMAL CHARACTERISTICS overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Low-KThermalResistance(1) 168 q Junction-to-air °C/W JA High-KThermalResistance 96.1 q Junction-to-BoardThermalResistance 61 °C/W JB q Junction-to-CaseThermalResistance 48 °C/W JC V =V =5.5V,T =150°C,C =15pF, P DevicePowerDissipation CC1 CC2 J L 220 mW D Inputa50%dutycyclesquarewave (1) TestedinaccordancewiththeLow-KorHigh-KthermalmetricdefinitionsofEIA/JESD51-3forleadedsurfacemountpackages. Spacer Spacer TYPICAL CHARACTERISTIC CURVES INPUTVOLTAGETHRESHOLD V FAILSAFETHRESHOLD CC1 vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 1.4 3 V at 5 V or 3.3 V, 5 V V CC 1.35 th+ 2.9 Load = 15 pF, Air Flow at 7/cf/m, V 2.8 Low-K Board put Voltage Threshold - V 11..11112...55123 5 V Vth- 3.3 V Vth+ ALoirw F_loKw B aota 7rd cf/m, VF-ailsafe Threshold - CC1 22222.....34567 Vfs+ Vfs- n I 2.2 1.05 3.3 V Vth- 2.1 1 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA- Free-Air Temperature -°C T - Free-Air Temperature -°C A Figure5. Figure6. HIGH-LEVELOUTPUTCURRENT LOW-LEVELOUTPUTCURRENT vs vs HIGH-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE 50 50 V = 5 V Load = 15 pF, Load = 15 pF, CC TA= 25°C 45 TA= 25°C 40 40 A A V = 3.3 V m 35 ut Current - m 30 CC put Current - 2350 VCC= 3.3 V VCC= 5 V utp 20 Out 20 - OO I- O 15 I 10 10 5 0 0 0 2 4 6 0 1 2 3 4 5 VO- Output Voltage - V VO- Output Voltage - V Figure7. Figure8. Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com APPLICATION INFORMATION 2 mm 2 mm VCC1 max. from max. from VCC2 VCC1 VCC2 0.1mF 0.1mF 1 16 GND1 GND2 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC IND 6 11 OUTD EN NC 7 10 GND1 GND2 8 9 ISO7240A Figure9. TypicalISO7240AApplicationCircuit Spacer LIFEEXPECTANCYvs.WORKINGVOLTAGE 100 S R A E Y E -- VIORMat 560-V F LI 28Years G N KI R O W 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (V ) -- V IORM Figure10. Time-DependantDielectricBreakdownTestingResults 12 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A www.ti.com SLLS905E–MAY2008–REVISEDJANUARY2010 PRODUCT NOTIFICATION An ISO724xA anomaly occurs when a negative-going pulse below the specified 1 ms minimum bit width is input tothedevice.Theoutputlocksinalogic-lowconditionuntilthenextrisingedgeoccursaftera1msperiod. Positive noise edges in pulses of less than the minimum specified 1 ms have no effect on the device, and are properlyfiltered. To prevent noise from interfering with ISO724xA performance, it is recommended that an appropriately sized capacitorbeplacedoneachinputofthedevice Figure11. ISO724xAAnomaly REVISION HISTORY ChangesfromOriginal(May2008)toRevisionA Page • ChangedInthePACKAGECHARACTERISTICStable,line1,changeL MINvaluefrom7.7mmto8.34mm. ........... 10 (IO1) ChangesfromRevisionA(July2008)toRevisionB Page • Addedinformationtothe1stFeaturebullettoincludeCSAandIEC60950-1certification ................................................. 1 • ChangedFigure9From:20mmmax.fromV To:2mmmax.fromV . ........................................................................ 12 CCx CCx ChangesfromRevisionB(December2008)toRevisionC Page • ChangedI forQuiescentand1MbpsFrom:10mATo:11mA ......................................................................................... 4 CC1 • ChangedI forQuiescentand1MbpsFrom:10mATo:11mA ......................................................................................... 5 CC1 ChangesfromRevisionC(March2009)toRevisionD Page • ChangedTheInputcircuitintheDEVICEI/OSCHEMATICSillustration. ......................................................................... 10 Copyright©2008–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ISO7240AISO7241AISO7242A

ISO7240A Not Recommended for New Designs ISO7241A ISO7242A SLLS905E–MAY2008–REVISEDJANUARY2010 www.ti.com ChangesfromRevisionD(December2009)toRevisionE Page • AddedtheIEC60747-5-2INSULATIONCHARACTERISTICtable ..................................................................................... 3 • AddedC -Trackingresistance(comparativetrackingindextothePACKAGECHARACTERISTICStable ................... 10 TI • AddedtheIEC60664-1RATINGSTABLE......................................................................................................................... 10 14 SubmitDocumentationFeedback Copyright©2008–2010,TexasInstrumentsIncorporated ProductFolderLink(s):ISO7240AISO7241AISO7242A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ISO7240ADW NRND SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7240A & no Sb/Br) ISO7240ADWG4 NRND SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7240A & no Sb/Br) ISO7240ADWR NRND SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7240A & no Sb/Br) ISO7241ADW NRND SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7241A & no Sb/Br) ISO7241ADWR NRND SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7241A & no Sb/Br) ISO7241ADWRG4 NRND SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7241A & no Sb/Br) ISO7242ADW NRND SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7242A & no Sb/Br) ISO7242ADWR NRND SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7242A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ISO7241A : •Enhanced Product: ISO7241A-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ISO7240ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7241ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7242ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ISO7240ADWR SOIC DW 16 2000 350.0 350.0 43.0 ISO7241ADWR SOIC DW 16 2000 350.0 350.0 43.0 ISO7242ADWR SOIC DW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016B SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4221009/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) SEE SEE DETAILS DETAILS 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 8 9 8 9 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL HV / ISOLATION OPTION 7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE LAND PATTERN EXAMPLE SCALE:4X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4221009/B 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 8 9 8 9 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL HV / ISOLATION OPTION 7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:4X 4221009/B 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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