Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 2 ISO154x Low-Power Bidirectional I C Isolators 1 Features 3 Description • Isolatedbidirectional,I2Ccompatible, The ISO1540 and ISO1541 devices are low-power, 1 bidirectional isolators that are compatible with I2C communication interfaces. These devices have logic input and output • Supportsupto1-MHzoperation buffers that are separated by Texas Instruments • 3-Vto5.5-Vsupplyrange Capacitive Isolation technology using a silicon dioxide • Open-drainoutputsWith3.5-mASide1and35- (SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate mASide2sinkcurrentcapability grounds,andpreventnoisecurrentsfromenteringthe • –40°Cto+125°Coperatingtemperature local ground and interfering with or damaging • ±50-kV/µstransientimmunity(Typical) sensitivecircuitry. • HBMESDprotectionof4kVonallpins; This isolation technology provides for function, 8kVonbuspins performance, size, and power consumption • Safety-relatedcertifications: advantages when compared to optocouplers. The ISO1540 and ISO1541 devices enable a complete – 4242-V isolationperDINVDEV0884- PK isolated I2C interface to be implemented within a 11:2017-01 smallformfactor. – 2500-V isolationfor1minuteperUL1577 RMS The ISO1540 has two isolated bidirectional channels – CSAapprovalperIEC60950-1andIEC for clock and data lines while the ISO1541 has a 62368-1endequipmentstandards bidirectional data and a unidirectional clock channel. – CQCbasicinsulationperGB4943.1-2011 The ISO1541 is useful in applications that have a single master while the ISO1540 is suitable for multi- 2 Applications master applications. For applications where clock stretching by the slave is possible, the ISO1540 • IsolatedI2Cbuses deviceshouldbeused. • SMBusandPMBusinterfaces Isolated bidirectional communication is accomplished • Open-drainnetworks within these devices by offsetting the low-level output • Motorcontrolsystems voltage on side 1 to a value greater than the high- • Batterymanagement level input voltage on side 1, thus preventing an internal logic latch that otherwise would occur with • I2Clevelshifting standarddigitalisolators. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) ISO1540 SOIC(8) 4.90mm×3.91mm ISO1541 (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic VCC1 VCC2 or cit a SDA1 ap SDA2 or SCL1 n C or SCL2 o ati ol s GND1 I GND2 VREF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................18 2 Applications........................................................... 1 8.2 FunctionalBlockDiagrams.....................................18 3 Description............................................................. 1 8.3 FeatureDescription.................................................19 8.4 IsolatorFunctionalPrinciple....................................19 4 RevisionHistory..................................................... 2 8.5 DeviceFunctionalModes........................................20 5 PinConfigurationandFunctions......................... 4 9 ApplicationandImplementation........................ 21 6 Specifications......................................................... 5 9.1 ApplicationInformation............................................21 6.1 AbsoluteMaximumRatings......................................5 9.2 TypicalApplication..................................................23 6.2 ESDRatings..............................................................6 10 PowerSupplyRecommendations..................... 25 6.3 RecommendedOperatingConditions.......................6 11 Layout................................................................... 25 6.4 ThermalInformation..................................................6 6.5 PowerRatings...........................................................6 11.1 LayoutGuidelines.................................................25 6.6 InsulationSpecifications............................................7 11.2 LayoutExample....................................................26 6.7 Safety-RelatedCertifications.....................................8 12 DeviceandDocumentationSupport................. 27 6.8 SafetyLimitingValues..............................................8 12.1 DocumentationSupport........................................27 6.9 ElectricalCharacteristics...........................................9 12.2 RelatedLinks........................................................27 6.10 SupplyCurrentCharacteristics.............................10 12.3 ReceivingNotificationofDocumentationUpdates27 6.11 TimingRequirements............................................10 12.4 CommunityResources..........................................27 6.12 SwitchingCharacteristics......................................11 12.5 Trademarks...........................................................27 6.13 InsulationCharacteristicsCurves.........................12 12.6 ElectrostaticDischargeCaution............................27 6.14 TypicalCharacteristics..........................................13 12.7 Glossary................................................................27 7 ParameterMeasurementInformation................16 13 Mechanical,Packaging,andOrderable Information........................................................... 28 8 DetailedDescription............................................ 18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(December2016)toRevisionE Page • ChangedVDEStandardnameFrom:DINVVDEV0884-10(VDEV0884-10):2006-12To:DINVDEV0884- 11:2017-01inFeatures ......................................................................................................................................................... 1 • ChangedFeaturesbulletFrom:CSAComponentAcceptanceNotice5A,IEC60950-1andIEC61010-1End EquipmentStandardsTo:CSAapprovalperIEC60950-1andIEC62368-1endequipmentstandards.............................. 1 • Updatedcertificationsapprovalstatus,numbers,standardnames,anddetailsaccordingtothelatestagency certificatesinSafety-RelatedCertificationstable................................................................................................................... 8 • ChangedbothbypasscapacitorsFrom:10µFTo:0.1µFinFigure31.Eventhoughlargercapacitorscanbeused, 0.1µFistheminimumrecommendedbypasscapacitorsize.............................................................................................. 24 • ChangedbothbypasscapacitorsFrom:10µFTo:0.1µFinFigure32.Eventhoughlargercapacitorscanbeused, 0.1µFistheminimumrecommendedbypasscapacitorsize.............................................................................................. 24 ChangesfromRevisionC(June2015)toRevisionD Page • DeletedtheDeviceComparisonTable;seetheFeaturesListtablefordevicecomparison ................................................ 4 • ChangedthestatusofCQCcertificationfromplannedtocertified ....................................................................................... 8 • ChangedtheRegulatoryInformationtabletoSafety-RelatedCertificationsandupdatedcontent........................................ 8 • Changedformattingofsupplycurrentparameterstocombinedeviceandsides.Movedparameterstoseparatetable ...10 • AddedtheReceivingNotificationofDocumentationUpdatessection ................................................................................ 27 ChangesfromRevisionB(May2013)toRevisionC Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 • VDEStandardchangedtoDINVVDEV0884-10(VDEV0884-10):2006-12 .................................................................... 1 • Changedminimumairgap(Clearance)parameter,L(I01),toexternalclearance,CLR,andminimumexternal tracking(creepage)parameter,L(I02),toexternalcreepage................................................................................................. 7 • ChangedvaluesandtestconditionsintheInsulationSpecificationstable............................................................................ 7 • ChangedthedescriptionsofVDEandCSAinformation ....................................................................................................... 8 ChangesfromRevisionA(October2012)toRevisionB Page • ChangeSafetyFeatureFrom:(VDE0884Part2)(Pending)To:(VDE0884Part2)(Approved)......................................... 1 • Changed,VDEcolumnFrom:Filenumber:40016131(pending)To:Filenumber:40016131.............................................. 8 ChangesfromOriginal(July2012)toRevisionA Page • ChangedFrom:CSAComponentAcceptanceNotice5A(Pending)To:CSAComponentAcceptanceNotice5A (Approved).............................................................................................................................................................................. 1 • ChangedFrom:IEC60950-1andIEC61010-1EndEquipmentStandards(Pending)To:IEC60950-1andIEC 61010-1EndEquipmentStandards(Approved)..................................................................................................................... 1 • ChangedSafety-RelatedCertifications,CSAcolumnFrom:Filenumber:220991(pending)To:Filenumber:220991....... 8 Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 5 Pin Configuration and Functions ISO1540DPackage 8-PinSOIC TopView VCC1 1 8 VCC2 SDA1 2 n 7 SDA2 o ati SCL1 3 sol 6 SCL2 I GND1 4 5 GND2 Side 1 Side 2 Not to scale PinFunctions—ISO1540 PIN I/O DESCRIPTION NAME NO. GND1 4 — Ground,side1 GND2 5 — Ground,side2 SCL1 3 I/O Serialclockinput/output,side1 SCL2 6 I/O Serialclockinput/output,side2 SDA1 2 I/O Serialdatainput/output,side1 SDA2 7 I/O Serialdatainput/output,side2 VCC1 1 — Supplyvoltage,side1 VCC2 8 — Supplyvoltage,side2 4 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 ISO1541DPackage 8-PinSOIC TopView VCC1 1 8 VCC2 SDA1 2 n 7 SDA2 o ati SCL1 3 sol 6 SCL2 I GND1 4 5 GND2 Side 1 Side 2 Not to scale PinFunctions—ISO1541 PIN I/O DESCRIPTION NAME NO. GND1 4 — Ground,side1 GND2 5 — Ground,side2 SCL1 3 I Serialclockinput,side1 SCL2 6 O Serialclockoutput,side2 SDA1 2 I/O Serialdatainput/output,side1 SDA2 7 I/O Serialdatainput/output,side2 VCC1 1 — Supplyvoltage,side1 VCC2 8 — Supplyvoltage,side2 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT VCC1,VCC2 –0.5 6 Voltage SDA1,SCL1 –0.5 VCC1+0.5(3) V SDA2,SCL2 –0.5 VCC2+0.5(3) SDA1,SCL1 –20 20 I Outputcurrent mA O SDA2,SCL2 –100 100 T Maximumjunctiontemperature 150 °C J(MAX) T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesherewithinarewithrespecttothelocalgroundpin(GND1orGND2)andarepeakvoltagevalues. (3) Maximumvoltagemustnotexceed6V. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDEC Buspins ±8000 JS-001(1) Allpins ±4000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±1500 V C101(2) MachineModelJEDECJESD22-A115-A,allpins ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions MIN MAX UNIT VCC1,VCC2 Supplyvoltage 3 5.5 V V ,V Inputandoutputsignalvoltages,side1 0 VCC1 V SDA1 SCL1 V ,V Inputandoutputsignalvoltages,side2 0 VCC2 V SDA2 SCL2 V Low-levelinputvoltage,side1 0 0.5 V IL1 V High-levelinputvoltage,side1 0.7×VCC1 VCC1 V IH1 V Low-levelinputvoltage,side2 0 0.3×VCC2 V IL2 V High-levelinputvoltage,side2 0.7×VCC2 VCC2 V IH2 I Outputcurrent,side1 0.5 3.5 mA OL1 I Outputcurrent,side2 0.5 35 mA OL2 C1 Capacitiveload,side1 40 pF C2 Capacitiveload,side2 400 pF f Operatingfrequency(1) 1 MHz MAX T Ambienttemperature –40 125 °C A T Junctiontemperature –40 136 °C J T Thermalshutdown 139 171 °C SD (1) Thisrepresentsthemaximumfrequencywiththemaximumbusload(C)andthemaximumcurrentsink(I ).Ifthesystemhaslessbus O capacitance,thenhigherfrequenciescanbeachieved. 6.4 Thermal Information ISO154x THERMALMETRIC(1) D(SOIC) UNIT 8PINS R Junction-to-ambientthermalresistance 114.6 °C/W θJA R Junction-to-case(top)thermalresistance 69.6 °C/W θJC(top) R Junction-to-boardthermalresistance 55.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 27.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 54.7 °C/W JB R Junction-to-case(bottom)thermalresistance N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). 6.5 Power Ratings PARAMETER TESTCONDITIONS MIN TYP MAX UNIT P Maximumpowerdissipation(bothsides) 85 mW D VCC1=VCC2=5.5V,T =150°C,C1= J P Maximumpowerdissipation(side-1) 40pF,C2=400pF; 34 mW D1 Inputa1-MHz50%dutycycleclocksignal P Maximumpowerdissipation(side-2) 51 mW D2 6 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 6.6 Insulation Specifications PARAMETER TESTCONDITIONS VALUE UNIT GENERAL CLR Externalclearance(1) Shortestterminal-to-terminaldistancethroughair >4 mm CPG Externalcreepage(1) Shortestterminal-to-terminaldistanceacrossthe >4 mm packagesurface DTI Distancethroughtheinsulation Minimuminternalgap(internalclearance) 0.014 mm CTI Comparativetrackingindex DINEN60112(VDE0303-11);IEC60112 >400 V Materialgroup II Ratedmainsvoltage≤150V I–IV RMS Overvoltagecategory Ratedmainsvoltage≤300V I–III RMS DINVVDEV0884-10(VDEV0884-10):2006-12(2) V Maximumrepetitivepeakisolationvoltage ACvoltage(bipolar) 566 V IORM PK V =V TEST IOTM V Maximumtransientisolationvoltage t=60s(qualification) 4242 V IOTM PK t=1s(100%production) Methoda:AfterI/Osafetytestsubgroup2/3,V = ini V ,t =60s;V =1.2×V =680V ,t <5 IOTM ini pd(m) IORM PK m =10s Methoda:Afterenvironmentaltestssubgroup1, q Apparentcharge(3) V =V ,t =60s;V =1.6×V =906 <5 pC pd ini IOTM ini pd(m) IORM V ,t =10s PK m Methodb1:Atroutinetest(100%production)and preconditioning(typetest)V =V ,t =1s; <5 ini IOTM ini V =1.875×V =1062V ,t =1s pd(m) IORM PK m C Barriercapacitance,inputtooutput(4) V =0.4sin(2πft),f=1MHz ~1 pF IO IO V =500V,T =25°C >1012 IO A R Isolationresistance,inputtooutput(4) V =500V,100°C≤T ≤125°C >1011 Ω IO IO A V =500VatT =150°C >109 IO S Pollutiondegree 2 Climaticcategory 40/125/21 UL1577 V =V =2500V ,t=60s(qualification); TEST ISO RMS V Withstandisolationvoltage V =1.2×V =3000V ,t=1s(100% 2500 V ISO TEST ISO RMS RMS production) (1) Creepageandclearancerequirementsshouldbeappliedaccordingtothespecificequipmentisolationstandardsofanapplication.Care shouldbetakentomaintainthecreepageandclearancedistanceofaboarddesigntoensurethatthemountingpadsoftheisolatoron theprinted-circuitboarddonotreducethisdistance.Creepageandclearanceonaprinted-circuitboardbecomeequalincertaincases. Techniquessuchasinsertinggroovesand/orribsonaprintedcircuitboardareusedtohelpincreasethesespecifications. (2) Thiscouplerissuitableforbasicelectricalinsulationonlywithinthemaximumoperatingratings.Compliancewiththesafetyratingsshall beensuredbymeansofsuitableprotectivecircuits. (3) Apparentchargeiselectricaldischargecausedbyapartialdischarge(pd). (4) Allpinsoneachsideofthebarriertiedtogethercreatingatwo-terminaldevice Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 6.7 Safety-Related Certifications VDE CSA UL CQC CertifiedaccordingtoDINVDEV RecognizedunderUL1577 CertifiedaccordingtoCSA/IEC CertifiedaccordingtoGB4943.1- 0884-11:2017-01andDINEN ComponentRecognition 60950-1andCSA/IEC62368-1 2011 61010-1(VDE0411-1):2011-07 Program 2.5-kV InsulationRating; RMS 400V BasicInsulation BasicInsulation RMS workingvoltageperCSA60950- MaximumTransientOvervoltage, BasicInsulation,Altitude≤5000 1-07+A1+A2andIEC60950-1 4242V ; Singleprotection,2500V m,TropicalClimate,250V PK 2ndEd.+A1+A2; RMS RMS MaximumRepetitivePeakVoltage, maximumworkingvoltage 300V BasicInsulation 566V RMS PK workingvoltageperCSA62368- 1-14andIEC62368-1:2014, Certificatenumber: Certificatenumber:40047657 Mastercontractnumber:220991 Filenumber:E181974 CQC14001109540 6.8 Safety Limiting Values Safetylimitingintendstominimizepotentialdamagetotheisolationbarrieruponfailureofinputoroutputcircuitry.Afailureof theI/Ocanallowlowresistancetogroundorthesupplyand,withoutcurrentlimiting,dissipatesufficientpowertooverheat thedieanddamagetheisolationbarrier,potentiallyleadingtosecondarysystemfailures. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT R =114.6°C/W,V =5.5V,T =150°C,T =25°C, θJA I J A 198 Safetyinput,output,orsupply seeFigure1 I mA S current R =114.6°C/W,V =3.6V,T =150°C,T =25°C, θJA I J A 303 seeFigure1 T Safetytemperature 150 °C S The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the powertimesthejunction-to-airthermalresistance. 8 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 6.9 Electrical Characteristics overrecommendedoperatingconditions,unlessotherwisenoted PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SIDE1(ONLY) Voltageinputthresholdlow,SDA1 V 500 550 660 mV ILT1 andSCL1 Voltageinputthresholdhigh,SDA1 V 540 610 700 mV IHT1 andSCL1 V Voltageinputhysteresis V –V 40 60 mV HYST1 IHT1 ILT1 Low-leveloutputvoltage,SDA1 VOL1 andSCL1(1) 0.5mA≤(ISDA1andISCL1)≤3.5mA 650 800 mV Low-leveloutputvoltagetohigh- ΔV levelinputvoltagethreshold 0.5mA≤(I andI )≤3.5mA 50 mV OIT1 SDA1 SCL1 difference,SDA1andSCL1(1)(2) SIDE2(ONLY) Voltageinputthresholdlow,SDA2 V 0.3×VCC2 0.4×VCC2 V ILT2 andSCL2 Voltageinputthresholdhigh,SDA2 V 0.4×VCC2 0.5×VCC2 V IHT2 andSCL2 V Voltageinputhysteresis V –V 0.05×VCC2 V HYST2 IHT2 ILT2 Low-leveloutputvoltage,SDA2 V 0.5mA≤(I andI )≤35mA 0.4 V OL2 andSCL2 SDA2 SCL2 BOTHSIDES Inputleakagecurrents,SDA1, V ,V =VCC1; |I| SDA1 SCL1 0.01 10 µA I SCL1,SDA2,andSCL2 V ,V =VCC2 SDA2 SCL2 Inputcapacitancetolocalground, C V =0.4×sin(2E6πt)+2.5V 7 pF I SDA1,SCL1,SDA2,andSCL2 I CMTI Common-modetransientimmunity SeeFigure21 25 50 kV/µs VCCundervoltagelockout VCCUV threshold(3) 2.1 2.5 2.8 V (1) ThisparameterdoesnotapplytotheISO1541SCL1lineasitisunidirectional. (2) ∆V =V –V .ThisrepresentstheminimumdifferencebetweenaLow-LevelOutputVoltageandaHigh-LevelInputVoltage OIT1 OL1 IHT1 Thresholdtopreventapermanentlatchconditionthatwouldotherwiseexistwithbidirectionalcommunication. (3) AnyVCCvoltages,oneitherside,lessthantheminimumwillensuredevicelockout.BothVCCvoltagesgreaterthanthemaximumwill preventdevicelockout. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 6.10 Supply Current Characteristics overrecommendedoperatingconditions,unlessotherwisenoted.Formoreinformation,seeFigure19. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 3V≤VCC1,VCC2≤3.6V V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 2.4 3.6 R1,R2=Open;C1,C2=Open ISO1540 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 2.5 3.8 R1,R2=Open;C1,C2=Open I Supplycurrent,side1 mA CC1 V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 2.1 3.3 R1,R2=Open;C1,C2=Open ISO1541 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 2.3 3.6 R1,R2=Open;C1,C2=Open V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 1.7 2.7 ISO1540and R1,R2=Open;C1,C2=Open I Supplycurrent,side2 mA CC2 ISO1541 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 1.9 3.1 R1,R2=Open;C1,C2=Open 4.5V≤VCC1,VCC2≤5.5V V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 3.1 4.7 R1,R2=Open;C1,C2=Open ISO1540 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 3.1 4.7 R1,R2=Open;C1,C2=Open I Supplycurrent,side1 mA CC1 V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 2.8 4.4 R1,R2=Open;C1,C2=Open ISO1541 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 2.9 4.5 R1,R2=Open;C1,C2=Open V ,V =GND1;V ,V =GND2; SDA1 SCL1 SDA2 SCL2 2.3 3.7 ISO1540and R1,R2=Open;C1,C2=Open I Supplycurrent,side2 mA CC2 ISO1541 V ,V =VCC1;V ,V =VCC2; SDA1 SCL1 SDA2 SCL2 2.5 4 R1,R2=Open;C1,C2=Open 6.11 Timing Requirements MIN NOM MAX UNIT t Inputnoisefilter 5 12 ns SP t TimetorecoverfromUVLO 2.7Vto0.9V;SeeFigure22 30 50 110 µs UVLO 10 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 6.12 Switching Characteristics overrecommendedoperatingconditions,unlessotherwisenoted PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 3V≤VCC1,VCC2≤3.6V SeeFigure19 0.7×VCC1to0.3×VCC1 8 17 29 OutputSignalFallTime t R1=953Ω, ns f1 (SDA1,SCL1) C1=40pF 0.9×VCC1to900mV 16 29 48 SeeFigure19 0.7×VCC2to0.3×VCC2 14 23 47 OutputSignalFallTime t R2=95.3Ω, ns f2 (SDA2,SCL2) C2=400pF 0.9×VCC2to400mV 35 50 100 Low-to-HighPropagation t 0.55Vto0.7×VCC2 33 65 ns pLH1-2 Delay,Side1toSide2 High-to-LowPropagation t 0.7Vto0.4V 90 181 ns PHL1-2 Delay,Side1toSide2 PWD PulseWidthDistortion SeeFigure19 55 123 ns 1-2 |tpHL1-2–tpLH1-2| R1=953Ω, tPLH2-1(1) LDoewla-yto,-SHidigeh2PtroopSaidgeat1ion RC21,=C925=.31Ω0,pF 0.4×VCC2to0.7×VCC1 47 68 ns t (1) High-to-LowPropagation 0.4×VCC2to0.9V 67 109 ns PHL2-1 Delay,Side2toSide1 PWD (1) PulseWidthDistortion 20 49 ns 2-1 |t –t | pHL2-1 pLH2-1 SeeFigure20; t (1) Round-trippropagation R1=953Ω,C1=40pF 0.4Vto0.3×VCC1 100 165 ns LOOP1 delayonSide1 R2=95.3Ω,C2=400pF 4.5V≤VCC1,VCC2≤5.5V SeeFigure19 0.7×VCC1to0.3×VCC1 6 11 20 OutputSignalFallTime t R1=1430Ω, ns f1 (SDA1,SCL1) C1=40pF 0.9×VCC1to900mV 13 21 39 SeeFigure19 0.7×VCC2to0.3×VCC2 10 18 35 OutputSignalFallTime t R2=143Ω, ns f2 (SDA2,SCL2) C2=400pF 0.9×VCC2to400mV 28 41 76 Low-to-HighPropagation t 0.55Vto0.7×VCC2 31 62 ns pLH1-2 Delay,Side1toSide2 High-to-LowPropagation t 0.7Vto0.4V 70 139 ns PHL1-2 Delay,Side1toSide2 PWD PulseWidthDistortion SeeFigure19 38 80 ns 1-2 |tpHL1-2–tpLH1-2| R1=1430Ω, tPLH2-1(1) Ldoewla-yt,os-hidigeh2ptroopsaidgeat1ion RC21,2==14130Ωp,F 0.4×VCC2to0.7×VCC1 55 80 ns t (1) High-to-lowpropagation 0.4×VCC2to0.9V 47 85 ns PHL2-1 delay,Side2toside1 PWD (1) PulseWidthDistortion 8 21 ns 2-1 |t –t | pHL2-1 pLH2-1 SeeFigure20; t (1) Round-trippropagation R1=1430Ω,C1=40pF 0.4Vto0.3×VCC1 110 180 ns LOOP1 delayonside1 R2=143Ω,C2=400pF (1) ThisparameterdoesnotapplytotheISO1541SCL1lineasitisunidirectional. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 6.13 Insulation Characteristics Curves 350 VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 300 A) m nt ( 250 e urr 200 C g n miti 150 Li ety 100 af S 50 0 0 50 100 150 200 Ambient Temperature (qC) Figure1.ThermalDeratingCurveforLimitingCurrentperVDE 12 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 6.14 Typical Characteristics 0.800 3.0 0.780 IIOOLL11== 03..55 mmAA 2.5 Output Voltage, V(V)OL1 000000......776767428660000000 utput Current, I(mA)OL1 1201....0550 0.640 O 0.0 0.620 -0.5 0.600 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 −40 −25 −10 5 20 35 50 65 80 95 110 125 Applied Voltage, V , V (V) Free−AirTemperature (°C) SDA1 SCL1 T =25°C A Figure3.Side1:OutputLowCurrentvsS orS Figure2.Side1:OutputLowVoltagevsFree-Air DA1 CL1 AppliedVoltage Temperature 20 20 R1 = 1430 : 18 18 R1 = 2.2 k: 16 16 14 14 s) s) n n e, t (f1 1102 e, t (f1 1102 m m all Ti 8 all Ti 8 F 6 F 6 4 4 2 R1= 953 : 2 R1= 2.2 k: 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D001 D002 VCC1=3.3V C1=40pF VCC1=5V C1=40pF Falltimemeasuredfrom70%to30%VCC1 Falltimemeasuredfrom70%to30%VCC1 Figure4.Side1:OutputFallTimevsFree-AirTemperature Figure5.Side1:OutputFallTimevsFree-airTemperature 30 30 25 25 s) 20 s) 20 n n e t (f2 15 e t (f2 15 m m Ti Ti Fall 10 Fall 10 5 5 R2 = 95.3 : R2 = 143 : R2 = 2.2 k: R2 = 2.2 k: 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D003 D004 VCC2=3.3V C2=400pF VCC2=5V C2=400pF Falltimemeasuredfrom70%to30%VCC2 Falltimemeasuredfrom70%to30%VCC2 Figure6.Side2:OutputFallTimevsFree-AirTemperature Figure7.Side2:OutputFallTimevsFree-AirTemperature Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com Typical Characteristics (continued) 45 120 40 s) s) 100 (nPLH1-2 3305 (nPHL1-2 80 y, t 25 y, t ela ela 60 D 20 D n n o o ati 15 ati 40 g g a a op 10 op Pr Pr 20 5 VCC1 and VCC2 = 3.3 V, R2 = 95.3 : VCC1 and VCC2 = 3.3 V, R2 = 95.3 : VCC1 and VCC2 = 5 V, R2 = 143 : VCC1 and VCC2 = 5 V, R2 = 143 : 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D005 D006 C2=10pF C2=10pF Figure8.t PropagationDelayvsFree-AirTemperature Figure9.t PropagationDelayvsFree-AirTemperature PLH1-2 PHL1-2 1050 90 VCC1 and VCC2 = 3.3 V 1045 VCC1 and VCC2 = 5 V 80 Propagation Delay, tPLH1-2 (ns) 11111111000000000112233450505050 Propagation Delay, t (ns)PHL1-2 12345670000000 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 1000 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D007 D008 R2=2.2kΩ C2=400pF R2=2.2kΩ C2=400pF Figure10.t PropagationDelayvsFree-Air Figure11.t PropagationDelayvsFree-Air PLH1-2 PHL1-2 Temperature Temperature 70 80 60 70 s) s) n n (PHL2-1 50 (PHL2-1 5600 y, t 40 y, t a a el el 40 D D n 30 n o o 30 ati ati g 20 g pa pa 20 o o Pr 10 VCC1 and VCC2 = 3.3 V, R1 = 953 : Pr 10 VCC1 and VCC2 = 3.3 V, R1 = 953 : VCC1 and VCC2 = 5 V, R1 = 1430 : VCC1 and VCC2 = 5 V, R1 = 1430 : 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D009 D010 C1=10pF C1=10pF Figure12.t PropagationDelayvsFree-Air Figure13.t PropagationDelayvsFree-Air PLH2-1 PHL2-1 Temperature Temperature 14 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 Typical Characteristics (continued) 148 80 146 70 (ns)H2-1 144 (ns)L2-1 60 gation Delay, tPL 111344802 ation Delay,tPH 345000 Propa 136 opag 20 134 VCC1 and VCC2 = 3.3 V Pr 10 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V VCC1 and VCC2 = 5 V 132 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 Free-Air Temperature (qC) −40 −25 −10 5 20 35 50 65 80 95 110 125 D011 Free-AirTemperature (°C) R1=2.2kΩ C1=40pF R1=2.2kΩ C1=40pF Figure14.t PropagationDelayvsFree-Air PLH2-1 Figure15. t PropagationDelayvsFree-Air Temperature PHL2-1 Temperature 140 600 120 595 100 ns) 80 ns) 590 (P1 (P1 tLOO 60 tLOO 585 40 580 20 VCC1 and VCC2 = 3.3 V, R1 = 953 :, R2 = 95.3 : VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V, R1 = 1430 :, R2 = 143 : VCC1 and VCC2 = 5 V 0 575 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) Free-Air Temperature (qC) D013 D014 C1=40pF C2=400pF C1=40pF C2=400pF R1=2.2kΩ R2=2.2kΩ Figure16.t vsFree-AirTemperature Figure17.t vsFree-AirTemperature LOOP1 LOOP1 70 s) P V/ k 60 y ( nit u 50 m m nt I 40 e si n a 30 Tr e od 20 M n- mo 10 VCC1 and VCC2 = 3.3 V m o VCC1 and VCC2 = 5 V C 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature (qC) D015 Figure18.CMTIvsFree-AirTemperature Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 7 Parameter Measurement Information – – VCC1 + + VCC2 R1 R1 R2 R2 SDA1 ISO1540 SDA2 ISO1541 SCL2 SCL1 C1 C1 C2 C2 Copyright © 2016, Texas Instruments Incorporated Figure19. TestDiagram VCC1 VCC2 VCC1 R1 GND1 n SSDCAL11 or C1 solatio SDA1 tLOOP1 0.3 VCC1 Output I SCL1 (ISO1540 Only) 0.4 V GND1 Copyright © 2016, Texas Instruments Incorporated Figure20. t SetupandTimingDiagram Loop1 VCCx VCCy 2 k(cid:13) 2 k(cid:13) Input n + o ati ol Output s I – GNDx GNDy VCMTI Figure21. Common-ModeTransientImmunityTestCircuit 16 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 Parameter Measurement Information (continued) VCCx VCCy Side x, Side y VCCx,VCCy Ry 1, 2 3.3 V, 3.3 V 95.3Ω VCCx Ry 2, 1 3.3 V, 3.3 V 953Ω 0 V SDAx or SCLx n o + ati ol s Output I - GNDx GNDy or VCCx VCCy VCCy Ry SDAx or 0 V SCLx n o + ati ol s Output I GNDx GNDy VCCx or VCCy 2.7V t UVLO 0.9V Output Figure22. t TestCircuitandTimingDiagrams UVLO Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 8 Detailed Description 8.1 Overview The I2C bus is used in a wide range of applications because it is simple to use. The bus consists of a two-wire communication bus that supports bidirectional data transfer between a master device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL) line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode (0 to 3.4 Mbps).Themostcommonspeedsarethestandardandfastmodes. TheI2Cbusoperatesinbidirectional,half-duplexmode,whilestandarddigitalisolatorsareunidirectional devices. To make efficient use of one technology supporting the other, external circuitry is required that separates the bidirectional bus into two unidirectional signal paths without introducing significant propagation delay. These devices have their logic input and output buffers separated by TI's capacitive isolation technology using a silicon dioxide (SiO ) barrier. When used in conjunction with isolated power supplies, these devices block high voltages, 2 isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitivecircuitry. 8.2 Functional Block Diagrams VCC1 VCC2 SDA2 SDA1 or cit a p a VREF n C o ati ol s I SCL1 SCL2 GND1 GND2 VREF Figure23. ISO1540BlockDiagram 18 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 Functional Block Diagrams (continued) VCC1 VCC2 SDA1 SDA2 or cit a p a C n o VREF ati ol s I SCL1 SCL2 GND1 GND2 Figure24. ISO1541BlockDiagram 8.3 Feature Description The device enables a complete isolated I2C interface to be implemented within a small form factor having the featureslistedinTable1. Table1.FeaturesList PARTNUMBER CHANNELDIRECTION RATEDISOLATION(1) MAXIMUMFREQUENCY Bidirectional(SCL) ISO1540 Bidirectional(SDA) 2500V RMS 1MHz Unidirectional(SCL) 4242VPK ISO1541 Bidirectional(SDA) (1) SeeSafety-RelatedCertificationsfordetailedIsolationspecifications. 8.4 Isolator Functional Principle To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540 connects to a low- capacitance I2C node, while side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF of capacitance. VCC1 VCC2 RPU1 B A RPU2 VC-out SDA1 SDA2 ISO1540 40 mV 50 mV Cnode C Cbus VSDA1 D VILT1 VIHT1 VOL1 GND1 GND2 VREF Figure25. SDAChannelDesignandVoltageLevelsatSDA1 Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com Isolator Functional Principle (continued) At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V (maximum)drivendirectlybySDA1andthebufferedoutputlow-levelofB. Figure 26 demonstrate the switching behavior of the I2C isolator, ISO1540, between a master node at SDA1 and aheavyloadedbusatSDA2. VCC2 VCC2 VCC1 VCC1 V SDA2 50% SDA1 OL1 30% VIHT1 Receive Receive Transmit Delay Delay Delay Receive VCC1 Delay VCC1 VCC2 VCC2 Transmit V SDA2 Delay IHT2 SDA1 50% 30% Figure26. SDAChannelTiminginReceiveandTransmitDirections 8.4.1 ReceiveDirection(LeftDiagramofFigure26) When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the bufferedoutputofV =0.75V,whichis sufficiently low to be detected by Schmitt-trigger inputs with a minimum OL1 input-lowvoltageofV =0.9Vat3Vsupplylevels. IL When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by R and C . After the receive delay, SDA1 is released and also rises towards VCC1, following the time- PU2 bus constant R × C . Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 PU1 node reachesVCC2potential. 8.4.2 TransmitDirection(RightDiagramofFigure26) When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed immediatelyasitisoverwrittenbythelowerlow-levelofthemaster. However, when the master releases SDA1, the voltage potential increases and first must pass the upper input threshold of the comparator, V , to release SDA2. SDA1 then increases further until it reaches the buffered IHT1 output level of V = 0.75 V, maintained by the receive path. When comparator C turns high, SDA2 is released OL1 after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases SDA1tomovetowardVCC1potential. 8.5 Device Functional Modes Table2liststheISO154x functionalmodes. Table2.FunctionTable(1) POWERSTATE INPUT OUTPUT VCC1orVCC2<2.1V X Z VCC1andVCC2>2.8V L L VCC1andVCC2>2.8V H Z VCC1andVCC2>2.8V Z(2) ? (1) H=HighLevel;L=LowLevel;Z=HighImpedanceorFloat;X=Irrelevant;?=Indeterminate (2) InvalidinputconditionasanI2CsystemrequiresthatapullupresistortoVCCisconnected. 20 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information 9.1.1 I2CBusOverview The inter-integrated circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC communicationinhalf-duplexmode. I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected to VDDbyresistors(seeFigure27).Pullingthelinetogroundisconsidereda logic zero while letting the line float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply voltages are3.3Vand5V,althoughsystemswithhigherorlowervoltagesareallowed. VDD RPU RPU RPU RPU RPU RPU RPU RPU SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL GND GND GND GND (cid:29)C ADC DAC (cid:29)C Master Slave Slave Slave Figure27. I2CBus I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified, totalbuscapacitanceof400pF,whichrestrictscommunicationdistancestoafewmeters. The specified signaling rates for the ISO1540 and ISO1541 devices are 100 kbps (standard mode), 400 kbps (fastmode),1Mbps(fastmodeplus). The bus has two roles for nodes: master and slave. A master node issues the clock and slave addresses, and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to requestsfromthemaster.Figure28showsatypicaldatatransferbetweenmasterandslave. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com Application Information (continued) 7-bit 8-bit 8-bit ACK/ SDA R/W ACK ACK ADDRESS DATA DATA NACK SCL 1 -7 8 9 1 -8 9 1 -8 9 S P START STOP Condition condition Figure28. TimingDiagramofaCompleteDataTransfer The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave it wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the masterwishestowriteto0,ortoread from 1 the slave. The master then releases the SDA line to allow the slave toacknowledgethereceiptofdata. The slave responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the 9th clock pulse on the SCL signal, after which the master continues in either transmit or receive mode (according totheR/Wbitsent),whiletheslavecontinuesinthecomplementarymode(receiveortransmit,respectively). The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a high-to-lowtransitionofSDAwhileSCLishigh.TheSTOP condition is created by a low-to-high transition of SDA whileSCLishigh. If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the masterisinmaster-transmitmodeandtheslaveisinslave-receivemode. If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the receipt of every byte but the last one (see Figure 29). In this situation, the master is in master-receive mode and theslaveisinslave-transmitmode. The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for furthertransfers. S SlaveAddress WA DATA A DATA A P A=acknowledge A=not acknowledge From Master to Slave MasterTransmitter writing to Slave Receiver S=Start From Slave to Master P=Stop S SlaveAddress RA DATA A DATA A P R=Read W=Write Master Receiver reading from SlaveTransmitter Figure29. TransmitorReceiveModeChangesDuringaDataTransfer When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when receivingacknowledgmentfromtheslave. When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a transaction. NOTE The master ends a reading sequence by not acknowledging (NACK) the last byte received. This procedure resets the slave state machine and allows the master to send theSTOPcommand. 22 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 9.2 Typical Application In Figure 30, the ultra low-power microcontroller, MSP430G2132, controls the I2C data traffic of configuration data and conversion results for the analog inputs and outputs. Low-power data converters build the analog interface to sensors and actuators. The ISO1541 device provides the required isolation between different ground potentials of the system controller, remote sensor, and actuator circuitry to prevent ground loop currents that otherwisemayfalsifytheacquireddata. The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501, drives a center- tapped transformer with an output that is rectified and linearly regulated to provide a stable 5-V supply for the dataconverter. VS 3.3V 0.1μF Vc2c 3 1:2.2 MBR0520L 1 5 5VISO 0.1μF D2 IN OUT 8 LP2981-50 10μF SN6501 10μF 0.1μF 3ON GND2 9SDA VDD AIN04 GND D11 1Ω 10SCL ADS1115 4IAnnpaultosg 10μF MBR0520L 1 4,5 ADDR AIN3 GNDRDY 7 3 2 5VISO ISO-BARRIER 5VISO SDA SCL 0.1μF 5VISO22μF 6VOUT VIN 2 1μF REF5040 4 GND 0.1μF 0.1μF 0.1μF 15 4 12 3 2 1.5kΩ 1.5kΩ 1 8 1.5kΩ 1.5kΩ 11 SDAA2 VDD IOVDD VREFVH A1 10 OUT 5 XOUT MSDPV4cc30 SDA 9 2SVDCA1C1 SVDCAC227 9SLDCALC DAC8574 4OAuntpaulotsg 6 XIN GD2V1s3s2 SCL 8 3SGCNL1D1ISO1541GSNCDL226 14A1A0 A3GND VREFLVOUTD8 13 16 6 5 4 4 5 Copyright©2016,TexasInstrumentsIncorporated Figure30. IsolatedI2CDataAcquisitionSystem 9.2.1 DesignRequirements The recommended power supply voltages (VCC1 and VCC2) must be from 3 V to 5.5 V. A recommended decoupling capacitor with a value of 0.1 µF is required between both the VCC1 and GND1 pins, and the VCC2 andGND2pinstosupportofpowersupplyvoltagestransientandtoensurereliableoperationatalldatarates. 9.2.2 DetailedDesignProcedure The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible. The recommended placement of the capacitors must be 2-mm maximum from input and output power supply pins(VCC1andVCC2). The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 40 pF and on the output lines, SDA2 andSCL2,is≤ 400pF. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com Typical Application (continued) The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that inputcurrentdrawnis≤ 3.5mA.Theminimumpullupresistorsontheinputlines,SDA2andSCL2,toVCC2must be selected in such a way that output current drawn is ≤ 35 mA. The maximum pullup resistors on the input lines (SDA1 and SCL1) to VCC1 and on output lines (SDA1 and SCL1) to VCC2, depends on the load and rise time requirementsontherespectivelines. ISO1540 2mm 2 mm maximum maximum VCC1 VCC2 11 8 0.1 (cid:29)F 0.1 (cid:29)F 1 k(cid:13) 1 k(cid:13) 1 k(cid:13) 1 k(cid:13) SDA1 2 acitor 7 SDA2 p a C n SCL1 3 olatio 6 SCL2 s I GND1 GND2 4 5 Side 1 Side 2 Figure31. TypicalISO1540CircuitHookup 2mm ISO1541 2 mm maximum maximum VCC1 VCC2 11 8 0.1 (cid:29)F 0.1 (cid:29)F 1 k(cid:13) 1 k(cid:13) 1 k(cid:13) 1 k(cid:13) SDA1 2 acitor 7 SDA2 p a C n SCL1 3 olatio 6 SCL2 s I GND1 GND2 4 5 Side 1 Side 2 Figure32. TypicalISO1541CircuitHookup 9.2.3 ApplicationCurve 24 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 Typical Application (continued) TA= 25oC VCC1 = 3.6 V v di V/ m 0 0 5 900 mV VOL1 GND1 Time - 50 ns/div Figure33. Side1:Low-to-HighTransition 10 Power Supply Recommendations To help ensure reliable operation at data rates and supply voltages, TI recommends connecting a 0.1-µF bypass capacitor at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single, primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501 device. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501TransformerDriverforIsolatedPowerSupplies. (SLLSEA0). 11 Layout 11.1 Layout Guidelines AminimumoffourlayersisrequiredtoaccomplishalowEMIPCB design (see Figure 34). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signallayer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits ofthedatalink. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmissionlineinterconnectsandprovidesanexcellentlow-inductancepathforthereturncurrentflow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately100pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usuallyhavemargintotoleratediscontinuitiessuchasvias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to thestacktokeepitsymmetrical.Thismakesthestackmechanicallystableandpreventsit from warping. Also the powerandgroundplaneofeachpowersystemcanbeplacedclosertogether,thusincreasing the high-frequency bypasscapacitancesignificantly. Fordetailedlayoutrecommendations,seetheDigitalIsolatorDesignGuide(SLLA284) 11.1.1 PCBMaterial For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternativesbecauseof lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness,andtheself-extinguishingflammability-characteristics. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 11.2 Layout Example High-speed traces 10 mils Ground plane Keep this space free FR-4 40 mils from planes, 0 ~ 4.5 r traces, pads, and vias Power plane 10 mils Low-speed traces Figure34. RecommendedLayerStack 26 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 www.ti.com SLLSEB6E–JULY2012–REVISEDAPRIL2019 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • DigitalIsolatorDesignGuide(SLLA284) • ISO154xEVMLow-PowerBidirectionalI2CIsolatorsEvaluationModule(SLLU166) • TIIsolationGlossary(SLLA353) • SN6501TransformerDriverforIsolatedPowerSupplies. (SLLSEA0) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY ISO1540 Clickhere Clickhere Clickhere Clickhere Clickhere ISO1541 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2012–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ISO1540 ISO1541

ISO1540,ISO1541 SLLSEB6E–JULY2012–REVISEDAPRIL2019 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 28 SubmitDocumentationFeedback Copyright©2012–2019,TexasInstrumentsIncorporated ProductFolderLinks:ISO1540 ISO1541

PACKAGE OPTION ADDENDUM www.ti.com 25-Mar-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ISO1540D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540 & no Sb/Br) ISO1540DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540 & no Sb/Br) ISO1541D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541 & no Sb/Br) ISO1541DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 25-Mar-2019 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ISO1540, ISO1541 : •Automotive: ISO1540-Q1, ISO1541-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ISO1540DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO1541DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ISO1540DR SOIC D 8 2500 350.0 350.0 43.0 ISO1541DR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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