DATASHEET ISL97671A FN7709 6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control Rev.4.00 Sep 14, 2017 The ISL97671A is a 6-Channel 45V dual dimming capable LED Features driver that can be used with either SMBus/I2C or PWM signal for dimming control. The ISL97671A can drive six channels of • 6 x 50mA channels LEDs from an input of 4.5V~26.5V to an output of up to 45V. It • 4.5V to 26.5V input with 45V maximum output can also operate from an input as low as 3V to an output of up • 3V (see Figure38 on page26) to 21V input with 26.5V to 26.5V in bootstrap configuration (refer to Figure38 on maximum output page26). • PWM dimming with phase shift control The ISL97671A features optional channel phase shift control to minimize the input/output ripple characteristics, and load • SMBus/I2C controlled PWM or DC dimming transients to improve efficiency and eliminate audible noise. • Direct PWM dimming The device can also be configured for Direct PWM Dimming • PWM dimming linearity with a minimum dimming duty cycle of 0.007% at 200Hz. - PWM dimming with adjustable dimming frequency and The ISL97671A headroom control circuit monitors the highest duty cycle linear from 0.4% to 100% <30kHz LED forward voltage string for output regulation, to minimize - Direct PWM dimming duty cycle linear from 0.007% to the voltage headroom and power loss in a typical multi-string 100% at 200Hz operation. • Current matching ±0.7% The ISL97671A is offered in a compact and thermally efficient • 600kHz/1.2MHz selectable switching frequency 20 Ld QFN 4mmx3mm package. • Dynamic headroom control Related Literature • Fault protection • For a full list of related documents, visit our website - String open/short-circuit, OVP, OTP, and optional output short-circuit fault protection - ISL97671A product page • 20 Ld 4mmx3mm QFN package Applications • Tablet PC to notebook displays LED backlighting • LCD monitor LED backlighting • Field sequential RGB LED backlighting Typical Application Circuits VIN = 4.5~26.5V 45V*, 6 x 50mA VIN = 4.5~26.5V 45V*, 6 x 50mA VIN = 4.5~26.5V 45V*, 6 x 50mA Q1(OPTIONAL) Q1(OPTIONAL) Q1(OPTIONAL) ISL97671A ISL97671A ISL97671A 1FAULT 1FAULT 1FAULT 2VIN LX20 2VIN LX20 2 VIN LX20 OVP16 OVP16 OVP16 4VDC 4VDC 4 VDC 8FPWM PGND19 PGND19 PGND19 7SMBCLK/SCL 7SMBCLK/SCL 7 SMBCLK/SCL 6SMBDAT/SDA CH010 6SMBDAT/SDACH010 6 SMBDAT/SDA CH010 CH111 CH111 CH111 5PWM CH212 5PWM CH212 5 PWM CH212 3EN CH313 3EN CH313 3 EN CH313 17RSET CH414 17RSET CH414 17RSET CH414 8FPWM CH515 8FPWM CH515 CH515 9AGND COMP18 *VIN > 12V 9AGND COMP18 *VIN > 12V 9 AGND COMP18 *VIN > 12V FIGURE 1A. SMBus/I2C CONTROLLED FIGURE 1B. PWM DIMMING WITH PWM INPUT FIGURE 1C. DIRECT PWM DIMMING DIMMING AND ADJUSTABLE AND ADJUSTABLE DIMMING DIMMING FREQUENCY FREQUENCY FIGURE 1. ISL97671A TYPICAL APPLICATION DIAGRAMS FN7709 Rev.4.00 Page 1 of 28 Sep 14, 2017

ISL97671A Table of Contents Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM Boost Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Dynamic Headroom Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM Dimming Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5V Low Dropout Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IC Protection Features and Fault Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SMBus/I2C Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Slave Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SMBus/I2C Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWM Brightness Control Register (0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device Control Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Fault/Status Register (0x02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Identification Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Brightness Control Register (0x07). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output Channel Mask/Fault Readout Register (0x09). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Phase Shift Control Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Component Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Schottky Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High-Current Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low Voltage Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16-Bit Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Field Sequential RGB LED Backlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FN7709 Rev.4.00 Page 2 of 28 Sep 14, 2017

ISL97671A Block Diagram VIN = 4.5V TO 26.5V 45V*, 6 x 50mA VIN FAULT LX EN ISL97671A OVP VDC REG OVP FAULT/STATUS REGISTER OSRCA MAPND  = 0 DRFIEVTER COMP LOGIC FPWM IMAX ILIMIT LED PWM PGND CONTROL CH0 COMP GM HIGHEST VF AMP REFERENCE STRING DOECT,E SCCT GENERATOR DETECT CH5 ++-- DOECT,E SCCT *VIN > 12V ++ -- RSET FAULT/STATUS AGND REGISTER TEMP SENSOR REGISTERS ++ -- PWM BRIGHTNESS CONTROL SMBCLK/SCL SMBUS/I2C DEVICE CONTROL PWM/OC/SC FARUELGT/ISSTTAETRUS SMBDAT/SDA INTERFACE FAULT/STATUS DC AND PWM PWM IDENTIFICATION CONTROL LOGIC DC BRIGHTNESS CONTROL CONFIGURATION FIGURE 2. ISL97671A BLOCK DIAGRAM FN7709 Rev.4.00 Page 3 of 28 Sep 14, 2017

ISL97671A Ordering Information Pin Configuration ISL97671A PACKAGE (20 LD QFN) PART NUMBER PART (RoHS PKG. TOP VIEW (Notes1, 2, 3) MARKING COMPLIANT) DWG. # ISL97671AIRZ 671A 20 Ld 3x4 QFN L20.3x4 ND MP ET X G O S L P C R ISL97671AIRZ-EVALZ Evaluation Board 20 19 18 17 NOTES: FAULT 1 16 OVP 1. Add -T” suffix for 6k unit or “-TK” suffix for 1k unit tape and reel options. Please refer to TB347 for details on reel specifications. VIN 2 15 CH5 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and EN 3 EPAD 14 CH4 100% matte tin plate plus anneal (e3 termination finish, which is VDC 4 13 CH3 RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at PWM 5 12 CH2 Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. SMBDAT/SDA 6 11 CH1 3. For Moisture Sensitivity Level (MSL), refer to the ISL97671A device 7 8 9 10 information page. For more information about MSL, refer to TB363. L M D 0 C W N H K/S FP AG C L C B M S Pin Descriptions (I = Input, O = Output, S = Supply) PIN NAME PIN # TYPE DESCRIPTION FAULT 1 O Fault disconnect switch gate control. VIN 2 S Input voltage for the device and LED power. EN 3 I Enable input. The device needs 4ms for the initial power-up enable. It will be disabled if it is not biased for longer than 30.5ms. VDC 4 S Internal LDO output. Connect a decoupling capacitor to ground. PWM 5 I PWM brightness control pin or DPST control input. SMBDAT/SDA 6 I/O SMBus/I2C serial data input and output. When Pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the drivers will be controlled by the external PWM signal. SMBCLK/SCL 7 I SMBus/I2C serial clock input. When Pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the drivers will be controlled by external PWM signal. FPWM 8 I Sets the PWM dimming frequency by connecting a resistor between this pin and ground. When FPWM is tied to VDC and SMBCLK/SMBDAT is tied to ground, the device will be in Direct PWM Dimming where the output follows the input frequency and duty cycle without any digitization. AGND 9 S Analog ground for precision circuits. CH0, CH1 10, 11, I Current source and channel monitoring input for Channels 0-5. CH2, CH3 12, 13, CH4, CH5 14, 15 OVP 16 I Overvoltage protection input. RSET 17 I Resistor connection for setting LED current, (see Equation1 to calculate the I ). LED(peak) COMP 18 O Boost compensation pin. PGND 19 S Power ground. LX 20 O Boost switch node. EPAD No electrical connection, but should be used to connect PGND and AGND. For example, use the top plane as PGND and the bottom plane as AGND with vias on EPAD to allow heat dissipation and minimum noise coupling from PGND to AGND operation. FN7709 Rev.4.00 Page 4 of 28 Sep 14, 2017

ISL97671A Absolute Maximum Ratings Thermal Information (T = +25°C) A VIN, EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 28V Thermal Resistance (Typical)  (°C/W)  (°C/W) JA JC FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V 20 Ld QFN Package (Notes 4, 5, 7) . . . . . . 40 2.5 VDC, COMP, RSET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V Thermal Characterization (Typical) PSI (°C/W) JT SMBCLK/SCL, SMBDAT/SDA, FPWM, PWM . . . . . . . . . . . . . . -0.3V to 5.5V 20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . . 1 OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 45V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to AGND pin Operating Conditions ESD Rating Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 3kV Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 300V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T J C A CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. Refer to JA TB379. 5. For  , the “case temp” location is the center of the exposed metal pad on the package underside. JC 6. PSI is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating, then the die JT junction temperature can be estimated more accurately than the  and  thermal resistance ratings. JC JC 7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs. Electrical Specifications V = 12V, EN = 5V, R =20.1kΩ, unless otherwise noted. Boldface limits apply across the operating IN SET temperature range, -40°C to +85°C. MIN MAX PARAMETER SYMBOL CONDITION (Note8) TYP (Note8) UNIT GENERAL Backlight Supply Voltage V (Note9) ≤13 LEDs per channel 4.5 26.5 V IN (3.2V/20mA type) V Shutdown Current I T = +25°C 5 µA IN VIN_STBY A V Active Current I EN = 5V 5 mA IN VIN Output Voltage V 4.5V < V ≤26V, 45 V OUT IN f = 600kHz SW 8.55V < V ≤26V, 45 V IN f = 1.2MHz SW 4.5V < V ≤8.55V, f =1.2MHz V /0.19 V IN SW IN Undervoltage Lockout Threshold V 2.1 2.6 V UVLO Undervoltage Lockout Hysteresis V 200 mV UVLO_HYS REGULATOR LDO Output Voltage V V ≥ 6V 4.55 4.8 5 V DC IN Standby Current I EN = 0V 5 µA VDC_STBY VDC LDO Droop Voltage V V > 5.5V, 20mA 20 200 mV LDO IN Guaranteed Range for EN Input Low Voltage EN 0.5 V LOW Guaranteed Range for EN Input High Voltage EN 1.8 V HI EN Low Time Before Shut-down t 30.5 ms ENLow FN7709 Rev.4.00 Page 5 of 28 Sep 14, 2017

ISL97671A Electrical Specifications V = 12V, EN = 5V, R =20.1kΩ, unless otherwise noted. Boldface limits apply across the operating IN SET temperature range, -40°C to +85°C. (Continued) MIN MAX PARAMETER SYMBOL CONDITION (Note8) TYP (Note8) UNIT BOOST Boost FET Current Limit SW 1.5 2.0 2.7 A ILimit Internal Boost Switch ON-resistance r T = +25°C 235 300 mΩ DS(ON) A Soft-Start SS 100% LED Duty Cycle 7 ms Peak Efficiency Eff_peak V = 12V, 72 LEDs, 20mA each, L=10µH 92.9 % IN with DCR 101mΩT =+25°C A V = 12V, 60 LEDs, 20mA each, L=10µH 90.8 % IN with DCR 101mΩT =+25°C A Line Regulation I /V 0.1 % OUT IN Boost Maximum Duty Cycle D f = 1, 600kHz 90 % MAX SW f = 0, 1.2MHz 81 SW Boost Minimum Duty Cycle D f = 1, 600kHz 9.5 % MIN SW f = 0, 1.2MHz 17 SW Lx Frequency High f f = 1, 600kHz 475 600 640 kHz OSC_hi SW Lx Frequency Low f f = 0, 1.2MHz 0.97 1.14 1.31 MHz OSC_lo SW LX Pin Leakage Current I LX = 45V, EN = 0V 10 µA LX_leakage REFERENCE FAULT DETECTION Short Circuit Threshold Accuracy V 7.5 8.2 V SC Temperature Shutdown Threshold Temp_shtdwn 150 °C Temperature Shutdown Hysteresis Temp_Hyst 23 °C Overvoltage Limit on OVP Pin V 1.199 1.24 V OVPlo CURRENT SOURCES DC Channel-to-Channel Current Matching I R = 20.1kΩ, Reg0x00=0xFF, ±0.7 ±1.0 % MATCH SET (I =20mA) OUT Current Accuracy I -1.5 +1.5 % ACC Dominant Channel Current Sink Headroom V I = 20mA 500 mV HEADROOM LED Range at CHx Pin T = +25°C (Note10) A Dominant Channel Current Sink Headroom V I = 20mA 90 mV HEADROOM_RANGE LED Range at CHx Pin T = +25°C A Voltage at RSET Pin V R = 20.1kΩ 1.2 1.22 1.24 V RSET SET Maximum LED Current per Channel I V = 12V, V = 45V, f = 1.2MHz, 50 mA LED(max) IN OUT SW T =+25°C A PWM GENERATOR Guaranteed Range for PWM Input Low Voltage V 0.8 V IL Guaranteed Range for PWM Input High Voltage V 1.5 VDD V IH PWM Input Frequency Range F 200 30,000 Hz PWMI PWM Dimming Accuracy (Except Direct PWM PWMACC 8 bits Dimming) Direct PWM Minimum On Time t Direct PWM Mode 250 350 ns DIRECTPWM PWM Dimming Frequency Range F 100 30,000 Hz PWM FN7709 Rev.4.00 Page 6 of 28 Sep 14, 2017

ISL97671A Electrical Specifications V = 12V, EN = 5V, R =20.1kΩ, unless otherwise noted. Boldface limits apply across the operating IN SET temperature range, -40°C to +85°C. (Continued) MIN MAX PARAMETER SYMBOL CONDITION (Note8) TYP (Note8) UNIT FAULT PIN Fault Pull-down Current I V = 12V 12 21 30 µA FAULT IN Fault Clamp Voltage with Respect to VIN VFAULT VIN = 12, VIN - VFAULT 6 7 8.3 V LX Start-up Threshold LXstart_thres 0.9 1.2 V LX Start-up Current ILXStart-up 1 3.5 5 mA SMBus/I2C INTERFACE Guaranteed Range for Data, Clock Input Low V 0.8 V IL Voltage Guaranteed Range for Data, Clock Input High V 1.5 VDD V IH Voltage SMBus/I2C Data line Logic Low Voltage V I = 4mA 0.17 V OL PULLUP Input Leakage On SMBData/SMBClk I Measured at 4.8V -10 10 µA LEAK SMBus/I2C TIMING SPECIFICATIONS Minimum Time Between EN high and t -SMB/I2C 1µF capacitor on VDC 2 ms EN SMBus/I2C Enabled Pulse Width Suppression on SMBCLK/SMBDAT PWS 0.15 0.45 µs SMBus/I2C Clock Frequency f 400 kHz SMB Bus Free Time Between Stop and Start t 1.3 µs BUF Condition Hold Time After (Repeated) START Condition. t 0.6 µs HD:STA After this Period, the First Clock is Generated Repeated Start Condition Setup Time t 0.6 µs SU:STA Stop Condition Setup Time t 0.6 µs SU:STO Data Hold Time t 300 ns HD:DAT Data Setup Time t 100 ns SU:DAT Clock Low Period t 1.3 µs LOW Clock High Period t 0.6 µs HIGH Clock/data Fall Time t 300 ns F Clock/data Rise Time t 300 ns R NOTES: 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. At maximum V of 26.5V, minimum V is limited 28V. IN OUT 10. Varies within range specified by V . HEADROOM_RANGE FN7709 Rev.4.00 Page 7 of 28 Sep 14, 2017

ISL97671A Typical Performance Curves 100 100 6P10S LEDs 90 90 80 80 CY (%) 7600 12VIN 24VIN 5VIN CY (%) 6700 580kHz 1.2MHz N 50 N 50 E E CI 40 CI 40 FI FI EF 30 EF 30 20 20 10 10 0 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 ILED(mA) VIN(V) FIGURE 3. EFFICIENCY vs UP TO 30mA LED CURRENT (100%LED FIGURE 4. EFFICIENCY vs V vs SWITCHING FREQUENCY AT 20mA IN DUTY CYCLE) vs V (100% LED DUTY CYCLE) IN 100 100 90 80 80 %) 1.2MHz %) 70 +25°C -40°C Y ( 60 580k Y ( 60 +85°C 0°C C C N N 50 E E CI CI 40 FI 40 FI EF EF 30 20 20 10 0 0 0 5 10 15 20 25 30 0 5 10 15 20 25 30 VIN(V) VIN(V) FIGURE 5. EFFICIENCY vs V vs SWITCHING FREQUENCY AT 30mA FIGURE 6. EFFICIENCY vs V vs TEMPERATURE AT 20mA IN IN (100% LED DUTY CYCLE) (100%LED DUTY CYCLE) 0.40 1.2 0.30 %) 1.0 G( 0.20 CHIN 0.10 mA) 0.8 4.5 VIN NT MAT -00..1000 4.5VIN 12VIN RRENT( 0.6 12 VIN E U 0.4 R C R -0.20 U C 0.2 -0.30 21VIN -0.40 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 CHANNEL PWM DIMMING DUTY CYCLE(%) FIGURE 7. CHANNEL-TO-CHANNEL CURRENT MATCHING FIGURE 8. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs V IN FN7709 Rev.4.00 Page 8 of 28 Sep 14, 2017

ISL97671A Typical Performance Curves (Continued) 0.60 -40°C +25°C VOUT = 50mV/DIV 0.55 2.00µs/DIV V) (M O RO 0.50 HEAD 0°C VLX = 20V/DIV V 2.00µs/DIV 0.45 0.40 0 5 10 15 20 25 30 VIN (V) FIGURE 9. VHEADROOM vs VIN vs TEMPERATURE AT 20mA FIGURE 10. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT 20mA/CHANNEL VV__OOUUTT VV__OOUUTT VV__EENN VV__EENN VV__LLXX VV__LLXX I_I_IINNDDUUCTCOTROR I_I_IINNDDUUCTCOTROR FIGURE 11. SOFT-START INDUCTOR CURRENT AT V = 6V FOR FIGURE 12. SOFT-START INDUCTOR CURRENT AT V = 12V FOR IN IN 6P12S AT 20mA/CHANNEL 6P12S AT 20mA/CHANNEL 6P12S, 20mA/CH 6P12S, 20mA/CH VIN = 10V/DIV VIN = 10V/DIV 10ms/DIV 10.0ms/DIV I_VIN = 1A/DIV I_VIN = 1A/DIV ILED = 20mA/DIV ILED = 20mA/DIV EN FIGURE 13. LINE REGULATION WITH V CHANGE FROM 6V TO 26V, FIGURE 14. LINE REGULATION WITH V CHANGE FROM 26V TO 6V IN IN 6P12S AT 20mA/CHANNEL FOR 6P12S AT 20mA/CHANNEL FN7709 Rev.4.00 Page 9 of 28 Sep 14, 2017

ISL97671A Typical Performance Curves (Continued) 6P12S, 20mA/CH 6P12S, 20mA/CH VO = 1V/DIV VO = 1V/DIV 10.0ms/DIV 10.0ms/DIV ILED = 20mA/DIV ILED = 20mA/DIV FIGURE 15. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE FIGURE 16. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE FROM 0% TO 100%, V = 12V, 6P12S AT FROM 100% TO 0%, V = 12V, 6P12S AT IN IN 20mA/CHANNEL 20mA/CHANNEL 6P12S, 20mA/CH VO = 10V/DIV 0.0030 20.0ms/DIV 0.0025 A) m 0.0020 (D E ILED = 20mA/DIV I_VIN = 1A/DIV IL 0.0015 FPWM = 200Hz EN NO CH CAPS ILED = 20mA @ 100% DUTY CYCLE 0.0010 0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014 PWM DIMMING DUTY CYCLE (%) FIGURE 17. ISL97671A SHUTS DOWN AND STOPS SWITCHING FIGURE 18. DIRECT PWM DIMMING LINEARITY AT VERY LOW DUTY ~30ms AFTER EN GOES LOW CYCLE FN7709 Rev.4.00 Page 10 of 28 Sep 14, 2017

ISL97671A Theory of Operation Dynamic Headroom Control The ISL97671A features a proprietary Dynamic Headroom PWM Boost Converter Control circuit that detects the highest forward voltage string or The current mode PWM boost converter produces the minimal effectively the lowest voltage from any of the CH0-CH5 pins. voltage needed to enable the LED stack with the highest forward When this lowest channel voltage is lower than the short-circuit voltage drop to run at the programmed current. The ISL97671A threshold, VSC, such voltage will be used as the feedback signal employs current mode control boost architecture that has a fast for the boost regulator. The boost makes the output to the correct current sense loop and a slow voltage feedback loop. Such level such that the lowest channel pin is at the target headroom architecture achieves a fast transient response that is essential voltage. Since all LED stacks are connected to the same output for notebook backlight applications in which drained batteries voltage, the other channel pins will have a higher voltage, but the can be instantly changed to an AC/DC adapter without regulated current source circuit on each channel will ensure that noticeable visual disturbance. The number of LEDs that can be each channel has the same programmed current. The output driven by ISL97671A depends on the type of LED chosen in the voltage will regulate cycle-by-cycle and is always referenced to application. The ISL97671A is capable of boosting up to 45V and the highest forward voltage string in the architecture. typically driving 13 LEDs in series for each of the 6 channels, MAXIMUM DC CURRENT SETTING enabling a total of 78 pieces of the 3.2V/20mA type of LEDs. Set the initial brightness by choosing an appropriate value for Enable R . This should be chosen to fix the maximum possible LED SET current: The EN pin enables or disables the ISL97671A operation. It is a high voltage pin that can be tied directly to V up to 26.5V. If EN is pulled 410.5 IN I = --------------- low for longer than 30ms, the device will shut down. LEDmax RSET (EQ. 1) Current Matching and Current Accuracy Once RSET is fixed, the LED DC current can be adjusted through Register 0x07 (BRTDC) as follows: Each channel of the LED current is regulated by the current I = 1.61xBRTDCR  (EQ. 2) source circuit, as shown in Figure19. LED SET The LED peak current is set by translating the R current to the BRTDC can be programmed from 0 to 255 in decimal and SET output with a scaling factor of 410.5/R . The source terminals defaults to 255 (0xFF). If left at the default value, the LED current SET of the current source MOSFETs are designed to operate within a will be fixed at I . BRTDC can be adjusted dynamically on LEDmax range at about 500mV to optimize power loss versus accuracy the fly during operation. BRTDC = 0 disconnects all channels. requirements. The sources of the channel-to-channel current For example, if the maximum required LED current (I ) is matching errors come from the opamp offset, internal layout, LED(max) 20mA, rearranging Equation1 yields Equation3: reference, and current source resistors. These parameters are optimized for current matching and absolute current accuracy. RSET = 410.50.02 = 20.52k (EQ. 3) On the other hand, the absolute accuracy is additionally If BRTDC is set to 200, then: determined by the external R , and therefore, additional SET tolerance will be contributed by the current setting resistor. A 1% I = 1.6120020100=16.02mA (EQ. 4) LED tolerance resistor is therefore recommended. PWM DIMMING CONTROL The ISL97671A provides multiple PWM dimming methods, as described in the following. Table Figure1 on page12 summarizes the dimming mode selection. Each of these methods results in PWM chopping of the current in the LEDs for all 6 channels to provide a lower average LED current. During the On periods, the LED current will be defined by the value of R SET and BRTDC, as described in Equations1 and 2. The source of the PWM signal can be described as follows: + - + REF 1. Internally generated - 256 step duty cycle BRT register - programmed through the SMBus/I2C. RSET 2. External - Signal from PWM. + 3. DPST mode - Internally generated signal with duty cycle - defined by the product of the PWM input duty cycle and PWM DIMMING SMBus/I2C programmed BRT register. DC DIMMING 4. Direct PWM mode - The output duty cycle and dimming frequency follow the input PWM signal. FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT FN7709 Rev.4.00 Page 11 of 28 Sep 14, 2017

ISL97671A The default PWM dimming mode is in DPST. In all of the For example, if the SMBus/I2C controlled PWM duty is 80% methods, the average LED channel current is controlled by I dimming at 200Hz (see Equation11) and the external PWM duty LED and the PWM duty cycle in percent, as shown in Equation5: cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is 48% dimming at 200Hz. ILEDave = ILEDPWM (EQ. 5) In DPST mode, the ISL97671A features 8-bit dimming resolution; Method 1 (SMBus/I2C Controlled Dimming) it calculates the dimming level by taking the eight most significant bits of the product of the PWMI duty cycle (digitized The average LED channel current is controlled by the internally with 8-bit resolution) and of the BRT I2C register. generated PWM signal, as shown in Equation6: I = I BRT255 (EQ. 6) Method 4 (Direct PWM Mode) LEDave LED Direct PWM Dimming mode is selected when f is tied to V PWM DC where BRT is the PWM brightness level programmed in the and SMBCLK/SMBDAT are grounded. The current of the Register 0x00. BRT ranges from 0 to 255 in decimal and defaults sixchannels will follow the incoming PWM signal’s frequency to 255 (0xFF). BRT = 0 disconnects all channels. and duty cycle. The minimum duty cycle can be as low as 0.007% at 200Hz (or an equivalent pulse width of 350ns). This ultra low To use only the SMBus/I2C controlled PWM brightness control, duty cycle dimming performance can be achieved if no channel set Register 0x01 to 0x05. Alternatively, the same operation can capacitor is present. Additionally, the Phase Shift function is be obtained by leaving Register 0x01 at its default value of 0x01 disabled in Direct PWM Dimming mode. (DPST mode) and connecting the PWM input to VDC, so that the dimming level depends only on the BRT register. TABLE 1. DIMMING MODE SELECTION The PWM dimming frequency is adjusted by a resistor at the SMBCLK/ SMBDAT/ FPWM pin. SCL PIN SDA PIN DIMMING METHOD SIGNAL SIGNAL FPWM PIN 0x01 REGISTER SELECTION Method 2 (PWM Controlled Dimming with Settable Dimming SMBUS SMBUS Resistor to Set to 0x05, or Method 1 Frequency) /I2C /I2C ground set to 0x01 and (SMBUS/I2C The average LED channel current can also be controlled by the duty clock data connect PWM to controlled cycle of the external PWM signal, as shown in Equation7: VDC dimming) ILILEDave = ILEDPWMI (EQ. 7) SMBUS SMBUS Resistor to Set to 0x03, or Method 2 (PWM /I2C clock /I2C data ground set to 0x01 and controlled with The PWM dimming frequency is adjusted by a resistor at the not program settable dimming FPWM pin. The PWM input cannot be low for more than 30.5ms register 0x00 frequency) or else the driver will enter shutdown. Grounded Grounded Resistor to N/A Method 2 (PWM ground controlled with To use the externally applied PWM signal only for brightness settable dimming control, set Register 0x01 to 0x03. Alternatively, the same frequency) operation can be obtained by leaving Register 0x01 at its default value of 0x01 (DPST mode), and not programming Register BRT, SMBUS SMBUS Resistor to Set to 0x01 Method 3 (DPST so that it contains its default value of 0xFF. A third way to obtain /I2C clock /I2C data ground mode) this mode of operation is to tie both SCL and SDA to ground. Grounded Grounded Tie to VDC N/A Method 4 (Direct PWM dimming) Method 3 (DPST Mode) The average LED channel current can also be controlled by the PWM Dimming Frequency Adjustment product of the SMBus/I2C controlled PWM and the external PWM signals as: For dimming methods 1-3, the PWM dimming frequency is set by I = I xPWM (EQ. 8) an external resistor at the FPWM pin as: LEDave LED DPST 7 6.6610 where: FPWM = R-----F----P-----W------M---- (EQ. 11) PPWM = BRT255PWMI (EQ. 9) DPST where f is the PWM dimming frequency and R is the PWM FPWM therefore: setting resistor. I = I BRT255PWMI (EQ. 10) The maximum PWM dimming frequency is 30kHz when the duty LEDave LED cycle is from 0.4% to 100%. where BRT is the value held in Register 0x00 (default setting Phase Shift Control 0xFF) controlled by SMBus/I2C and PWMI is the duty cycle of the incoming PWM signal. In this way, users can change the PWM For dimming methods 1-3, the ISL97671A is capable of delaying current in a ratiometric manner to achieve DPST compliant the phase of each current source to minimize load transients. By backlight dimming. To use the DPST mode, set Register 0x01 to default, phase shifting is disabled as shown in Figure20 where 0x01. The PWM dimming frequency is adjusted by a resistor at the channels PWM currents are switching at the same time. the FPWM pin. FN7709 Rev.4.00 Page 12 of 28 Sep 14, 2017

ISL97671A tFPWM tPWMin PWMI 60% 40% ILED0 tON tOFF tFPWM (tPWMout) ILED1 ILED1 tON60% tOF40F% tD1 ILED2 ILED2 tD1 ILED3 ILED3 tD1 ILED4 ILED4 ILED5 FIGURE 20. NO DELAY (DEFAULT PHASE SHIFT DISABLED) tD2 ILED1 When EqualPhase = 1 (Register 0x0A, Bit 7), the phase shift evenly tD1= Fixed Delay with Integer only while the decimal value will bediscarded (eg. 63.75=63) spreads the channels switching across the PWM cycle, depending on FIGURE 22. 4 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION how many channels are enabled, as shown in Figures21 and 22. Equal phase means fixed delays occur between channels. Such delay can be calculated using Equation12 and Figures21 and 22. tFPWM tD1 = t--F---2-P--5--W--5---M----x2---N-5---5--- (EQ. 12) ILED0 tPD tON tOFF ILED1 Equation13 shows the phase delay between the last channel of tPD ILED2 the current duty cycle and the first channel of the next duty cycle in Figures21 and 22. tPD ILED3 tD2 = t--F---2-P--5--W--5---M----x255–N–12---N-5---5--- (EQ. 13) ILED4 tPD tPD where (255/N) is rounded down to the nearest integer. For ILED5 example, if N = 6, (255/N) = 42, leading to: FIGURE 23. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY t = t x 42/255 D1 FPWM The ISL97671A allows the user to program the amount of phase tD2 = tFPWM x 45/255 shift degree with 7-bit resolution, as shown in Figure23. To enable programmable phase shifting, write to the Phase Shift where t is the sum of t and t . N is the number of LED FPWM ON OFF channels. The ISL97671A will detect the number of operating Control register with EqualPhase = 0 and the desirable phase channels automatically. shift value of PhaseShift[6:0]. The delay between CH5 and the repeated CH0 is the rest of the PWM cycle. PWMI 60% 40% Switching Frequency The default switching frequency is 600kHz but it can be selected ILED0 60% 40% from 600kHz or 1.2MHz if the SMBus/I2C communications is used. The switching frequency select bit is accessible in the tD1 ILED1 SMBus/I2C Configuration Register 0x08 Bit 2. tD1 ILED2 5V Low Dropout Regulator tD1 An internal 5V low dropout (LDO) regulator develops the ILED3 necessary low-voltage supply, which is used by the chip’s internal tD1 ILED4 control circuitry. VDC is the output of this LDO regulator, which tD1 requires a bypass capacitor of 1µF or more for the regulation. ILED5 The VDC pin can be used as a coarse reference as long as it is tD2 tFPWM sourcing only a few milliamps. ILED0 tON tOFF IC Protection Features and Fault Management FIGURE 21. 6 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION ISL97671A has several protection and fault management features that improve system reliability. The following sections describe them in more detail. FN7709 Rev.4.00 Page 13 of 28 Sep 14, 2017

ISL97671A Inrush Control and Soft-Start All LED faults are reported via the SMBus/I2C interface to Register 0x02 (Fault/Status register). The controller is able to The ISL97671A has separate, built-in, independent inrush control determine which channels have failed via Register 0x09 (Output and soft-start functions. The inrush control function is built Masking register). The controller can also choose to use Register around an external short-circuit protection P-channel FET in 0x09 to disable faulty channels at start-up, resulting in only series with V . At start-up, the fault protection FET is turned on IN further faulty channels being reported by Register 0x02. slowly due to a 21µA pull-down current output from the FAULT pin. This discharges the fault FET's gate-source capacitance, Short-Circuit Protection (SCP) turning on the FET in a controlled fashion. As this happens, the output capacitor is charged slowly through the low-current FET The short-circuit detection circuit monitors the voltage on each channel and disables faulty channels that are above before it becomes fully enhanced. This results in a low inrush approximately 7.5V. This action is described in Table2 on current. This current can be further reduced by adding a page16. capacitor (in the 1nF to 5nF range) across the gate source terminals of the FET. Open-Circuit Protection (OCP) Once the chip detects that the fault protection FET is turned on When one of the LEDs becomes an open circuit, it can behave as fully, it assumes that inrush is complete. At this point, the boost either an infinite resistance or as a gradually increasing finite regulator begins to switch, and the current in the inductor ramps resistance. The ISL97671A monitors the current in each channel up. The current in the boost power switch is monitored, and such that any string that reaches the intended output current is switching is terminated in any cycle in which the current exceeds considered “good.” Should the current subsequently fall below the the current limit. The ISL97671A includes a soft-start feature in target, the channel is considered an “open circuit.” Furthermore, which this current limit starts at a low value (275mA). This value should the boost output of the ISL97671A reach the OVP limit, or is stepped up to the final 2.2A current limit in seven additional should the lower over-temperature threshold be reached, all steps of 275mA each. These steps happen over at least 8ms and channels that are not good are immediately considered to be open are extended at low LED PWM frequencies if the LED duty cycle is circuit. Detection of an open circuit channel results in a time-out low. This extension allows the output capacitor to charge to the before the affected channel is disabled. This time-out is sped up required value at a low current limit and prevents high input when the device is above the lower over-temperature threshold, in current for systems that have only a low to medium output an attempt to prevent the upper over-temperature trip point from current requirement. being reached. For systems with no master fault protection FET, the inrush Some users employ special types of LEDs that have a Zener current flows towards COUT when VIN is applied. The inrush diode structure in parallel with the LED. This configuration current is determined by the ramp rate of V and the values of IN provides ESD enhancement and enables open-circuit operation. C and L. OUT When this type of LED is open circuited, the effect is as if the LED forward voltage has increased but the lighting level has not Fault Protection and Monitoring increased. Any affected string will not be disabled, unless the The ISL97671A features extensive protection functions to cover failure results in the boost OVP limit being reached, which allows all perceivable failure conditions. all other LEDs in the string to remain functional. In this case, ensure that the boost OVP limit and SCP limit are set properly, so The failure mode of an LED can be either an open circuit or a that multiple failures on one string do not cause all other good short. The behavior of an open-circuited LED can additionally channels to fault out. This condition could arise if the increased take the form of either infinite resistance or, for some LEDs, a forward voltage of the faulty channel makes all other channels Zener diode, which is integrated into the device in parallel with look as if they have LED shorts. Refer to Table2 on page16 for the now-opened LED. details about responses to fault conditions. For basic LEDs (which do not have built-in Zener diodes), an open-circuit failure of an LED results only in the loss of one OVP and VOUT channel of LEDs, without affecting other channels. Similarly, a The Overvoltage Protection (OVP) pin sets the overvoltage trip short-circuit condition on a channel that results in that channel level and limits the V regulation range. OUT being turned off does not affect other channels unless a similar The ISL97671A OVP threshold is set by R and R such fault is occurring. UPPER LOWER that: Due to the lag in boost response to any load change at its output, certain transient events (such as LED current steps or significant R +R  UPPER LOWER step changes in LED duty cycle) can transiently look like LED V = 1.22Vx------------------------------------------------------------ (EQ. 14) OUT_OVP R fault modes. The ISL97671A uses feedback from the LEDs to LOWER determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any and the output voltage VOUT can regulate between 64% and of the LED stacks to fault out. Refer to Table2 on page16 for 100% of the VOUT_OVP such that: details. Allowable V = 64% to 100% of V OUT OUT_OVP A fault condition that results in an input current that exceeds the If R and R are chosen such that the OVP level is set at 40V, device’s electrical limits will result in a shutdown of all output 1 2 then V is allowed to operate between 25.6V and 40V. If the channels. OUT V requirement is changed to an application of six LEDs of 21V, OUT FN7709 Rev.4.00 Page 14 of 28 Sep 14, 2017

ISL97671A then the OVP level must be reduced. Follow the V =(64% start-up, the LX pins inject a fixed current into the output OUT ~100%) OVP level requirement, otherwise the headroom control capacitor. The device does not start unless the voltage at LX will be disturbed such that the channel voltage can be much exceeds 1.2V. The OVP pin is also monitored such that if it rises higher than expected. This can sometimes prevent the driver above and subsequently falls below 20% of the target OVP level, from operating properly. the input protection FET is also switched off. The resistances should be large to minimize power loss. For Over-Temperature Protection (OTP) example, a 1MΩ R and a 30kΩ R sets OVP to 41.9V. UPPER LOWER The ISL97671A includes two over-temperature thresholds. The lower Large OVP resistors also allow C to discharge slowly during the OUT threshold is set to +130°C. When this threshold is reached, any PWM Off time. Parallel capacitors should also be placed across channel that is outputting current at a level significantly below the the OVP resistors such that R /R = C /C . UPPER LOWER LOWER UPPER regulation target is treated as “open circuit” and is disabled after a Using a C value of 30pF is recommended. These capacitors UPPER time-out period. This time-out period is 800µs when it is above the reduce the AC impedance of the OVP node, which is important lower threshold. The lower threshold isolates and disables bad when using high-value resistors. For example, if channels before they cause enough power dissipation (as a result of R /R = 33/1, then C /C = 1/33 with UPPER LOWER UPPER LOWER other channels having large voltages across them) to hit the upper C = 100pF and C =3.3nF UPPER LOWER temperature threshold. Undervoltage Lock-out The upper threshold is set to +150°C. Each time this threshold is If the input voltage falls below the UVLO level, the device stops reached, the boost stops switching, and the output current switching and is reset. Operation restarts only when V returns sources switch off. Once the device has cooled to approximately IN to the normal operating range. +100°C, the device restarts, with the DC LED current level reduced to 75% of the initial setting. If dissipation persists, Input Overcurrent Protection subsequent hitting of the limit causes identical behavior, with the During a normal switching operation, the current through the current reduced in steps to 50% and finally 25%. Unless disabled internal boost power FET is monitored. If the current exceeds the via the EN pin, the device stays in an active state throughout. current limit, the internal switch is turned off. Monitoring occurs For complete details about fault protection conditions, refer to on a cycle-by-cycle basis in a self-protecting way. Additionally, the Figure24 and Table2. ISL97671A monitors the voltage at the LX and OVP pins. At VIN LX VOUT FAULT O/P DRIVER SHORT OVP IMAX ILIMIT LOGIC DRFIEVTER VSC CH0 CH5 VSET/2 REG TTHHRRMM SSHHDDNN REF T2 TEMP OOTTPP SENSOR T1 VSET + Q0 VSET + Q5 - - PWM/OC0/SC0 PWM/OC5/SC5 FAULT/ SMBUS/I2C STATUS CONTROL REGISTER LOGIC DC CURRENT FIGURE 24. SIMPLIFIED FAULT PROTECTIONS FN7709 Rev.4.00 Page 15 of 28 Sep 14, 2017

ISL97671A TABLE 2. PROTECTIONS TABLE V OUT CASE FAILURE MODE DETECTION MODE FAILED CHANNEL ACTION GOOD CHANNELS ACTION REGULATED BY 1 CHx Short-Circuit Upper Over-Temperature CHx ON and burns power. Remaining channels normal Highest VF of all Protection limit (OTP) not channels triggered and CHx < 7.5V 2 CHx Short-Circuit Upper OTP triggered but All channels turn off until chip Same as CHx Highest VF of CHx < 7.5V cooled, then turn back on with remaining current reduced to 76%. Subsequent channels OTP triggers will reduce I further. OUT 3 CHx Short-Circuit Upper OTP not triggered CHx disabled after 6 PWM cycle Remaining channels normal Highest VF of but CHx > 7.5V time-outs. remaining channels 4 CHx Open Circuit with Upper OTP not triggered V will ramp to OVP. CHx will time- Remaining channels normal Highest VF of OUT infinite resistance and CHx < 7.5V out after 6 PWM cycles and switch remaining off. V will drop to normal level. channels OUT 5 CHx LED Open Circuit Upper OTP not triggered CHx remains ON and has highest VF, Remaining channels ON, VF of CHX but has paralleled and CHx < 7.5V thus V increases. remaining channel FETs burn OUT Zener power 6 CHx LED Open Circuit Upper OTP triggered but All channels turn off until chip Same as CHx VF of CHx but has paralleled CHx < 7.5V cooled, then turn back on with Zener current reduced to 76%. Subsequent OTP triggers will reduce I further. OUT 7 CHx LED Open Circuit Upper OTP not triggered CHx remains ON and has highest VF, V increases, then CH-X VF of CHx OUT but has paralleled but CHx > 7.5V thus V increases. switches OFF after 6 PWM cycles. OUT Zener This is an unwanted shut off and can be prevented by setting OVP at an appropriate level. 8 Channel-to-Channel Lower OTP triggered but Any channel below the target current will fault out after 6 PWM cycles. Highest VF of VF too high CHx < 7.5V Remaining channels driven with normal current. remaining channels 9 Channel-to-Channel Upper OTP triggered but All channels go off until chip cools and then come back on with current Boost switch OFF VF too high CHx < 7.5V reduced to 76%. Subsequent OTP triggers will reduce I further. OUT 10 Output LED stack V > VOVP Any channel that is below the target current will time-out after 6 PWM Highest VF of OUT voltage too high cycles, and V will return to the normal regulation voltage required for remaining OUT other channels. channels 11 V /LX shorted to LX current and timing are The chip is permanently shutdown 31ms after power-up if V /Lx is OUT OUT GND at start-up or monitored. shorted to GND. V shorted in OVP pins monitored for OUT operation excursions below 20% of OVP threshold. FN7709 Rev.4.00 Page 16 of 28 Sep 14, 2017

ISL97671A SMBCLK tLOW tR tF VIH VIL tHIGH tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO SMBDAT VIH VIL P tBUF S S P NOTES: SMBus/I2C Description S = start condition P = stop condition A = acknowledge A = not acknowledge R/W = read enable at high; write enable at low FIGURE 25. SMBUS/I2C INTERFACE 1 7 1 1 8 1 8 1 1 S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P MASTER TO SLAVE SLAVE TO MASTER FIGURE 26. WRITE BYTE PROTOCOL 1 7 1 1 8 1 1 8 1 1 8 1 1 S SLAVE W A COMMAND A S SLAVE R A Data Byte A P ADDRESS CODE ADDRESS MASTER TO SLAVE SLAVE TO MASTER FIGURE 27. READ BYTE PROTOCOL FN7709 Rev.4.00 Page 17 of 28 Sep 14, 2017

ISL97671A SMBus/I2C Communications Slave Device Address The ISL97671A can be controlled by the SMBus/I2C for PWM or DC The slave address contains seven MSB plus one LSB as a R/W bit, dimming. The LEDs are off by default and the user must use the but these eight bits are usually called Slave Address bytes. Figure28 SMBus/I2C interface to turn them on, except when both the SDA shows that the high nibble of the Slave Address byte is 0x5 or 0101b and SCL input pins are tied to ground. When both SDA and SCL are to denote the “backlight controller class.” Bit 3 in the lower nibble of shorted to ground, the LEDs turn on by default when the IC is turned the Slave Address byte is 1. Bit 0 is always the R/W bit, as specified on, and the customer can use the ISL97671A without having to by the SMBus/I2C protocol. control the SMBus/I2C interface. The switching frequency is fixed at Note: In this document, the device address will always be expressed 600kHz if SMBus/I2C is not used. as a full 8-bit address instead of the shorter 7-bit address typically Write Byte used in other backlight controller specifications to avoid confusion. Therefore, if the device is in the write mode where Bit 0 is 0, the The Write Byte protocol is only three bytes long. The first byte starts slave address byte is 0x58 or 01011000b. If the device is in the read with the slave address followed by the “command code,” which mode where Bit 0 is 1, the slave address byte is 0x59 or translates to the “register index” being written. The third byte 01011001b. contains the data byte that must be written into the register selected by the “command code”. A shaded label is used on cycles during SMBus/I2C Register Definitions which the slaved backlight controller “owns” or “drives” the Data The backlight controller registers are a byte wide and accessible via line. All other cycles are driven by the “host master.” the SMBus/I2C Read/Write Byte protocols. Their bit assignments are Read Byte provided in the following sections with reserved bits containing a default value of “0”. Figure27 on page17 shows that the four byte long Read Byte protocol starts out with the slave address followed by the MSB LSB “command code” which translates to the “register index.” Subsequently, the bus direction turns around with the re-broadcast of the slave address with Bit 0 indicating a read (“R”) cycle. The 0 1 0 1 1 0 0 R/W fourth byte contains the data being returned by the backlight controller. That byte value in the data byte reflects the value of the register being queried at the “command code” index. Note the bus T DEVICE DEVICE BI directions, which are highlighted by the shaded label that is used IDENTIFIER ADDRESS TE on cycles during which the slaved backlight controller “owns” or RI W “drives” the Data line. All other cycles are driven by the “host D/ A master.” RE FIGURE 28. SLAVE ADDRESS BYTE DEFINITION FN7709 Rev.4.00 Page 18 of 28 Sep 14, 2017

ISL97671A TABLE 3A. ISL97671A REGISTER LISTING DEFAULT SMBUS/I2C ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VALUE PROTOCOL 0x00 PWM BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 0xFF Read and Write Brightness Control Register 0x01 Device Control Reserved Reserved Reserved Reserved Reserved PWM_MD PWM_SEL BL_CTL 0x00 Read and Write Register 0x02 Fault/Status Reserved Reserved 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN FAULT 0x00 Read Only Register 0x03 Identification LED MFG3 MFG2 MFG1 MFG0 REV2 REV1 REV0 0xC8 Read Only Register PANEL 0x07 DC Brightness BRTDC7 BRTDC6 BRTDC5 BRTDC4 BRTDC3 BRTDC2 BRTDC1 BRTDC0 0xFF Read and Write Control Register 0x08 Configuration Reserved Reserved Reserved BstSlew BstSlew FSW Reserved VSC 0x1F Read and Write Register Rate1 Rate0 0x09 Output Channel Reserved Reserved CH5 CH4 CH3 CH2 CH1 CH0 0x3F Read and Write Register 0x0A Phase Shift Equal Phase Phase Phase Phase Phase Phase Phase 0x00 Read and Write Deg Phase Shift6 Shift5 Shift4 Shift3 Shift2 Shift1 Shift0 TABLE 3B. DATA BIT DESCRIPTIONS ADDRESS REGISTER DATA BIT DESCRIPTIONS 0x00 PWM Brightness Control Register BRT[7..0] = 256 steps of DPWM duty cycle brightness control 0x01 Device Control Register PWM_MD, PWM_SEL: select the dimming method. Refer to Table4 for more details. Default = 00 BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0 0x02 Fault/Status Register 2_CH_SD = Two LED output channels are shutdown (1 = Shutdown, 0 = OK) 1_CH_SD = One LED output channel is shutdown (1 = Shutdown, 0 = OK) BL_STAT = BL status (1 = BL On, 0 = BL Off) OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK) THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK) FAULT = Fault occurred (Logic “OR” of all of the fault conditions) 0x03 Identification Register LED PANEL = 1 MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9) REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) 0x07 DC Brightness Control Register BRTDC[7..0] = 256 steps of DC brightness control 0x08 Configuration Register BstSlewRate[1..0] = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50% drive strength, 10 - 75% drive strength, 11 - 100% drive strength. f = Switching frequencies selection, f = 0 = 1.2MHz. f = 1 = 600kHz SW SW SW VSC[0] = Short-circuit thresholds selection, 0 = disabled, 1 = 7.2V minimum 0x09 Output Channel Mask/Fault CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In Readout Register Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled 0x0A Phase Shift Degree EqualPhase = Controls phase shift mode. When 1, phase shift is 360/N (where N is the number of channels enabled). When 0, phase shift is defined by PhaseShift<6:0>. PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz. FN7709 Rev.4.00 Page 19 of 28 Sep 14, 2017

ISL97671A PWM Brightness Control Register (0x00) Device Control Register (0x01) The Brightness control resolution has 256 steps of PWM duty cycle This register has two bits that control either SMBus/I2C adjustment. Figure29 shows the bit assignment. All of the bits in controlled or external PWM controlled PWM dimming and a this Brightness Control Register can be read or written. Step 0 single bit that controls the backlight ON/OFF state. The corresponds to the minimum step where the current is less than remaining bits are reserved. The bit assignment is shown in 10µA. Steps 1 to 255 represent the linear steps between 0.39% and Figure30. All other bits in the Device Control Register will read as 100% duty cycle with approximately 0.39% duty cycle adjustment low unless otherwise written. per step. • All reserved bits have no functional effect when written. • An SMBus/I2C Write Byte cycle to Register 0x00 sets the PWM • All defined control bits return their current, latched value when brightness level only if the backlight controller is in SMBus/I2C read. mode (see Table4). Operating Modes are selected by Device A value of 1 written to BL_CTL turns on the backlight in 4ms or less Control Register Bits 1 and 2. after the write cycle completes. The backlight is deemed to be on • An SMBus/I2C Read Byte cycle to Register 0x00 returns the when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not0. programmed PWM brightness level. A value of 0 written to BL_CTL immediately turns off the BL. The • An SMBus/I2C setting of 0xFF for Register 0x00 sets the BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 backlight controller to the maximum brightness. and Register 0x09 is 0. • An SMBus/I2C setting of 0x00 for Register 0x00 sets the The default value for Register 0x01 is 0x00. backlight controller to the minimum brightness output. • The default value for Register 0x00 is 0xFF. REGISTER 0x00 PWM BRIGHTNESS CONTROL REGISTER BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BIT FIELD DEFINITIONS BRT[7..0] = 256 steps of PWM brightness levels FIGURE 29. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER REGISTER 0x01 DEVICE CONTROL REGISTER RESERVED RESERVED RESERVED RESERVED RESERVED PWM_MD PWM_SEL BL_CTL Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) PWM_MD PWM_SEL BL_CTL MODE X X 0 Backlight Off 0 0 1 SMBus/I2C and PWM input controlled (DPST) dimming (Method 3) 1 0 1 SMBus/I2C controlled PWM dimming (Method 1) X 1 1 PWM input controlled PWM dimming (Method 2) FIGURE 30. DESCRIPTIONS OF DEVICE CONTROL REGISTER FN7709 Rev.4.00 Page 20 of 28 Sep 14, 2017

ISL97671A TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL For example, the Cbt = 50% duty cycle programmed in the REGISTER BITS 1 AND 2 SMBus/I2C Register 0x00 and the PWM frequency is tuned to be 200Hz with an appropriate capacitor at the FPWM pin. On the other PWM_MD PWM_SEL MODE hand, PWM is fed with a 1kHz 30% high PWM signal. When 0 0 SMBus/I2C and PWM input controlled PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation (DPST) dimming (Method 3) where DPST brightness = 15% PWM dimming at 200Hz. 1 0 SMBus/I2C controlled PWM dimming (Method 1) Fault/Status Register (0x02) X 1 PWM input controlled PWM dimming This register has six status bits that allow monitoring of the (Method 2) backlight controller’s operating state. Not all of the bits in this register are fault related (Bit 3 is a simple BL status indicator). The The PWM_SEL bit determines whether the SMBus/I2C or PWM remaining bits are reserved and return a “0” when read and ignore input should drive the output brightness in terms of PWM the bit value when written. All of the bits in this register are read- dimming. When PWM_SEL bit is 1, the PWM input only drives the only, with the exception of Bit 0, which can be cleared by writing to it. output brightness regardless of what the PWM_MD is. • BL_STAT indicates the current backlight on/off status in When the PWM_SEL bit is 0, the PWM_MD bit selects the BL_STAT (1 if the BL is on, 0 if the BL is off). manner in which the PWM dimming is to be interpreted. When • FAULT is the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, this bit is 1, the PWM dimming is based on the SMBus/I2C and 1_CH_SD should these events occur. brightness setting only. When this bit is 0, the PWM dimming reflects a percentage change in the current brightness • 1_CH_SD returns a 1 if one or more channels have faulted out. programmed in the SMBus/I2C Register 0x00, i.e., DPST (Display • 2_CH_SD returns a 1 if two or more channels have faulted out. Power Saving Technology) mode as: • When FAULT is set to 1, it will remain at 1 even if the signal DSPT Brightness = CbtPWM (EQ. 15) which sets it goes away. FAULT will be cleared when the BL_CTL bit of the Device Control Register is toggled or when a where: 0 is written into the FAULT bit. At that time, if the fault Cbt = Current brightness setting from SMBus/I2C Register 0x00 condition is still present or reoccurs, FAULT will be set to 1 again. BL_STAT will not cause FAULT to be set. without influence from the PWM • The default value for Register 0x02 is 0x00. PWM = is the percent duty cycle of the PWM REGISTER 0x02 FAULT/STATUS REGISTER RESERVED RESERVED 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN FAULT Bit 7 (R) Bit 6 (R) Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R) Bit 0 (R) BIT BIT ASSIGNMENT BIT FIELD DEFINITIONS Bit 5 2_CH_SD Two LED output channels are shutdown (1 = shutdown, 0 = OK) Bit 4 1_CH_SD One LED output channel is shutdown (1 = shutdown, 0 = OK) Bit 3 BL_STAT BL Status (1 = BL On, 0 = BL Off) Bit 2 OV_CURR Input Overcurrent (1 = Overcurrent condition, 0 = Current OK) Bit 1 THRM_SHDN Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK) Bit 0 FAULT Fault occurred (Logic “OR” of all of the fault conditions) FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER FN7709 Rev.4.00 Page 21 of 28 Sep 14, 2017

ISL97671A Identification Register (0x03) DC Brightness Control Register (0x07) The ID register contains three bit fields to denote the LED driver The DC Brightness Control Register 0x07 sets the LED current (always set to 1), manufacturer, and the silicon revision of the level between 0% and 100% of the level set using the RSET pin. controller IC. The bit field widths allow up to 16 vendors with up to When PWM dimming, the level set is the current during the on eight silicon revisions each. All of the bits in this register are read- time. This register allows additional dimming flexibility by: only. 1. Effectively achieving 16-bits of dimming control when DC • Vendor ID 9 represents Intersil Corporation. dimming is combined with PWM dimming 2. Achieving visual or audio noise free 8-bit DC dimming over • The default value for Register 0x03 is 0xC8. potentially noisy PWM dimming. The initial value of REV is 0. Subsequent values of REV will The bit assignment is shown in Figure33. All of the bits in this increment by 1. register can be read or written. Steps 0 to 255 represent the linear steps of current adjustment in DC on-the-fly. • An SMBus/I2C Write Byte cycle to Register 0x07 sets the DC LED current level. • An SMBus/I2C Read Byte cycle to Register 0x07 returns the DC LED current. • The default value for Register 0x07 is 0xFF. REGISTER 0x03 ID REGISTER LED PANEL MFG3 MFG2 MFG1 MFG0 REV2 REV1 REV0 Bit 7 = 1 Bit 6 (R) Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R) Bit 0 (R) BIT ASSIGNMENT BIT FIELD DEFINITIONS MFG[3..0] = Manufacturer ID. Refer to “Identification Register (0x03)” on page21. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents Intersil ID data 10 to 14 in decimal are reserved data 15 in decimal Manufacturer ID is not implemented REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) FIGURE 32. DESCRIPTIONS OF ID REGISTER REGISTER 0x07 DC BRIGHTNESS CONTROL REGISTER BRTDC7 BRTDC6 BRTDC5 BRTDC4 BRTDC3 BRTDC2 BRTDC1 BRTDC0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BIT FIELD DEFINITIONS BRTDC[7..0] = 256 steps of DC brightness levels FIGURE 33. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER FN7709 Rev.4.00 Page 22 of 28 Sep 14, 2017

ISL97671A Configuration Register (0x08) Output Channel Mask/Fault Readout Register (0x09) The Configuration Register provides many extra functions that can optimize the driver performance at a given application. This register can be read or written. It allows enabling and A BstSlewRate bit allows users to control the boost FET slew rate disabling each channel individually. The bit position corresponds (the rates of turn-on and turn-off). The slew rate can be selected to the channel. For example, Bit 0 corresponds to Ch0, Bit 5 to four relative strengths when driving the internal boost FET. This corresponds to Ch5, and so on. A 1 bit value enables the channel allows users to experiment with the slew rate with respect to EMI of interest. When reading data from this register, any disabled effect in the system. In general, the slower the slew rate is, the channel and any faulted out channel will read as0. This allows lower the EMI interference to the surrounding circuits. However, the user to determine which channel is faulty and optionally not the switching loss of the boost FET is also increased. enabling it in order to allow the rest of the system to continue to function. Additionally, a faulted out channel can be disabled and The FSW bit allows users to set the boost converter switching re-enabled in order to allow a retry for any faulty channel without frequency between 1.2MHz and 600kHz. The VSC bit allows having to power-down the other channels. users to set the LED string short-circuit threshold VSC to 7.2V or disable it. The bit assignment is shown in Figure35. The default value for Register 0x09 is 0x3F. The bit assignment is shown in Figure34. The default value for Register 0x08 is 0x1F. REGISTER 0x08 CONFIGURATION REGISTER RESERVED RESERVED BIT5 BIT4 BIT3 FSW RESERVED VSC Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BIT FIELD DEFINITIONS BstSlewRate[1:0] Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength, 10 -75% drive strength, 11 to 100% drive strength. FSW Two levels of switching frequencies (0 = 1.2MHz, 1 = 600kHz) VSC Enable / disable short-circuit protection (0 = Disabled, 1 = 7.5V minimum) FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER REGISTER 0x09 OUTPUT CHANNEL REGISTER RESERVED RESERVED CH5 CH4 CH3 CH2 CH1 CH0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BIT FIELD DEFINITIONS CH[5..0] CH5 = Channel 5, CH4 = Channel 4 and so on FIGURE 35. OUTPUT CHANNEL REGISTER FN7709 Rev.4.00 Page 23 of 28 Sep 14, 2017

ISL97671A REGISTER 0x0A PHASE SHIFT CONTROL REGISTER EQUALPHASE PHASESHIFT6 PHASESHIFT5 PHASESHIFT4 PHASESHIFT3 PHASESHIFT2 PHASESHIFT1 PHASESHIFT0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BIT FIELD DEFINITIONS EqualPhase Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift is 360/N (where N is the number of channels enabled). PhaseShift[6..0] 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq) FIGURE 36. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER Phase Shift Control Register (0x0A) Input Capacitor The Phase Shift Control register sets phase delay between Switching regulators require input capacitors to deliver peak channels. When Bit 7 is set high, the phase delay is set by the charging current and to reduce the impedance of the input number of channels enabled and the PWM frequency. Referring supply. The capacitors reduce interaction between the regulator to Figure3 on page8, the delay time is defined by Equation16: and input supply, thus improving system stability. The high t = t N (EQ. 16) switching frequency of the loop causes almost all ripple current D1 FPWM to flow into the input capacitor, which must be rated accordingly. where N is the number of channels enabled, and t is the FPWM A capacitor with low internal series resistance should be chosen period of the PWM cycle. When Bit 7 is set low, the phase delay is to minimize heating effects and to improve system efficiency. set by Bits 6:0 and the PWM frequency. Referencing Figure23, The X5R and X7R ceramic capacitors offer small size and a lower the programmable delay time is defined by Equation17: value for temperature and voltage coefficient compared to other t = PS60xt 255 (EQ. 17) ceramic capacitors. PD FPWM An input capacitor of 10µF is recommended. Ensure that the where PS is an integer from 0 to 127, and t is the period of FPWM voltage rating of the input capacitor is able to handle the full the PWM cycle. By default, all the register bits are set low, which supply range. sets zero delay between each channel. Note: Do not program the register to have more than one period Inductor of the PWM cycle delay between the first and last enabled Inductor selection should be based on its maximum current (I ) SAT channels. characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value Component Selections influence many key parameters, including ripple current, current limit, efficiency, transient performance, and stability. According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On Inductor maximum current capability must be adequate to time is equal to the change of inductor current during the handle the peak current in the worst-case condition. If an switching regulator Off time. As shown in Equations18 and 19, inductor core with too low a current rating is chosen, saturation since the voltage across an inductor is: in the core will cause the effective inductor value to fall, leading V to an increase in peak-to-average current level, poor efficiency, L I = -------xt (EQ. 18) L L and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A and IL at On = IL at Off, therefore: shielded inductor is usually more suitable for EMI-susceptible applications such as LED backlighting. V –0LDt = V –V –VL1–Dt (EQ. 19) I S O D I S The peak current can be derived from the voltage across the where D is the switching duty cycle defined by the turn-on time inductor during the Off period, as shown in Equation22: over the switching period. V is a Schottky diode forward voltage D IL = V I 85%V +12V V –V LV f  that can be neglected for approximation. peak O O I I O I O S (EQ. 22) Rearranging the terms without accounting for V gives the boost D The value of 85% is an average term for the efficiency ratio and duty cycle, respectively, as shown in Equations20 and21: approximation. The first term is average current that is inversely V V =11–D (EQ. 20) proportional to the input voltage. The second term is inductor O I current change that is inversely proportional to L and f . As a S D = V –V V (EQ. 21) result, for a given switching frequency and minimum input O I O voltage at which the system operates, the inductor I must be SAT chosen carefully. FN7709 Rev.4.00 Page 24 of 28 Sep 14, 2017

ISL97671A Output Capacitors Applications The output capacitor smooths the output voltage and supplies High-Current Applications load current directly during the conduction phase of the power switch. Output ripple voltage consists of discharge and charge of Each channel of the ISL97671A can support up to 30mA the output capacitor during FET On and OFF time and the voltage (50mAat V = 12V). For applications that need higher current, IN drop due to flow through the ESR of the output capacitor. The multiple channels can be grouped to achieve the desired current ripple voltage can be shown as Equation23: (Figure37). For example, the cathode of the last LED can be V = I C Df +I ESR (EQ. 23) connected to CH0 through CH2; this configuration can be treated C O O S O O as a single string with 90mA current driving capability. The conservation of charge principle shown in Equation21 also VOUT indicates that, during the boost switch Off period, the output capacitor is charged with the inductor ripple current, minus a relatively small output current in boost topology. As a result, the user must select an output capacitor with low ESR and adequate input ripple current capability. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. C in Equation23 assumes the effective value of the capacitor at CH0 O a particular voltage and not the manufacturer’s stated value, CH1 measured at 0V. CH2 The value of VC can be reduced by increasing C or f , or by O O S using small ESR capacitors. In general, ceramic capacitors are the best choice for output capacitors in small- to medium-sized FIGURE 37. GANGING MULTIPLE CHANNELS FOR HIGH CURRENT APPLICATIONS LCD backlight applications, due to their cost, form factor, and low ESR. Low Voltage Operations A larger output capacitor also eases driver response during the The ISL97671A VIN pin can be separately biased from the LED PWM dimming Off period, due to the longer sample and hold power input to allow low-voltage operation. effect of the output drooping. The driver does not need to boost harder in the next On period that minimizes transient current. In systems that have only a single supply, VOUT can be tied to the driver VIN pin to allow initial start-up (Figure38). The circuit The output capacitor is also needed for compensation, and in works as follows: when the input voltage is available and the general, 2x4.7µF/50V ceramic capacitors are suitable for device is not enabled, V follows V with a Schottky diode notebook display backlight applications. OUT IN voltage drop. The V boot-strapped to the VIN pin allows initial OUT Output Ripple start-up, once the part is enabled. Once the driver starts up with V regulating to the target, the VIN pin voltage also increases. OUT VCO can be reduced by increasing CO or fSW, or by using small As long as VOUT does not exceed 26.5V and the extra power loss ESR capacitors. In general, ceramic capacitors are the best on V is acceptable, this configuration can be used for input IN choice for output capacitors in small to medium sized LCD voltage as low as 3.0V. The Fault Protection FET feature cannot backlight applications due to their cost, form factor, and low ESR. be used in this configuration. A larger output capacitor will also ease the driver response In systems that have dual supplies, the VIN pin can be biased during PWM dimming Off period due to the longer sample and from 5V to 12V, while input voltage can be as low as 2.7V hold effect of the output drooping. The driver does not need to (Figure39). In this configuration, VBIAS must be greater than or boost harder in the next On period that minimizes transient equal to VIN to use the fault FET. current. The output capacitor is also needed for compensation, and, in general 2x4.7µF/50V ceramic capacitors are suitable for notebook display backlight applications. Schottky Diode A high-speed rectifier diode is necessary to prevent excessive voltage overshoot. Schottky diodes are recommended because of their fast recovery time, low forward voltage, and reverse leakage current, which minimize losses. The reverse voltage rating of the selected Schottky diode must be higher than the maximum output voltage. Additionally, the average/peak current rating of the Schottky diode must meet the output current and peak inductor current requirements. FN7709 Rev.4.00 Page 25 of 28 Sep 14, 2017

ISL97671A Compensation VIN = 3V~21V 26.5V, 6 x 50mA* The ISL97671A incorporates a transconductance amplifier in its feedback path to allow the user to optimize boost stability and ISL97671A transient response. The ISL97671A uses current mode control 1 FAULT architecture, which has a fast current sense loop and a slow 2 VIN LX20 voltage feedback loop. The fast current feedback loop does not OVP16 require any compensation, but for stable operation, the slow 4 VDC voltage loop must be compensated. The compensation is a PGND19 series of Rc, Cc1 network from COMP pin to ground, with an 7 SMBCLK/SCL optional Cc2 capacitor connected between the COMP pin and 6 SMBDAT/SDA CH010 ground. The Rc sets the high-frequency integrator gain for fast CH111 5 PWM transient response, and the Cc1 sets the integrator zero to CH212 3 EN ensure loop stability. For most applications, the component CH313 values in Figure40 can be used: Rc is 10kΩ and Cc1 is 3.3nF. 17RSET CH414 Depending upon the PCB layout, for stability, a Cc2 of 390pF may 8 FPWM CH515 be needed to create a pole to cancel the output capacitor ESR’s 9 AGND COMP18 *VIN>12V zero effect. FIGURE 38. SINGLE SUPPLY 3V OPERATION Rc 10k COMP VIN = 2.7~26.5V 45V, 6 x 50mA* Cc1 Cc2 Q1(OPTIONAL) 3.3nF 390pF ISL97671A 1 FAULT VBIAS = 5V~12V LX20 2 VIN OVP16 FIGURE 40. COMPENSATION CIRCUIT 4 VDC PGND19 7 SMBCLK/SCL 6 SMBDAT/SDA CH010 CH111 5 PWM CH212 3 EN CH313 17RSET CH414 8 FPWM CH515 9 AGND COMP18 *VIN > 12V FIGURE 39. DUAL SUPPLIES 2.7V OPERATION 16-Bit Dimming The SMBus/I2C controlled PWM and DC dimmings can be combined to effectively provide 16 bits of dimming capability, which can be valuable for automotive and avionics display applications. Field Sequential RGB LED Backlighting The ISL97671A is able to turn each channel ON and OFF independently. In field sequential RGB LED application, it is possible to have different DC current and PWM duty cycle for different channels as long as only one channel is active at a time. This is achieved by continuously setting a new DC current and/or PWM duty cycle each time a channel is turned ON. The ISL97671A does not allow different DC currents or PWM duty cycles for channels that are ON at the same time. FN7709 Rev.4.00 Page 26 of 28 Sep 14, 2017

ISL97671A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE September 14, 2017 FN7709.4 Added Related Literature section. Added V spec to EC table on page6. HEADROOM_RANGE Fixed parentheses in Equation 23. Fixed Bit Field Definitions for Bit FSW in Figure 34. Fixed FSW frequencies in Table 3B. October 3, 2012 FN7709.3 Minor changes to improve the wording of various sections. page5 - Thermal Information, removed Pb-Free Reflow Profile link. page 6- V in the spec table, changed to Min 1.199 and Max 1.24 from Min 1.19 and Max 1.24 OVPlo page 8 - Figure 3 “EFFICIENCY vs up to 20mA LED CURRENT (100% LED DUTY CYCLE) vs VIN” removed. page9 - Figures 11, 12 replaced to clear waveforms page12 & page16 respectively, Tables 1, 2 improved. page18 - I2C section, specified that the backlight can turns on when SDA/SCL are connected to ground. page20 - Improved description of PWM_MD and PWM_SEL I2C register bits. Corrected Figure 30. Removed Direct PWM and PWM-to-DC register bits from the description July 11, 2012 FN7709.2 PWM-to-DC bit and BstSlewRate bit in the register 0x08 updated on page19, page22 and page23. In “Current Matching and Current Accuracy” on page11, changed 401.8 to 410.5. On page11 Equation 1, changed 401.8 to 410.5. March 24, 2011 FN7709.1 Initial Release to web. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com. For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary. You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2011-2017. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7709 Rev.4.00 Page 27 of 28 Sep 14, 2017

ISL97671A Package Outline Drawing For the most recent package outline drawing, see L20.3x4. L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3.00 A 0.10M C A B 0.05M C 16X 0.50 B 4 20X 0.25+-00..0075 6 A 17 20 P(CIN 0 .14 0IN)DEX AREA 6 16 1 PIN 1 INDEX AREA 4.00 2.65+0.10 -0.15 11 6 A 0.15 (4X) 10 7 VIEW "A-A" 1.65+0.10 -0.15 TOP VIEW 20x 0.40±0.10 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0.9± 0.10 SEATING PLANE 0.08 C (16 x 0.50) SIDE VIEW (2.65) (3.80) (20 x 0.25) C 0.2 REF 5 (20 x 0.60) 0.00 MIN. (1.65) 0.05 MAX. (2.80) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. FN7709 Rev.4.00 Page 28 of 28 Sep 14, 2017