DATASHEET ISL97519A FN6683 600kHz/1.2MHz PWM Step-Up Regulator Rev 3.00 February 16, 2012 The ISL97519A is a high frequency, high efficiency step-up Features voltage regulator operated at constant frequency PWM mode. With an internal 2.0A, 200m MOSFET, it can deliver up to 1A • >90% Efficiency output current at over 90% efficiency. Two selectable • 2.0A, 200m Power MOSFET frequencies, 600kHz and 1.2MHz, allow trade offs between • 2.3V to 5.5V Input smaller components and faster transient response. An external compensation pin gives the user greater flexibility in • 1.1*VIN up to 25V Output setting frequency compensation allowing the use of low ESR • 600kHz/1.2MHz Switching Frequency Selection Ceramic output capacitors. • Adjustable Soft-Start When shut down, it draws <1µA of current and can operate • Internal Thermal Protection down to 2.3V input supply. These features, along with 1.2MHz switching frequency, make it an ideal device for portable • 1.1mm Max Height 8 Ld MSOP Package equipment and TFT-LCD displays. • Pb-Free (RoHS compliant) The ISL97519A is available in an 8 Ld MSOP package with a • Halogen Free maximum height of 1.1mm. The device is specified for Applications operation over the full -40°C to +85°C temperature range. • TFT-LCD displays • DSL modems • PCMCIA cards • Digital cameras • GSM/CDMA phones • Portable equipment • Handheld devices FSEL EN SS SHUTDOWN REFERENCE VDD OSCILLATOR AND START-UP GENERATOR CONTROL LX PWM LOGIC FET CONTROLLER DRIVER COMPARATOR CURRENT GND SENSE FB GM AMPLIFIER COMP FN6683 Rev 3.00 Page 1 of 9 February 16, 2012

ISL97519A Pin Configuration ISL97519A (8 LD MSOP) TOP VIEW COMP 1 8 SS FB 2 7 FSEL EN 3 6 VDD GND 4 5 LX Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 COMP Compensation pin. Output of the internal error amplifier. Capacitor and resistor from COMP pin to ground. 2 FB Voltage feedback pin. Internal reference is 1.24V nominal. Connect a resistor divider from VOUT. VOUT=1.24V (1 + R1/R2). See “Typical Application Circuit” on page2. 3 EN Shutdown control pin. Pull EN low to turn off the device. 4 GND Analog and power ground. 5 LX Power switch pin. Connected to the drain of the internal power MOSFET. 6 VDD Analog power supply input pin. 7 FSEL Frequency select pin. When FSEL is set low, switching frequency is set to 620kHz. When connected to high or VDD, switching frequency is set to 1.25MHz. 8 SS Soft-start control pin. Connect a capacitor to control the converter start-up. Typical Application Circuit R3 1 COMP SS 8 C4 1k OPEN R1 85.2k 2 FB FSEL 7 27nF C5 R2 4.7nF C5 10k 3 EN VDD 6 2.3V TO 5.5V C2 + C1 4 GND LX 5 0.1µF 22µF 10µH 12V S1 + C3 D1 22µF Ordering Information PART NUMBER PART PACKAGE PKG. (Notes 2, 3) MARKING (Pb-Free) DWG. # ISL97519AIUZ 7519A 8 Ld MSOP M8.118A ISL97519AIUZ-T (Note 1) 7519A 8 Ld MSOP M8.118A ISL97519AIUZ-TK (Note 1) 7519A 8 Ld MSOP M8.118A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97519A. For more information on MSL please see techbrief TB363. FN6683 Rev 3.00 Page 2 of 9 February 16, 2012

ISL97519A Absolute Maximum Ratings (TA = +25°C) Thermal Information LX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27V Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C COMP, FB, EN, SS, FSEL to GND . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves on page5 Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VIN = 3.3V, VOUT = 12V, IOUT = 0mA, FSEL = GND, TA = -40°C to +85°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. MIN MAX PARAMETER DESCRIPTION CONDITIONS (Note 4) TYP (Note 4) UNIT IQ1 Quiescent Current - Shutdown EN = 0V 1 5 µA IQ2 Quiescent Current - Not Switching EN = VDD, FB = 1.3V 0.7 mA IQ3 Quiescent Current - Switching EN = VDD, FB = 1.0V 3 4.5 mA VFB Feedback Voltage 1.228 1.24 1.252 V IB-FB Feedback Input Bias Current 0.01 0.5 µA VDD Input Voltage Range 2.3 5.5 V DMAX-600kHz Maximum Duty Cycle FSEL = 0V 85 92 % DMAX-1.2MHz Maximum Duty Cycle FSEL = VDD 85 90 % ILIM1 Current Limit - Max Peak Input Current VDD < 2.8V 1.0 A ILIM2 Current Limit - Max Peak Input Current VDD > 2.8V 1.5 2.0 A IEN Shutdown Input Bias Current EN = 0V 0.01 0.5 µA rDS(ON) Switch ON-Resistance VDD = 2.7V, ILX = 1A 0.2  ILX-LEAK Switch Leakage Current VSW = 27V 0.01 3 µA VOUT/VIN Line Regulation 3V < VIN < 5.5V, VOUT = 12V 0.2 % VOUT/IOUT Load Regulation VIN = 3.3V, VOUT = 12V, IO = 30mA to 200mA 0.3 % FOSC1 Switching Frequency Accuracy FSEL = 0V 500 620 740 kHz FOSC2 Switching Frequency Accuracy FSEL = VDD 1000 1250 1500 kHz VIL EN, FSEL Input Low Level 0.5 V VIH EN, FSEL Input High Level 1.5 V GM Error Amp Tranconductance I = 5µA 70 130 150 1µ/ VDD-ON VDD UVLO On Threshold 1.95 2.1 2.25 V HYS VDD UVLO Hysteresis 140 mV ISS Soft-Start Charge Current 2 3 4 µA VSS-en Minimum Soft-Start Enable Voltage 40 65 150 mV ILIM-VSS-en Current Limit Around SS Enable V SS = 200mV 300 350 400 mA OTP Over-Temperature Protection 150 °C NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6683 Rev 3.00 Page 3 of 9 February 16, 2012

ISL97519A Typical Performance Curves 95 92 VIN = 3.3V, VO = 9V, 90 90 fs = 620kHz 88 85 %) %) VIN = 5V, VO = 12V, fs = 1.25 MHz Y ( 86 EFFICIENCY ( 778050 VIVNI N= =5 V5,V V, OV O= =9 V1,2 fVs, =fs 6 =2 06 2k0H zkHz EFFICIENC 888024 VfsI N= =6 230.3kVH,z VO = 12VV, IN = 3.3V, VO = 12V, 78 fs = 1.25MHz 65 VIN = 5V, VO = 9V, fs = 1.25MHz VIN = 3.3V, VO = 9V, 76 fs = 1.25MHz 60 74 0 200 400 600 800 1000 0 100 200 300 400 500 IOUT (mA) IOUT (mA) FIGURE 1. BOOST EFFICIENCY vs IOUT FIGURE 2. BOOST EFFICIENCY vs IOUT 0.7 0.9 0.8 VfsI N= =1 .52V5,M VHOz = 12V, VfsIN = = 1 .52V5,M VHOz = 9V, 0.6 VfsI N= =1 .32.53MV,H VzO = 12V, VfsIN = = 1 3.2.35VM,H VzO = 9V, 0.7 LOAD REGULATION (%) 00000.....23456 VfsIN = = 6 250Vk, HVOz = 9V, LOAD REGULATION (%) 0000....2345 VfsIN = =6 230.3k,H VzO = 9V, 0.1 VIN = 5V, VO = 12V, 0.1 VIN = 3.3, VO = 12V, fs = 620kHz fs = 620kHz 0 0 0 200 400 600 800 1000 0 100 200 300 400 500 IOUT (mA) IOUT (mA) FIGURE 3. LOAD REGULATION vs IOUT FIGURE 4. LOAD REGULATION vs IOUT 0.6 0.5 VO = 9V, IO = 80mA VO = 12V IO = 50mA TO 300mA fs = 1.25MHz %) 0.4 VO = 9V, IO = 100mA N ( fs = 620kHz O 0.3 LATI VO = 12V, IO = 80mA VIN = 3.3V fs = 600kHz GU 0.2 fs = 1.25MHz E R NE 0.1 LI 0 VO = 12V, IO = 80mA fs = 620kHz -0.1 2 3 4 5 6 VIN (V) FIGURE 5. LINE REGULATION vs VIN FIGURE 6. TRANSIENT RESPONSE FN6683 Rev 3.00 Page 4 of 9 February 16, 2012

ISL97519A Typical Performance Curves (Continued) IO = 50mA to 300mA VO = 12V VIN = 3.3V fs = 1.2MHz FIGURE 7. TRANSIENT RESPONSE FIGURE 8. SS DELAY AND LX DELAY DURING EN = VDD START- UP JEDEC JESD51-7 HIGH EFFECTIVE THERMAL JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD CONDUCTIVITY TEST BOARD 1.0 0.6 0.9 WER DISSIPATION (W) 000000......643857 870mW JA= +1M1S5°OCP/W8 WER DISSIPATION (W) 0000....4325 486mW JA= +2M0S6O°CP/8W PO 0.2 PO 0.1 0.1 0 0.0 0 25 50 75 85 100 125 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE TEMPERATURE Applications Information boost converter operates in two cycles. During the first cycle, as shown in Figure 12, the internal power FET turns on and the The ISL97519A is a high frequency, high efficiency boost Schottky diode is reverse biased and cuts off the current flow regulator operated at constant frequency PWM mode. The to the output. The output current is supplied from the output boost converter stores energy from an input voltage source capacitor. The voltage across the inductor is VIN and the and delivers it to a higher output voltage. The input voltage inductor current ramps up in a rate of VIN/L, L is the range is 2.3V to 5.5V and output voltage range is 5V to 25V. inductance. The inductance is magnetized and energy is stored The switching frequency is selectable between 600kHz and in the inductor. The change in inductor current is shown in 1.2MHz allowing smaller inductors and faster transient Equation 1: response. An external compensation pin gives the user greater V flexibility in setting output transient response and tighter load I = T1----I--N-- L1 L regulation. The converter soft-start characteristic can also be controlled by external CSS capacitor. The EN pin allows the T1 = ----D------- user to completely shutdown the device. FSW Boost Converter Operations D = Duty Cycle Figure 11 shows a boost converter with all the key I components. In steady state operating and continuous VO = C---O----U----T--T1 (EQ. 1) OUT conduction mode where the inductor current is continuous, the FN6683 Rev 3.00 Page 5 of 9 February 16, 2012

ISL97519A During the second cycle, the power FET turns off and the L D Schottky diode is forward biased, (see Figure 13). The energy stored in the inductor is pumped to the output supplying VIN VOUT output current and charging the output capacitor. The Schottky CIN COUT diode side of the inductor is clamped to a Schottky diode ISL97519A above the output voltage. So the voltage drop across the inductor is VIN - VOUT. The change in inductor current during the second cycle is shown in Equation 2: V –V IL2 IL IL = T2----I--N-------L------O---U----T-- T2 VO 1–D T2 = ------------- (EQ. 2) FIGURE 13. BOOST CONVERTER - CYCLE 2, POWER SWITCH F SW OPEN For stable operation, the same amount of energy stored in the Output Voltage inductor must be taken out. The change in inductor current An external feedback resistor divider is required to divide the during the two cycles must be the same, as shown in output voltage down to the nominal 1.24V reference voltage. Equation3. The current drawn by the resistor network should be limited to I1+I2 = 0 maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias ----D-------V----I--N--+1------–----D---V----I--N-----–----V----O---U----T-- = 0 current and the potential for noise being coupled into the F L F L SW SW feedback pin. A resistor network less than 100k is recommended. The boost converter output voltage is V----O----U---T-- = ------1------- (EQ. 3) determined by the relationship in Equation 4: V 1–D IN V = V 1+R-----1-- (EQ. 4) OUT FB  R2 The nominal VFB voltage is 1.24V. LL DD VVIINN VVOOUUTT Inductor Selection CCIINN CCOOUUTT The inductor selection determines the output ripple voltage, ISL97519A transient response, output current capability, and efficiency. Its selection depends on the input voltage, output voltage, switching frequency, and maximum output current. For most applications, the inductance should be in the range of 2µH to FIGURE 11. BOOST CONVERTER 33µH. The inductor maximum DC current specification must be greater than the peak inductor current required by the regulator.The peak inductor current can be calculated in Equation 5: L I V V V –V  I = --O----U----T------------O----U---T--+12----I--N---------------O----U----T------------I--N---- (EQ. 5) VIN VOUT LPEAK V LV FREQ IN OUT CIN COUT Output Capacitor ISL97519A Low ESR capacitors should be used to minimized the output voltage ripple. Multi-layer ceramic capacitors (X5R and X7R) are preferred for the output capacitors because of their lower ESR and small packages. Tantalum capacitors with higher ESR IL IL1 can also be used. The output ripple can be calculated as shown T1 in Equation 6: VO I D V = ----O----U---T-------------+I ESR (EQ. 6) FIGURE 12. BOOST CONVERTER - CYCLE 1, POWER SWITCH O FSWCO OUT CLOSE For noise sensitive application, a 0.1µF placed in parallel with the larger output capacitor is recommended to reduce the switching noise coupled from the LX switching node. FN6683 Rev 3.00 Page 6 of 9 February 16, 2012

ISL97519A Schottky Diode enough that it doesn't reach 0.6V before the output voltage reaches the final value. In selecting the Schottky diode, the reverse break down voltage, forward current and forward voltage drop must be When the ISL97519A is disabled, the soft-start capacitor will considered for optimum converter performance. The diode be discharged to ground. must be rated to handle 2.0A, the current limit of the Frequency Selection ISL97519A. The breakdown voltage must exceed the maximum output voltage. Low forward voltage drop, low The ISL97519A switching frequency can be user selected to leakage current, and fast reverse recovery will help the operate at either constant 620kHz or 1.25MHz. Connecting converter to achieve the maximum efficiency. FSEL pin to ground sets the PWM switching frequency to Input Capacitor 620kHz. When connecting FSEL high or VDD, the switching frequency is set to 1.25MHz. The value of the input capacitor depends the input and output Shutdown Control voltages, the maximum output current, the inductor value and the noise allowed to put back on the input line. For most When the EN pin is pulled down, the ISL97519A is shutdown applications, a minimum 10µF is required. For applications reducing the supply current to <1µA. that run close to the maximum output current limit, input capacitor in the range of 22µF to 47µF is recommended. Maximum Output Current The ISL97519A is powered from the VIN. A high frequency The MOSFET current limit is nominally 2.0A and guaranteed 0.1µF bypass capacitor is recommended to be close to the VIN 1.5A when VDD is greater than 2.8V. This restricts the pin to reduce supply line noise and ensure stable operation. maximum output current, IOMAX, based on Equation 8: I = I +12I  (EQ. 8) Loop Compensation L L-AVG L The ISL97519A incorporates a transconductance amplifier in where: its feedback path to allow the user some adjustment on the transient response and better regulation. The ISL97519A uses IL = MOSFET current limit current mode control architecture which has a fast current IL-AVG = average inductor current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow IL = inductor ripple current voltage loop must be compensated for stable operation. The V V +V –V  I = ----I--N------------------O-------------D----I--O---D----E---------------I--N----- (EQ. 9) compensation network is a series RC network from COMP pin L LV +V F O DIODE S to ground. The resistor sets the high frequency integrator gain for fast transient response and the capacitor sets the VDIODE = Schottky diode forward voltage, typically, 0.6V integrator zero to ensure loop stability. For most applications, the compensation resistor in the range of 0.5k to 7.5k and the FS = switching frequency, 600kHz or 1.2MHz I compensation capacitor in the range of 3nF to 10nF. I = ---O----U----T-- (EQ. 10) L-AVG 1–D Soft-Start D = MOSFET turn-on ratio: During power-up, assuming EN is tied to VDD, as VDD rises V above VDD UVLO, the SS capacitor begins to charge up with a D = 1–-------------------I--N------------------ (EQ. 11) V +V constant 3µA current. During the time the part takes to rise to OUT DIODE 60mV the boost will not be enabled. Depending on the value of Table 1 gives typical maximum IOUT values for 1.2MHz the capacitor on the SS pin, this provides sufficient (540µs for switching frequency and 10µH inductor. a 27nf capacitor or 2ms for a 100nf capacitor) time for the passive in-rush current to settle down, allowing the output TABLE 1. TYPICAL MAXIMUM IOUT VALUES capacitors to be charged to a diode drop below VDD. VIN (V) VOUT (V) IOMAX (mA) After the SS pin passes above the threshold beyond which the 3.3 5 1150 part is enabled (60mV) the part begins to switch. The linearly 3.3 9 655 rising SS voltage, at a charge rate proportional to 3µA, has a 3.3 12 500 direct effect on the current limit allowing the current limit to linearly ramp-up to full current limit. SS voltage of 200mV 5 9 990 corresponds to a current limit around 350mA and 0.6V 5 12 750 corresponds to full current limit. The total soft-start time is calculated in Equation 7: Cascaded MOSFET Application Css0.6V 5 t = ---------------------------- = Css210 (EQ. 7) A 25V N-Channel MOSFET is integrated in the boost regulator. ss 3A For applications where the output voltage is greater than 25V, The full current is available after the soft-start period is an external cascaded MOSFET is needed as shown in Figure finished. The soft-start capacitor should be selected to be big 14. The voltage rating of the external MOSFET should be greater than AVDD. FN6683 Rev 3.00 Page 7 of 9 February 16, 2012

ISL97519A DC PATH BLOCK APPLICATION VIN AVDD Note that there is a DC path in the boost converter from the input to the output through the inductor and diode. The input voltage will be seen at the output less a forward voltage drop of the diode before the part is enabled. If this direct connection is not desired, the following circuit can be inserted between input and inductor LX to disconnect the DC path when the part is disabled (see FB Figure15). INTERSIL ISL9751 9A TO INDUCTOR INPUT EN FIGURE 14. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT FIGURE 15. CIRCUIT TO DISCONNECT THE DC PATH OF BOOST VOLTAGE APPLICATIONS CONVERTER © Copyright Intersil Americas LLC 2008-2012. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6683 Rev 3.00 Page 8 of 9 February 16, 2012

ISL97519A Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 4.9±0.15 DETAIL "X" 3.0±0.1 1.10 Max PIN# 1 ID B 0.18 ± 0.05 SIDE VIEW 2 1 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 H GAUGE PLANE C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 3°±3° 0.08 CAB 0.10 ± 0.05 0.10C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not 0.65 included. 0.40 4. Plastic interlead protrusions of 0.25mm max per side are not included. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP 8L. FN6683 Rev 3.00 Page 9 of 9 February 16, 2012