Green Hybrid Digital Four Phase PWM Controller for Intel VR12.5™ CPUs ISL95820 Features The ISL95820 Pulse Width Modulation (PWM) controller IC • Serial data bus provides a complete low-cost solution for Intel VR12.5™ • SMBus/PMBus/I2C interface with SVID conflict free compliant microprocessor core power supplies. It provides the • Configurable 4-, 3-, 2- or 1-phase for the output using three control and protection for a Voltage Regulator (VR). The VR integrated gate drivers incorporates 3 integrated drivers and can operate in 4-, 3-, 2- •Green Hybrid Digital R3™ modulator or 1-phase configurations. The VR uses a serial control bus to communicate with the CPU and achieve lower cost and smaller - Excellent transient response board area. - Phase shedding with power state selection - Diode emulation in single-phase for high light-load The VR utilizes Intersil’s Robust Ripple Regulator R3 efficiency Technology™. The R3™ modulator has many advantages compared to traditional modulators, including faster transient • 0.5% system accuracy over-temperature response, variable switching frequency in response to load • Supports multiple current sensing methods transients, and improved light load efficiency due to diode - Lossless inductor DCR current sensing emulation mode with load-dependent low switching frequency. - Precision resistor current sensing The ISL95820 has several other key features. It supports • Differential remote voltage sensing either DCR current sensing with a single NTC thermistor for DCR temperature compensation, or more precise resistor • Programmable VBOOT voltage at start-up current sensing if desired. The output comes with remote • Resistor programmable IMAX, load line, diode emulation, voltage sense, programmable VBOOT voltage, IMAX, voltage slope compensation, and switching frequency transition slew rate and switching frequency, adjustable • Adaptive body diode conduction time reduction overcurrent protection and Power-Good signal. Applications • Intel VR12.5 desktop computers VIN PHASE4 INTERSIL DRIVER VIN VCORE PHASE3 ISL95820 VIN PHASE2 VIN PHASE1 FIGURE 1. SIMPLIFIED APPLICATION CIRCUIT February 4, 2013 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. FN8318.0 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

ISL95820 Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General Design Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Integrated Driver Operation and Adaptive Shoot-through Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Inductor Current Sensing and Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current Sense Circuit Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fault Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 VR_HOT#/ALERT# Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Serial VID (SVID) Supported Data and Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Serial PMBus (I2C/SMBus/PMBus) Supported Data and Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2 FN8318.0 February 4, 2013

ISL95820 Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) PART MARKING (°C) (Pb-Free) DWG. # ISL95820CRTZ ISL9582 0CRTZ 0 to +70 40 Ld 5x5 TQFN L40.5x5 ISL95820IRTZ ISL9582 0IRTZ -40 to +85 40 Ld 5x5 TQFN L40.5x5 ISL95820EVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95820. For more information on MSL please see techbrief TB363. Pin Configuration ISL95820 (40 LD TQFN) TOP VIEW SCLK ALERT# SDA I2CLK I2DATA PROG1 PROG2 PROG3 VIN PWM4 40 39 38 37 36 35 34 33 32 31 VR_ON 1 30 BOOT3 PGOOD 2 29 UGATE3 IMON 3 28 PHASE3 VR_HOT# 4 27 LGATE3 NTC 5 GND PAD 26 LGATE2 COMP 6 (BOTTOM) 25 VCCP FB 7 24 UGATE2 FB2 8 23 PHASE2 FB3 9 22 BOOT2 ISEN4 10 21 LGATE1 11 12 13 14 15 16 17 18 19 20 3 2 1 N N P D 1 1 1 ISEN ISEN ISEN RT ISUM ISUM VD BOOT PHASE UGATE 3 FN8318.0 February 4, 2013

ISL95820 Pin Descriptions PIN # SYMBOL DESCRIPTION BOTTOM GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pad. It should also be used as the PAD thermal pad for heat removal. 1 VR_ON Controller enable input. A high level logic signal on this pin enables the controller. 2 PGOOD Power-Good open-drain output indicating when VR is able to supply regulated voltage. Pull-up externally to VDD or to a lower supply, such as 3.3V. 3 IMON VR output current monitor. IMON sources a current proportional to the regulator output current. A resistor to ground determines the scaling of the IMON voltage to output current. 4 VR_HOT# Open drain thermal overload output indicator. Part of the communication bus with the CPU. 5 NTC The thermistor input to VR_HOT# circuit. Use it to monitor VR temperature. 6 COMP This pin is the output of the VR error amplifier. It provides error amplifier feedback to the compensation network. 7 FB This pin is the inverting input of the VR error amplifier. A DAC-derived voltage equal to the VID reference voltage is connected internally to the non-inverting error amplifier input. 8 FB2 There is an internal switch between FB pin and FB2 pin. The switch is off (open) when VR is in 1-phase mode and is on (closed) otherwise. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve optimum performance for VR. 9 FB3 There is an internal switch between pins FB and FB3. The switch will be on (closed) in droop mode (whenever programmable output DC loadline operation is enabled), and off (open) when no-droop mode is selected. The purpose is to include a resistor in parallel with the fixed droop resistor when droop is active, and to isolate that resistor when droop is inactive. This parallel resistor increases the open-loop gain of the compensator while droop is active. The effective droop (output DC loadline) programming resistance is the parallel combination of these two resistors. 10 ISEN4 Individual current sensing for Phase4. When ISEN4 is pulled to VDD (5V), the controller will disable VR Phase 4. This signal is used to monitor for and to correct phase current imbalance. 11 ISEN3 Individual current sensing for Phase3. When ISEN4 and ISEN3 is pulled to VDD (5V), the controller will disable VR Phases 4 and 3. Do not disable Phase 3 without also disabling Phase 4. This signal is used to monitor for and to correct phase current imbalance. 12 ISEN2 Individual current sensing for Phase 2. When ISEN4, ISEN3 and ISEN2 are pulled to VDD (5V), the controller will disable VR Phases 4, 3 and 2. Do not disable Phase 2 without also disabling Phases 3 and 4. This signal is used to monitor for and to correct phase current imbalance. 13 ISEN1 Individual current sensing for Phase 1. This signal is used to monitor for and to correct phase current imbalance. 14 RTN Remote ground (return) voltage sensing. Part of the differential remote VR voltage sense network. 15, 16 ISUMN and VR droop current sensing inputs. ISUMP 17 VDD +5V bias power. 18 BOOT1 Phase 1 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode. 19 PHASE1 Current return path for Phase 1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase1. 20 UGATE1 Output of Phase 1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of Phase 1 high-side MOSFET. 21 LGATE1 Output of Phase 1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of Phase 1 low-side MOSFET. 22 BOOT2 Phase 2 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode. 23 PHASE2 Current return path for Phase 2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2. 24 UGATE2 Output of Phase 2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of Phase 2 high-side MOSFET. 25 VCCP Input voltage bias for the internal gate drivers. Connect +5V or +12V to the VCCP pin. Decouple with at least 1µF of an MLCC capacitor. Diode Emulation Mode must be disabled (using PROG2 pin resistor) for +5V driver operation. 4 FN8318.0 February 4, 2013

ISL95820 Pin Descriptions (Continued) PIN # SYMBOL DESCRIPTION 26 LGATE2 Output of Phase 2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of Phase 2 low-side MOSFET. 27 LGATE3 Output of Phase 3 low-side MOSFET gate driver. Connect the LGATE3 pin to the gate of Phase 3 low-side MOSFET. 28 PHASE3 Current return path for Phase 3 high-side MOSFET gate driver. Connect the PHASE3 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 3. 29 UGATE3 Output of Phase 3 high-side MOSFET gate driver. Connect the UGATE3 pin to the gate of Phase 3 high-side MOSFET. 30 BOOT3 Phase 3 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the BOOT3 and the PHASE3 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT3 pin, each time the PHASE3 pin drops below VCCP minus the voltage dropped across the internal boot diode. 31 PWM4 PWM output for Phase 4. Phase 4 requires an external gate driver device. The Intersil ISL6625A driver is recommended. 32 VIN Input supply voltage, used for feed-forward. Connect this pin to the input voltage of the output drive stages. 33 PROG3 A resistor from the PROG3 pin to GND programs the internal modulator slope compensation and switching frequency. 34 PROG2 A resistor from the PROG2 pin to GND programs the initial power-up voltage (VBOOT), enables/disables the DC loadline (droop) function, and enables/disables diode emulation mode (DEM) in Power States 2 and 3 (PS2 and PS3). 35 PROG1 A resistor from PROG1 pin to GND programs IMAX, the designed nominal maximum load current of the VR. The value of IMAX establishes the scaling of the reported VR output current, which can be read via the SVID or PMBus interfaces. The PROG1 resistor is chosen such that the reported IMAX current is FFh when the output current is equal to the maximum load current. 36, 37 I2DATA, I2CLK Interface of SMBus/PMBus/I2C. Tie to VCC with 4.7kΩ pull-up resistor when not used. 38, 39, 40 SDA, SVID communication bus between the CPU and the VR. ALERT#, SCLK, 5 FN8318.0 February 4, 2013

ISL95820 Block Diagram VDD NTC TEMP MONITOR T_MONITOR VIN VR_HOT# PWM4 IMAX PROG1 VBOOT PROG PROG2 DROOP BOOT3 FREQUENCY PROG3 SLOPE COMP DRIVER UGATE3 PHASE3 VR_ON IDROOP A/D SDA DIGITAL DAC ALERT# INTERFACE D/A DRIVER LGATE3 SCLK MODE I2DATA BOOT2 I2CLK DRIVER UGATE2 COMP R3TM MODULATOR /DRIVER PHASE2 + CONTROL + Σ RTN + E/A FB _ DRIVER LGATE2 FB2/FB3 FB2 CIRCUIT FB3 IDROOP BOOT1 ISUMP + CURRENT _ SENSE DRIVER UGATE1 ISUMN PHASE1 IMON ISEN1 DRIVER LGATE1 ISEN2 CURRENT BALANCING ISEN3 VCCP ISEN4 OC FAULT PGOOD IBAL FAULT GND OV FAULT 6 FN8318.0 February 4, 2013

ISL95820 Typical Application Circuit +5V VDD VCCP 12V SDA SDA VIN 12V ALERT# ALERT# VCCP SCLK SCLK VCC L4 UGATE LVCC PHASE ISL6625A PWM4 PWM LBGOAOTET GND SMBUS/PMBUS/I²C CLOCK I2CLK 10Ω SMBUS/PMBUS/I²C DATA I2DATA BOOT3 UGATE3 L3 PHASE3 LGATE3 10Ω PROG1 BOOT2 PROG2 RROG3 UGATE2 L2 VCORE RNTC PHASE2 NTC °C LGATE2 VR_HOT# VR_HOT# 10Ω PGOOD PGOOD BOOT1 VR_ON VR_ON UGATE1 L1 IMON PHASE1 LGATE1 10Ω ISL95820 RSUM4 ISUMP FB3 RSUM3 FB2 RSUM2 CN COMP RN RSUM1 RI ISUMN VSUMN FB CVSUMN RDROOP CISEN1CISEN2CISEN3CISEN4RISEN4 ISEN4 RISEN3 ISEN3 RISEN2 VCCSENSE ISEN2 VSSSENSE RTN RISEN1 ISEN1 GND FIGURE 2. TYPICAL ISL95820 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 7 FN8318.0 February 4, 2013

ISL95820 Absolute Maximum Ratings Thermal Information VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V 40 Ld TQFN Package (Notes 4, 5) . . . . . . . 31 3 VCCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C LGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VVCCP + 0.3V GND - 5V (<100ns Pulse Width, 2µJ) to VVCCP + 0.3V Recommended Operating Conditions PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 25VDC GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT - GND < 36V) Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V Input Voltage, VIN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to 20.0V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Driver Supply Voltage, VCCP (Note 6). . . . . . . . . . . . . . . . . +4.5V to +13.2V Ambient Temperature CRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Junction Temperature CRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +125°C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. It is recommended that VIN+VCCP not exceed 24V nominally. For VCCP < 7V, Diode Emulation Mode (DEM) must be disabled using the PROG2 pin programming resistor. Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C (ISL95820CRTZ), TA = -40°C to +85°C (ISL95820IRTZ), fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS INPUT POWER SUPPLIES VDD Supply Current IVDD VVDD = 5V; VR_ON = 1V 6.4 8.0 mA VVDD = 5V; VR_ON = 0V 125 µA VIN Supply Current RVIN VVIN = 25V; VR_ON = 1V 600 kΩ IVIN VVIN = 25V; VR_ON = 0V 1 µA VCCP No Load Switching Supply IVCCP VVCCP = 12V; fsw = fsw_300k; Phases 1-3 8 mA Current active; CBOOT1,2,3 = 0.1µF VVCCP = 12V; Phases inactive 0.72 1.5 mA POWER-ON-RESET THRESHOLDS VDD Power-On-Reset Threshold VDD_PORr VVDD rising 4.3 4.35 4.5 V VDD_PORf VVDD falling 4.0 4.15 4.3 V VIN Power-On-Reset Threshold VIN_PORr VVIN rising 3.75 4.00 4.5 V VIN_PORf VVIN falling 3.05 3.50 3.7 V VCCP Power-On-Reset Threshold VCCP_PORr VVCCP rising 4.0 4.30 4.5 V VCCP_PORf VVCCP falling 3.45 3.90 4.1 V SYSTEM AND REFERENCES Maximum Output Voltage VOUT(MAX) VID = [10110101] 2.3 V Minimum Output Voltage VOUT(MIN) VID = [00000001] 0.5 V Fast Slew Rate (for VID changes) 10 12 mV/µs Slow Slew Rate (for VID changes) 2.5 3 mV/µs 8 FN8318.0 February 4, 2013

ISL95820 Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C (ISL95820CRTZ), TA = -40°C to +85°C (ISL95820IRTZ), fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS System Accuracy CRTZ No load; closed loop, active mode range, -0.5 +0.5 % Error (VOUT) VID= 1.00V to 2.3V, VID = 0.80V to 0.99V -5 +5 mV VID = 0.5V to 0.79V -8 +8 mV IRTZ No load; closed loop, active mode range, -0.8 +0.8 % Error (VOUT) VID= 1.00V to 2.3V VID = 0.8V to 0.99V -8 +8 mV VID = 0.5V to 0.79V -10 +10 mV Internal VBOOT CRTZ 1.64 1.65 1.66 V 1.69 1.70 1.71 V 1.74 1.75 1.76 V IRTZ 1.635 1.65 1.665 V 1.685 1.70 1.715 V 1.735 1.75 1.765 V CHANNEL FREQUENCY 200kHz Configuration fsw_200k 180 200 220 kHz 300kHz Configuration fsw_300k 275 300 325 kHz 450kHz Configuration fsw_450k 410 450 490 kHz AMPLIFIERS Current-Sense Amplifier Input Offset CRTZ IFB = 0A -0.2 +0.2 mV IRTZ IFB = 0A -0.3 +0.3 mV Error Amp DC Gain AV0 119 dB Error Amp Gain-Bandwidth Product GBW CL = 20pF 17 MHz ISEN ISEN Offset Voltage Maximum of ISEN - Minimum of ISEN 1 mV ISEN Input Bias Current 20 nA GATE DRIVER BOOTSTRAP SWITCHES (Phases 1-3) On-resistance RF 40 Ω Reverse Leakage IR VVDDP = 12V, VVR_ON = 0, BOOT and PHASE 0.2 µA connected and total current measured GATE DRIVER OUTPUTS (Phases 1-3) UGATE Pull-Up Resistance RUGPU 250mA Source Current 3.70 Ω UGATE Source Current IUGSRC UGATE - PHASE = 2.5V 1.30 A UGATE Pull-Down Resistance RUGPD 250mA Sink Current 1.41 Ω UGATE Sink Current IUGSNK UGATE - PHASE = 2.5V 1.27 A LGATE Pull-Up Resistance RLGPU 250mA Source Current 2.75 Ω LGATE Source Current ILGSRC LGATE - VSSP = 2.5V 1.75 A LGATE Pull-Down Resistance RLGPD 250mA Sink Current 0.60 Ω LGATE Sink Current ILGSNK LGATE - VSSP = 2.5V 2.14 A 9 FN8318.0 February 4, 2013

ISL95820 Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C (ISL95820CRTZ), TA = -40°C to +85°C (ISL95820IRTZ), fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load, 59 ns VVDDP = 7V LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load, 37 ns VVDDP = 7V PWM4 (Phase 4) PWM4 Output Low V0L Sinking 5mA 1.0 V PWM4 Output High V0H Sourcing 5mA 4.5 V PWM4 Tri-State Leakage PWM = 2.5V 1 µA PROTECTION Overvoltage Threshold OVH VSEN > setpoint for >1µs, SET_OV = 00h VID + V 300mV VSEN > setpoint for >1µs, SET_OV = 01h 3.3 V Current Imbalance Threshold One ISEN above another ISEN for >3.2ms 19 mV Overcurrent Threshold OCP_TH PS0 in 4-, 3-, 2-, 1-Phase configuration, 54 60 66 µA (See Table 1 for configuration and PSn or any PSx in 1-Phase configuration dependencies.) PS1 in 3-Phase configuration 36 40 44 µA PS1 in 4-Phase configuration 27 30 33 µA PS1/2/3 in 2-Phase configuration PS2/3 in 4-, 3-Phase configuration 18 20 22 µA NTC Source Current NTC = 1.3V 54 60 66 µA NTC VR_HOT# Trip Voltage, TZ 7Fh to NTC voltage forced, voltage falling threshold 0.881 0.893 0.905 V TZ FFh Threshold NTC Thermal Alert# Trip Voltage, TZ NTC voltage forced, voltage falling threshold 0.92 0.932 0.944 V 3Fh to TZ 7Fh Threshold NTC VR_HOT# Reset Voltage, TZ 7Fh NTC voltage forced, voltage rising threshold 0.923 0.936 0.948 V to TZ 3Fh Threshold NTC Thermal Alert# Reset Voltage, TZ NTC voltage forced, voltage rising threshold 0.96 0.974 0.986 V 3Fh to TZ 1Fh Threshold POWER-GOOD AND PROTECTION MONITORS PGOOD Low Voltage VOL IPGOOD = 4mA 0.15 0.4 V PGOOD Leakage Current IOH PGOOD = 3.3V 1 µA PGOOD Delay tpgd Time from VR_ON high to PGOOD high; 3 ms VBOOT = 1.7V VR_HOT# Low Resistance IVR_HOT# = 10mA 7 12 Ω VR_HOT# Leakage Current VVR_HOT# = 5V 1 µA ALERT# Low Resistance IALERT# = 10mA 7 12 Ω ALERT# Leakage Current VALERT = 5V 1 µA LOGICAL AND SERIAL INTERFACE VR_ON Input Low VIL 0.3 V VR_ON Input High VIH CRTZ 0.7 V VIH IRTZ 0.75 V 10 FN8318.0 February 4, 2013

ISL95820 Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C (ISL95820CRTZ), TA = -40°C to +85°C (ISL95820IRTZ), fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS VR_ON Leakage Current IVR_ON VR_ON = 0V -1 0 µA VR_ON = 1V 3.5 6 µA SCLK Maximum Speed 42 MHz SCLK Minimum Speed 13 MHz SCLK, SDA Leakage VR_ON = 0V, SCLK and SDA = 0V and 1V -1 1 µA VR_ON = 1V, SCLK and SDA = 1V -2 1 µA VR_ON = 1V, SDA = 0V -26 −21 −16 µA VR_ON = 1V, SCLK= 0V -52 −42 −32 µA SDA Low Resistance ISDA = 10mA 7 12 Ω I2CLK Maximum Speed 400 kHz I2CLK Minimum Speed 50 kHz I2C Timeout 25 30 35 ms I2DATA Low Resistance II2DATA = 4mA 28 40 Ω I2CLK, I2DATA Leakage VR_ON = 0V, I2CLK and I2DATA = 0V and 1V -1 1 µA VR_ON = 1V, I2CLK and I2DATA = 1V -2 1 µA VR_ON = 1V, I2DATA = 0V -1 1 µA VR_ON = 1V, I2CLK= 0V -1 1 µA NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11 FN8318.0 February 4, 2013

ISL95820 Theory of Operation The ISL95820 is a 1-, 2-, 3-, or 4-phase PWM controller for the Intel IL1 + IL2 + IL3, 7A/DIV microprocessor VR12.5 core voltage regulator. The ISL95820 is designed to be compliant to Intel VR12.5 specifications with SerialVID Features. The SMBus/PMBus/I2C can be programmed IL1, 7A/DIV with the Embedded Controller. The system parameters and SVID PWM1, 5V/DIV required registers are programmable with two dedicated pins. This greatly simplifies the system design for various platforms and IL2, 7A/DIV lowers inventory complexity and cost by using a single device. PWM2, 5V/DIV Multiphase Power Conversion IL3, 7A/DIV Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are PWM3, 5V/DIV impossible to ignore. Multiphase converters overcome the 1µs/DIV daunting technical challenges in producing a cost-effective and FIGURE 3. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR thermally viable single-phase converter. The ISL95820 controller 3-PHASE CONVERTER reduces the complexity of multiphase implementation by In a multiphase converter, the output capacitor current is the integrating vital functions, including integrated drivers for three superposition of the ripple currents from each of the individual phases, direct interface for a fourth external driver device, and phases. Compare Equation 1 to the expression for the peak-to-peak requiring minimal output components. The “Typical Application current after the summation of N (symmetrically phase-shifted Circuit” on page7 provides the top level views of multiphase inductor currents) in Equation 2, the peak-to-peak overall ripple power conversion using the ISL95820 controller. current (IC(P-P)) decreases with the increase in the number of channels, as shown in Figure 4, which introduces the concept of the Interleaving Ripple Current Multiplier (KRCM). At the (steady state) duty cycles for The switching of each channel in a multiphase converter is timed which the ripple current, and thus the KRCM, is zero, the turn-off of to be symmetrically out-of-phase with the other channels. For the one phase corresponds exactly with the turn-on of another phase, example of a 3-phase converter, each channel switches 1/3 cycle resulting in the sum of all phase currents being always the after the previous channel and 1/3 cycle before the following (constant) load current, and therefore there is no ripple current in channel. As a result, the 3-phase converter has a combined this case. ripple frequency three times that of the ripple frequency of any one phase, as illustrated in Figure 3. The three channel currents M C (IL1, IL2, and IL3) combine to form the AC ripple current and to R K supply the DC load current. R, E The ripple current of a multiphase converter is less than that of a LI P single-phase converter supplying the same load. To understand TI N=1 L U why, examine Equation 1, which represents an individual M channel’s peak-to-peak inductor current. T N 2 E (V –V )⋅ V R IP-P= -------I--N---L-----⋅---F---O-S----UW----T--⋅----V----I--N---O----U-----T-- (EQ. 1) LE CUR 43 In Equation 1, VIN and VOUT are the input and output voltages PP 5 respectively, L is the single-channel inductor value, and FSW is RI the switching frequency. 6 DUTY CYCLE (VOUT/VIN) FIGURE 4. RIPPLE CURRENT MULTIPLIER vs DUTY CYCLE Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and the summed inductor ripple current. Increased ripple frequency and lower ripple amplitude mean that the designer can use lower saturation-current inductors and fewer or less costly output capacitors for any performance specification. 12 FN8318.0 February 4, 2013

ISL95820 V phases. Crm voltage Vcrm is a sawtooth waveform traversing I = -------O----U-----T----K (EQ. 2) between the VW and COMP voltages. It resets (charges quickly) to C(P-P) L⋅F RCM SW VW when it discharges (with discharge current gmVo) to COMP and (N⋅D–m+1)⋅(m–(N⋅D)) generates a one-shot master clock signal. A phase sequencer K = ----------------------------------------------------------------------------- RCM N⋅D distributes the master clock signal to the active slave circuits. If VR is in 4-phase mode, the master clock signal will be distributed to the for m–1≤N⋅D≤m four phases 90° out-of-phase, in 3-phase mode distributed to the m = ROUNDUP(N⋅D,0) three phases 120° out-of-phase, and in 2-phase mode distributed to Another benefit of interleaving is to reduce the input ripple Phases 1 and 2 180° out-of-phase. If VR is in 1-phase mode, the current. Input capacitance is determined in part by the maximum master clock signal will be distributed to Phase 1 only and will be input ripple current. Multiphase topologies can improve overall the Clock1 signal. system cost and size by lowering input ripple current and Each slave circuit has its own ripple capacitor Crsn, whose allowing the designer to reduce the cost of input capacitors. voltage mimics the inductor ripple current. A gm amplifier Figure 5 example illustrates input currents from a three-phase converts the inductor voltage (or alternatively, series sense converter combining to reduce the total input ripple current. resistor voltage, indicative of that phase’s inductor current) into a INPUT-CAPACITOR CURRENT, 10A/DIV current source to charge and discharge Crsn. The slave circuit turns on its PWM pulse upon receiving its respective clock signal Clockn, and the current source charges Crsn with a current proportional to its respective positive inductor voltage. When Crsn voltage VCrsn rises to VW, the slave circuit turns off the PWM CHANNEL 1 pulse, and the current source then discharges Crsn, with a current INPUT CURRENT proportional to its respective now-negative inductor voltage. Crsn 10A/DIV discharges until the next Clockn pulse, and the cycle repeats. CHANNEL 2 Since the modulator works with the Vcrsn, which are INPUT CURRENT large-amplitude and noise-free synthesized signals, it achieves 10A/DIV lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode CHANNEL 3 converters, the ISL95820 uses an error amplifier that allows the INPUT CURRENT controller to maintain a 0.5% output voltage accuracy. 10A/DIV 1µs/DIV VW MASTER CLOCK CIRCUIT FIGURE 5. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR MASTER RMS CURRENT FOR 3-PHASE CONVERTER MASTER COMP CLOCK PHASE CLOCK1 CLOCK Vcrm SEQUENCER CLOCK2 The converter depicted in Figure 5 delivers 36A to a 1.5V load from CLOCK3 a 12V input. The RMS input capacitor current is 5.9A. Compare this gmVo Crm to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9ARMS input capacitor current. SLAVE CIRCUIT 1 PHASE1 L1 The single-phase converter must use an input capacitor bank with VW CLOCK1 S Q PWM1 Vo twice the RMS current capacity as the equivalent three-phase R converter. IL1 Co Vcrs1 A more detailed exposition of input capacitor design is provided gm in “Input Capacitor Selection” on page20. Crs1 Multiphase R3™ Modulator SLAVE CIRCUIT 2 PHASE2 L2 The Intersil ISL95820 multiphase regulator uses the patented VW CLOCK2 S Q PWM2 R R3™ (Robust Ripple Regulator™) modulator. The R3™ modulator IL2 combines the best features of fixed frequency PWM and hysteretic Vcrs2 PWM while eliminating many of their shortcomings. Figure 6 gm shows the conceptual multiphase R3™ modulator circuit, and Crs2 Figure 7 illustrates the operational principles. SLAVE CIRCUIT 3 PHASE3 L3 The internal modulator uses a master clock circuit to generate the VW CLOCK3 S Q PWM3 clocks for the slave circuits, one per phase. The R3™ modulator R IL3 master oscillator slews between two voltage signals, the COMP voltage (the output of the voltage sense error amplifier) and VW Vcrs3 gm (Voltage Window), a voltage positively offset from COMP by an offset Crs3 voltage that is dependent on the nominal switching frequency. The modulator discharges the master clock ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor, dependent FIGURE 6. R3™ MODULATOR CIRCUIT AT 3-PHASE MODE on nominal switching frequency, and also on number of active 13 FN8318.0 February 4, 2013

ISL95820 voltage, making the PWM on-time pulses wider. During load VW release response, the COMP voltage falls. It takes the master Vcrm HYSTERETIC clock circuit longer to generate the next master clock signal so WINDOW the PWM pulse is held off until needed. The VW voltage falls with COMP the COMP voltage, reducing the current PWM pulse width. The inherent pulse frequency and width increases due to an MASTER increasing load transient, and likewise the pulse frequency and CLOCK width reductions due to a decreasing load transient, produce the CLOCK1 excellent load transient response of the R3™ modulator. PWM1 Since all phases share the same VW window (master clock frequency generator) and threshold (slave pulse width generator) CLOCK2 voltage, dynamic current balance among phases is ensured, inherently, for the duration of any load transient event. PWM2 The R3™ modulator intrinsically has input voltage feed-forward CLOCK3 control, due to the proportional dependence of the clock generator slave transconductance gains on the input voltage. This dependence PWM3 decreases the on-time pulse-width of each phase in proportion to an VW increase in input voltage, making the output voltage insensitive to a fast slew rate input voltage change. Diode Emulation and Period Stretching Vcrs2 Vcrs3 Vcrs1 FIGURE 7. R3™ MODULATOR OPERATION PRINCIPLES IN STEADYSTATE AT 3-PHASE MODE VW PHASE UGATE COMP Vcrm LGATE MASTER IL CLOCK CLOCK1 FIGURE 9. DIODE EMULATION PWM1 The ISL95820 can operate in diode emulation mode (DEM) to CLOCK2 improve light load efficiency. Diode emulation can be optionally PWM2 enabled in PS2 and PS3, in Phase-1 only operation, by selection of PROG2 pin resistance to ground. In DEM, the low-side MOSFET CLOCK3 conducts while the current is flowing from source to drain and PWM3 blocks reverse current, emulating a diode. As illustrated in Figure 9, when LGATE is on, the low-side MOSFET carries current, creating VW negative voltage on the phase node due to the voltage drop across the ON-resistance. The controller monitors the inductor current by monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current Vcrs1 from reversing the direction and creating unnecessary power loss. Vcrs3 Vcrs2 If the load current is light enough, as Figure 9 illustrates, the inductor current will reach and stay at zero before the next phase FIGURE 8. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD node pulse and the regulator is in discontinuous conduction INSERTION RESPONSE AT 3-PHASE MODE mode (DCM). If the load current is heavy enough, the inductor Figure 8 illustrates the operational principles during load current will never reach 0A, and the regulator will appear to insertion response. The COMP voltage rises during load insertion operate in continuous conduction mode (CCM), although the (due to the sudden discharge of the output capacitor driving the controller is nevertheless configured for DEM. inverting input of the error amplifier), generating the master Figure 10 shows the operation principle in diode emulation mode clock signal more quickly, so the PWM pulses turn on earlier, at light load. The load gets incrementally lighter in the three cases increasing the effective switching frequency. This phenomenon from top to bottom. The PWM on-time is determined by the VW allows for higher control loop bandwidth than conventional fixed window size, making the inductor current triangle the same in the frequency PWM controllers. The VW voltage rises with the COMP 14 FN8318.0 February 4, 2013

ISL95820 three cases (only the time between inductor current triangles Modes of Operation changes). The controller clamps the ripple capacitor voltage Vcrs in DEM to make it mimic the inductor current. It takes the COMP TABLE 1. VR MODES OF OPERATION voltage longer to hit Vcrm, which produces master clock pulses, OCP naturally stretching the switching period. The inductor current THRESHOLD triangles move further apart from each other, such that the ISEN4 ISEN3 ISEN2 CONFIG. PS MODE (µA) inductor current average value is equal to the load current. The To Power To Power To 4-phase 0 4-phase 60 reduced switching frequency improves light load efficiency. Stage Stage Power CPU VR CCM Stage Config. Because the next clock pulse occurs when VCOMP (which tracks 1 2-phase 30 output voltage error) rises above VCRM, DEM switching pulse CCM frequency is responsive to load transient events in a manner 2 1-phase 20 similar to that of multiphase CCM operation. opt: DEM 3 or CCM Tied to 3-phase 0 3-phase 60 CCM/DCM BOUNDARY VW 5V CPU VR CCM Config. Vcrs 1 2-phase 40 CCM 2 1-phase 20 opt: DEM IL 3 or CCM LIGHT DCM VW Tied to 2-phase 0 2-phase 60 Vcrs 5V CPU VR CCM Config. 1 1-phase 30 CCM IL 2 1-phase opt: DEM DEEP DCM 3 VW or CCM Vcrs Tied to 1-phase 0 1-phase 60 5V CPU VR CCM 1 Config. 2 1-phase IL opt: DEM 3 or CCM FIGURE 10. PERIOD STRETCHING VR can be configured for 4-, 3-, 2-, or 1-phase operation. Table 1 Adaptive Body Diode Conduction Time shows VR configurations and operational modes, programmed Reduction by the ISEN4, ISEN3 and ISEN2 pin status, and the Set PS command. For the 3-phase configuration, tie the ISEN4 pin to 5V. When in DCM, the controller ideally turns off the low-side In this configuration, phases 1, 2, and 3 are active. For the MOSFET when the inductor current approaches zero. During 2-phase configuration, tie the ISEN3 and ISEN4 pin to 5V. In this on-time of the low-side MOSFET, phase voltage is negative by the configuration, phases 1 and 2 are active. For the 1-phase product of the (negative) inductor current and the low-side configuration, tie the ISEN4, ISEN3, and ISEN2 pin to 5V. In this MOSFET rDS(ON), producing a voltage drop that is proportional to configuration, only Phase 1 is active. the inductor current. A phase comparator inside the controller monitors the phase voltage during on-time of the low-side In the 4-phase configuration, VR operates in 4-phase CCM in PS0. MOSFET and compares it with a threshold to determine the It enters 2-phase CCM mode in PS1 by dropping phases 4 and 3 zero-crossing point of the inductor current. If the inductor current and reducing the overcurrent protection level to 1/2 of the initial has not reached zero when the low-side MOSFET turns off, it will value. It enters 1-phase DEM (optionally CCM) in PS2 and PS3 by flow through the low-side MOSFET body diode, causing the phase dropping phases 4, 3, and 2, and reducing the overcurrent node to have a larger voltage drop until it decays to zero. If the protection levels to 1/4 of the initial value. inductor current has crossed zero and reversed the direction In the 3-phase configuration, VR operates in 3-phase CCM in PS0. when the low-side MOSFET turns off, it will flow through the (Phase 4 is disabled). It enters 2-phase CCM mode in PS1 by high-side MOSFET body diode, causing the phase node to have a dropping phase 3 and reducing the overcurrent protection level to positive voltage spike (to VIN plus a PN diode voltage drop) until 2/3 of the initial value. It enters 1-phase DEM (optionally CCM) in the current decays to zero. The controller continues monitoring PS2 and PS3 by dropping phases 3 and 2, and reducing the the phase voltage after turning off the low-side MOSFET and overcurrent and the protection level to 1/3 of the initial value. adjusts the phase comparator threshold voltage accordingly in iterative steps, such that the low-side MOSFET body diode In the 2-phase configuration, VR operates in 2-phase CCM in PS0. conducts for approximately 40ns (turning off 40ns before the (Phases 4 and 3 are disabled.) It enters 1-phase mode in PS1, inductor current zero-crossing) to minimize the body PS2, and PS3 by dropping phase 2 and reducing the overcurrent diode-related loss. 15 FN8318.0 February 4, 2013

ISL95820 protection level to 1/2 of the initial value. PS1 operates in CCM, the VR alone, select RPROG2 for VBOOT of 1.65V, 1.7V or 1.75V. and PS2 and PS3 operate in DEM (optionally CCM). Table 3 shows how to select RPROG2 to enable droop, select VBOOT, and select operational mode in PS2 and PS3 (CCM vs DEM). Note In the 1-phase configuration, VR operates in 1-phase CCM in PS0 that the effective resistance value of the DC loadline, i.e., the output and PS1, and enters 1-phase DEM (optionally CCM) in PS2 and voltage droop due to load current, is determined by components of PS3. the overcurrent protection level is the same for all power the output current sense, voltage feedback, and modulator states. compensation networks. This information is summarized in Table 1. TABLE 3. PROG2 PROGRAMMING TABLE Programming Resistors RPROG2 (kΩ) OPERATIONAL There are three programming resistors: RPROG1, RPROG2 and EIA E96 1% DROOP MODE IN PS2 VBOOT RPROG3. Table2 shows how to select RPROG1 based on VR VALUE ENABLED AND PS3 (V) ICC(MAX) register settings. Determine the maximum current VR 3.24 YES DEM 0 can support and set the VR ICC(MAX) register value accordingly, by selecting the appropriate RPROG1 value. The CPU will read the 5.76 YES DEM 1.65 VR ICC(MAX) register value and ensure that the CPU CORE current 9.53 YES DEM 1.7 doesn’t exceed the value specified by VR ICC(MAX). 13.3 YES DEM 1.75 TABLE 2. PROG1 PROGRAMMING TABLE 16.9 YES CCM 1.75 RPROG1 (kΩ) VR ICC(MAX) 21.0 YES CCM 1.7 EIA E96 1% VALUE (A) 24.9 YES CCM 1.65 3.24 15 28.7 YES CCM 0 5.76 20 34.0 NO DEM 0 9.53 25 13.3 30 42.2 NO DEM 1.65 16.9 35 49.9 NO DEM 1.7 21.0 40 57.6 NO DEM 1.75 24.9 45 64.9 NO CCM 1.75 28.7 50 73.2 NO CCM 1.7 34.0 55 80.6 NO CCM 1.65 42.2 60 88.7 NO CCM 0 49.9 65 SWITCHING FREQUENCY SELECTION 57.6 70 There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the 64.9 75 upper-MOSFET loss calculation. These effects are outlined in 73.2 80 “MOSFETs” on page17, and they establish the upper limit for the 80.6 90 switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage 88.7 100 ripple as outlined in “Output Filter Design” on page20. Choose the 100 115 lowest switching frequency that allows the regulator to meet the transient-response and output-voltage ripple requirements. 113 130 124 145 The resistor from PROG3 to GND selects one of three available switching frequencies, 200kHz, 300kHz, and 450kHz, and sets 137 160 the modulator slope compensation value. Note that when the 154 180 ISL95820 is in continuous conduction mode (CCM), the switching frequency is not strictly constant due to the nature of the R3™ 169 200 modulator. As explained in “Multiphase R3™ Modulator” on 187 225 page13, the effective switching frequency will increase during load insertion and will decrease during load release to achieve 221 225 fast response. However, the switching frequency is nearly RPROG2 sets the start-up (VBOOT) voltage, and selects whether the constant at constant load. Variation is expected when the power Droop (programmable DC loadline) function is enabled on power-up, stage condition, such as input voltage, output voltage, load, etc. and whether Diode Emulation is enabled in PS2 and PS3. When the changes. The variation is usually less than 15% and doesn’t have controller works in the targeted application with a CPU, select any significant effect on output voltage ripple magnitude. Table 4 RPROG2, such that VR powers up to VBOOT=0V, as required by shows how to select RPROG3 to obtain the desired modulator slope the SVID command. In the absence of a CPU, such as testing of 16 FN8318.0 February 4, 2013

ISL95820 compensation and switching frequency. There are many choices of end of this current range. If through-hole MOSFETs and inductors slope compensation for each switching frequency. can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be TABLE 4. PROG3 PROGRAMMING TABLE pushed as high as 40A per phase, but these designs require heat RPROG3 (kΩ) SLOPE SWITCHING sinks and forced air to cool the MOSFETs, inductors and EIA E96 1% VALUE COMPENSATION FREQUENCY (kHz) heat-dissipating surfaces. 3.24 0.25x 200 MOSFETs 5.76 0.5x 200 The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of 9.53 0.75x 200 the MOSFETs to dissipate heat; and the availability and nature of 13.3 1x 200 heat sinking and air flow. 16.9 1.25x 200 Lower MOSFET Power Calculation 21.0 1.5x 200 The calculation for heat dissipated in the lower (alternatively called low-side) MOSFET of each phase is simple, since virtually 24.9 1.75x 200 all of the heat loss in the lower MOSFET is due to current 34.0 0.25x 300 conducted through the channel resistance (rDS(ON)). In 42.2 0.5x 300 Equation3, IM is the maximum continuous output current; IP-P is the peak-to-peak inductor current per phase (see Equation 1 on 49.9 0.75x 300 page12); d is the duty cycle (VOUT/VIN); and L is the per-channel 57.6 1x 300 inductance. Equation 3 shows the approximation. 64.9 1.25x 300 73.2 1.5x 300 PLOW,1 = rDS(ON) I-N-M----2+I--P1----2---P--2 ⋅(1–d) (EQ. 3) 80.6 1.75x 300 88.7 2x 300 A term can be added to the lower-MOSFET loss equation to account for the loss during the dead time when inductor current 100 0.25x 450 is flowing through the lower-MOSFET body diode. This term is 113 0.5x 450 dependent on the diode forward voltage at IM, VD(ON); the 124 0.75x 450 switching frequency, Fsw; and the length of dead times (td1 and td2) at the beginning and the end of the lower-MOSFET 137 1x 450 conduction interval respectively. 154 1.25x 450 ⎛I I ⎞ ⎛I I ⎞ 169 1.5x 450 PLOW,2 = VD(ON)FSW ⎝⎜-N-M----–--P--2-----P--⎠⎟ td1 +⎝⎜-N-M----–--P--2-----P--⎠⎟ td2 (EQ. 4) 187 1.75x 450 221 2x 450 Finally, the power loss of output capacitance of the lower MOSFET is approximated in Equation 5: General Design Guide P ≈2---⋅V1.5⋅C ⋅ V ⋅F (EQ. 5) This design guide is intended to provide a high-level explanation of LOW,3 3 IN OSS_LOW DS_LOW SW the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills where COSS_LOW is the output capacitance of lower MOSFET at and techniques referenced in the following. In addition to this the test voltage of VDS_LOW. Depending on the amount of guide, Intersil provides complete reference designs, which include ringing, the actual power dissipation will be slightly higher than schematics, bill of materials, and example board layouts for this. common microprocessor applications. Thus the total maximum power dissipated in each lower MOSFET Power Stages is approximated by the summation of PLOW,1, PLOW,2 and PLOW,3. The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily upon Upper MOSFET Power Calculation the cost analysis, which in turn depends on system constraints In addition to rDS(ON) losses, a large portion of the upper-MOSFET that differ from one design to the next. Principally, the designer losses are due to currents conducted across the input voltage (VIN) will be concerned with whether components can be mounted on during switching. Since a substantially higher portion of the both sides of the circuit board; whether through-hole components upper-MOSFET losses are dependent on switching frequency, the are permitted; and the total board space available for power power calculation is more complex. Upper MOSFET losses can be supply circuitry. Generally speaking, the most economical divided into separate components involving the upper-MOSFET solutions are those in which each phase handles between 15A switching times; the lower-MOSFET body-diode reverse-recovery and 25A. All surface-mount designs will tend toward the lower charge, Qrr; and the upper MOSFET rDS(ON) conduction loss. 17 FN8318.0 February 4, 2013

ISL95820 When the upper MOSFET turns off, the lower MOSFET does not Integrated Driver Operation and Adaptive conduct any portion of the inductor current until the voltage at Shoot-through Protection the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero The ISL95820 provides three integrated MOSFET drivers, for as the current in the lower MOSFET ramps up to assume the full phases 1 through 3, and a PWM signal to operate a single external inductor current. In Equation 6, the required time for this driver device, required if a fourth phase is required. Designed for commutation is t1 and the approximated associated power loss high-speed switching, the internal MOSFET drivers control both is PUP(1). high-side and low-side N-Channel FETs from the internal PWM signal I I ⎛t ⎞ P ≈V ⎛--M----+--P-------P--⎞⎜--1--⎟F (EQ. 6) UP(1) IN⎝N 2 ⎠⎝2⎠ SW A rising transition on the internal PWM signal (phases 1 through 3) initiates the turn-off of the lower MOSFET. After a short At turn on, the upper MOSFET begins to conduct and this propagation delay [tPDLL], the lower gate begins to fall. Following a transition occurs over a time (t2). In Equation 7, the approximate 25ns blanking period, adaptive shoot-through circuitry monitors power loss is PUP(2). the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1.75V. P ≈V ⎜⎛I--M----–I--P-------P--⎟⎞⎜⎛t--2--⎟⎞F (EQ. 7) The upper gate drive then begins to rise [tRU] and the upper UP(2) IN⎝N 2 ⎠⎝2⎠ SW MOSFET turns on. A falling transition on the internal PWM signal indicates the turn- A third component involves the lower MOSFET’s reverse-recovery off of the upper MOSFET and the turn-on of the lower MOSFET. A charge, Qrr. Since the inductor current has fully commutated to the short propagation delay [tPDLU] is encountered before the upper upper MOSFET before the lower-MOSFET’s body diode can draw all gate begins to fall [tFU]. The adaptive shoot-through circuitry of Qrr, it is conducted through the upper MOSFET across VIN. The monitors the UGATE-PHASE voltage and turns on the lower power dissipated as a result is PUP(3) and is approximated in MOSFET a short delay time [tPDHL] after the upper MOSFET’s Equation 8: PHASE voltage drops below +0.8V or 40ns after the upper MOSFET’s gate voltage [UGATE-PHASE] drops below ~1.75V. The PUP(3) = VINQrrFSW (EQ. 8) lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from The resistive part of the upper MOSFET is given in Equation 9 as conducting simultaneously (shoot-through), while adapting the PUP(4). dead time to the gate charge characteristics of the MOSFETs being 2 2 used. PUP(4)≈rDS(ON) ⎝⎜⎛I-N-M----⎠⎟⎞ +I--P1----2---P-- ⋅d (EQ. 9) The internal drivers are optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger Equation 10 accounts for some power loss due to the compared to the upper MOSFET because the lower MOSFET drain-source parasitic inductance (LDS, including PCB parasitic conducts for a longer time during a switching period. The lower inductance) of the upper MOSFET, although it is not exact: gate driver is therefore sized much larger to meet this application requirement. The 0.8Ω ON-resistance and 3A sink current 2 PUP(5)≈LDS⎝⎜⎛I-N-M----+I--P--2-----P--⎠⎟⎞ (EQ. 10) cinajpeactbeidlit iyn eton athbele l othwee rlo gwaeter gthartoeu dgrhiv ethr et od raabisno-trob- gtahtee c cuarpreancti tor of the lower MOSFET and help prevent shoot-through caused by the Finally, the power loss of output capacitance of the upper self turn-on of the lower MOSFET due to high dV/dt of the switching MOSFET is approximated in Equation 11: node. P ≈2---⋅V1.5⋅C ⋅ V ⋅F (EQ. 11) For VCCP < 7V, Diode Emulation Mode (DEM) must be disabled UP(6) 3 IN OSS_UP DS_UP SW using the PROG2 pin programming resistor. INTERNAL BOOTSTRAP DEVICE where COSS_UP is the output capacitance of the lower MOSFET at test voltage of VDS_UP. Depending on the amount of ringing, the The integrated drivers feature an internal bootstrap Schottky actual power dissipation will be slightly higher than this. diode equivalent circuit implemented by switchers with a typical ON-resistance of 40Ω and without the typical diode forward The total power dissipated by the upper MOSFET at full load can voltage drop. Simply adding an external capacitor across the now be approximated as the summation of the results from BOOT and PHASE pins completes the bootstrap circuit. The Equations 6 through 11. Since the power equations depend on bootstrap function is also designed to prevent the bootstrap MOSFET parameters, choosing the correct MOSFET can be an capacitor from overcharging due to the large negative swing at iterative process involving repetitive solutions to the loss the trailing-edge of the PHASE node. This reduces the voltage equations for different MOSFETs and different switching stress on the BOOT to PHASE pins. frequencies. The bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for UVCC. Its minimum capacitance value can be estimated using Equation12: 18 FN8318.0 February 4, 2013

ISL95820 Q MOSFET datasheet; IQ is the driver’s total quiescent current with C ≥------------U-----G----A----T----E--------- no load at both drive outputs; NQ1 and NQ2 are the number of, BOOT_CAP ΔV BOOT_CAP (EQ. 12) and UVCC and LVCC are the drive voltages for, the upper and lower MOSFETs, respectively. The IQ*VCCP product is the Q •UVCC quiescent power of the driver without a load. G1 Q = ------------------------------------•N UGATE V Q1 GS1 The total gate drive power losses are dissipated among the resistive components along the transition path, as outlined in where QG1 is the amount of gate charge per upper MOSFET at Equation 15. The drive resistance dissipates a portion of the total VGS1 gate-source voltage and NQ1 is the number of control gate drive power losses; the rest will be dissipated by the external MOSFETs. The ΔVBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Select results are gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 exemplified in Figure 11. and RGI2) of MOSFETs. Figures 12 and 13 show the typical upper and lower gate drives turn-on current paths. . 1.6 P = P +P +I •VCC (EQ. 15) DR DR_UP DR_LOW Q 1.4 ⎛ RHI1 RLO1 ⎞ PQg_Q1 P = ⎜--------------------------------------+----------------------------------------⎟•--------------------- 1.2 DR_UP ⎝RHI1+REXT1 RLO1+REXT1⎠ 2 µ(F)AP 1.0 PDR_LOW = ⎝⎜⎛R-----H----I--2--R---+--H--R--I--2-E----X----T---2--+R-----L---O-----2R----+-L---O-R----2-E----X----T---2--⎠⎟⎞•P-----Q----g-2---_--Q-----2- _C 0.8 OT R R O R = R +-----G-----I-1-- R = R +-----G-----I-2-- CB 0.6 EXT1 G1 NQ1 EXT2 G2 NQ2 QUGATE = 100nC 0.4 . 50nC VCCP BOOT 0.2 20nC D 0.0 CGD 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ΔVBOOT_CAP (V) RHI1 G CDS FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE RLO1 RL1 RG1 POWER DISSIPATION IN THE INTEGRATED DRIVERS CGS Q1 Internal driver power dissipation is mainly a function of the S switching frequency (FSW), the output drive impedance, the layout PHASE resistance, and the selected MOSFET’s internal gate resistance FIGURE 12. TYPICAL UPPER-GATE DRIVE TURN-ON PATH and total gate charge (QG). Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level may VCCP push the IC beyond the maximum recommended operating D junction temperature. The DFN package is more suitable for high frequency applications. The total gate drive power losses due to CGD the gate charge of MOSFETs and the driver’s internal circuitry and RHI2 G their corresponding average driver current, per driver, can be CDS estimated using Equations 13 and 14, respectively: RLO2 RL2 RG2 CGS Q2 P = P +P +I •VCCP Qg_TOT Qg_Q1 Qg_Q2 Q S Q •UVCC2 G1 P = ---------------------------------------•F •N Qg_Q1 VGS1 SW Q1 FIGURE 13. TYPICAL LOWER-GATE DRIVE TURN-ON PATH QG2•LVCC2 UPPER MOSFET SELF TURN-ON EFFECT AT START-UP P = --------------------------------------•F •N Qg_Q2 V SW Q2 GS2 (EQ. 13) Should a driver have insufficient bias voltage applied (at pin VCCP), its outputs are floating. If the input bus is energized at a I = ⎜⎛Q-----G-----1----•-----U----V-----C-----C------•----N----Q-----1--+Q-----G-----2----•-----L---V-----C-----C------•----N----Q-----2--⎟⎞•F +I high dV/dt rate while the driver outputs are floating, due to DR ⎝ VGS1 VGS2 ⎠ SW Q self-coupling via the internal CGD of the MOSFET, the gate of the upper MOSFET could momentarily rise up to a level greater than (EQ. 14) the threshold voltage of the device, potentially turning on the where the gate charge (QG1 and QG2) is defined at a particular upper switch. Therefore, if such a situation could conceivably be gate-to-source voltage (VGS1 and VGS2) in the corresponding encountered, it is a common practice to place a resistor (RUGPH) 19 FN8318.0 February 4, 2013

ISL95820 across the gate and source of the upper MOSFET to suppress the di Miller coupling effect. The value of the resistor depends mainly ΔV≈(ESL)-----+(ESR)ΔI (EQ. 17) dt on the input voltage’s rate of rise, the CGD/CGS ratio, as well as The filter capacitor must have sufficiently low ESL and ESR so the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper that ΔV < ΔVMAX. FET will require a smaller resistor to diminish the effect of the Most capacitor solutions rely on a mixture of high-frequency internal capacitive coupling. For most applications, the capacitors with relatively low capacitance in combination with integrated 20kΩ resistor is sufficient, not affecting normal bulk capacitors having high capacitance but limited performance and efficiency. high-frequency performance. Minimizing the ESL of the high-frequency capacitors, allows them to support the output –V voltage as the current increases. Minimizing the ESR of the bulk ⎛ -----------------D-----S------------⎞ VGS_MILLER = d--d--V-t--⋅R⋅Crss⎜⎜⎜1–ed--d--V-t--⋅R⋅Ciss⎟⎟⎟ (EQ. 16) coauptpaucti tvoorslt,a aglelo dwesv tiahteimon .to supply the increased current with less ⎜ ⎟ ⎝ ⎠ The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the R = RUGPH+RGI Crss = CGD Ciss = CGD+CGS inductor AC ripple current (see “Interleaving” on page12 and Equation 2), a voltage develops across the bulk-capacitor ESR The coupling effect can be roughly estimated with Equation16, equal to IC(P-P)(ESR). Thus, once the output capacitors are which assumes a fixed linear input ramp and neglects the selected, the maximum allowable ripple voltage, VP-P(MAX), clamping effect of the body diode of the upper drive and the determines a lower limit on the inductance, as shown in bootstrap capacitor. Other parasitic components such as lead Equation18. inductances and PCB capacitances are also not taken into account. Figure 6 provides a visual reference for this V ⋅K phenomenon and its potential solution. L ≥ESR⋅ -----------------O----U----T------------R----C-----M-------------- (EQ. 18) F ⋅V ⋅V SW IN P-P(MAX) EXTERNAL (PHASE 4) DRIVER SELECTION Since the capacitors are supplying a decreasing portion of the When a fourth phase is to be used, it is recommended that the load current while the regulator recovers from the transient, the Intersil ISL6625A driver be selected as the external Phase 4 capacitor voltage becomes slightly depleted. The output driver device. inductors must be capable of assuming the entire load current Output Filter Design before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. The output inductors and the output capacitor bank together to Equation 19 gives the upper limit on L for the cases when the form a low-pass filter responsible for smoothing the pulsating trailing edge of the current transient causes a greater voltage at the phase nodes. The output filter also must provide output-voltage deviation than the leading edge. Equation 20 the transient energy until the regulator can respond. Because it addresses the leading edge. Normally, the trailing edge dictates has a low bandwidth compared to the switching frequency, the the selection of L because duty cycles are usually less than 50%. output filter necessarily limits the system transient response. The Nevertheless, both inequalities should be evaluated, and L output capacitor must supply or sink load current while the should be selected based on the lower of the two results. In each current in the output inductors increases or decreases to meet equation, L is the per-channel inductance, C is the total output the demand. capacitance, and N is the number of active channels. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter 2⋅N⋅C⋅V L≤------------------------------O-----U----T-- ΔV –ΔI⋅ESR (EQ. 19) design begins with minimizing the cost of this part of the circuit. (ΔI)2 MAX The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under L≤1----.--2---5-----⋅---N------⋅---C--- ΔV –ΔI⋅ESR ⎛V –V ⎞ (EQ. 20) transient loading, ΔVMAX. Capacitors are characterized according (ΔI)2 MAX ⎝ IN OUT⎠ to their capacitance, equivalent series resistance (ESR), and equivalent series inductance (ESL). Input Capacitor Selection At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by The input capacitors are responsible for sourcing the AC an amount approximated by the voltage drop across the ESL. As the component of the input current flowing into the upper MOSFETs. load current increases, the voltage drop across the ESR increases Their RMS current capacity must be sufficient to handle the AC linearly until the load current reaches its final value. The capacitors component of the current drawn by the upper MOSFETs, which is selected must have sufficiently low ESL and ESR so that the total related to duty cycle and the number of active phases. The input output-voltage deviation is less than the allowable maximum. RMS current can be calculated with Equation 21.. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, as I = K2 •Io2+K2 •I2 (EQ. 21) IN(RMS) IN(CM) RAMP(CM) Lo(P-P) shown in Equation 17: 20 FN8318.0 February 4, 2013

ISL95820 0.3 KIN(CM) = (---N------•----D------–----m-------+-----1N----)2---•----(---m------–-----N------•----D------) (EQ. 22) I) S/O IILL((PP--PP)) == 00.25 IO IILL((PP--PP)) == 00..57 5IO IO M KRAMP(CM) = m------2---(---N-----•-----D------–----m-------+----1----1)---32----N+----2-(--m-D----2--–----1----)--2----(--m-------–----N------•----D-----)--3-- (EQ. 23) ENT (IR0.2 R R 0.3 U C /I) SO TOR M CI0.1 R A T (I AP N0.2 C RE UT- R P U N C I R 0 O 0 0.2 0.4 0.6 0.8 1.0 CIT0.1 DUTY CYCLE (VOUT/VIN) CAPA IL(P-P) = 0 FIGURE 16. NDOURTYM CAYLCIZLEED F IONRP U4T-P-CHAAPSAEC CITOONRV ERRMTSE RCURRENT vs UT- IL(P-P) = 0.5 IO Figures 15 and 16 provide the same input RMS current NP IL(P-P) = 0.75 IO information for 3- and 4-phase designs, respectively. Use the I 0 same approach to selecting the bulk capacitor type and number, 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VOUT/VIN) as previously described. FIGURE 14. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs Low capacitance, high-frequency ceramic capacitors are needed DUTY CYCLE FOR 2-PHASE CONVERTER in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. The result from the high current slew rates For a 2-phase design, use Figure 14 to determine the input capacitor produced by the upper MOSFETs turn on and off. Select low ESL RMS current requirement given the duty cycle, maximum sustained ceramic capacitors and place one as close as possible to each output current (IO), and the ratio of the per-phase peak-to-peak upper MOSFET drain to minimize board parasitic impedances inductor current (IL(P-P)) to IO. Select a bulk capacitor with a ripple and maximize noise suppression. current rating, which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25x greater 0.6 than the maximum input voltage. ) O IS/ M ) O0.3 IL(P-P) = 0 IL(P-P) = 0.5 IO NT (IR0.4 IS/ IL(P-P) = 0.25 IO IL(P-P) = 0.75 IO RE M R R U ENT (I0.2 OR C R T R CI0.2 U A CITOR C0.1 PUT-CAP IIILLL(((PPP---PPP))) === 000..57 5IO IO APA IN 0 C 0 0.2 0.4 0.6 0.8 1.0 T- PU DUTY CYCLE (VOUT/VIN) N FIGURE 17. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs I 0 DUTY CYCLE FOR SINGLE-PHASE CONVERTER 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VOUT/VIN) MULTIPHASE RMS IMPROVEMENT FIGURE 15. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 3-PHASE CONVERTER Figure 17 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multiphase topology. For example, compare the input RMS current requirements of a 2-phase converter versus that of a single-phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of IL(P-P) to IO of 0.5. The single-phase converter would require 17.3ARMS current capacity, while the 2-phase converter would only require 10.9ARMS. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single-phase approach. 21 FN8318.0 February 4, 2013

ISL95820 Inductor Current Sensing and Balancing DCR INDUCTOR DCR CURRENT-SENSING NETWORK ω = ------------- (EQ. 27) L L PHASE1 PHASE2 PHASE3 Rsum 1 ω = -------------------------------------------------------- (EQ. 28) Rsum sns Rsum R ×--------------- ntcnet N Rsum ISUMP ------------------------------------------×C R n R +-----s---u---m---- ntcnet N L L L Rntcs where N is the number of phases. Rp CnVcn The inductor DCR value increases as the inductor temperature DCR DCR DCR Rntc increases, due to the positive temperature coefficient of the Ro Ri ISUMN copper windings. If uncompensated, this will cause the estimate of inductor current to increase with temperature. The resistance Ro of the co-located NTC thermistor, Rntc, decreases as its Ro temperature increases, compensating for the increase in DCR. Proper selections of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represents the inductor total DC current over the Io temperature range of interest. FIGURE 18. DCR CURRENT-SENSING NETWORK There are many sets of parameters that can properly Figure 18 shows the inductor DCR current-sensing network for the temperature-compensate the DCR change. Since the NTC network example of a 3-phase voltage regulator. An inductor’s current flows and the Rsum resistors form a voltage divider, Vcn is always a through the inductor’s DCR and creates a voltage drop. Each fraction of the inductor DCR voltage. It is recommended to have a inductor has two resistors, Rsum and Ro, connected to the pads to high ratio of Vcn to the inductor DCR voltage, so the current sense accurately sense the inductor current by sensing the DCR voltage circuit has a higher signal level to work with. drop. The Rsum and Ro resistors are connected in a summing A typical set of parameters that provide good temperature network as shown, and feed the total current information to the compensation are: Rsum = 3.65kΩ, Rp=11kΩ, Rntcs = 2.61kΩ NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters Rntc is a negative temperature coefficient (NTC) thermistor, used may need to be fine tuned on actual boards. One can apply full to compensate for the change in inductor DCR due to temperature load DC current and record the output voltage reading changes. immediately; then record the output voltage reading again when The inductor output side pads are electrically shorted in the the board has reached the thermal steady state. A good NTC schematic, but have some parasitic impedance in actual board network can limit the output voltage drift to within 2mV. It is layout, which is why one cannot simply short them together for the recommended to follow the Intersil evaluation board layout and current-sensing summing network. It is recommended to use current-sensing network parameters to minimize engineering 1Ω~10Ω Ro to create quality signals. Since the Ro value is much time. smaller than the rest of the current sensing circuit, the following VCn(s) response must track Io(s) over a broad range of frequency analysis will ignore it for simplicity. for the controller to achieve good transient response. Transfer The summed inductor current information is presented to the function Acs(s) (Equation 29) has unity gain at DC, a pole ωsns, capacitor Cn. Equations 24 thru 28 describe the and a zero ωL. To obtain unity gain at all frequencies, set ωL frequency-domain relationship between inductor total current equal to ωsns and solve for Cn. Io(s) and Cn voltage VCn(s): C = ------------------------------L--------------------------------- (EQ. 29) n R sum R ×--------------- ⎛ ⎞ ntcnet N VCn(s) = ⎝⎜⎜⎜R-----n---t--c-R--n---n-e--t-t-c--+-n----eR------t---s--N----u-------m-------×D-----CN-----R---⎠⎟⎟⎟×Io(s)×Acs(s) (EQ. 24) R-----n---t--c---n----e---t---+-----R---------s--N-----u------m-------×DCR For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ, Rntcnet = (---RR-----n---t--c---s----++-----RR----n----t--c---)-+--×--R---R----p-- (EQ. 25) REqnutcast=ion2 .2691 kgΩiv,e Rsn Ctcn == 100.3k9Ω7, µDFC.R = 0.9mΩ and L=0.36µH, ntcs ntc p Assuming the loop compensator design is correct, Figure 26 s shows the expected load transient response waveforms for the 1+------- ωL correctly chosen value of Cn. When the load current Icore has a A (s) = ----------------------- (EQ. 26) cs 1+------s------- step change, the output voltage Vcore also has a step change, ω determined by the DC loadline resistance (the output voltage sns droop value of the regulator, (see “Current Sense Circuit 22 FN8318.0 February 4, 2013

ISL95820 Adjustments” on page28). If the Cn value is too large or too small, VCn(s) will not accurately represent real-time Io(s) and will worsen the transient response. Fsmiguarlle. V2c8o rseh wowills d trhoeo lpo aexdc tersasnisvieelny,t brerisepfloyn, usep ownh aebnr Cupn ti slo taodo ARsen(s) = 1-----+-----------1----------s------------------ (EQ. 3 insertion, before recovering to the intended DC value, which may ωRsen create a system failure. There will be excessive overshoot during load decreases, which may potentially hurt the CPU reliability. With the proper selection of Cn, assume that Acs(s) = 1. With this assumption, Equation 29 can be recast as Equation 30: ⎛ ⎞ V----I-C-o---n-- = ⎝⎜⎜⎜R-----n---t--c--R-n---n-e--t-t-c--+-n----eR-------t---s-N-----u------m-------×D-----CN-----R---⎠⎟⎟⎟ (EQ. 30) ωRsen = -R---------s------u-------m----1------×----C------- (EQ. 3 N n With a properly designed inductor temperature compensation network, we may also assume the room temperature inductor DCR value together with the room temperature value of Rntcnet in subsequent calculations, since any temperature variation in one RESISTOR CURRENT-SENSING NETWORK value will be, ideally, exactly compensated by a variation in the other value. Equation 31 can be evaluated, using room temperature PHASE1 PHASE2 PHASE3 resistance values, to obtain a constant value of the ratio VCn/Io, in units of resistance, for a given DCR current sense network design. This constant value, designated ρο, will be required to L L L complete the regulator design. DCR DCR DCR ⎛ ⎞ Rsum ρ = ⎜⎜-----------R-----n---t--c---n----e---t-----------×D-----C-----R---⎟⎟ (EQ. 31) o ⎜ Rsum N ⎟ Rsum ⎝Rntcnet+------N--------- ⎠ Rsum ISUMP RoomTemp This expression applies to the DCR current sense circuit of Rsen Rsen Rsen Vcn Cn Figure18. Ro Ri ISUMN Figure 19 shows the resistor current-sensing network for the Ro example of a 3-phase regulator. Each inductor has a series Ro current-sensing resistor Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum and Ro resistors are connected to capacitor Cn. Rsum Io and Cn form a filter for noise attenuation. Equations 32 thru 34 give VCn(s) expression: FIGURE 19. RESISTOR CURRENT-SENSING NETWORK Transfer function ARsen(s) always has unity gain at DC. Current-sensing resistor Rsen value will not have significant variation over-temperature, so there is no need for the NTC R network. sen (EQ. 3 V (s) = -------------×I (s)×A (s) Cn N o Rsen The recommended values are Rsum = 1kΩ and Cn=5600pF. As with the DCR current sense network, Equation 34 can be recast as Equation 35: V R Cn sen ----------- = ------------- (EQ. 35) I N o This equation can be evaluated to obtain a constant value of the ratio VCn/Io, in Ω units, for a given sense-resistor current sense network design. This constant value will be designated ρο in 23 FN8318.0 February 4, 2013

ISL95820 Equation36. always 60µA in PS0, so Ri must be chosen to obtain the desired R IOCP using Equation 37: sen ρ = ------------- (EQ. 36) I o N Ri = ρ ×---O----C-----P--- (EQ. 37) o 60μA As with the DCR-sense design, this constant value will be where ρo is the constant value determined in Equations 31 or 36. required to complete the regulator design. This expression applies to the resistor current sense circuit of Figure 19. For a given value of output current, Io, Idroop will have the value: ρ o I = ------×I (EQ. 38) PROGRAMMING OF OUTPUT OVERCURRENT droop Ri o PROTECTION, I , AND IMON DROOP Idroop is also used to program the slope of the output DC The final step in designing the current sense network is the loadline. The DC loadline slope is the programmable regulator selection of resistor Ri of Figures 18 or 19. This resistor output resistance. determines the ratio of the controller’s internal representation of The IOUT register will contain an 8-bit unsigned number output current (Idroop, also called the “droop current”) to the indicative of the IMON pin voltage, scaled such that its value is actual output current, that is, to the sum of all the measured inductor currents. This internal representation is itself a current 00h when VIMON = 0V, and FFh when VIMON = 1.2V. With Ri that will be used (a) to compare to the overcurrent protection determined, RIMON is chosen, such that VIMON = 1.2V when the threshold, (b) to drive the IMON pin external resistor to produce a regulator load current is equal to ICC(MAX), the maximum current voltage to represent the output current, which is measured and value programmed by RPROG1. Select RIMON using Equation 39: wthreit tFeBn ptoin t htoe pIOroUvTid ree gthiset eprr, oagnrda m(cm) toa bsloeu lrocaed t-hdee pIdernodoep nctu orruetnptu tto RIMON = 1.2V×⎝⎛ρo×I--C----R-C----i(--M-×----A4----X----)⎠⎞–1 (EQ. 39) voltage “droop”, or output DC loadline. where again ρo is the constant value determined in Begin by selecting the maximum current that the regulator is Equations31or 36. designed to provide. This will be the value of VR ICC(MAX) programmed with the PROG1 pin resistance to ground, as per PROGRAMMING THE DC LOADLINE Table2 on page16. Select RPROG1 to program the lowest The DC loadline is the effective DC series resistance of the available value of ICC(MAX) that exceeds the expected maximum voltage regulator output. The output series resistance causes the load. The Overcurrent Protection (OCP) threshold IOCP must output voltage to “droop” below the selected regulation voltage exceed this value. IOCP is typically chosen to be 20% to 25% by a voltage equal to the load current multiplied by the output greater than ICC(MAX). IOCP will determine the value of Ri. resistance. The linear relationship of output voltage drop to load current is called the loadline, and is expressed in units of Refer to Table1 on page15. The value of OCP THRESHOLD for any phase configuration (1- through 4-phase regulator) and any resistance. It will be designated RLL. Figure 21 shows the equivalent circuit of a voltage regulator (VR) with the droop powerstate (PS0-PS3) is the value of Idroop that will trigger function. An ideal VR is equivalent to a voltage source (V =VID) output overcurrent protection. Notice that the OCP THRESHOLD value of the PS0 row of any phase configuration is 60µA. Ri and output impedance Zout(s). If Zout(s) is equal to the load line should be chosen, such that Idroop will be 60µA when the slope RLL, i.e., constant output impedance independent of regulator output current is equal to the chosen value of output frequency, Vo will have step response when Io has a step change. IOCP. The mechanism by which Ri determines Idroop is illustrated in Zout(s) = RLL io Figure 20. ... VID VR LOAD Vo VCn Cn ISUMP 1 1/4 1 ... ISUMN gm Ri Idroop FIGURE 21. VOLTAGE REGULATOR EQUIVALENT CIRCUIT IMON The ISL95820 provides programmable DC loadline resistance. ADC This feature can be disabled by choice of the programming RIMON resistor on pin PROG2, or disabled via the serial bus. A typical IOUT desired value of the DC loadline for Intel VR12.5 applications is REGISTER RLL = 1.5mΩ. The programmable DC loadline mechanism is integral to the FIGURE 20. regulator’s output voltage feedback compensator. This is illustrated in the feedback circuit and recommended The ISUM transconductance amplifier produces the current that drops the voltage VCn across Ri, to make VISUMP = VISUMN. This current is mirrored 1:1 to produce Idroop, and 4:1 to produce IIMON. Idroop is compared directly to the OCP THRESHOLD, 24 FN8318.0 February 4, 2013

ISL95820 compensation network shown in Figure 22. Rdroop Vdroop VCCSENSE = VOUT Vdroop = Idroop×Rdroop= ρ-R---o--i×Io×Rdroop (EQ. 4 FB VR LOCAL Idroop R“ECSAITSCTHO”R VOUT E/A VIDs Σ COMP DAC VID VDAC PHASE DUTY CYCLE BALANCING RTN To equally distribute power dissipation between the phases, the VSSSENSE INTERNAL TO IC X 1 VSS ISL95820 provides a means to reduce the deviation of the duty cycle of each phase from the average of all phases. The “CATCH” controller achieves duty cycle balance by matching the ISENn pin RESISTOR voltages. The connection of these pins to their respective phase nodes is depicted in Figure23 for the inductor DCR current sense FIGURE 22. DIFFERENTIAL VOLTAGE SENSING AND LOAD LINE method. The current balancing methods described in this section IMPLEMENTATION apply also to current sensing using discrete sense resistors. The ISL95820 implements the DC loadline by injecting a current, V3p L3 Rdcr3 Rpcb3 Idroop, which is proportional to the regulator output current IOUT, PHASE3 into the voltage feedback node (the FB pin). The scaling of Idroop Risen ISEN3 IL3 with respect to IOUT was selected in the previous section to Cisen obtain the desired output IOCP threshold. The droop voltage is the INTERNAL V2p L2 Rdcr2 Rpcb2 Vo voltage drop across the resistance, called Rdroop, between the FB TO IC PHASE2 pin and the output voltage due to Idroop. Rdroop will be selected ISEN2 Risen IL2 to implement the desired DC loadline resistance RLL. The FB pin Cisen voltage is thus raised above VOUT by the droop voltage, requiring V1p L1 Rdcr1 Rpcb1 the regulator to reduce VOUT to make VFB equal to the voltage PHASE1 Risen regulator reference voltage applied to the Error Amplifier ISEN1 IL1 non-inverting input. Cisen Rdroop is a component of the voltage regulator stability compensation network. Regulator stability and dynamic FIGURE 23. CURRENT BALANCING CIRCUIT response are somewhat insensitive to the value of Rdroop, since a parallel series-RC will dominate the compensator response at, The phase nodes have high amplitude square-wave voltage and well below, the open loop crossover frequency. But Rdroop waveforms, for which the comparative duty cycle is indicative of plays a singular role in determining the DC loadline, and so will each phase’s relative contribution to the output. Risen and Cisen be chosen solely for that purpose. form lowpass filters to remove the switching ripple of the phase node voltages, such that the average voltages at the ISENn pins For a desired RLL, the output voltage reduction, Vdroop, due to an approximately indicate each phase’s duty cycle, and thus the output load current, Io, is as shown by Equation 40. relative contribution of each phase. The controller gradually, and continually, trims the R3™ modulator slave circuits, such that the relative duty cycle of each phase, as indicated by each VISENn, is equal to the others. This adjustment occurs slowly compared to V = R ×I (EQ. 4 the dynamic response of the multi-phase modulator to output droop LL o voltage commands, load transients, and other system perturbations. It is recommended to use a large RisenCisen time constant, such that the ISENn voltages have small ripple and are representative of the average or steady-state contribution of each phase to the output. Recommended values are The value of Vdroop obtained from the ISL95820 controller is the droop current, Idroop, multiplied by the droop resistor, Rdroop. Risen=10kΩ and Cisen=0.22µF. Using Equation 41, this value is as shown by Equation 41. Ideally, balancing the phase duty cycles will also balance the output current provided by each phase, and thus the power Equate these two expressions for Vdroop and solve for Rdroop to dissipated in each phase’s components. This will be the case if obtain the value in Equation 42. the current sense elements of each phase are identical (DCR of Ri×R the inductors, or discrete current sense resistors, and the LL Rdroop = ---------ρ-------------- (EQ. 42) associated current sense networks), and if parasitic resistances o of the circuit board traces from the sense connections to the common output voltage node are identical. Figure23 includes 25 FN8318.0 February 4, 2013

ISL95820 the printed circuit trace resistances from each phase to the common output node. If these trace resistances are all equal, V3p L3 Rdcr3 Rpcb3 PHASE3 then the ideal of phase current balance will be achieved. This Risen balance assumes the inductors and other current sense ISEN3 IL3 V3n Cisen Risen components are identical, comparing each phase to the others, a Risen true assumption within the published tolerance of component INTERNAL parameters. TO IC V2p L2 Rdcr2 Rpcb2 Vo PHASE2 Risen Figure23 includes the trace-resistance from each inductor to a ISEN2 IL2 V2n single common output node. Note that each Risen connection Cisen Risen (V1p, V2p, and V3p) should be routed to its respective inductor Risen phase-node-side pad in order to eliminate the effect of phase node L1 Rdcr1 V1p Rpcb1 parasitic PCB resistance from the switching elements to the PHASE1 Risen inductor. Equations 43 thru 45 give the ISEN pin voltages: ISEN1 IL1 V1n Cisen Risen VISEN1 = (Rdcr1+Rpcb1)×IL1+Vo (EQ. 43) Risen V = (R +R )×I +Vo (EQ. 44) FIGURE 24. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT ISEN2 dcr2 pcb2 L2 Each ISEN pin sees the average voltage of three sources: its own phase inductor phase-node pad, and the other two phases V = (R +R )×I +Vo (EQ. 45) ISEN3 dcr3 pcb3 L3 inductor output-side pads. Equations 46 thru 48 give the ISEN pin voltages: where Rdcr1, Rdcr2 and Rdcr3 are the respective inductor DCRs; (V +V +V ) Rpcb1, Rpcb2 and Rpcb3 are the respective parasitic PCB VISEN1 = -------1---p-------------3-2---n--------------3---n----- (EQ. 46) resistances between the inductor output-side pad and the output voltage rail; and IL1, IL2 and IL3 are inductor average currents. (V +V +V ) The controller will adjust the phase pulse-width relative to the VISEN2 = -------1---n-------------3-2---p--------------3---n----- (EQ. 47) other phases to make VISEN1=VISEN2=VISEN3, thus to achieve IL1=IL2=IL3, when there are Rdcr1=Rdcr2=Rdcr3 and (V +V +V ) Rpcb1=Rpcb2=Rpcb3. VISEN3 = -------1---n-------------3-2---n--------------3---p----- (EQ. 48) Since using the same components for L1, L2 and L3 will typically pdreotevirdmei na eg oRopdcb m1,a Rtcphc bo2f Randcdr 1R,p Rcdbc3r,2 a anndd t hRudsc rt3h,e b moaartdc lhaiynogu ot fw ill tThhee ecqounatrloitlileesr swhilol wmna ikne E VqIuSaENtio1n =s V4I9SE aNn2d = 5 V0I:SEN3, resulting in current per phase. It is recommended to have symmetrical layout for the power delivery path between each inductor and the output V1p+V2n+V3n = V1n+V2p+V3n (EQ. 49) voltage rail, such that Rpcb1=Rpcb2=Rpcb3. While careful symmetrical layout of the circuit board can achieve V +V +V = V +V +V (EQ. 50) very good matching of these trace resistances, such layout is 1n 2p 3n 1n 2n 3p often difficult to achieve in practice. If trace resistances differ, then exact matching the duty cycles of the phases will result in the imbalance of the phase currents. A modification of this circuit (to couple the signals of all the phases in the ISENn networks), can correct the current imbalance due to unequal trace resistances to the output. For the example case of a 3-phase configuration, Figure24 shows the current balancing circuit with the recommended trace-resistance imbalance correction. As before, V1p, V2p, and V3p should be routed to their respective inductor phase-node-side pads in order to eliminate the effect of phase node parasitic PCB resistance from the switching elements to each inductor. The sensing traces for V1n, V2n, and V3n should be routed to the VOUT output-side inductor pads so they indicate the voltage due only to the voltage drop across the inductor DCR, and not due to the PCB trace resistance. 26 FN8318.0 February 4, 2013

ISL95820 Simplifying Equation 49 gives Equation 51: REP RATE = 10kHz V1p–V1n = V2p–V2n (EQ. 51) and simplifying Equation 50 gives Equation 52: V2p–V2n = V3p–V3n (EQ. 52) Combining Equations 51 and 52 gives Equation 53: V1p–V1n = V2p–V2n = V3p–V3n (EQ. 53) Which produces the desired result in Equation 54: REP RATE = 25kHz Rdcr1×IL1 = Rdcr2×IL2 = Rdcr3×IL3 (EQ. 54) Current balancing (IL1=IL2=IL3) will be achieved independently of any mismatch of Rpcb1, Rpcb2, and Rpcb3, to within the tolerance of the resistance of the current sense elements. Note that with the crosscoupling of Figure 25, the phase balancing circuit no longer seeks to equalize the duty cycles of the phases, but rather to equalize the DC components of the voltage drops across the current sense elements. Small absolute differences in PCB trace resistance from the REP RATE = 50kHz inductors to the common output node, can result in significant phase current imbalance. It is strongly recommended that the resistor pads and connections for the current balancing method be included in any PCB layout. The decision to include the additional Nx(N-1) trace-resistance-correcting resistors can then be deferred until the extent of the current imbalance can be measured on a functioning circuit. Considerations for making this decision are described in “Current Sense OFFSET Error” on page28. With the ISENn phase balancing mechanism (with cross coupling resistors if needed, or without if not needed), the R3™ modulator REP RATE = 100kHz achieves excellent current balancing during both steady state and transient operation. Figure25 shows current balancing performance of an evaluation board with load transient of 12A/51A at different rep rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current well at low rep rate, but cannot track the load when the rep rate gets into the hundred-kHz range, which is outside of the control loop bandwidth. Regardless, the controller achieves excellent current balancing in all cases. REP RATE = 200kHz FIGURE 25. CURRENT BALANCING DURING DYNAMIC OPERATION. CH1: IL1, CH2: ILOAD, CH3: IL2, CH4: IL3 27 FN8318.0 February 4, 2013

ISL95820 Current Sense Circuit Adjustments CURRENT SENSE SENSITIVITY ERROR Once the voltage regulator is designed and a functional prototype The current sense, IMON, and DC Loadline (droop) network has been assembled, adjustments may be necessary to correct component values should be designed according to the for non-ideal components, or assembly and printed circuit board instructions in “Current Sense Circuit Adjustments” on page28. parasitic effects. These are effects that are usually not known This will ensure the correct ratio of VIMON to Idroop (which until the design has been realized. The following adjustments determines RLL) for the chosen system design parameters, for should be considered when refining a product design. which no adjustment should be required. However, testing of the resulting circuit may reveal a measurement sensitivity error VERIFICATION OF INDUCTOR-DCR CURRENT-SENSE factor, which should effect VIMON and Idroop equally. This error POLE-ZERO MATCHING may be seen as a too-large RLL value (droop voltage per load current), and as a too-large IMON voltage for a given load current. Recall that if the inductor DCR is used as the phase current A single component modification will correct both errors. sense-element, it is necessary to select the capacitor Cn such that the current sense transfer function pole at ωsns, matches The current sense resistance value per phase (either a discrete the zero at ωL. The ideal response to a load step, with DC sense resistor, or the inductor DCR) is typically very small, on the Loadline (i.e., “droop”) enabled, is shown in Figure 26. order of 1mΩ. The solder connections used in the assembly of such sense elements may contribute significant resistance to io these sense elements, resulting in a larger load-dependent voltage drop than due to the sense element alone. Thus, the sensed output current value will be greater than intended for a given load current. If this is the case, then the value of Ri (the ISUMN pin resistor) should be increased by the factor of the Vo sensitivity error. For example, if the current sense value is 3% larger than intended, then Ri should be increased by 3%. Changing Ri will change the sensitivity, with respect to IOUT, of FIGURE 26. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS VIMON and Idroop by the same factor, thus simultaneously correcting the IMON voltage error and the loadline resistance, Figure27 shows the load step transient response when Cn is too while preserving the intended ratio between the two parameters. large. Vcore droop response (rising or falling) lags in settling to its final value. Note that the assembly procedure for installing the current sense elements (sense resistors or inductors) can have a significant impact on the effective total resistance of each sense element. It is important that any adjustments to Ri be performed on circuits io that have been assembled with the same procedures that will be used in mass production. The current measurement sensitivity error should be determined on a sufficient number of samples to avoid adjusting sensitivity to correct what may be a component-tolerance outlier. Vo CURRENT SENSE OFFSET ERROR FIGURE 27. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE Nonlinearity of the RSUM resistors can induce a small positive offset in the ISUMP voltage, and thus in the IMON pin current Figure 28 shows the load step response when Cn is too small. (viewed as a positive offset in the ICC register value), and also in Vcore response is underdamped, and overshoots before settling the droop current (viewed as an output voltage negative offset). to its final voltage. The offset error occurs as follows: for each inductor, the instantaneous voltage across its RSUM resistor is approximately VRSUM = VPHASE – VVOUT. During that phase’s on time, io VPHASE=VVIN, giving VRSUM-ON = VVIN – VVOUT. During the off time, VPHASE = 0V, and so VRSUM-OFF = –VVOUT. For the example of VVOUT = 1.8V and VVIN = 12V, VRSUM-ON = 10.2V and VRSUM-OFF = –1.8V, a sign-dependent magnitude difference exceeding 8V. Inexpensive thick film resistors can have a voltage nonlinearity of 25ppm/volt or more, with the device resistance Vo decreasing with increasing voltage. Because of this RSUM resistor nonlinearity, each RSUM’s (positive) current into the common ISUMP node (during its on-time) will be biased slightly greater FIGURE 28. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL than the nominal V/R value expected. Each RSUM’s (negative) current (during its off-time) will also be biased negatively due to Once the regulator design is complete, the measured load step response can be compared to Figures 26 through 28. Cn should be tmhea grneistiusdtoer ins oanlwlinaeyas rmityu, cbhu tle lsess sd usori nbge cthaeu soef ft-htiem ReS tUhMan v odlutarigneg adjusted if necessary to obtain the behavior of Figure 26. the on-time. This nonlinearity-bias-current polarity mismatch causes a small positive offset error in VISUMP. 28 FN8318.0 February 4, 2013

ISL95820 The exact magnitude of this offset error is difficult to predict. It of the sense element resistance, independently of the PCB trace depends on an attribute of the sense resistors that is typically not resistance differences. specified or controlled, and so not reliably quantified. It also The decision to populate the cross-coupling phase sense varies with the input voltage and the output voltage. If battery resistors will depend upon the magnitude of, and system powered, the input voltage can vary significantly. The output tolerance of, the uncorrected imbalance current. voltage is subject to the VID setting, and to a lesser extent on the droop voltage. A further complication is that the nonlinearity LOAD STEP RING BACK offset changes with the number of active phases. For a 4-phase Figure 29 shows the output voltage ring back problem during configuration in PS0, four RSUM resistors are subjected to the load transient response with DC Loadline (i.e., “droop”) enabled. high difference in on-time compared to off-time voltage magnitudes. But in PS1, two phases are disabled with the The load current io has a fast step change, but the inductor respective PHASE nodes approximately following the output. So current iL cannot accurately follow. Instead, iL responds in first order system fashion due to the nature of current loop. The ESR VRSUM for the disabled phases is approximately zero for the and ESL effect of the output capacitors makes the output voltage entire switching cycle, reducing the offset error by half. In PS2, three phases are disabled, leaving only a fourth of the PS0 offset Vo dip quickly upon load current change. However, the controller error. regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore it pulls Vo back to the The most direct solution to the phenomenon of current sense level dictated by iL, causing the ring back problem. This offset due to resistor nonlinearity is to use highly linear summing phenomenon is not observed when the output capacitor bank resistors, such as thin film resistors. But the magnitude of the has very low ESR and ESL, such as if using only ceramic offset error typically does not warrant the considerably greater capacitors. expense of doing so. Instead, a correcting fixed offset can be introduced to the current sense network. For the example case described, with each thick film io i RSUM=3.65kΩ, and an ICC(MAX) setting of 100A, the current L sense offset error in PS0 typically represents less than 1% of full scale, and is always positive. It has been found empirically that a 10MΩ pulldown resistor, from the ISUMP node to ground, provides a good correcting offset compromise, slightly Vo under-correcting in PS0, and slightly over-correcting in PS2, but RING meeting processor vendor specification tolerances with adequate BACK margin in all cases. For other applications, a suitable compromise pull-down resistor can be determined empirically by FIGURE 29. OUTPUT VOLTAGE RING BACK PROBLEM testing over the full range of expected operating conditions and power states. It is recommended that this resistor be included in any VR design layout to allow population of the pull-down resistor ISUMP if required. Because of the high value of resistance, two smaller valued resistors in series may be preferred, to reduce the environmental sensitivity of high resistance value devices. Rntcs Cn.1 PHASE CURRENT BALANCING Rp Cn.2 Vcn Phase current imbalance should be measured on a functioning circuit. First determine the correct assembly of the current Rntc Rn balancing mechanism by measuring, on a stable operating regulator, the voltage difference between the ISEN1 pin and the OPTIONAL Ri ISUMN remaining ISENn pins (of all the operational phases) with various static loads applied. Whether using the simplest circuit of Figure1 on page1, or the PCB trace resistance compensating Rip Cip circuit of Figure 2 on page7, the voltage difference between any pair of the ISENn pins should be very small, usually less than 1mV. If not, there may be an assembly error. OPTIONAL Then, again with various static loads applied, measure the FIGURE 30. OPTIONAL CIRCUITS FOR RING BACK REDUCTION voltage directly across each active sense element (sense resistor Figure 30 shows two optional circuits for reduction of the ring or inductor). Any discrepancy in the phase sense element back. voltages beyond what can be attributed to the sense element resistance tolerance must be due to PCB trace resistance Cn is the capacitor used to match the inductor time constant. It deviations. Install the cross-coupling resistors of Figure 29, and often takes the paralleling of multiple capacitors to get the again compare the sense element voltages. Now the sense desired value. Figure 30 shows that two capacitors Cn.1 and Cn.2 element voltages should be the same among the phases in all are in parallel. Resistor Rn is an optional component to reduce cases (to within the tolerance of the cross-coupling resistors), and the Vo ring back. At steady state, Cn.1+ Cn.2 provides the desired the phase current balance will be within the parametric tolerance Cn capacitance. At the beginning of io change, the effective 29 FN8318.0 February 4, 2013

ISL95820 capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 28 shows, Vo tends to dip when Cn is too L Vo small, and this effect will reduce the Vo ring back. This effect is Q1 more pronounced when Cn.1 is much larger than Cn.2. It is also more pronounced when Rn is bigger. However, the presence of Vin GATE Q2 COUT io Rn increases the ripple of the Vn signal if Cn.2 is too small. It is DRIVER recommended to keep Cn.2 greater than 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values should be determined through tuning the load transient response LOAD LINE SLOPE waveforms directly on the target system circuit board. 20Ω Rip and Cip form an R-C branch in parallel with Ri, providing a MOD.COMP EA lower impedance path than Ri at the beginning of IOUT change. VID ISOLATION Rip and Cip do not have any effect at steady state. Through TRANSFORMER CHANNEL B proper selection of Rip and Cip values, Idroop can resemble IOUT LOOP GAIN =CHANNEL A rather than iL, and Vo will not ring back. The recommended value CHANNEL A CHANNEL B for Rip is 100Ω. Cip should be determined by observing the load NETWORK transient response waveforms in a physical circuit. The ANALYZER EXCITATION OUTPUT recommended range for Cip is 100pF~2000pF. However, it should be noted that the Rip -Cip branch may distort the Idroop FIGURE 31. LOOP GAIN T1(s) MEASUREMENT SET-UP waveform. Instead of being triangular as the real inductor current, Idroop may have sharp spikes, which may adversely aOfCfePc at cIdcruoroapc ya.verage value detection and therefore may affect L VO Q1 Voltage Regulation VIN GATE Q2 COUT IO DRIVER COMPENSATOR Intersil provides a Microsoft Excel-based spreadsheet to help design the compensator and the current sensing network, so the LOAD LINE SLOPE VR achieves constant output impedance as a stable system. 20Ω Please go to www.intersil.com/design/ to request spreadsheet. MOD. EA COMP A VR with active droop function is a dual-loop system consisting of VID ISOLATION a voltage loop and a droop loop, which is a current loop. However, TRANSFORMER CHANNEL B neither loop alone is sufficient to describe the entire system. The LOOP GAIN= CHANNEL A spreadsheet shows two loop gain transfer functions, T1(s) and CHANNEL A CHANNEL B T2(s), that describe the entire system. Figure 31 conceptually NETWORK shows T1(s) measurement set-up and Figure 32 conceptually ANALYZER EXCITATION OUTPUT shows T2(s) measurement set-up. The VR senses the inductor current, multiplies it by a gain of the load line slope, then adds it FIGURE 32. LOOP GAIN T2(s) MEASUREMENT SET-UP on top of the sensed output voltage and feeds it to the FB2 Function compensator. T(1) is measured after the summing node, and T2(s) is measured in the voltage loop before the summing node. The The FB2 function allows modification of the compensator when spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) operating in 1-phase. Figure 33 shows the FB2 function. can be actually measured on an ISL95820 regulator. CONTROLLER IN C1 R2 CONTROLLER IN C1 R2 T1(s) is the total loop gain of the voltage loop and the droop loop. 4/3/2-PHASE 1-PHASE MODE It always has a higher crossover frequency than T2(s) and has MODE C3.1 C3.1 more meaning of system stability. C2 R3 FB2 C3.2 C2 R3 FB2 C3.2 T2(s) is the voltage loop gain with closed droop loop. It has more meaning of output voltage response. VSEN R1 VSEN R1 FB E/A FB E/A Design the compensator to get stable T1(s) and T2(s) with COMP COMP VREF VREF sufficient phase margin, and output impedance equal or smaller than the load line slope. FIGURE 33. FB2 FUNCTION A switch (called FB2 switch) turns on (closes) to short, internally, the FB and the FB2 pins when the controller is in 4-phase, 3-phase or 2-phase mode. When FB2 is closed, capacitors C3.1 and C3.2 are in parallel, serving as part of the compensator. When the controller enters 1-phase mode, the FB2 switch opens, removing 30 FN8318.0 February 4, 2013

ISL95820 C3.2 and leaving only C3.1 in the compensator. The compensator gain will increase with the removal of C3.2. By properly sizing C3.1 VDD and C3.2, the compensator can be optimized separately for 4-, 3-, 2-phase modes and for 1-phase mode. VR_ON SLEW RATE 2.5mV/µs VID VID While the FB2 switch is open and C3.2 is disconnected from the COMMAND FB pin, the controller actively drives the FB2 pin voltage to track 2.3ms VOLTAGE the FB pin voltage, such that the C3.2 voltage remains equal to DAC the C3.1 voltage. When the controller closes the FB2 switch, C3.2 will be reconnected to the compensator smoothly with no PGOOD capacitor voltage discontinuities. ALERT# …... The FB2 function ensures excellent transient response in 4-, 3-, FIGURE 35. VR SOFT-START WAVEFORMS 2-phase modes and in 1-phase mode. If one decides not to use the FB2 function, simply populate C3.1 only. VOLTAGE REGULATION FB3 Function After the start sequence, the controller regulates the output The FB3 function allows for changing the compensator loop gain voltage to the value set by the VID information per Table 5. The depending on whether the VOUT droop function is enabled. controller will control the no-load output voltage to an accuracy of Figure34 shows the FB3 pin function. ±0.5% over the VID range. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. CONTROLLER C1 R2 CONTROLLER C1 R2 This mechanism is illustrated in Figure 22. VCCSENSE and WITH DROOP WITH DROOP VSSSENSE are the remote voltage sensing signals from the ENABLED DISABLED processor die. A unity gain differential amplifier senses the C2 C2 R3 C3.1 R3 C3.1 VSSSENSE voltage and adds it to the DAC output. Note how the illustrated DC Loadline mechanism (the “droop” mechanism, VSEN R1 FB VSEN R1 FB described in “Programming the DC Loadline” on page24), VREF E/A VREF E/A introduces a load-dependent reduction in the output voltage, R1' FB3 COMP R1' FB3 COMP (denoted VCCSENSE), below the VID value output by the DAC. The error amplifier regulates the inverting and the non-inverting input FIGURE 34. FB3 FUNCTION voltages to be equal, as shown in Equation55: A switch (called the FB3 switch) turns on to short ( internally) the VCC +V = V +VSS (EQ. 55) FB and the FB3 pins, whenever the droop function is enabled. SENSE droop DAC SENSE Resistors R1 and R1’ are in parallel when droop is enabled, together setting the droop loadline resistance, and serving as part Rewriting Equation 55 and substitution of Equation 5 gives of the compensator. When droop is disabled, the FB3 switch turns Equation 56: off (opens), removing R1’ and leaving only R1 in the compensator. VCCSENSE–VSSSENSE = VDAC–Rdroop×Idroop (EQ. 56) The compensator gain will decrease with the removal of R1’. By properly sizing R1 and R1’, the compensator can be optimized separately for both droop enabled and disabled. Equation 56 is the exact equation required for load line implementation. To use the FB3 function, the droop resistor (Rdroop in Equation56) is the parallel combination of R1 and R1’. The The VCCSENSE and VSSSENSE signals come from the processor die. compensator will use R1 only while droop is disabled, and R1 in The feedback will be open circuit in the absence of the processor. As parallel with R1’ when droop is enabled. If one decides not to use Figure 22 shows, it is recommended to add a “catch” resistor to feed the FB3 function, simply populate R1 only. the VR local output voltage back to the compensator, and add another “catch” resistor to connect the VR local output ground to the START-UP TIMING RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage feedback if the system is powered up without a processor installed. With the controller's VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the logic high The maximum VID (output voltage command) value supported is threshold. Figure 35 shows the typical start-up timing. The 2.3V. Any VID command (or sum of VID command and VID offset) controller uses digital soft-start to ramp-up DAC to the voltage above 2.3V will be ignored. programmed by the SetVID command. PGOOD is asserted high and ALERT# is asserted low at the end of the ramp up. Similar TABLE 5. VID TABLE behavior occurs if VR_ON is tied to VDD, with the soft-start VID VO (V) sequence starting 2.3ms after VDD crosses the POR threshold. 7 6 5 4 3 2 1 0 HEX VR12.5 0 0 0 0 0 0 0 0 0 0 0.00000 0 0 0 0 0 0 0 1 0 1 0.50000 0 0 0 0 0 0 1 0 0 2 0.51000 0 0 0 0 0 0 1 1 0 3 0.52000 31 FN8318.0 February 4, 2013

ISL95820 TABLE 5. VID TABLE (Continued) TABLE 5. VID TABLE (Continued) VID VO (V) VID VO (V) 7 6 5 4 3 2 1 0 HEX VR12.5 7 6 5 4 3 2 1 0 HEX VR12.5 0 0 0 0 0 1 0 0 0 4 0.53000 0 0 1 0 1 1 1 0 2 E 0.95000 0 0 0 0 0 1 0 1 0 5 0.54000 0 0 1 0 1 1 1 1 2 F 0.96000 0 0 0 0 0 1 1 0 0 6 0.55000 0 0 1 1 0 0 0 0 3 0 0.97000 0 0 0 0 0 1 1 1 0 7 0.56000 0 0 1 1 0 0 0 1 3 1 0.98000 0 0 0 0 1 0 0 0 0 8 0.57000 0 0 1 1 0 0 1 0 3 2 0.99000 0 0 0 0 1 0 0 1 0 9 0.58000 0 0 1 1 0 0 1 1 3 3 1.00000 0 0 0 0 1 0 1 0 0 A 0.59000 0 0 1 1 0 1 0 0 3 4 1.01000 0 0 0 0 1 0 1 1 0 B 0.60000 0 0 1 1 0 1 0 1 3 5 1.02000 0 0 0 0 1 1 0 0 0 C 0.61000 0 0 1 1 0 1 1 0 3 6 1.03000 0 0 0 0 1 1 0 1 0 D 0.62000 0 0 1 1 0 1 1 1 3 7 1.04000 0 0 0 0 1 1 1 0 0 E 0.63000 0 0 1 1 1 0 0 0 3 8 1.05000 0 0 0 0 1 1 1 1 0 F 0.64000 0 0 1 1 1 0 0 1 3 9 1.06000 0 0 0 1 0 0 0 0 1 0 0.65000 0 0 1 1 1 0 1 0 3 A 1.07000 0 0 0 1 0 0 0 1 1 1 0.66000 0 0 1 1 1 0 1 1 3 B 1.08000 0 0 0 1 0 0 1 0 1 2 0.67000 0 0 1 1 1 1 0 0 3 C 1.09000 0 0 0 1 0 0 1 1 1 3 0.68000 0 0 1 1 1 1 0 1 3 D 1.10000 0 0 0 1 0 1 0 0 1 4 0.69000 0 0 1 1 1 1 1 0 3 E 1.11000 0 0 0 1 0 1 0 1 1 5 0.70000 0 0 1 1 1 1 1 1 3 F 1.12000 0 0 0 1 0 1 1 0 1 6 0.71000 0 1 0 0 0 0 0 0 4 0 1.13000 0 0 0 1 0 1 1 1 1 7 0.72000 0 1 0 0 0 0 0 1 4 1 1.14000 0 0 0 1 1 0 0 0 1 8 0.73000 0 1 0 0 0 0 1 0 4 2 1.15000 0 0 0 1 1 0 0 1 1 9 0.74000 0 1 0 0 0 0 1 1 4 3 1.16000 0 0 0 1 1 0 1 0 1 A 0.75000 0 1 0 0 0 1 0 0 4 4 1.17000 0 0 0 1 1 0 1 1 1 B 0.76000 0 1 0 0 0 1 0 1 4 5 1.18000 0 0 0 1 1 1 0 0 1 C 0.77000 0 1 0 0 0 1 1 0 4 6 1.19000 0 0 0 1 1 1 0 1 1 D 0.78000 0 1 0 0 0 1 1 1 4 7 1.20000 0 0 0 1 1 1 1 0 1 E 0.79000 0 1 0 0 1 0 0 0 4 8 1.21000 0 0 0 1 1 1 1 1 1 F 0.80000 0 1 0 0 1 0 0 1 4 9 1.22000 0 0 1 0 0 0 0 0 2 0 0.81000 0 1 0 0 1 0 1 0 4 A 1.23000 0 0 1 0 0 0 0 1 2 1 0.82000 0 1 0 0 1 0 1 1 4 B 1.24000 0 0 1 0 0 0 1 0 2 2 0.83000 0 1 0 0 1 1 0 0 4 C 1.25000 0 0 1 0 0 0 1 1 2 3 0.84000 0 1 0 0 1 1 0 1 4 D 1.26000 0 0 1 0 0 1 0 0 2 4 0.85000 0 1 0 0 1 1 1 0 4 E 1.27000 0 0 1 0 0 1 0 1 2 5 0.86000 0 1 0 0 1 1 1 1 4 F 1.28000 0 0 1 0 0 1 1 0 2 6 0.87000 0 1 0 1 0 0 0 0 5 0 1.29000 0 0 1 0 0 1 1 1 2 7 0.88000 0 1 0 1 0 0 0 1 5 1 1.30000 0 0 1 0 1 0 0 0 2 8 0.89000 0 1 0 1 0 0 1 0 5 2 1.31000 0 0 1 0 1 0 0 1 2 9 0.90000 0 1 0 1 0 0 1 1 5 3 1.32000 0 0 1 0 1 0 1 0 2 A 0.91000 0 1 0 1 0 1 0 0 5 4 1.33000 0 0 1 0 1 0 1 1 2 B 0.92000 0 1 0 1 0 1 0 1 5 5 1.34000 0 0 1 0 1 1 0 0 2 C 0.93000 0 1 0 1 0 1 1 0 5 6 1.35000 0 0 1 0 1 1 0 1 2 D 0.94000 0 1 0 1 0 1 1 1 5 7 1.36000 32 FN8318.0 February 4, 2013

ISL95820 TABLE 5. VID TABLE (Continued) TABLE 5. VID TABLE (Continued) VID VO (V) VID VO (V) 7 6 5 4 3 2 1 0 HEX VR12.5 7 6 5 4 3 2 1 0 HEX VR12.5 0 1 0 1 1 0 0 0 5 8 1.37000 1 0 0 0 0 0 1 0 8 2 1.79000 0 1 0 1 1 0 0 1 5 9 1.38000 1 0 0 0 0 0 1 1 8 3 1.80000 0 1 0 1 1 0 1 0 5 A 1.39000 1 0 0 0 0 1 0 0 8 4 1.81000 0 1 0 1 1 0 1 1 5 B 1.40000 1 0 0 0 0 1 0 1 8 5 1.82000 0 1 0 1 1 1 0 0 5 C 1.41000 1 0 0 0 0 1 1 0 8 6 1.83000 0 1 0 1 1 1 0 1 5 D 1.42000 1 0 0 0 0 1 1 1 8 7 1.84000 0 1 0 1 1 1 1 0 5 E 1.43000 1 0 0 0 1 0 0 0 8 8 1.85000 0 1 0 1 1 1 1 1 5 F 1.44000 1 0 0 0 1 0 0 1 8 9 1.86000 0 1 1 0 0 0 0 0 6 0 1.45000 1 0 0 0 1 0 1 0 8 A 1.87000 0 1 1 0 0 0 0 1 6 1 1.46000 1 0 0 0 1 0 1 1 8 B 1.88000 0 1 1 0 0 0 1 0 6 2 1.47000 1 0 0 0 1 1 0 0 8 C 1.89000 0 1 1 0 0 0 1 1 6 3 1.48000 1 0 0 0 1 1 0 1 8 D 1.90000 0 1 1 0 0 1 0 0 6 4 1.49000 1 0 0 0 1 1 1 0 8 E 1.91000 0 1 1 0 0 1 0 1 6 5 1.50000 1 0 0 0 1 1 1 1 8 F 1.92000 0 1 1 0 0 1 1 0 6 6 1.51000 1 0 0 1 0 0 0 0 9 0 1.93000 0 1 1 0 0 1 1 1 6 7 1.52000 1 0 0 1 0 0 0 1 9 1 1.94000 0 1 1 0 1 0 0 0 6 8 1.53000 1 0 0 1 0 0 1 0 9 2 1.95000 0 1 1 0 1 0 0 1 6 9 1.54000 1 0 0 1 0 0 1 1 9 3 1.96000 0 1 1 0 1 0 1 0 6 A 1.55000 1 0 0 1 0 1 0 0 9 4 1.97000 0 1 1 0 1 0 1 1 6 B 1.56000 1 0 0 1 0 1 0 1 9 5 1.98000 0 1 1 0 1 1 0 0 6 C 1.57000 1 0 0 1 0 1 1 0 9 6 1.99000 0 1 1 0 1 1 0 1 6 D 1.58000 1 0 0 1 0 1 1 1 9 7 2.00000 0 1 1 0 1 1 1 0 6 E 1.59000 1 0 0 1 1 0 0 0 9 8 2.01000 0 1 1 0 1 1 1 1 6 F 1.60000 1 0 0 1 1 0 0 1 9 9 2.02000 0 1 1 1 0 0 0 0 7 0 1.61000 1 0 0 1 1 0 1 0 9 A 2.03000 0 1 1 1 0 0 0 1 7 1 1.62000 1 0 0 1 1 0 1 1 9 B 2.04000 0 1 1 1 0 0 1 0 7 2 1.63000 1 0 0 1 1 1 0 0 9 C 2.05000 0 1 1 1 0 0 1 1 7 3 1.64000 1 0 0 1 1 1 0 1 9 D 2.06000 0 1 1 1 0 1 0 0 7 4 1.65000 1 0 0 1 1 1 1 0 9 E 2.07000 0 1 1 1 0 1 0 1 7 5 1.66000 1 0 0 1 1 1 1 1 9 F 2.08000 0 1 1 1 0 1 1 0 7 6 1.67000 1 0 1 0 0 0 0 0 A 0 2.09000 0 1 1 1 0 1 1 1 7 7 1.68000 1 0 1 0 0 0 0 1 A 1 2.10000 0 1 1 1 1 0 0 0 7 8 1.69000 1 0 1 0 0 0 1 0 A 2 2.11000 0 1 1 1 1 0 0 1 7 9 1.70000 1 0 1 0 0 0 1 1 A 3 2.12000 0 1 1 1 1 0 1 0 7 A 1.71000 1 0 1 0 0 1 0 0 A 4 2.13000 0 1 1 1 1 0 1 1 7 B 1.72000 1 0 1 0 0 1 0 1 A 5 2.14000 0 1 1 1 1 1 0 0 7 C 1.73000 1 0 1 0 0 1 1 0 A 6 2.15000 0 1 1 1 1 1 0 1 7 D 1.74000 1 0 1 0 0 1 1 1 A 7 2.16000 0 1 1 1 1 1 1 0 7 E 1.75000 1 0 1 0 1 0 0 0 A 8 2.17000 0 1 1 1 1 1 1 1 7 F 1.76000 1 0 1 0 1 0 0 1 A 9 2.18000 1 0 0 0 0 0 0 0 8 0 1.77000 1 0 1 0 1 0 1 0 A A 2.19000 1 0 0 0 0 0 0 1 8 1 1.78000 1 0 1 0 1 0 1 1 A B 2.20000 33 FN8318.0 February 4, 2013

ISL95820 TABLE 5. VID TABLE (Continued) In the example scenario of Figure 36, the controller receives a SetVID_decay command at t1. The VR enters DEM and the VID VO (V) output voltage Vo decays down slowly. At t2, before Vo reaches 7 6 5 4 3 2 1 0 HEX VR12.5 the intended VID target of the SetVID_decay command, the controller receives a SetVID_fast (or SetVID_slow) command to 1 0 1 0 1 1 0 0 A C 2.21000 go to a voltage higher than the actual Vo. The controller will 1 0 1 0 1 1 0 1 A D 2.22000 preempt the decay to the lower voltage and slew Vo to the new 1 0 1 0 1 1 1 0 A E 2.23000 target voltage at the slew rate specified by the SetVID command. At t3, Vo reaches the new target voltage and the controller 1 0 1 0 1 1 1 1 A F 2.24000 asserts the ALERT# signal. 1 0 1 1 0 0 0 0 B 0 2.25000 SLEW RATE COMPENSATION CIRCUIT FOR VID 1 0 1 1 0 0 0 1 B 1 2.26000 TRANSITION 1 0 1 1 0 0 1 0 B 2 2.27000 During a large VID transition, the DAC steps through the VID table 1 0 1 1 0 0 1 1 B 3 2.28000 at proscribed step rate. For example, the DAC may change 1 tick 1 0 1 1 0 1 0 0 B 4 2.29000 (10mV) per 1+µs, controlling output voltage Vcore slew rate at less than 10mV/µs, or 1 tick per 4+µs, controlling output voltage 1 0 1 1 0 1 0 1 B 5 2.30000 Vcore slew rate at less than 2.5mV/µs. Figure 37 shows the waveforms of VID transition. DYNAMIC VID OPERATION The controller receives VID commands via either the Serial VID (SVID) port or the serial I2C/SMBus/PMBus port. It responds to Rdroop Vcore VID changes by slewing to the new voltage at a slew rate indicated in the SetVID command. There are three SetVID slew Rvid Cvid OPTIONAL rates: SetVID_fast, SetVID_slow, and SetVID_decay. FB Ivid SetVID_fast command prompts the controller to enter CCM and to actively drive the output voltage to the new VID value at a slew I droop_vid rate up to but not to exceed 10mV/µs. E/A VIDs Σ SetVID_slow command prompts the controller to enter CCM and COMP DAC VID VDAC to actively drive the output voltage to the new VID value at a slew RTN rate up to but not to exceed 2.5mV/µs. VSSSENSE X 1 VSS SetVID_decay command prompts the controller to enter DEM. The INTERNAL TO output voltage will decay down to the new VID value at a slew rate IC determined by the load. If the voltage decay rate is too fast, the controller will limit the voltage slew rate to the fast slew rate of VID 10mV/µs. If DEM is disabled by the PROG2 programming resistor, the SVID command "SetVID_decay" executes as single-phase (Phase 1 only) “SetVID_slow” except that ALERT# signaling mimics Vfb that of the “SetVID_decay” command. ALERT# is asserted (low) upon completion of all non-zero VID Ivid transitions. Figure 36 shows SetVID Decay Pre-Emptive response, which occurs whenever a new VID command is received before Vcore completion of a previous SetVID Decay command. SetVID_decay SetVID_fast/slow Idroop_vid Vo FIGURE 37. SLEW RATE COMPENSATION CIRCUIT FOR VID TRANSITION VID During VID transition, the output capacitor is being charged and t3 discharged, causing Coutx dVcore/dt current on the inductor. The t1 T_alert t2 controller senses the inductor current increase during the up ALERT# transition (as the Idroop_vid waveform shows) and will droop the output voltage Vcore accordingly, making Vcore slew rate slow. Similar behavior occurs during the down transition. To get the FIGURE 36. SETVID DECAY PRE-EMPTIVE BEHAVIOR correct Vcore slew rate during VID transition, one can add the Rvid-Cvid branch, whose current Ivid compensates for Idroop_vid. 34 FN8318.0 February 4, 2013

ISL95820 Choose the R, C values from the reference design as a starting Because the higher output voltage requires a higher switching point, then tweak the actual values on the board to get the best duty cycle, a higher slope compensation value may be required performance. for stability. During normal transient response, the FB pin voltage is held The abrupt inclusion of Rg to the feedback network will create a constant, therefore is virtual ground in small signal sense. The step in the selected output voltage, which may result in high Rvid- Cvid network is between the virtual ground and the real overshoot or ringing in the output. The RC network on the gate of ground, and hence has no effect on transient response. the 2N7002 may slow the transition from normal range to extended range. EXTENDED V RANGE OUT Note that with extended range enabled, the VID step size will If a higher (than max supported VID) output voltage is required, increase by the inverse divider ratio. Consequently, the DVID slew such as for overclocking applications, the feedback voltage can rates will also increase by the same ratio. be divided down to the FB pin such that VFB = VID for VVOUT > VID. Figure 38 shows the addition of resistor Rg (and optional Fault Protection 2N7002 switch), which adds the feedback voltage division to the schematic of Figure 22 on page25. The ISL95820 provides overcurrent, current-balance and overvoltage fault protections. The controller also provides With the 2N7002 off, VVOUT = VID – Vdroop = VID – Rdroop*Idroop, over-temperature protection. the same as in the normal configuration. But with the 2N7002 switch closed, VOUT = VID -(Idroop-VID/Rg)*Rdroop = VID The controller determines overcurrent protection (OCP) by (1+Rdroop/Rg) – Idroop*Rdroop. comparing the average value of the droop current Idroop with an internal current source threshold as Table 4 shows. It declares OCP when Idroop is above the threshold for 120µs. The controller monitors the ISEN pin voltages to determine Rdroop current-balance protection. If the difference of one ISEN pin Vdroop VCCSENSE = VOUT voltage and the average ISENs pin voltage is greater than 9mV (for at most 4ms), the controller will declare a fault and latch off. FB Rg 2N7002 EN_EXT_VOUT Idroop The controller takes the same actions for all of the above fault protections: de-assertion of PGOOD and turn-off of all the E/A Σ high-side and low-side power MOSFETs. Any residual inductor COMP DAC VID VDAC current will decay through the MOSFET body diodes. COMP RTN VSSSENSE The controller will declare an overvoltage protection (OVP) fault and INTERNAL TO IC X 1 VSS de-assert PGOOD if the voltage of the ISUMN pin (approximately the output voltage) exceeds the VID set value by +300mV. Optionally, the overvoltage threshold can be set, via the PMBus interface, to 3.3V fixed. The controller will immediately declare an OV fault, FIGURE 38. EXTENDING THE RANGE OF VOUT WITH A FEEDBACK de-assert PGOOD, and turn on the low-side power MOSFETs. The RESISTOR DIVIDER low-side power MOSFETs remain on until the output voltage is The unloaded output voltage is then VVOUT (unloaded) = VID pulled down below the VID set value when all power MOSFETs are (1+Rdroop/Rg), and the droop voltage Vdroop = Idroop*Rdroop. turned off. If the output voltage rises above the VID set value again, Notice that the droop voltage is determined by the droop resistor, the protection process is repeated. This behavior provides the and is independent of whether the feedback voltage is divided or maximum amount of protection against shorted high-side power not. Then Rg is selected to obtain the desired divider ratio. The MOSFETs while preventing output ringing below ground. programmed loadline resistance is not affected by the addition The default overvoltage fault threshold is 2.6V when output of Rg.  voltage ramps up from 0V. The overvoltage fault threshold To avoid false OVP faults, the OVP threshold may have to be reverts to VID + 300mV after the output voltage settles. changed to 3.3V fixed, rather than at the relative value of 300mV Optionally, via the PMBus interface, the overvoltage threshold above VID, via the PMBus interface (see “Fault Protection” on can be fixed at 3.3V prior to increasing VID from 0V. page35 for details). The OVP threshold must be changed prior to All the above fault conditions can be reset by bringing VR_ON low turning on the EN_EXT_VOUT switch. Because of OVP, a practical uVpIDp evar lluime.i tT fhoer VmVaOxUimT ius m3. 0su4pVp, worhteicdh VisID a lvsaol uthe ein m thaexi mISLu9m5 d8e2f0in iesd oVrD bDy r ebtruinrgni ntog tVhDeDir bheiglohw o ptheera PtiOnRg ltehvreelssh, oal ds.o Wft-hsetanr tV wR_ilOl oNc caunrd. 2.3V, so the inverse divider ratio (1 + Rdroop/Rg) should not exceed 1.32. 35 FN8318.0 February 4, 2013

ISL95820 Table 6 summarizes the fault protections. TABLE 7. TZONE TABLE VNTC (V) TMAX (%) TZONE TABLE 6. FAULT PROTECTION SUMMARY 1.04 88 0Fh FAULT DURATION BEFORE PROTECTION FAULT 1.08 85 07h FAULT TYPE PROTECTION ACTION RESET 1.12 82 03h Overcurrent 120µs PWM4/Phase tri- VR_ON 1.16 79 01h state, PGOOD toggle or 1.2 76 01h latched low VDD >1.2 <76 00h toggle Phase Current 4ms Imbalance Figure 39 shows how the NTC network should be designed to get correct VR_HOT#/ALERT# behavior when the system temperature Overvoltage: VOUT > Immediate PGOOD latched rises and falls, manifested as the NTC pin voltage falls and rises. The VID+ 300mV low. Actively pulls series of events are: (optionally 3.3V the output voltage fixed) to below VID 1. The temperature rises so the NTC pin voltage drops. Tzone value, then value changes accordingly. Overvoltage: VOUT > tri-states the 2. The temperature crosses the threshold where Tzone register 2.6V = VIDmax + phase switches 300mV (optionally (Phases 1, 2, 3) Bit 6 changes from 0 to 1. 3.3V fixed) during and PWM4. 3. The controller changes Status_1 register bit 1 from 0 to 1. output voltage ramp 4. The controller asserts ALERT#. up from 0V 5. The CPU reads Status_1 register value to know that the alert assertion is due to Tzone register Bit 6 flipping. VR_HOT#/ALERT# Behavior 6. The controller clears ALERT#. VR Temperature 7. The temperature continues rising. Temp Zone 3% Hysteresis 7 1111 1111 Bit 7 =1 8. The temperature crosses the threshold where Tzone register 1 10 0111 1111 Bit 7 changes from 0 to 1. Bit 6 =1 0011 1111 9. The controller asserts VR_HOT# signal. The CPU reduces Bit 5 =1 power consumption, and the system temperature eventually 12 0001 1111 drops. Temp Zone 10. The temperature crosses the threshold where Tzone register Register 2 8 Bit6 changes from 1 to 0. This threshold is 1 ADC step lower 0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111 Status 1 3 than the one when VR_HOT# gets asserted, to provide 3% Register = “001” = “011” = “001” hysteresis. 5 13 15 GerReg GerReg 11.The controllers de-asserts VR_HOT# signal. SVID Status1 Status1 12.The temperature crosses the threshold where Tzone register ALERT# 4 6 14 16 Bit 5 changes from 1 to 0. This threshold is 1 ADC step lower than the one when ALERT# gets asserted during the VR_HOT# 9 11 temperature rise to provide 3% hysteresis. 13.The controller changes Status_1 register bit 1 from 1 to 0. FIGURE 39. VR_HOT#/ALERT# BEHAVIOR 14.The controller asserts ALERT#. The controller drives 60µA current source out of the NTC pin. The 15.The CPU reads Status_1 register value to know that the alert current source flows through the respective NTC resistor assertion is due to Tzone register Bit 5 flipping. networks on the pins and creates voltages that are monitored by the controller through an A/D converter (ADC) to generate the 16. The controller clears ALERT#. Tzone value. Table 7 shows the programming table for Tzone. The To disable the NTC function, connect the NTC pin to VDD using a user needs to scale the NTC network resistance, such that it pullup resistor. generates the NTC pin voltage that corresponds to the left-most column. Do not use any capacitor to filter the voltage. Serial Interfaces TABLE 7. TZONE TABLE Serial VID (SVID) Supported Data and VNTC (V) TMAX (%) TZONE Configuration Registers 0.84 >100 FFh The controller supports the following data and configuration 0.88 100 FFh registers, accessible via the SVID interface. 0.92 97 7Fh The device is compliant with Intel VR12.5/VR12/IMVP7 SVID 0.96 94 3Fh protocol. To ensure proper CPU operation, refer to this document 1.00 91 1Fh for SVID bus design and layout guidelines; each platform requires 36 FN8318.0 February 4, 2013

ISL95820 different pull-up impedance on the SVID bus, while impedance TABLE 8. SUPPORTED DATA AND CONFIGURATION matching and spacing among DATA, CLK, and ALERT# signals REGISTERS (Continued) must be followed. Common mistakes are insufficient spacing REGISTER DEFAULT among signals and improper pull-up impedance. INDEX NAME DESCRIPTION VALUE TABLE 8. SUPPORTED DATA AND CONFIGURATION 31h VID Setting Data register containing currently REGISTERS programmed VID voltage. See Table 5 beginning on page31. REGISTER DEFAULT INDEX NAME DESCRIPTION VALUE 32h Power State Register containing the current 00h programmed power state. 00h Vendor ID Uniquely identifies the VR vendor. 12h Assigned by Intel. 33h Voltage Sets offset in VID steps added to the 00h Offset VID setting for voltage margining, 01h Product ID Uniquely identifies the VR product. 10h expressed as an 8-bit 2's-complement Intersil assigns this number. offset value. For example: 02h Product Uniquely identifies the revision of the ... Revision VR control IC. Intersil assigns this data. FEh = -2 VID steps FFh = -1 VID step 05h Protocol ID Identifies what revision of SVID 03h 00h = zero offset, no margin protocol the controller supports. 01h = +1 VID step 06h Capability Identifies the SVID VR capabilities and 81h 02h = +2 VID steps which of the optional telemetry ... registers are supported. 34h Multi VR Data register that configures multiple 00h 10h Status_1 Data register read after ALERT# 00h Config VRs behavior on the same SVID bus. signal. Indicating if a VR rail has settled, has reached VRHOT condition The SVID alertB is asserted for the following conditions: or has reached ICC max. 1. When VRsettled is asserted for non-zero volt 11h Status_2 Data register showing status_2 00h commandedVID. If the commandedVID is changed, the communication. alertB will de-assert while the DAC is moving to the new 12h Temperature Data register showing temperature 00h target. Zone zones that have been entered. 2. Therm alert changing from 0 to 1 or from 1 to 0. (Read 15h ICC Read output current, range 00h to FFh Status1 required to clear this alert flag.) 1Ch Status_2_ This register contains a copy of the 00h LastRead Status_2 data that was last read with 3. ICC(MAX) alert changing from 0 to 1 or from 1 to 0. (Read Status1 required to clear this alert flag.) the GetReg (Status_2) command. 21h ICC(MAX) Data register containing the ICC max Refer to Serial PMBus (I2C/SMBus/PMBus) Supported the platform supports, set at start-up Table 2 Data and Configuration Registers by resistors Rprog1 and Rprog2. The platform design engineer programs The ISL95820 features SMBus, PMBus, and I2C with fixed write this value during the design process. address 80h and fixed read address 81h. (The least significant Binary format in amps, i.e., 100A= bit of the 8-bit address is for write (0h) and read (1h).) 64h SMBus/PMBus includes an Alert# line and Packet Error Check 22h Temp max Not supported 00h (PEC) to ensure data properly transmitted. In addition, the output 24h SR-fast Slew Rate Normal. The fastest slew 0Ah voltage and offset, droop enable, overvoltage setpoint, and the rate the platform VR can sustain. priority of SVID and SMBus/PMBus/I2C can be written and read Binary format in mV/µs. i.e., via this bus, as summarized in Table 9. Output current and 0Ah=10mV/µs. voltage setting can be read as summarized in Table 10. For 25h SR-slow Is 4x slower than normal. Binary 02h proper operation, users should follow the SMBus, PMBus, and I2C format in mV/µs. i.e., 02h=2.5mV/µs protocol, as shown in Figure 42. Note that STOP (P) bit is NOT 26h VBOOT If programmed by the platform, the VR 00h allowed before the repeated START condition when “reading” supports VBOOT voltage during contents of register, as shown in Figure 42. start-up ramp. The VR will ramp to VBOOT and hold at VBOOT until it receives a new SetVID command to move to a different voltage. 30h VOUT max This register is programmed by the B5h master and sets the maximum VID the VR will support. If a higher VID code is received, the VR will respond with “not supported” acknowledge. 37 FN8318.0 February 4, 2013

ISL95820 SMBus/PMBus/I2C allows programming the registers of Table 9, 11ms after VCC above POR, and after VR_ON input is high. 5V VCC VCC POR READER User Can Change TIME OUT DONE READER Resistor Divider READER SVID 0C-0F CONFIGURATION RE-LOADED To Reset 0C- 0F RE-LOADED LOADED WITH New DC-DF 9 ms 2 ms INDEFINITELY ENABLE 4.6 ms 4.6 ms D0 to F3 D0 to F3 COMMAND COMMAND NO SUCCESFUL BUS SEND COMMAND VOUT FIGURE 40. SIMPLIFIED SMBus/PMBus/I2C INITIALIZATION TIMING DIAGRAM WHEN NO BUS WRITE COMMAND RECEIVED 5V VCC VCC POR READER SVID 0C-0F CONFIGURATION TIME OUT DONE LOADED WITH DC-DF USE PREVIOUS SLOVIADD 0ECD- 0WF ICTHO NNFEIWGU DRCA-TDIFON SVID 0C-0F 9 ms 2 ms INDEFINITELY ENABLE DC to DF D1 to F3 D0 to F3 D0 to F3 DC to DF D0 to F3 COMMAND COMMAND COMMAND COMMAND COMMAND COMMAND VOUT FIGURE 41. SIMPLIFIED SMBus/PMBus/I2C INITIALIZATION TIMING DIAGRAM WHEN BUS WRITE COMMAND SUCESSFULLY RECEIVED Not Used for One Byte Word Write Byte/Word Protocol 1 7 + 1 1 8 1 8 1 8 1 8 1 1 S Slave Address_0 A Command Code A Low Data Byte A High Data Byte A PEC A P Optional 9 Bits for SMBus/PMBus NOT used in I2C Example command: DAh SET_VID (one word, High Data Byte and ACK are not used) S: Start Condition A: Acknowledge (“0”) N: Not Acknowledge (“1”) W: Write (“0”) RS: Repeated Start Condition R: Read (“1”) PEC: Packet Error Checking P: Stop Condition Acknowledge or DATA from Slave, ISL95820 Controller FIGURE 42. SMBus/PMBus/I2C PROTOCOL 38 FN8318.0 February 4, 2013

ISL95820 TABLE 9. SMBus, PMBus, AND I2C WRITE AND READ REGISTERS COMMAND CODE ACCESS DEFAULT COMMAND NAME DESCRIPTION D4h[0] R/W DROOP_EN 0h=Droop Disabled; 1h = Droop Enabled; default determined by PROG2 pin resistance to ground. See Table 3. When the controller is reset by the VR_ON pin transitioning from low to high, the PROG2 resistance is measured and this register is stored accordingly. D6h[1:0] R/W 00h LOCK_SVID set SVID and SMBus/PMBus/I2C Priority (See Table 11 for details) D8h[0] R/W 00h SET_OV 0h = VID+300mV, 1h = 3.3V fixed. DAh[7:0] R/W SET_VID SVID Bus VID Code. See Table 5 beginning on page31. Default to VBOOT value on start-up, determined by PROG2 pin resistance to ground. DBh[7:0] R/W 00h SET_OFFSET SVID Bus VID offset code, expressed as an 8-bit 2's-complement offset value. For example: ... FEh = -2 VID steps FFh = -1 VID step 00h = zero offset, no margin 01h = +1 VID step 02h = +2 VID steps ... TABLE 10. SMBus, PMBus, AND I2C TELEMETRIES WORD LENGTH CODE (BYTE) COMMAND NAME DESCRIPTION TYPICAL RESOLUTION 8Bh TWO READ_VOUT Output Voltage 8-BIT, 10mV (VID+OFFSET, see Table 5 8Ch TWO READ_IOUT Output Current (FF = ICC(MAX) 8-BIT, ICC(MAX)/255 39 FN8318.0 February 4, 2013

ISL95820 TABLE 11. LOCK_SVID SVID SMBus, PMBus or I2C SETPS (1/2/3) D6h SETVID AND SETDECAY SET OFFSET SETVID SET OFFSET FINAL DAC TARGETED APPLICATIONS 00h Yes Yes Yes Not Not SV_VID + SV_OFFSET Not Overclocking 01h Yes Yes Yes Not Yes SV_VID + PM_OFFSET Not Overclocking 02h Yes ACK ONLY ACK ONLY Not Yes SV_VID + PM_OFFSET Overclocking 03h ACK ONLY ACK ONLY ACK ONLY Yes Yes PM_VID + PM_OFFSET Overclocking NOTE: 8. The ISL95820 controller is designed such that all SVID commands are acknowledged as if the SMBus, PMBus or I2C does not exist. To avoid conflict between SMBus/PMBus/I2C and SVID bus during operation, execute this command prior to writing the VID setting or offset commands. With 01h option, SMBus/PMBus/I2C’s OFFSET should only adjust slightly higher or lower (say ±20mV) than SVID OFFSET for margining purpose or PCB loss compensation so that CPU will not draw significantly more power in PSI1/2/3/Decay mode. To program full range of PM_OFFSET for overclocking applications, select 02h or 03h options. 03h option gives full control of the output voltage (VID+OFFSET) via SMBus/PMBus/I2C, commonly used in overclocking applications. Prior to a successful written PMBus VID or OFFSET, the controller will continue executing SVID VID or OFFSET command. 40 FN8318.0 February 4, 2013

ISL95820 Layout Guidelines ISL95820 PIN NUMBER SYMBOL LAYOUT GUIDELINES BOTTOM PAD GND Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect to ground planes in PCB internal layers. This is also the primary conduction path for heat removal. 1 VR_ON No special consideration. 2 PGOOD No special consideration. 3 IMON No special consideration. 4 VR_HOT# No special consideration. 5 NTC The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU Vcore thermal throttling. Recommend placing it at the hottest spot of the CPU Vcore VR. 6 COMP Place the compensator components in general proximity of the controller. 7 FB 8 FB2 9 FB3 10 ISEN4 Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small: 11 ISEN3 1. Any ISEN pin to another ISEN pin 12 ISEN2 2. Any ISEN pin to GND 13 ISEN1 The red traces in the following drawing show the loops that need to minimized. Phase1 L3 Risen Ro ISEN3 Cisen Vo Phase2 L2 Risen Ro ISEN2 Cisen Phase3 L1 Risen Ro ISEN1 Vsumn GND Cisen Cvsumn 14 RTN Place the RTN filter in close proximity of the controller for good decoupling. 41 FN8318.0 February 4, 2013

ISL95820 Layout Guidelines (Continued) ISL95820 PIN NUMBER SYMBOL LAYOUT GUIDELINES 15 ISUMN Place the current sensing circuit in general proximity of the controller. 16 ISUMP Place capacitor Cn very close to the controller. Place the inductor temperature sensing NTC thermistor next to phase-1 inductor (L1) so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route the ISUMPn and ISENn resistor traces to the phase-side pad of each inductor. The ISUMNn network Ro resistor traces should be routed to the VOUT-side pad of each inductor. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. INDUCTOR INDUCTOR VIAS CURRENT-SENSING TRACES CURRENT-SENSING TRACES 17 VDD A capacitor decouples it to GND. Place it in close proximity of the controller. 18 BOOT1 Place the Phase1 bootstrap capacitor between BOOT1 and PHASE1, near the controller. 19 PHASE1 No special consideration. 20 UGATE1 No special consideration. 21 LGATE1 No special consideration. 22 BOOT2 Place the Phase2 bootstrap capacitor between BOOT2 and PHASE2, near the controller. 23 PHASE2 No special consideration. 24 UGATE2 No special consideration. 25 VCCP A capacitor decouples it to GND. Place it in close proximity of the controller. 26 LGATE2 No special consideration. 27 LGATE3 No special consideration. 28 PHASE3 No special consideration. 29 UGATE3 No special consideration. 30 BOOT3 Place the Phase3 bootstrap capacitor between BOOT3 and PHASE3, near the controller. 31 PWM4 No special consideration. 32 VIN A capacitor decouples it to GND. Place it in close proximity of the controller. 33 PROG3 No special consideration. 34 PROG2 No special consideration. 35 PROG1 No special consideration. 36, 37, 38, 39, I2DATA, Follow Intel recommendation. 40 I2CLK, SDA, ALERT#, SCLK 42 FN8318.0 February 4, 2013

ISL95820 Typical Performance FIGURE 43. SOFT-START, VIN = 12V, IO = 5A, VID = 1.7V, FIGURE 44. SHUT DOWN, VIN = 12V, IO = 5A, VID = 1.7V, Ch1:PHASE1, Ch2: VR_ON, Ch3: PGOOD, Ch4: VOUT Ch1:PHASE1, Ch2: VR_ON, Ch3: PGOOD, Ch4: VOUT FIGURE 45. STEADY STATE, PS0, VIN = 12V, IO = 5A, VID = 1.8V FIGURE 46. STEADY STATE, PS1, VIN = 12V, IO = 5A, VID = 1.8V Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3, Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3, Ch4: VOUT, PHASE4 NOT SHOWN Ch4: VOUT, PHASE4 NOT SHOWN FIGURE 47. STEADY STATE, PS2, VIN = 12V, IO = 5A, VID = 1.8V Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3, Ch4: VOUT, PHASE4 NOT SHOWN 43 FN8318.0 February 4, 2013

ISL95820 Typical Performance (Continued) FIGURE 48. VR1 LOAD RELEASE RESPONSE, VIN = 12V, FIGURE 49. VR1 LOAD INSERTION RESPONSE, VIN = 12V, VID = 1.8V, IO = 61A/1A, SLEW TIME = 50ns, VID = 1.8V, IO = 1A/61A, SLEW TIME = 50ns, LL = 1.5mΩ, Ch1: PHASE1, Ch2: PHASE2, LL = 1.5mΩ, Ch1: PHASE1, Ch2: PHASE2, Ch3:PHASE3, Ch4: VOUT, PHASE4 NOT SHOWN Ch3:PHASE3, Ch4: VOUT, PHASE4 NOT SHOWN FIGURE 50. SETVID-FAST RESPONSE, IO = 5A, VID = 1.6V - 1.8V, FIGURE 51. SETVID-FAST RESPONSE, IO = 5A, VID = 1.8V - 1.6V, Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT FIGURE 52. SETVID-SLOW RESPONSE, IO = 5A, VID = 1.6V - 1.8V, FIGURE 53. SETVID-SLOW RESPONSE, IO = 5A, VID = 1.8V - 1.6V, Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT 44 FN8318.0 February 4, 2013

ISL95820 Typical Performance (Continued) FIGURE 54. SETVID DECAY RESPONSE, IO = 5A, VID = 1.8V - 1.6V, FIGURE 55. SETVID SLOW RESPONSE FOLLOWING SETVID DECAY, Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT IO = 5A, VID = 1.6V - 1.8V, Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT FIGURE 56. SETVID FAST RESPONSE FOLLOWING SETVID DECAY, IO = 5A, VID = 1.6V - 1.8V, Ch1: PHASE1, Ch3: ALERT#, Ch4: VOUT 45 FN8318.0 February 4, 2013

ISL95820 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web for the latest Rev. DATE REVISION CHANGE February 4, 2013 FN8318.0 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: ISL95820 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 46 FN8318.0 February 4, 2013

ISL95820 Package Outline Drawing L40.5x5 40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 9/10 4X 3.60 5.00 A B 36X 0.40 6 6 PIN #1 INDEX AREA PIN 1 INDEX AREA 5.00 3.50 (4X) 0.15 40X 0.4± 0 .1 0.20 TOP VIEW BOTTOM VIEW b 0.10M C A B 4 PACKAGE OUTLINE 0.40 0.750 SEE DETAIL “X” // 0.10C C BASE PLANE 0.050 SEATING PLANE 0.08C SIDE VIEW 0 0 0 5 5. 3. (36X 0.40 0.2 REF (40X 0.20) 5 C (40X 0.60) 0.00 MIN 0.05 MAX TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. JEDEC reference drawing: MO-220WHHE-1 47 FN8318.0 February 4, 2013