DATASHEET ISL9440, ISL9440A, ISL9441 FN6383 Triple, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller Rev 2.00 February 9, 2015 The ISL9440, ISL9440A and ISL9441 are quad-output Features synchronous buck controllers that integrate 3 PWM • Three integrated synchronous buck PWM controllers controllers and 1 low drop-out linear regulator controller, which are full featured and designed to provide multi-rail power for - Internal bootstrap diodes use in products such as cable and satellite set-top boxes, - Internal compensation VoIP gateways, cable modems, and other home connectivity - Internal soft-start products as well as a variety of industrial and general purpose • Independent control for each regulator and programmable applications. Each output is adjustable down to 0.8V. The output voltages; independent enable/shutdown PWMs are synchronized at 180° out of phase thus reducing • Fixed Switching Frequency: 300kHz (ISL9440, ISL9441); the RMS input current and ripple voltage. 600kHz (ISL9440A) The ISL9440, ISL9440A and ISL9441 offer internal soft-start, • Adaptive shoot through protection on all synchronous independent enable inputs for ease of supply rail buck controllers sequencing, and integrated UV/OV/OC/OT protections in a space conscious 5mmx5mm QFN package. The ISL9440 • Independently programmable voltage outputs and ISL9440A offers an early warning function to output a • Out-of-phase switching to reduce input capacitance logic signal to warn the system to back up data when the (0°/180°/0°) input voltage falls below a certain level. • No external current sense resistor The ISL9440, ISL9440A and ISL9441 are utilize internal loop - Uses lower MOSFET’s r DS(ON) compensation to keep minimum peripheral components for • Current mode controller with voltage feed forward compact design and a low total solution cost. These devices are implemented with current mode control with feed forward • Complete protection to cover various applications even with fixed internal - Overcurrent, overvoltage, undervoltage lockout, compensations. over-temperature The table below shows the difference in terms of the • Cycle-by-cycle current limiting ISL9440, ISL9440A and ISL9441 features. • Wide input voltage range - Input rail powers VIN Pin: 5.6V to 24V PART EARLY SWITCHING FREQUENCY NUMBER WARNING (kHz) - Input rail powers VCC_5V Pin (VIN tied to VCC_5V, for 5V input applications): 4.5V to 5.6V ISL9440 YES 300 • Early warning (ISL9440, ISL9440A) on input voltage ISL9440A YES 600 failure ISL9441 NO 300 • Integrated reset function (ISL9440, ISL9440A) • Pb-free (RoHS compliant) Applications • Satellite and cable set-top boxes • Cable modems • VoX gateway devices • NAS/SAN devices Related Literature • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages” FN6383 Rev 2.00 Page 1 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Pinout ISL9440, ISL9440A, ISL9441 (32 LD 5X5 QFN) TOP VIEW E1 1 E1 E1 E2 E2 2 E2 AS OT AT AT AT AT OT AS H O G G G G O H P B U L L U B P 32 31 30 29 28 27 26 25 ISEN1 1 24 ISEN2 PGOOD 2 23 PGND VCC_5V 3 22 LGATE3 VIN 4 21 UGATE3 EN1 5 20 BOOT3 FB1 6 19 PHASE3 OCSET1 7 18 ISEN3 RST 8 17 EN3 9 10 11 12 13 14 15 16 4 B D 2 2 2 3 3 G F N T B N T B O G E F E E F LD S CS CS O O Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Note 1, 2, 3) MARKING (°C) (Pb-Free) DWG. # ISL9440IRZ* ISL9440IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B ISL9440AIRZ* 9440AIRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B ISL9441IRZ* ISL9441IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B NOTES: 1. *Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9440, ISL9440A, ISL9441. For more information on MSL, please see tech brief TB363 FN6383 Rev 2.00 Page 2 of 20 February 9, 2015

FeFN Block Diagram IS bruary 9, 20156383Rev 2.0 PUBHGOAOASTTEE111 ADAPTIVE DEAVDC-TCIM_5EV PGOOD RST VCC_5V VIN PGND EN1 EN2 EN3 AVDCACP_T5IVVE DEAD-TIME PUBHGOAAOSTEET222 L9440, ISL944 0 VCC_5V 0 V/I SAMPLE TIMING A LGATE1 V/I SAMPLE TIMING VLCGCA_T5VE2 , IS POR L 9 4 PGND ENABLE 41 BIAS SUPPLIES PGND BOOT3 0.8V REF REFERENCE VCC_5V G4 + 0.8V REF UGATE3 VE FAULT LATCH gm*VE - PHASE3 FB4 SOFT-START ADAPTIVE DEAD-TIME EARLY WARNING V/I SAMPLE TIMING VCC_5V (see note 6) LGATE3 0.8V REF 1400k 18.5pF OCP PGOOD PGND FB1 180k - + 16k - PWM1 OC1OC2OC3 UV/OV UV PWM3 FB3 0.8V REF ERROR AMP 1 + FB1 FB2FB3FB4 VIN ISEN3 OCSET3 OC3 DUTY CYCLE RAMP GENERATOR ISEN1 CHANNEL 3 PWM CHANNEL PHASE CONTROL - CURRENT SAMPLE + CURRENT PWM2 SAMPLE OCSET1 FB2 + 1.75V REFERENCE ISEN2 - OC2 P OC1 OCSET2 a g + SAME STATE FOR e 2 CLOCK CYCLES CHANNEL 2 3 REQUIRED TO LATCH VIN SGND VCC_5V o OVERCURRENT FAULT f 2 CHANNEL 1 0 0.8V REF

ISL9440, ISL9440A, ISL9441 Typical Application - ISL9440, ISL9441 +12V + C1 56µF C2 4.7µF C16 1µF VIN VCC_5V 4 3 C3 BOOT1 BOOT2 C6 10µF 31 26 10µF 0.C1µ7F UGATE1 30 27 UGATE2 C0.81µF PHASE1 32 25 PHASE2 VOUT1 L1 R3 ISEN1 1 24 ISEN2 R4 L2 VOUT2 +2.5V, 6A C9 + C14+ 3.3µH 8.45k 8.45k 2.2µH +C10 +C15 +1.5V, 6A 330µF 330µF 330µF 330µF Q1 LGATE1 29 28 LGATE2 R5 10.R21k IRF7907 FB2 QIR2F7907 4.02k 13 FB1 6 R6 R2 C11 +12V 4.53k 4.75k VOUT3 0.01µF ISL9440/ISL9441 +5V C61 R12 BOOT3 100 G4 20 1µF Q4 9 VOUT4 IRF7404 C81 UGATE3 21 0.1µF +3.3V, 500mA PHASE3 R10 19 C12+ 15k LDOFB 68µF 10 ISEN3 R41 L3 VOUT3 18 R11 2.8k 15µH +C13 +5V, 2A R52 4.75k 330µF LGATE3 100 R71 OCSET1 22 FB3 QIR3F7907 R245.13k C2.522nF 301k 7 16 R72 OCSET2 V VCC_5V 301k 12 OCSET3 R91 R61 2R6713k 15 10k 4.53k 8 RST RST V VCC_5V R9 10k PGOOD 2 PGOOD 5 14 17 23 11 EN1 EN2 EN3 PGND SGND FN6383 Rev 2.00 Page 4 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Typical Application - ISL9440A +12V + C1 56µF C2 4.7µF C16 1µF VIN VCC_5V 4 3 C3 BOOT1 BOOT2 C6 10µF 31 26 10µF 0.C1µ7F UGATE1 30 27 UGATE2 C0.81µF PHASE1 32 25 PHASE2 VOUT1 L1 R3 ISEN1 1 24 ISEN2 R4 L2 VOUT2 +2.5V, 6A C9 + C14+ 1.8µH 8.45k 8.45k 1.2µH +C10 +C15 +1.5V, 6A 330µF 330µF 330µF 330µF Q1 LGATE1 29 28 LGATE2 R5 10.R21k IRF7907 FB2 QIR2F7907 4.02k 13 FB1 6 R6 R2 C11 +12V 4.53k 4.75k VOUT3 0.01µF ISL9440A +5V C61 R10120 G4 20 BOOT3 1µF Q4 9 VOUT4 IRF7404 C81 UGATE3 21 0.1µF +3.3V, 500mA PHASE3 R10 19 C12+ 15k LDOFB 68µF 10 ISEN3 R41 L3 VOUT3 18 R11 2.8k 8.2µH +C13 +5V, 2A 4.75k 330µF LGATE3 22 R51 Q3 24.3k OCSET1 IRF7907 R71 FB3 301k 7 16 R72 OCSET2 V VCC_5V 301k 12 OCSET3 R91 R61 2R6713k 15 10k 4.53k 8 RST RST V VCC_5V R9 10k PGOOD 2 PGOOD 5 14 17 23 11 EN1 EN2 EN3 PGND SGND FN6383 Rev 2.00 Page 5 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Absolute Maximum Ratings Thermal Information VCC_5V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Thermal Resistance (Typical)  (oC/W)  (oC/W) JA JC VCC_5V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA 32 Ld QFN Package (Note 4). . . . . . . . 31 3 VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C BOOT/UGATE to PHASE . . . . . . . . . . . . . -0.3V to VCC_5V + 0.3V Maximum Operating Temperature. . . . . . . . . . . . . . .-40°C to +85°C PHASE1,2,3 and ISEN1, 2,3, to GND Maximum Storage Temperature. . . . . . . . . . . . . . . .-65°C to +150°C . . . . . . . . . . . . . . . . . . . . .-5V (<100ns, 10µJ)/-0.3V (DC) to +28V Pb-Free Reflow Profilesee link below EN1,EN2, EN3, FB1, FB2, FB3, to GND. . -0.3V to VCC_5V + 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp LDOFB, OCSET1, OCSET2, OCSET3, LGATE1, LGATE2, LGATE3, to GND. . . -0.3V to VCC_5V + 0.3V PGOOD, RST, G4 to GND. . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech JA Brief TB379. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, T = -40°C to +85°C (Note 8), IN A Typical values are at T = +25°C, unless otherwise specified. A PARAMETER TEST CONDITIONS MIN TYP MAX UNITS V SUPPLY IN Input Voltage Range 5.6 12.0 24.0 V Input Voltage Range V = VCC_5V (Note 9) 4.5 5.0 5.6 V IN VCC_5V SUPPLY (Note 5) Operation Voltage 4.5 5.0 5.6 V Internal LDO Output Voltage V > 5.6V, I = 60mA 4.5 5.0 5.5 V IN L Maximum Supply Current of Internal LDO V = 12V 60 mA IN V SUPPLY CURRENT IN Shutdown Current (Note 6) EN = EN2 = EN3 = 0, V =12V 50 100 µA IN Operating Current (Note 7) 3 5 mA REFERENCE SECTION Internal Reference Voltage Across specified temperature range 0.8 V Reference Voltage Accuracy Across specified temperature range -1 +1 % PWM CONTROLLER ERROR AMPLIFIERS DC Gain (Note 8) 88 dB Gain-BW Product (Note 8) 15 MHz Slew Rate (Note 8) 2.0 V/µs PWM REGULATOR Switching Frequency (ISL9440, ISL9441) 260 300 340 kHz Maximum Duty Cycle (ISL9440, ISL9441) 93 % Minimum Duty Cycle (ISL9440, ISL9441) 3 % Switching Frequency (ISL9440A) 522 600 678 kHz Maximum Duty Cycle (ISL9440A) 86 % FN6383 Rev 2.00 Page 6 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, T = -40°C to +85°C (Note 8), IN A Typical values are at T = +25°C, unless otherwise specified. (Continued) A PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Minimum Duty Cycle (ISL9440A) 6 % FB Bias Current (Note 8) 50 nA Peak-to-Peak Saw-tooth Amplitude (Note 8) V = 12V 1.6 V IN V = 5.5V 0.667 V IN Ramp Offset 1 V Soft-start Period 1.1 1.7 2.3 ms PWM GATE DRIVER CHANNEL 1, 2 (UGATE1, 2; LGATE 1, 2) (Note 8) Source Current 800 mA Sink Current 2000 mA Upper Drive Pull-Up VCC_5V = 5.0V 4 8  Upper Drive Pull-Down VCC_5V = 5.0V 1.6 3  Lower Drive Pull-Up VCC_5V = 5.0V 4 8  Lower Drive Pull-Down VCC_5V = 5.0V 0.9 2  Rise Time C = 1000pF 18 ns OUT Fall Time C = 1000pF 18 ns OUT PWM GATE DRIVER CHANNEL 3 (UGATE3; LGATE 3) (Note 8) Sink/Source Current 400 mA Upper Drive Pull-Up VCC_5V = 5.0V 8.0 12  Upper Drive Pull-Down VCC_5V = 5.0V 3.2 6.0  Lower Drive Pull-Up VCC_5V = 5.0V 8 12  Lower Drive Pull-Down VCC_5V = 5.0V 1.8 3.5  Rise Time C = 1000pF 18 ns OUT Fall Time C = 1000pF 18 ns OUT LOW DROP OUT CONTROLLER Drive Sink Current LDOFB = 0.76V 50 mA Amplifier Trans-conductance 2 A/V LDOFB Input Leakage Current (Note 8) LDOFB = 0.8V 50 nA ENABLE1, ENABLE2, ENABLE3 THRESHOLD Enable Pin Logic Input Low 0.8 V Enable Pin Logic Input High 2.0 V POWER GOOD MONITORS PGOOD Upper Threshold, PWM 1, 2 and 3 105.5 111 115.5 % PGOOD Lower Threshold, PWM 1, 2 and 3 87 91 96 % PGOOD for Linear Controller 70 75 80 % PGOOD Low Level Voltage I_SINK = 4mA 0.4 V PGOOD Leakage Current PGOOD = 5V 0.025 1 µA PGOOD Rise Time RPULLUP = 10k to 3.3V 0.05 µs FN6383 Rev 2.00 Page 7 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, T = -40°C to +85°C (Note 8), IN A Typical values are at T = +25°C, unless otherwise specified. (Continued) A PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PGOOD Fall Time RPULLUP = 10k to 3.3V 0.05 µs EARLY WARNING FUNCTIONS Undervoltage Lockout Rising (VCC_5V Pin) 4.25 4.45 4.50 V Undervoltage Lockout Falling (VCC_5V Pin) 3.95 4.20 4.40 V Early Warning Voltage Rising (VIN Pin; ISL9440, ISL9440A only) 5.75 5.90 V Early Warning Voltage Falling (VIN Pin; ISL9440, ISL9440A only) 5.30 5.55 V RST RST Voltage Low I_SINK = 4mA 0.4 V RST Leakage Current RST = 5V 0.025 1 µA RST Rise Time RPULLUP = 10k to 3.3V 0.05 µs RST Fall Time RPULLUP = 10k to 3.3V 0.05 µs PGOOD/RST TIMING RISING VIN/VOUT Rising Threshold to PGOOD High Rising 100 200 300 ms PGOOD Rising to RST Rising 1.0 µs PGOOD/RST TIMING FALLING VIN/VOUT Falling Threshold to PGOOD Falling 40 70 100 µs PGOOD Falling to RST Falling 4.5 5.5 6.5 µs OVER VOLTAGE PROTECTION OV Trip Point 118 % OVER CURRENT PROTECTION Overcurrent Threshold (OCSET_) (Note 5) ROCSET = 55k 32 µA Full Scale Input Current (ISEN_) (Note 5) 15 µA Overcurrent Set Voltage (OCSET_) 1.70 1.75 1.80 V OVER-TEMPERATURE Over-Temperature Shutdown 150 °C Over-Temperature Hysteresis 20 °C NOTES: 5. In normal operation, where the device is supplied with voltage on the V pin, the VCC_5V pin provides a 5V output capable of 60mA (min). IN When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the V input pin must be connected to the IN VCC_5V pin. (Refer to the Pin Descriptions section for more details.) 6. This is the total shutdown current with V = 5.6 and 24V. IN 7. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 8. Limits established by characterization and are not production tested. 9. Check Note 5 for VCC_5V and VIN configurations at 5V ±10% input applications. ISL9440, ISL9440A’s PGOOD signal will fall LOW when VIN pin voltage drops below 5.55V (TYP), which results from the early warning detection on VIN pin voltage. ISL9441 doesn’t have an early warning function, so when VIN pin voltage is below 5.55V, PGOOD will not be pulled LOW; ISL9441’s PGOOD only shows the output voltage regulation status. FN6383 Rev 2.00 Page 8 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Pin Descriptions VIN (Pin 4) Use this pin to power the device with an external supply BOOT3, BOOT2, BOOT1 (Pin 20, 26, 31) voltage with a range of 5.6V to 24V. For 5V ±10% operation, These pins are bootstrap pins to provide bias for high side connect this pin to VCC_5V. driver. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. For ISL9440 and ISL9440A, the voltage on this pin is monitored for early warning function. If the voltage on this UGATE3, UGATE2, UGATE1 (Pin 21, 27, 30) pin drop below 5.55V, the PGOOD will be pulled low. RST These pins provide the gate drive for the upper MOSFETs. will be low after PGOOD toggles to low for 5.5µs (TYP). PHASE3, PHASE2, PHASE1 (Pin 19, 25, 32) Refer to Figure 1 for detailed time sequence. These pins are connected to the junction of the upper ISL9441 doesn’t have early warning functions, which means MOSFET’s source, output filter inductor, and lower MOSFET’s the VIN pin voltage is not monitored. drain. VCC_5V (Pin 3) LGATE3, LGATE2, LGATE1 (Pin 22, 28, 29) This pin is the output of the internal 5V linear regulator. This These pins provide the gate drive for the lower MOSFETs. output supplies the bias for the IC, the low side gate drivers, and the external boot circuitry for the high side gate drivers. PGND (Pin 23) The IC may be powered directly from a single 5V (±10%) This pin provides the power ground connection for the lower supply at this pin. When used as a 5V supply input, this pin gate drivers for all PWM1, PWM2 and PWM3. This pin must be externally connected to V . The VCC_5V pin must IN should be connected to the sources of the lower MOSFETs be always decoupled to power ground with a minimum of and the (-) terminals of the external input capacitors. 4.7F ceramic capacitor, placed very close to the pin. FB3, FB2, FB1, LDOFB (Pin 16, 13, 6, 10) EN3, EN2, EN1 (Pin 17, 14, 5) These pins are connected to the feedback resistor divider These pins provide an enable/disable function for their and provide the voltage feedback signals for the respective respective PWM output. The output is enabled when this pin controller. They set the output voltage of the converter. In is floating or pulled HIGH, and disabled when the pin is addition, the PGOOD circuit uses these inputs to monitor the pulled LOW. output voltage status. G4 (Pin 9) ISEN3, ISEN2, ISEN1 (Pin 18, 24, 1) This pin is the open drain output of the linear regulator These pins are used to monitor the voltage drop across the controller. lower MOSFET for current loop feedback and overcurrent protection. OCSET3, OCSET2, OCSET1 (Pin 15, 12, 7) A resistor from this pin to ground sets the overcurrent PGOOD (Pin 2) threshold for the respective PWM. This is an open drain logic output used to indicate the status of the output voltages AND input voltage (voltage on VIN pin; RST (Pin 8) early warning for ISL9440 and ISL9440A). This pin is pulled Reset pulse output. This pin outputs a logic LOW signal after low when either of the three PWM outputs is not within 10% PGOOD toggles to low for 5.5µs (TYP). It can be used to of the respective nominal voltage, or if the linear controller reset system. output is less than 75% of it’s nominal value, or VIN pin Refer to Figure 1 for detailed time sequence of ISL9440 and voltage drops below 5.55V. ISL9440A with early warning function. ISL9440 and ISL9440A’s PGOOD pin also indicates the VIN ISL9441 doesn’t have early warning functions, which means pin status for early warning function. If the voltage on VIN pin the VIN pin voltage is not monitored. But RST still output drops below 5.55V, this pin will be pulled low. LOW signal following PGOOD LOW. SGND (Pin 11) This is the small-signal ground, common to all 4 controllers, and are suggested to be routed separately from the high current ground (PGND). In case of one whole solid ground and no noisy current going through around chip, SGND and PGND can be tied to the same ground copper plane. All voltage levels are measured with respect to this pin. A small ceramic capacitor should be connected right next to this pin for noise decoupling. FN6383 Rev 2.00 Page 9 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 8 VIN = 5.5V FALLING/ VIN/VOUT 7 VOUT 1-4 OUT OF REGULATION 6 VVININ = = 5 5.5.5VV R RISISININGG// E (V) 5 VVOOUUTT 1 1-4-4 I NIN R REEGGUULLAATTIOIONN G 4 PGOOD TYP = 200ms RST A T L O 3 V MAX = 100µs 2.4V 2 MAX = 2µs 1 0.4V 0 0 5 10 15 20 25 MAX = 6.5µs TIME (NOT TO SCALE) FIGURE 1. PGOOD AND RST TIMING Typical Performance Curves (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, V = 12V Unless Otherwise Noted.) IN 2.55 95 2.54 90 2.53 V) GE ( 2.52 %) 85 OLTA 22..5501 NCY ( 80 V E T 2.49 CI 75 UTPU 2.48 EFFI 70 O 2.47 2.46 65 2.45 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 2. PWM1 LOAD REGULATION FIGURE 3. PWM1 EFFICIENCY vs LOAD (V = 2.5V), O V =12V, 1 DUAL SO-8 MOSFET (IRF7907) FOR IN UPPER AND LOWER MOSFETS 1.55 90 1.54 1.53 85 V) AGE ( 11..5512 Y (%) 80 OLT 1.50 NC 75 T V 1.49 CIE U FI TP 1.48 EF 70 U O 1.47 65 1.46 1.45 60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 4. PWM2 LOAD REGULATION FIGURE 5. PWM2 EFFICIENCY vs LOAD (V = 1.5V), O V =12V, 1 DUAL SO-8 MOSFET (IRF7907) FOR IN UPPER AND LOWER MOSFETS FN6383 Rev 2.00 Page 10 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Typical Performance Curves (Continued) (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, V = 12V Unless Otherwise Noted.) IN 5.10 100 5.10 95 5.09 V) 90 E ( 5.09 %) AG 5.08 Y ( 85 T C UT VOL 55..0078 FICIEN 7850 P F T 5.07 E U 70 O 5.06 65 5.06 5.05 60 0.0 1.0 2.0 3.0 4.0 0.0 1.0 2.0 3.0 4.0 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 6. PWM3 LOAD REGULATION FIGURE 7. PWM3 EFFICIENCY vs LOAD (V = 5V), V =12V, O IN 1 DUAL SO-8 MOSFET (IRF7907) FOR UPPER AND LOWER MOSFETS VOUT1 50mV/DIV, AC COUPLED VOUT3 1V/DIV VOUT2 50mV/DIV, AC COUPLED VOUT4 (LDO) 1V/DIV VOUT3 50mV/DIV, AC COUPLED VOUT1 1V/DIV VOUT2 1V/DIV VOUT4 50mV/DIV, AC COUPLED 0.2ms/DIV 5µs/DIV FIGURE 8. PWM SOFT-START WAVEFORMS FIGURE 9. OUTPUT RIPPLE UNDER MAXIMUM LOAD (I = I = 6A, I = 2A, I = 0.5A) O1 O1 O3 O4 VIN, 1V/DIV, CH1 VIN, 1V/DIV, CH1 RST, 5V/DIV, CH3 CH1 CH3 RST, 5V/DIV, CH3 CH3 PGOOD, 5V/DIV, CH4 PGOOD, 5V/DIV, CH4 CH4 CH4 CH1 100µs/DIV 10µs/DIV FIGURE 10. VIN FALLING TO PGOOD FALLING DELAY TIME FIGURE 11. PGOOD FALLING TO RST FALLING FN6383 Rev 2.00 Page 11 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Typical Performance Curves (Continued) (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, V = 12V Unless Otherwise Noted.) IN VOUT1, 100mV/DIV, 0A to 6A, 1.6A/µs VIN, 1V/DIV, CH1 VOUT2, 100mV/DIV, 0A to 6A, 1.6A/µs RST, 1V/DIV, CH3 CH3 VOUT3, 100mV/DIV, 0A to 2A, 1A/µs PGOOD, 5V/DIV, CH4 VOUT4 (LDO), 100mV/DIV, 0A to 0.5A, 1A/µs CH4 CH1 500µs/DIV 500ns/DIV FIGURE 12. PGOOD RISING TO RST RISING FIGURE 13. OUTPUT RIPPLE UNDER TRANSIENT LOAD PWM1, 5V/DIV Vo1, 1V/DIV PWM2, 5V/DIV Vo2, 1V/DIV Vo3, 1V/DIV PWM3, 5V/DIV 5ms/DIV 1µs/DIV FIGURE 14. THREE CHANNEL HARD-SHORT OCP AT THE FIGURE 15. PHASE NODE PWM WAVEFORMS, V = 24V IN SAME TIME FN6383 Rev 2.00 Page 12 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Functional Description soft-start is done and all the four outputs are up and in regulations. General Description Output Voltage Programming The ISL9440, ISL9440A and ISL9441 are integrate control circuits for three synchronous buck converters and one linear The ISL9440, ISL9440A and ISL9441 use a precision internal controller. The three synchronous bucks operate out of phase reference voltage to set the output voltage. Based on this to substantially reduce the input ripple and thus reduce the internal reference, the output voltage can thus be set from 0.8V input filter requirements. The chip has 3 control lines (EN1, up to a level determined by the input voltage, the maximum EN2 and EN3), which provide independent control for each of duty cycle, and the conversion efficiency of the circuit. the synchronous buck outputs. A resistive divider from the output to ground sets the output The buck PWM controllers employ free-running frequency of voltage of either PWM channel. The center point of the divider 300kHz (ISL9440 and ISL9441) and 600kHz (ISL9440A). The shall be connected to FBx pin. The output voltage value is current mode control scheme with an input voltage determined by Equation 1. feed-forward ramp input to the modulator provides an excellent V = 0.8VR-----1-----+-----R-----2-- (EQ. 1) rejection of input voltage variations and provides simplified OUTx  R2  loop compensations. where R1 is the top resistor of the feedback divider network The linear controller can drive either a PNP or PFET to provide and R2 is the resistor connected from FBx to ground. ultra low-dropout regulation with programmable voltages. Out-of-Phase Operation Internal 5V Linear Regulator (VCC_5V) To reduce input ripple current, Channel 1 and Channel 2 operate All ISL9440, ISL9440A and ISL9441 functions are internally 180° out-of-phase, Channel 3 keeps 0 phase degree with powered from an on-chip, low dropout 5V regulator. The Channel 1. Channel 1 and Channel 2 typically output higher load maximum regulator input voltage is 24V. Bypass the regulator’s compared to Channel 3 because of their stronger drivers. This output (VCC_5V) with a 4.7µF capacitor to ground. The reduces the input capacitor ripple current requirements, reduces dropout voltage for this LDO is typically 600mV, so when VIN is power supply-induced noise, and improves EMI. This effectively greater than 5.6V, VCC_5V is typically 5V. The ISL9440, helps to lower component cost, save board space and reduce ISL9440A and ISL9441 also employ an undervoltage lockout EMI. circuit that disables both regulators when VCC_5V falls below Triple PWMs typically operate in-phase and turn on both upper 4.4V. FETs at the same time. The input capacitor must then support the The internal LDO can source over 60mA to supply the IC, instantaneous current requirements of the three switching power the low side gate drivers and charge the external boot regulators simultaneously, resulting in increased ripple voltage capacitor. When driving large FETs especially at 300kHz and current. The higher RMS ripple current lowers the efficiency (ISL9440, ISL9441)/600kHz (ISL9440A) frequency, little or no due to the power loss associated with the ESR of the input regulator current may be available for external loads. capacitor. This typically requires more low-ESR capacitors in parallel to minimize the input voltage ripple and ESR-related For example, a single large FET with 15nC total gate charge losses, or to meet the required ripple current rating. requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also, at higher input voltages with larger FETs, the power With synchronized out-of-phase operation, the high-side dissipation across the internal 5V will increase. Excessive MOSFETs turn on 180° out-of-phase. The instantaneous input dissipation across this regulator must be avoided to prevent current peaks of both regulators no longer overlap, resulting in junction temperature rise. Larger FETs can be used with 5V reduced RMS ripple current and input voltage ripple. This reduces ±10% input applications. The thermal overload protection the required input capacitor ripple current rating, allowing fewer or circuit will be triggered, if the VCC_5V output is short-circuit. less expensive capacitors, and reducing the shielding Connect VCC_5V to VIN for 5V ±10% input applications. requirements for EMI. The typical operating curves show the synchronized 180° out-of-phase operation. Digital Enable Signals The typical applications for the ISL9440, ISL9440A and Input Voltage Range ISL9441 are using digital sequencing controllers for the power The ISL9440, ISL9440A and ISL9441 are designed to operate rails. Using a digital enable rather than an analog soft-start from input supplies ranging from 4.5V to 24V. provides a well controlled method for sequencing up and down For 5V ±10% input applications, ISL9441 is suggested. The on the power rails. reason is that VIN and VCC_5V Pin should be tied together for Soft-Start Operation this input application. The early warning function will pull The ISL9440, ISL9440A and ISL9441 have a fixed soft-start PGOOD and RST low for ISL9440 and ISL9440A. ISL9441 time, 1.7ms (TYP). PGOOD will not toggle to high until has not been implemented with early warning function. FN6383 Rev 2.00 Page 13 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 The input voltage range can be effectively limited by the available maximum duty cycle (D = 93% for ISL9440 and MAX VIN ISL9441, D = 86% for ISL9440A). VCC_5V MAX V +V V = -----O----U----T--------------d----1-+V –V (EQ. 2) INmin  0.93  d2 d1 BOOT where, Vd1 = Sum of the parasitic voltage drops in the inductor UGATE discharge path, including the lower FET, inductor and PC PHASE board. Vd2 = Sum of the voltage drops in the charging path, including the upper FET, inductor and PC board resistances. ISL9440, ISL9440A, ISL9441 The maximum input voltage and minimum output voltage is limited by the minimum on-time (t ). ON(min) FIGURE 16. V V -----------------------O----U----T--------------------- At start-up, the low-side MOSFET turns on and forces PHASE INmax t 300kHz (EQ. 3) ONmin to ground in order to charge the BOOT capacitor to 5V. After the low-side MOSFET turns off, the high-side MOSFET is where, t = 30ns ON(min) turned on by closing an internal switch between BOOT and Gate Control Logic UGATE. This provides the necessary gate-to-source voltage to The gate control logic translates generated PWM signals into gate turn on the upper MOSFET, an action that boosts the 5V gate drive signals providing amplification, level shifting and shoot- drive signal above VIN. The current required to drive the upper through protection. The gate drivers have some circuitry that MOSFET is drawn from the internal 5V regulator. helps optimize the IC performance over a wide range of Adaptive Dead Time operational conditions. As MOSFET switching times can vary The ISL9440, ISL9440A and ISL9441 incorporate an adaptive dramatically from type to type and with input voltage, the gate dead time algorithm on the synchronous buck PWM controllers control logic provides adaptive dead time by monitoring real gate that optimizes operation with varying MOSFET conditions. This waveforms of both the upper and the lower MOSFETs. Shoot- algorithm provides an approximately 20ns of dead time through control logic provides a 20ns dead-time to ensure that between switching the upper and lower MOSFET’s. This dead both the upper and lower MOSFETs will not turn on time is adaptive and allows operation with different MOSFET’s simultaneously and cause a shoot-through condition. without having to externally adjust the dead time using a Gate Drivers resistor or capacitor. During turn-off of the lower MOSFET, the The low-side gate driver is supplied from VCC_5V and provides LGATE voltage is monitored until it reaches a 1V threshold, at a peak sink current of 2A/2A/200mA and source current of which time the UGATE is released to rise. Adaptive dead time 800mA/800mA/400mA for Channels 1/2/3 respectively. The circuitry monitors the upper MOSFET gate voltage during high-side gate driver is also capable of delivering the same UGATE turn-off. Once the upper MOSFET gate-to-source current as those in low-side gate driver. Gate-drive voltages for voltage has dropped below a threshold of 1V, the LGATE is the upper N-Channel MOSFET are generated by the flying allowed to rise. capacitor boot circuit. A boot capacitor connected from the Internal Bootstrap Diode BOOT pin to the PHASE node provides power to the high side The ISL9440, ISL9440A and ISL9441 have integrated MOSFET driver. To limit the peak current in the IC, an external bootstrap diodes to help reduce total cost and reduce layout resistor may be placed between the UGATE pin and the gate of complexity. Simply adding an external capacitor across the the external MOSFET. This small series resistor also damps any BOOT and PHASE pins completes the bootstrap circuit. The oscillations caused by the resonant tank of the parasitic bootstrap capacitor must have a maximum voltage rating inductances in the traces of the board and the FET’s input above the maximum battery voltage plus 5V. The bootstrap capacitance. capacitor can be chosen from Equation 4. Q C -------G-----A----T---E----- (EQ. 4) BOOT V BOOT Where Q is the amount of gate charge required to fully GATE charge the gate of the upper MOSFET. The V term is BOOT defined as the allowable droop in the rail of the upper drive. FN6383 Rev 2.00 Page 14 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 As an example, suppose an upper MOSFET has a gate charge Overvoltage Protection (QGATE) of 25nC at 5V and also assume the droop in the drive All switching controllers within the ISL9440, ISL9440A and voltage over a PWM cycle is 200mV. One will find that a ISL9441 have fixed overvoltage set points. The overvoltage set bootstrap capacitance of at least 0.125µF is required. The next point is set at 118% of the output voltage set by the feedback larger standard value capacitance is 0.22µF. A good quality resistors. In the case of an overvoltage event, the IC will ceramic capacitor is recommended. attempt to bring the output voltage back into regulation by keeping the upper MOSFET turned off and modulating the Protection Circuits lower MOSFET for 2 consecutive PWM cycles. If the The converter output is monitored and protected against overvoltage condition has not been corrected in 2 cycles, the overload, short circuit and undervoltage conditions. A ISL9440, ISL9440A and ISL9441 will turn on the lower sustained overload on the output sets the PGOOD low and MOSFET until the overvoltage has been cleared, or the power initiates hiccup mode. path is interrupted by opening a fuse. Undervoltage Lockout Over-Temperature Protection The ISL9440, ISL9440A and ISL9441 include UVLO protection The IC incorporates an over-temperature protection circuit that will keep the devices in a reset condition until a proper that shuts the IC down when a die temperature of +150°C is operating voltage is applied and that will also shut down the reached. Normal operation resumes when the die ISL9440, ISL9440A and ISL9441 if the operating voltage drops temperatures drops below +130°C through the initiation of a below a pre-defined value. All controllers are disabled when full soft-start cycle. UVLO is asserted. When UVLO is asserted, PGOOD will be Feedback Loop Compensation valid and de-asserted. To reduce the number of external components and to simplify Overcurrent Protection the process of determining compensation components, all PWM All the PWM controllers use the lower MOSFET’s controllers have internally compensated error amplifiers. To on-resistance, rDS(ON), to monitor the current in the converter. make internal compensation possible several design measures The sensed voltage drop is compared with a threshold set by a were taken. resistor connected from the OCSETx pin to ground. First, the ramp signal applied to the PWM comparator is 7R  R = -------------------------C----S-------------- (EQ. 5) proportional to the input voltage provided via the VIN pin. This OCSET I r  OC DSON keeps the modulator gain constant with variation in the input voltage. Second, the load current proportional signal is derived where, I is the desired overcurrent protection threshold, and OC from the voltage drop across the lower MOSFET during the R is a value of the current sense resistor connected to the CS PWM time interval and is subtracted from the amplified error ISENx pin. If an overcurrent is detected for 2 consecutive clock signal on the comparator input. This creates an internal current cycles then the IC enters a hiccup mode by turning off the gate control loop. The resistor connected to the ISEN pin sets the drivers and entering into soft-start. The IC will cycle 4 times gain in the current feedback loop. The following expression through soft-start before trying to restart. The IC will continue to estimates the required value of the current sense resistor cycle through soft-start until the overcurrent condition is depending on the maximum operating load current and the removed. Hiccup mode is active during soft-start so care must value of the MOSFET’s r . be taken to ensure that the peak inductor current does not DS(ON) exceed the overcurrent threshold during soft-start. I r  R -----M-----A----X-----------D----S------O----N-------- (EQ. 6) CS 15A Because of the nature of this current sensing technique, and to accommodate a wide range of rDS(ON) variations, the value of Choosing RCS to provide 15µA of current to the current sample the overcurrent threshold should represent an overload current and hold circuitry is recommended but values down to 2µA and about 150% to 180% of the maximum operating current. If up to 100µA can be used. The higher sampling current will help more accurate current protection is desired, place a current to stabilize the loop. sense resistor in series with the lower MOSFET source. Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency determined by the load. 1 FPO = 2------------R-------------C-------- (EQ. 7) O O where R is load resistance and C is load capacitance. For O O this type of modulator, a Type 2 compensation circuit is usually sufficient. FN6383 Rev 2.00 Page 15 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Figure 17 shows a Type 2 amplifier and its response along with placed at the base of the PNP (or gate of the PFET), as a the responses of the current mode modulator and the capacitor from emitter to base (source to gate of a PFET). converter. The Type 2 amplifier, in addition to the pole at origin, Better load transient response is achieved however, if the has a zero-pole pair that causes a flat gain region at dominant pole is placed at the output, with a capacitor to frequencies in between the zero and the pole. ground at the output of the regulator. 1 Under no-load conditions, leakage currents from the pass F = ------------------------------- = 6kHz Z 2R2C1 (EQ. 8) transistors supply the output capacitors, even when the transistor is off. Generally this is not a problem since the 1 feedback resistor drains the excess charge. However, charge FP = 2------------R-----1-------C-----2-- = 600kHz (EQ. 9) may build up on the output capacitor making VLDO rise above its set point. Care must be taken to insure that the feedback resistor’s current exceeds the pass transistors leakage current C2 over the entire temperature range. R2 C1 CONVERTER The linear regulator output can be supplied by the output of R1 one of the PWMs. When using a PFET, the output of the linear EA regulator will track the PWM supply after the PWM output rises TYPE 2 EA to a voltage greater than the threshold of the PFET pass device. The voltage differential between the PWM and the GM = 17.5dB linear output will be the load current times the r . DS(ON) MODULATOR GEA = 18dB FZ FP 60 FPO FC 50 K N SI R A) 40 Em FIGURE 17. FEEDBACK LOOP COMPENSATION MPLIFIRENT ( 30 AR OR CU 20 The zero frequency, the amplifier high-frequency gain, and the RR E modulator gain are chosen to satisfy most typical applications. 10 The crossover frequency will appear at the point where the 0 modulator attenuation equals the amplifier high frequency 0.79 0.8 0.81 0.82 0.83 0.84 0.85 gain. The only task that the system designer has to complete is FEEDBACK VOLTAGE (V) to specify the output filter capacitors to position the load main FIGURE 18. LINEAR CONTROLLER GAIN pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase Base-Drive Noise Reduction margin is easily achieved due to zero-pole pair phase ‘boost’. The high-impedance base driver is susceptible to system Conditional stability may occur only when the main load pole is noise, especially when the linear regulator is lightly loaded. positioned too much to the left side on the frequency axis due Capacitively coupled switching noise or inductively coupled to excessive output filter capacitance. In this case, the ESR EMI onto the base drive causes fluctuations in the base zero placed within the 1.2kHz to 30kHz range gives some current, which appear as noise on the linear regulator’s output. additional phase ‘boost’. Some phase boost can also be Keep the base drive traces away from the step-down achieved by connecting capacitor C in parallel with the upper converter, and as short as possible, to minimize noise Z resistor R of the divider that sets the output voltage value. coupling. A resistor in series with the gate drivers reduces the 1 Please refer to “Output Inductor Selection” on page18 and switching noise generated by PWM. Additionally, a bypass “Input Capacitor Selection” on page18 for further details. capacitor may be placed across the base-to-emitter resistor. This bypass capacitor, in addition to the transistor’s input Linear Regulator capacitor, could bring in a second pole that will de-stabilize the The linear regulator controller is a trans-conductance amplifier linear regulator. Therefore, the stability requirements determine with a nominal gain of 2A/V. The N-channel MOSFET output the maximum base-to-emitter capacitance. device can sink a minimum of 50mA. The reference voltage is 0.8V. With zero volts differential at it’s input, the controller sinks Layout Guidelines 21mA of current. An external PNP transistor or PFET pass Careful attention to layout requirements is necessary for element can be used. The dominant pole for the loop can be successful implementation of an ISL9440, ISL9440A and FN6383 Rev 2.00 Page 16 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 ISL9441 based DC/DC converter. The ISL9440, ISL9440A and PHASE node. Since the phase nodes are subjected to very ISL9441 switch at a very high frequency and therefore the high dv/dt voltages, the stray capacitor formed between switching times are very short. At these switching frequencies, these islands and the surrounding circuitry will tend to even the shortest trace has significant impedance. Also, the couple switching noise. peak gate drive current rises significantly in extremely short 10. Route all high speed switching nodes away from the control time. Transition speed of the current from one device to circuitry. another causes voltage spikes across the interconnecting 11. Create a separate small analog ground plane near the IC. impedances and parasitic circuit elements. These voltage Connect the SGND pin to this plane. All small signal spikes can degrade efficiency, generate EMI, increase device grounding paths including feedback resistors, current limit overvoltage stress and ringing. Careful component selection setting resistors and ENx pull-down resistors should be and proper PC board layout minimizes the magnitude of these connected to this SGND plane. voltage spikes. 12. Ensure the feedback connection to the output capacitor is There are three sets of critical components in a DC/DC short and direct. converter using the ISL9440, ISL9440A and ISL9441: The Component Selection Guidelines controller, the switching power components and the small signal components. The switching power components are the MOSFET Considerations most critical from a layout point of view because they switch a The logic level MOSFETs are chosen for optimum efficiency large amount of energy so they tend to generate a large given the potentially wide input voltage range and output power amount of noise. The critical small signal components are requirements. Two N-Channel MOSFETs are used in each of those connected to sensitive nodes or those supplying critical the synchronous-rectified buck converters for the 3 PWM bias currents. A multi-layer printed circuit board is outputs. These MOSFETs should be selected based upon recommended. r , gate supply requirements, and thermal management DS(ON) Layout Considerations considerations. 1. The Input capacitors, Upper FET, Lower FET, Inductor and The power dissipation includes two loss components; Output capacitor should be placed first. Isolate these power conduction loss and switching loss. These losses are components on the topside of the board with their ground distributed between the upper and lower MOSFETs according terminals adjacent to one another. Place the input high to duty cycle (see the following equations). The conduction frequency decoupling ceramic capacitor very close to the losses are the main component of power dissipation for the MOSFETs. lower MOSFETs. Only the upper MOSFET has significant 2. Use separate ground planes for power ground and small switching losses, since the lower device turns on and off into signal ground. Connect the SGND and PGND together near zero voltage. The equations assume linear voltage- close to the IC. Do not connect them together anywhere current transitions and do not model power loss due to the else. reverse-recovery of the lower MOSFET’s body diode. 3. The loop formed by Input capacitor, the top FET and the 2 I r V  I V t F  bottom FET must be kept as small as possible. P = -----O---------------D----S------O----N----------------O----U----T-----+-----O--------------I-N-----------S----W--------------S----W------- UPPER V 2 4. Ensure the current paths from the input capacitor to the IN (EQ. 10) MOSFET, to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 2 I r V –V  5. Place The PWM controller IC close to lower FET. The PLOWER = -----O---------------D----S------O----N-V---------------I--N--------------O----U----T----- (EQ. 11) IN LGATE connection should be short and wide. The IC can be best placed over a quiet ground area. Avoid switching A large gate-charge increases the switching time, tSW, which ground loop current in this area. increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature 6. Place VCC_5V bypass capacitor very close to VCC_5V pin at high ambient temperature by calculating the temperature of the IC and connect its ground to the PGND plane. rise according to package thermal-resistance specifications. 7. Place the gate drive components BOOT diode and BOOT capacitors together near controller IC 8. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. Use copper filled polygons or wide but short trace to connect the junction of upper FET, Lower FET and output inductor. Also keep the PHASE node connection to the IC short. Do not unnecessarily oversize the copper islands for FN6383 Rev 2.00 Page 17 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Output Capacitor Selection small-case electrolytic capacitors perform better than a single large-case capacitor. The output capacitors for each output have unique requirements. In general, the output capacitors should be The stability requirement on the selection of the output selected to meet the dynamic regulation requirements capacitor is that the ‘ESR zero’ (f ) be between 1.2kHz and Z including ripple voltage and load transients. Selection of output 30kHz. This range is set by an internal, single compensation capacitors is also dependent on the output inductor, so some zero at 6kHz. The ESR zero can be a factor of five on either inductor analysis is required to select the output capacitors. side of the internal zero and still contribute to increased phase One of the parameters limiting the converter’s response to a margin of the control loop. Therefore: load transient is the time required for the inductor current to 1 C = ------------------------------------- slew to it’s new level. The ISL9440, ISL9440A and ISL9441 will OUT 2ESRfZ (EQ. 14) provide either 0% or maximum duty cycle in response to a load In conclusion, the output capacitors must meet three criteria: transient. 1. They must have sufficient bulk capacitance to sustain the The response time is the time interval required to slew the output voltage during a load transient while the output inductor current from an initial current value to the load current inductor current is slewing to the value of the load transient. level. During this interval the difference between the inductor 2. The ESR must be sufficiently low to meet the desired output current and the transient current level must be supplied by the voltage ripple due to the output inductor current. output capacitor(s). Minimizing the response time can minimize 3. The ESR zero should be placed, in a rather large range, to the output capacitance required. Also, if the load transient rise provide additional phase margin. time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output The recommended output capacitor value for the ISL9440, capacitor. ISL9440A and ISL9441 is between 150F to 680F, to meet stability criteria with external compensation. Use of aluminum The maximum capacitor value required to provide the full, electrolytic (POSCAP) or tantalum type capacitors is rising step, transient load current during the response time of recommended. Use of low ESR ceramic capacitors is possible the inductor is: but would take more rigorous loop analysis to ensure stability. 2 L I  C = -----------------O-----------T----R----A----N------------------- (EQ. 12) Output Inductor Selection OUT 2V –V DV  IN O OUT The PWM converters require output inductors. The output where, C is the output capacitor(s) required, L is the inductor is selected to meet the output voltage ripple OUT O output inductor, I is the transient load current step, V is requirements. The inductor value determines the converter’s TRAN IN the input voltage, V is output voltage, and DV is the drop ripple current and the ripple voltage is a function of the ripple O OUT in output voltage allowed during the load transient. current and output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the High frequency capacitors initially supply the transient current ripple current is approximated by Equation 15: and slow the load rate-of-change seen by the bulk capacitors. V –V V  The bulk filter capacitor values are generally determined by the IN OUT OUT I = ---------------------------------------------------------- (EQ. 15) ESR (Equivalent Series Resistance) and voltage rating L fSLVIN requirements as well as actual capacitance requirements. For the ISL9440, ISL9440A and ISL9441, inductor values The output voltage ripple is due to the inductor ripple current between 1.2µH to 10µH are recommended when using the and the ESR of the output capacitors as defined by: Typical Application Schematic. Other values can be used but a VRIPPLE = ILESR (EQ. 13) thorough stability study should be done. A smaller volume cap in combination with big inductor will be more prone to stability where, I is calculated in the “Output Inductor Selection” on issues. One way to get more phase margin is to add a small L page18. cap (typically 1nF to 10nF) in parallel with the upper resistor of the voltage sense resistor divider. For example, in ISL9440, High frequency decoupling capacitors should be placed as ISL9440A Application Schematic, the 5V output has a 15µH close to the power pins of the load as physically possible. Be inductor with which the system phase margin is less than 45°. careful not to add inductance in the circuit board wiring that An resistor and capacitor are added with the upper resistor of could cancel the usefulness of these low inductance the divider to get more phase margin. components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Input Capacitor Selection The important parameters for the bulk input capacitor(s) are Use only specialized low-ESR capacitors intended for switching- the voltage rating and the RMS current rating. For reliable regulator applications at 300kHz (ISL9440/ISL9441)/600kHz operation, select bulk input capacitors with voltage and current (ISL9440A) for the bulk capacitors. In most cases, multiple ratings above the maximum input voltage and largest RMS FN6383 Rev 2.00 Page 18 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum 5.0 input voltage and 1.5 times is a conservative guideline. The 4.5 AC RMS Input current varies with the load. The total RMS 4.0 current supplied by the input capacitance is: T IN PHASE N 3.5 E IRMS = IR2MS1+IR2MS2 (EQ. 16) URR 3.0 C S 2.5 M OUT OF PHASE where, R 2.0 T U IRMSx = DC–DC2IO (EQ. 17) INP 1.5 3.3V 5V 1.0 DC is duty cycle of the respective PWM. 0.5 Depending on the specifics of the input power and its 0 0 1 2 3 4 5 impedance, most (or all) of this current is supplied by the 3.3V AND 5V LOAD CURRENT input capacitor(s). Figure 19 shows the advantage of having FIGURE 19. INPUT RMS CURRENT vs LOAD the PWM converters operating out of phase. If the converters were operating in phase, the combined RMS Use a mix of input bypass capacitors to control the voltage current would be the algebraic sum, which is a much larger ripple across the MOSFETs. Use ceramic capacitors for the value as shown. The combined out-of-phase current is the high frequency decoupling and bulk capacitors to supply the square root of the sum of the square of the individual RMS current. Small ceramic capacitors can be placed very reflected currents and is significantly less than the combined close to the upper MOSFET to suppress the voltage induced in-phase current. in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON® series offer low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge- current at power-up. The TPS series available from AVX is surge current tested. © Copyright Intersil Americas LLC 2007-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6383 Rev 2.00 Page 19 of 20 February 9, 2015

ISL9440, ISL9440A, ISL9441 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 A 28X 0.50 6 B 25 32 PIN #1 INDEX AREA 6 PIN 1 24 1 INDEX AREA 0 5.0 3 .30 ± 0 . 15 17 8 (4X) 0.15 16 9 0.10MC AB + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( 28X 0 . 5 ) SIDE VIEW ( 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6383 Rev 2.00 Page 20 of 20 February 9, 2015