ISL85001 FN6769 1A Standard Buck PWM Regulator Rev.3.00 Apr 14, 2017 The ISL85001 is a high-performance, simple output controller Features that provides a single, high frequency power solution for a variety of point-of-load applications. The ISL85001 integrates a • Standard buck controller with integrated switching power 1A standard buck PWM controller and switching MOSFET. MOSFET • Integrated boot diode The PWM controller in the ISL85001 drives an internal switching N-channel power MOSFET and requires an external • Input voltage range Schottky diode to generate an output voltage from 0.6V to - Fixed 5V ±10% 19V. The integrated power switch is optimized for excellent - Variable 5.5V to 25V thermal performance for up to 1A of output current. The standard buck input voltage range supports a fixed 5V or • PWM output voltage adjustable from 0.6V to 19V with variable 5.5V to 25V range. The PWM regulator switches at a continuous output current up to 1A fixed frequency of 500kHz and utilizes simple voltage mode • ±1% VFB tolerance control with input voltage feed-forward to provide flexibility in • Voltage mode control with voltage feed-forward component selection and minimize solution size. Protection features include overcurrent, undervoltage and thermal • Fixed 500kHz switching frequency overload protection integrated into the IC. The ISL85001 • Externally adjustable soft-start time power-good signal output indicates loss of regulation on the PWM output. • Output undervoltage protection • Enable inputs ISL85001 is available in a small 4mmx3mm Dual Flat No-Lead (DFN) package. • PGOOD output Related Literature • Overcurrent protection • Thermal overload protection • For a full list of related documents, visit our website • Internal 5V LDO regulator - ISL85001 product page • Pb-free (RoHS compliant) Applications • General purpose • WLAN Cards-PCMCIA, Cardbus32, MiniPCI cards-compact flash cards • Hand-held instruments • LCD panel • Set-top box FN6769 Rev.3.00 Page 1 of 16 Apr 14, 2017

ISL85001 Typical Application Schematic R3 C3 301 100pF VOUT R4 C2 R101k 3.16k 2.2nF C1 R2 10pF C5 31k 0.1µF MP S B O S F C VIN 5.5V TO 25V C9 10µF EN L 22µH ISL85001 PHASE VOUT = 2.5V PG C10 C11 BOOT 0.1µF D 47µF B340LB GND VDD C13 1µF FIGURE 1. VIN RANGE FROM 5.5V TO 25V FN6769 Rev.3.00 Page 2 of 16 Apr 14, 2017

ISL85001 Functional Block Diagram P T M O B O O F C B VDD VDD SOFT-START VIN (x2) CONTROL 30µA OC VOLTAGE - PWM MONITOR MONITOR + - EA + SS 0.6V GATE REFERENCE RAMP VIN DRIVE GENERATOR PHASE (x2) FAULT EN MONITOR THERMAL MONITOR OSCILLATOR +150°C OC MONITOR POR VIN LDO POWER-ON GND VDD RESET MONITOR PG EPAD GND FIGURE 2. FUNCTIONAL BLOCK DIAGRAM Pin Configuration ISL85001 (12 LD 4x3 DFN) TOP VIEW FB 1 12 VIN COMP 2 11 VIN SS 3 10 PHASE GND EN 4 9 PHASE PG 5 8 BOOT GND 6 7 VDD FN6769 Rev.3.00 Page 3 of 16 Apr 14, 2017

ISL85001 Pin Descriptions PIN SYMBOL NUMBER DESCRIPTION FB 1 The standard buck regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. With a COMP 2 properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. Connecting an AC network across COMP and FB provides loop compensation to the amplifier. In addition, the PWM regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage. SS 3 Program pin for soft-start duration. A regulated 30µA pull-up current source charges a capacitor connected from the pin to GND. The output voltage of the converter follows the ramping voltage on the SS pin. EN 4 PWM controller enable input. The PWM converter output is held off when the pin is pulled to ground. When the voltage on this pin rises above 1.7V, the chip is enabled. PG 5 PWM converter power-good output. Open drain logic output that is pulled to ground when the output voltage is outside regulation limits. Connect a 100kΩ resistor from this pin to VDD. Pin is low when the buck regulator output voltage is not within 10% of the respective nominal voltage, or during the soft-start interval. Pin is high impedance when the output is within regulation. GND 6 Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to GND and soldered to the PCB. All voltage levels are measured with respect to this pin. VDD 7 Internal 5V linear regulator output provides bias to all the internal control logic. The ISL85001 may be powered directly from a 5V (±10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VDD pin must always be decoupled to GND with a ceramic bypass capacitor (minimum 1µF) located close to the pin. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 5.5V to 25V Connect the input supply to the VIN pin only. The VDD pin will provide a 5V output from the internal linear regulator. 5V ±10% Connect the input supply to the VIN and VDD pins. BOOT 8 Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn and hold on the internal N-channel MOSFET. Connect an external capacitor from this pin to PHASE. PHASE 9, 10 Switch node connections to internal power MOSFET source, external output inductor and external diode cathode. VIN 11, 12 The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF). Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes1, 2, 3) MARKING (°C) (RoHS COMPLIANT) DWG. # ISL85001IRZ 501Z -40 to +85 12 Ld DFN L12.4x3 ISL85001EVAL1Z Evaluation Board NOTES: 1. Add “-T” suffix for 6k unit tape and reel option. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85001. For more information on MSL please see tech brief TB363. FN6769 Rev.3.00 Page 4 of 16 Apr 14, 2017

ISL85001 Absolute Maximum Ratings Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 26V Thermal Resistance JA (°C/W) JC (°C/W) BOOT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V DFN Package (Notes4, 5). . . . . . . . . . . . . . 39 3 BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.03V to 6V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C VDD, FB, EN, COMP, PG, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 25V Load Current Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85° CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Typical specifications are measured at the following conditions: TA = -40°C to +85°C. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note8) TYP (Note8) UNIT SUPPLY VOLTAGE VIN Voltage Range VIN 5.5 - 25 V VIN connected to VDD 4.5 5.0 5.5 V VIN Operating Supply Current IOP (Note6) - 2.0 2.5 mA VIN Shutdown Supply Current ISD VIN = 15V, EN = GND - 80 100 µA POWER-ON RESET VDD POR Threshold Rising Edge 4.00 4.15 4.30 V Hysteresis - 275 - mV INTERNAL VDD LDO VDD Output Voltage Range VIN = 5.5V to 25V, IVDD = 0mA to 30mA 4.50 5.00 5.50 V REFERENCE Reference Voltage VFB VIN = 5.5V to 25V, IREF = 0 0.594 0.600 0.606 V STANDARD BUCK PWM REGULATOR FB Line Regulation IOUT = 0mA, VIN = 5.5V to 25V -0.05 - 0.05 % FB Leakage Current VFB = 0.6V -50 0 50 nA OSCILLATOR AND PWM MODULATOR Nominal Switching Frequency fSW 450 500 550 kHz Modulator Gain AMOD VIN = 12V (AMOD = 8/VIN) 0.65 0.75 0.95 V/V Peak-to-Peak Sawtooth Amplitude VRAMP VIN = 12V (VP-P = VIN/8) - 1.3 - V PWM Ramp Offset Voltage VOFFSET 0.75 0.80 0.85 V Maximum Duty Cycle DCmax COMP > 4V 80 - - % ERROR AMPLIFIER Open-Loop Gain - 88 - dB Gain Bandwidth Product GBWP - 15 - MHz Slew Rate SR COMP = 10pF - 5 - V/µs FN6769 Rev.3.00 Page 5 of 16 Apr 14, 2017

ISL85001 Electrical Specifications Typical specifications are measured at the following conditions: TA = -40°C to +85°C. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note8) TYP (Note8) UNIT ENABLE SECTION EN Threshold Rising Edge 1.2 1.7 2.2 V Hysteresis - 400 - mV EN Logic Input Current -1 - 1 µA FAULT PROTECTION Thermal Shutdown Temperature TSD Rising Threshold - 150 - °C THYS Hysteresis - 15 - °C PWM UV Trip Level VUV Referred to Nominal VOUT 70 75 80 % PWM UVP Propagation Delay - 270 - ns PWM OCP Threshold VIN = VDD = 5V, (Note7) 1.37 1.70 2.17 A OCP Blanking Time - 100 - ns POWER-GOOD PG Trip Level Referred to Nominal VOUT Lower level, falling edge, with typically 15mV hysteresis 85 88 91 % Upper level, rising edge, with typically 15mV hysteresis 108 112 116 % PG Propagation Delay - 9 - µs PG Low Voltage ISINK = 4mA - 0.05 0.30 V PG Leakage Current VPG = 5.5V, VFB = 0.6V, VDD = 5.5V -1 - 1 µA SOFT-START SECTION Soft-Start Threshold to Enable Buck 0.9 1.0 1.1 V Soft-Start Threshold to Enable PG 2.5 3.0 3.5 V Soft-Start Voltage High - 3.45 - V Soft-Start Charging Current 20 30 40 µA Soft-Start Pull-Down VSS = 3.0V - 25 - mA POWER MOSFET rDS(ON) IOUT = 100mA, Die Resistance - 120 200 mΩ NOTES: 6. Test Condition: VIN = 15V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 7. Excluding the blanking time. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6769 Rev.3.00 Page 6 of 16 Apr 14, 2017

ISL85001 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 22µH, C9 = 10µF, C11 = 47µF, IOUT = 0A to 1A. See “VIN” on page4. 1.0 1.0 3.3VOUT 0.9 0.9 0.8 0.8 %) 0.7 1.8VOUT 3.3VOUT %) 0.7 EFFICIENCY ( 0000....3456 2.5VOUT 1.5VOUT EFFICIENCY ( 0000....3456 1112....5825VVVVOOOOUUUUTTTT 5VOUT 0.2 0.2 0.1 0.1 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 3. EFFICIENCY vs LOAD, 500kHz, 5VIN FIGURE 4. EFFICIENCY vs LOAD, 500kHz, 12VIN 1.0 0.8 0.9 0.7 0.8 W) %) 0.7 ON ( 0.6 12VIN ENCY ( 00..56 1.2VOUT 5VOUT SIPATI 00..45 25VIN EFFICI 00..34 11..58VVOOUUTT ER DIS 0.3 0.2 2.5VOUT OW 0.2 0.1 P 0.1 5VIN 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 5. EFFICIENCY vs LOAD, 500kHz, 25VIN FIGURE 6. POWER DISSIPATION vs LOAD, 500kHz, 2.5VOUT 1.206 1.510 V) 11..220045 25VIN 12VIN V)11..550089 25VIN 12VIN E ( E ( AG 1.203 AG1.507 T T OL 1.202 OL1.506 V V UT 1.201 UT 1.505 UTP 1.200 5VIN UTP1.504 5VIN O O 1.199 1.503 1.198 1.502 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 7. VOUT REGULATION vs LOAD, 500kHz, 1.2VOUT FIGURE 8. VOUT REGULATION vs LOAD, 500kHz, 1.5VOUT FN6769 Rev.3.00 Page 7 of 16 Apr 14, 2017

ISL85001 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 22µH, C9 = 10µF, C11 = 47µF, IOUT = 0A to 1A. See “VIN” on page4. (Continued) 1.814 2.506 1.813 2.505 E (V) 1.812 25VIN 12VIN E (V) 2.504 25VIN 12VIN AG 1.811 AG 2.503 T T L L O 1.810 O 2.502 V V UT 1.809 UT 2.501 P P OUT 1.808 5VIN OUT 2.500 1.807 2.499 5VIN 1.806 2.498 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD, 500kHz, 1.8VOUT FIGURE 10. VOUT REGULATION vs LOAD, 500kHz, 2.5VOUT 3.330 4.99 3.328 12VIN 4.98 E (V) 3.326 25VIN E (V) 4.97 25VIN AG 3.324 AG 4.96 OLT 3.322 OLT 4.95 V V UT 3.320 UT 4.94 7VIN P P UT 3.318 7VIN UT 4.93 O O 3.316 4.92 12VIN 3.314 4.91 0.0 0.2 0.4 0.6 0.8 1.0 0.1 0.3 0.5 0.7 0.9 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 11. VOUT REGULATION vs LOAD, 500kHz, 3.3VOUT FIGURE 12. VOUT REGULATION vs LOAD, 500kHz, 5VOUT PHASE 5V/DIV PHASE 5V/DIV VOUT RIPPLE VOUT RIPPLE 20mV/DIV 20mV/DIV IL 0.1A/DIV IL 0.5A/DIV FIGURE 13. STEADY STATE OPERATION AT NO LOAD (5µs/DIV) FIGURE 14. STEADY STATE OPERATION AT FULL LOAD (1µs/DIV) FN6769 Rev.3.00 Page 8 of 16 Apr 14, 2017

ISL85001 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 22µH, C9 = 10µF, C11 = 47µF, IOUT = 0A to 1A. See “VIN” on page4. (Continued) PHASE 10V/DIV EN 5V/DIV VOUT 2V/DIV VOUT RIPPLE 100mV/DIV IL 0.5A/DIV PG 5V/DIV IL 0.5A/DIV SS 5V/DIV FIGURE 15. LOAD TRANSIENT (200µs/DIV) FIGURE 16. SOFT-START AT NO LOAD (2ms/DIV) EN 5V/DIV EN 5V/DIV VOUT V2VO/UDTIV IL 0.5A/DIV 2V/DIV IL 1A/DIV PG 5V/DIV SS 5V/DIV PG 5V/DIV FIGURE 17. SOFT-START AT FULL LOAD (2ms/DIV) FIGURE 18. SHUTDOWN CIRCUIT (100µs/DIV) PHASE 10V/DIV PHASE 10V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 19. OUTPUT SHORT-CIRCUIT (5µs/DIV) FIGURE 20. OUTPUT SHORT-CIRCUIT RECOVERY (1ms/DIV) FN6769 Rev.3.00 Page 9 of 16 Apr 14, 2017

ISL85001 Detailed Description MOSFET. Once exceeded, the controller initializes the internal soft-start circuitry. If either input supply drops below their falling The ISL85001 combines a standard buck PWM controller with an POR threshold during soft-start or operation, the buck regulator integrated switching MOSFET. The buck controller drives an latches off. internal N-channel MOSFET and requires an external diode to Enable and Disable deliver load current up to 1A. A Schottky diode is recommended for improved efficiency and performance over a standard diode. All internal power devices are held in a high-impedance state, The standard buck regulator can operate from either an which ensures they remain off while in shutdown mode. Typically, unregulated DC source, such as a battery, with a voltage ranging the enable input for a specific output is toggled high after the from +5.5V to +25V, or from a regulated system rail of +5V. input supply to that regulator is active and the internal LDO has When operating from +5.5V or greater, the controller is biased exceeded its POR threshold. from an internal +5V LDO voltage regulator. The converter output is regulated down to 0.6V from either input source. These The EN pin enables the buck controller portion of the ISL85001. features make the ISL85001 ideally suited for FPGA and wireless When the voltage on the EN pin exceeds the POR rising chipset power applications. threshold, the controller initiates the soft-start function for the PWM regulator. If the voltage on the EN pin drops below the POR The PWM control loop uses a single output voltage loop with falling threshold, the buck regulator shuts down. input voltage feed-forward, which simplifies feedback loop compensation and rejects input voltage variation. External Pulling the EN pin low simultaneously puts the output into feedback loop compensation allows flexibility in output filter shutdown mode and supply current drops to 100µA typical. component selection. The regulator switches at a fixed 500kHz. Soft-Start The buck regulator is equipped with a lossless current limit Once the input supply latch and enable threshold are met, the scheme. The current limit in the buck regulator is achieved by soft-start function is initialized. The soft-start circuitry begins monitoring the drain-to-source voltage drop of the internal sourcing 30µA, from an internal current source, which charges the switching power MOSFET. The current limit threshold is internally external soft-start capacitor. The voltage on SS begins ramping set at 1.7A. The part also features undervoltage protection by linearly from ground until the voltage across the soft-start latching the switching MOSFET driver to the OFF-state during an capacitor reaches 3.0V. This linear ramp is applied to the overcurrent, when the output voltage is lower than 75% of the noninverting input of the internal error amplifier and overrides the regulated output. This helps minimize power dissipation during a nominal 0.6V reference. The output voltage reaches its regulation short-circuit condition. Due to only the switching power MOSFET value when the soft-start capacitor voltage reaches 1.6V. Connect integration, there is no overvoltage protection feature for this a capacitor from the SS pin to ground. This capacitor (along with part. an internal 30µA current source) sets the soft-start interval of the +5V Internal Bias Supply (VDD) converter, tSS. Voltage applied to the VIN pin with respect to GND is regulated to CSSF = 50tSSs (EQ. 1) +5V DC by an internal LDO regulator. The output of the LDO, VDD, Upon disable, the SS pin voltage will discharge to zero voltage. is the bias voltage used by all the internal control and protection circuitry. The VDD pin requires a ceramic capacitor connected to Power-Good GND. The capacitor serves to stabilize the LDO and to decouple load transients. PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is The input voltage range for the ISL85001 is specified as +5.5V to actively held low when EN is low and during the buck regulator +25V or +5V ±10%. In the case of an unregulated supply case, soft-start period. After the soft-start period terminates, PG becomes the power supply is connected to VIN only. Once enabled, the high impedance as long as the output voltage is within ±12% of the linear regulator will turn-on and rise to +5V on VDD. In the +5V nominal regulation voltage set by FB. When VOUT drops 12% below supply case, the VDD and VIN pins must be tied together to or rises 12% above the nominal regulation voltage, the ISL85001 bypass the LDO. The external decoupling capacitor is still pulls PG low. Any fault condition forces PG low until the fault required in this mode. condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor between PG and VDD. Operation Initialization A 100kΩ resistor works well in most applications. The power-on reset circuit and enable inputs prevent false Output Voltage Selection start-up of the PWM regulator output. Once all the input criteria are met, the controller soft-starts the output voltage to the The regulator output voltages can be programmed using external programmed level. resistor dividers that scale the voltage feedback relative to the internal reference voltage. The scaled voltage is fed back to the Power-On Reset and Undervoltage Lockout inverting input of the error amplifier; refer to Figure21. The PWM portion of the ISL85001 automatically initializes upon The output voltage programming resistor, R4, will depend on the receipt of input power. The Power-On Reset (POR) function value chosen for the feedback resistor, R1, and the desired output continually monitors the VDD voltage. While below the POR thresholds, the controller inhibits switching off the internal power FN6769 Rev.3.00 Page 10 of 16 Apr 14, 2017

ISL85001 voltage, VOUT, of the regulator; see Equation2. The value for the There is 100ns blanking time for noise immunity. It is feedback resistor is typically between 1kΩ and 10kΩ. recommended to operate the duty cycle higher than the blanking R 0.6V time to insure proper overcurrent protection. R = ----------1------------------------ (EQ. 2) 4 V –0.6V OUT Undervoltage Protection If the output voltage desired is 0.6V, then RP is left unpopulated. If the voltage detected on the buck regulator FB pin falls 25% VOUT below the internal reference voltage, the undervoltage fault condition flag is set. The regulator is shut down. The controller R1 enters a recovery mode similar to the overcurrent hiccup mode. - No action is taken for 4 soft-start cycles and the internal + EA R4 undervoltage counter and fault condition flag are reset. A normal soft-start cycle is attempted and normal operation continues if 0.6V the fault condition has cleared. If the undervoltage counter REFERENCE overflows during soft-start, the converter is shut down and this hiccup mode operation repeats. FIGURE 21. EXTERNAL RESISTOR DIVIDER Thermal Overload Protection The buck output can be programmed as high as 19V. Proper Thermal overload protection limits total power dissipation in the heatsinking must be provided to insure that the junction ISL85001. There is a sensor on the chip to monitor the junction temperature does not exceed +125°C. temperature of the internal LDO and PWM switching power When the output is set greater than 2.7V, it is recommended to N-channel MOSFET. When the junction temperature (TJ) of the sensor exceeds +150°C, the thermal sensor sends a signal to the preload at least 10mA and make sure that the input rise time is fault monitor. much faster than the VOUT1 rise time. This allows the BOOT capacitor adequate time to charge for proper operation. The fault monitor commands the buck regulator to shut down. The buck regulator soft-starts turn on again after the IC’s junction Protection Features temperature cools by 20°C. The buck regulator experiences hiccup mode operation during continuous thermal overload The ISL85001 limits current in the power devices to limit on-chip conditions. For continuous operation, do not exceed the +125°C power dissipation. Overcurrent limits on the regulator protect the junction temperature rating. internal power device from excessive thermal damage. Undervoltage protection circuitry on the buck regulator provides Application Guidelines a second layer of protection for the internal power device under high current condition. Operating Frequency Buck Regulator Overcurrent Protection The ISL85001 operates at a fixed switching frequency of 500kHz. During the PWM on-time, the current through the internal switching MOSFET is sampled and scaled through an internal Buck Regulator Output Capacitor Selection pilot device. The sampled current is compared to a nominal 1.7A overcurrent limit. If the sampled current exceeds the overcurrent An output capacitor is required to filter the inductor current and limit reference level, an internal overcurrent fault counter is set supply the load transient current. The filtering requirements are a to 1 and an internal flag is set. The internal power MOSFET is function of the switching frequency and the ripple current. The immediately turned off and will not be turned on again until the load transient requirements are a function of the slew rate (di/dt) next switching cycle. and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and The protection circuitry continues to monitor the current and careful layout. turns off the internal MOSFET as described. If the overcurrent condition persists for eight sequential clock cycles, the Embedded processor systems are capable of producing transient overcurrent fault counter overflows, indicating an overcurrent load rates above 1A/ns. High frequency capacitors initially supply fault condition exists. The regulator is shut down and power-good the transient and slow the current load rate seen by the bulk goes low. If the overcurrent condition clears prior to the counter capacitors. The bulk filter capacitor values are generally reaching four consecutive cycles, the internal flag and counter determined by the ESR (Effective Series Resistance) and voltage are reset. rating requirements rather than actual capacitance requirements. The protection circuitry attempts to recover from the overcurrent condition after waiting 4 soft-start cycles. The internal overcurrent flag and counter are reset. A normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. If the overcurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. FN6769 Rev.3.00 Page 11 of 16 Apr 14, 2017

ISL85001 High frequency decoupling capacitors should be placed as close Rectifier Selection to the power pins of the load as physically possible. Be careful Current circulates from ground to the junction of the MOSFET and not to add inductance in the circuit board wiring that could the inductor when the high-side switch is off. As a consequence, cancel the usefulness of these low inductance components. the polarity of the switching node is negative with respect to Consult with the manufacturer of the load on specific decoupling ground. This voltage is approximately -0.5V (a Schottky diode drop) requirements. during the off-time. The rectifier's rated reverse breakdown voltage Use only specialized low-ESR capacitors intended for must be at least equal to the maximum input voltage, preferably switching-regulator applications for the bulk capacitors. The bulk with a 20% derating factor. The power dissipation is shown in capacitor’s ESR will determine the output ripple voltage and the Equation5: initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with P W = I V 1–V-----O----U----T--- (EQ. 5) lower ESR available in larger case sizes. However, the Equivalent D OUT D  VIN  Series Inductance (ESL) of these capacitors increases with case Where VD is the voltage of the Schottky diode = 0.5V to 0.7V size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified Input Capacitor Selection parameter. Work with your capacitor supplier and measure the Use a mix of input bypass capacitors to control the voltage capacitor’s impedance with frequency to select a suitable overshoot across the MOSFETs. Use small ceramic capacitors for component. In most cases, multiple electrolytic capacitors of high frequency decoupling and bulk capacitors to supply the small case size perform better than a single large case capacitor. current needed each time the switching MOSFET turns on. Place Output Inductor Selection the small ceramic capacitors physically close to the MOSFET VIN pins (switching MOSFET drain) and the Schottky diode anode. The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the The important parameters for the bulk input capacitance are the load transient. The inductor value determines the converter’s voltage rating and the RMS current rating. For reliable operation, ripple current and the ripple voltage is a function of the ripple select bulk capacitors with voltage and current ratings above the current. The ripple voltage and current are approximated by maximum input voltage and largest RMS current required by the Equation3: circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a V –V V I = -----I--Nf--------------O-L---U----T-------V-O----U----T--- VOUT = IESR (EQ. 3) conservative guideline. For most cases, the RMS current rating SW IN requirement for the input capacitor of a buck regulator is Increasing the value of inductance reduces the ripple current and approximately 1/2 the DC load current. voltage. However, the large inductance values reduce the The maximum RMS current required by the regulator may be converter’s response time to a load transient. closely approximated through Equation6: One of the parameters limiting the converter’s response to a IRMS_MAX = load transient is the time required to change the inductor cISuLr8re5n0t0. G1 iwveilnl par osuvifdfiec ieeinthtleyr f 0as%t coor n8t0ro%l ldouotpy dceycslieg nin, trhees ponse V----V-O---I--U-N----T-- V-----I--N-----V-–----IV--N--O------U----T---IOUTMAX2+1--1--2--V-----I--N-----V-–----IV--N--O------U----T---L--V----O--f--S-U----W-T---2 to a load transient. The response time is the time required to (EQ. 6) slew the inductor current from an initial current value to the transient current level. During this interval, the difference For a through-hole design, several electrolytic capacitors may be between the inductor current and the transient current level needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series The response time to a transient is different for the application of available from reputable manufacturers are surge current tested. load and the removal of load. Equation4 gives the approximate response time interval for application and removal of a transient load: LI LI TRAN TRAN tRISE = V------------–----V---------------- tFALL = -----V-------------------- (EQ. 4) IN OUT OUT Where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check Equation4 at the minimum and maximum output levels for the worst case response time. FN6769 Rev.3.00 Page 12 of 16 Apr 14, 2017

ISL85001 OSC DRIVER VIN 23.. PPllaaccee 12SNTD z ezeroro b ealto fwil tfeilrt’esr ’dso duobulbel ep oploel.e (~75% FLC). PWM COMPARATOR LO VDDQ 4. Place 1ST pole at the ESR zero. DVOSC +- D PHASE CO 5. Place 2ND pole at half the switching frequency. 6. Check gain against error amplifier’s open-loop gain. ESR (PARASITIC) 7. Estimate phase margin - repeat if necessary. ZFB VE/A Compensation Break Frequency Equations - ZIN + REFERENCE 1 1 ERROR F = ------------------------------- F = -------------------------------------------------- AMP Z1 2R2C2 P1 C1C2 DETAILED COMPENSATION COMPONENTS 2R2C-----1----+-----C-----2-- (EQ. 8) C2 C1R2 ZFB C3ZINR3VOUT FZ2 = 2---------------R----1-----+1----R-----3----------C----3-- FP2 = 2------------R--1---3-------C-----3-- R1 Figure23 shows an asymptotic plot of the DC/DC converter’s COMP gain vs frequency. The actual modulator gain has a high gain - FB peak due to the high Q factor of the output filter and is not shown + R4 in Figure23. Using the previously mentioned guidelines should ISL85001 give a compensation gain similar to the curve plotted. The open REFERENCE loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error FIGURE 22. VOLTAGE MODE BUCK CONVERTER COMPENSATION amplifier. The open loop gain is constructed on the graph of DESIGN AND OUTPUT VOLTAGE SELECTION Figure21 by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the Feedback Compensation modulator transfer function to the compensation transfer function and plotting the gain. Figure22 on page13 highlights the voltage mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error 100 FZ1FZ2 FP1 FP2 amplifier output (VE/A) is compared with the oscillator (OSC) 80 triangular wave to provide a Pulse-Width Modulated (PWM) wave OPEN LOOP with an amplitude of VIN at the PHASE node. The PWM wave is 60 ERROR AMP GAIN sTmheo motohdeudl abtyo trh tera onustfpeur tf ufinltcetri o(LnO i sa tnhde C sOm).all-signal transfer N (dB) 4200 (2R02L/OR1G) 20LOG faunndc ttihoen oouft VpOuUt Tfi/ltVeEr/ (AL.O T ahnisd f CuOnc),t iwointh is a d doomuibnlaet peodl eb yb are DakC Gain GAI 0 (VIN/VOSC) frequency at FLC and a zero at FESR. The DC Gain of the MODULATOR COMPENSATION -20 GAIN modulator is simply the input voltage (VIN) divided by the GAIN OPEN LOOP peak-to-peak oscillator voltage VOSC. -40 GAIN FLC FESR Modulator Break Frequency Equations -60 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 1 1 F = ------------------------------------ F = -------------------------------------- LC 2 LOCO ESR 2ESRCO (EQ. 7) FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB The compensation network consists of the error amplifier and ZIN to provide a stable, high bandwidth (BW) overall loop. A (internal to the ISL85001) and the impedance networks ZIN and stable control loop has a gain crossing with -20dB/decade slope ZFB. The goal of the compensation network is to provide an open and a phase margin greater than 45°. Include worst case loop transfer function with the highest 0dB crossing frequency component variations when determining phase margin. (f0dB) and adequate phase margin. Phase margin is the A more detailed explanation of voltage mode control of a buck difference between the open loop phase at f0dB and 180°. regulator can be found in TB417, entitled “Designing Stable Equation8 relates the compensation network’s poles, zeros and Compensation Networks for Single Phase Voltage Mode Buck gain to the components (R1, R2, R3, C1, C2, and C3) in Regulators.” Figure23. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Pick gain (R2/R1) for desired converter bandwidth. FN6769 Rev.3.00 Page 13 of 16 Apr 14, 2017

ISL85001 Layout Considerations Layout is very important in high frequency switching converter VIN VIN design. With power devices switching efficiently between 100kHz and 600kHz, the resulting current transitions from one device to CIN another cause voltage spikes across the interconnecting ISL85001 impedances and parasitic circuit elements. These voltage spikes L VOUT1 can degrade efficiency, radiate noise into the circuit and lead to 5V VDD PHASE device overvoltage stress. Careful component layout and printed D D circuit board design minimizes these voltage spikes. CBP1 GND COUT1 OA L As an example, consider the turn-off transition of the upper MOSFET. COMP Prior to turn-off, the MOSFET is carrying the full load current. During C2 C1 turn-off, current stops flowing in the MOSFET and is picked up by the R2 R1 Schottky diode. Any parasitic inductance in the switched current FB pCaatrhe fguel ncoemrapteosn ae nlat rsgeele vcotlitoang,e t isgphitk lea ydouurtin ogf tthhee scwritiitccahli ncog minpteornveanl.t s R4 C3 R3 and short, wide traces minimizes the magnitude of voltage spikes. GND PAD There are two sets of critical components in the ISL85001 switching converter. The switching components are the most KEY critical because they switch large amounts of energy, and ISLAND ON POWER PLANE LAYER therefore tend to generate large amounts of noise. Next are the small signal components, which connect to sensitive nodes or ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER supply critical bypass current and signal coupling. VIA CONNECTION TO GROUND PLANE A multi-layer printed circuit board is recommended. Figure24 FIGURE 24. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS shows the connections of the critical components in the converter. The switching components should be placed close to the Note that capacitors CIN and COUT could each represent numerous ISL85001 first. Minimize the length of the connections between physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors component ground connections with vias to this layer. Dedicate as close to the upper MOSFET drain as possible. Position the another solid layer as a power plane and break this plane into output inductor and output capacitors between the upper and smaller islands of common voltage levels. Keep the metal runs Schottky diode and the load. from the phase terminals to the output inductor short. The power plane should support the input power and output power nodes. The critical small signal components include any bypass Use copper filled polygons on the top and bottom circuit layers for capacitors, feedback components and compensation the phase nodes. Use the remaining printed circuit layers for small components. Place the PWM converter compensation signal wiring. components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with In order to dissipate heat generated by the internal LDO and vias tied straight to the ground plane as required. MOSFET, the ground pad, Pin 13, should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. FN6769 Rev.3.00 Page 14 of 16 Apr 14, 2017

ISL85001 Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE April 14, 2017 FN6769.3 Updated Related Literature section on page 1. Updated Figure2 on page3 by removing the VDD label next to power-on reset monitor. Added Evaluation Board to Ordering Information table on page4. Updated Note1 to include the unit amount for the tape and reel option. Updated 70% to 75% in the third paragraph under Detailed Description section. Replaced all of the ‘x’ in the formulas with the ‘·’. Updated Equation6 on page12. Updated POD to the latest revision, changes are as follows: Tiebar Note 5 updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). May 16, 2012 FN6769.2 Converted to new datasheet template. Added “Related Literature” to page1. Added MSL note to “Ordering Information” on page4. Updated Tape & Reel note in “Ordering Information” on page4 to new standard “Add “-T*” suffix for tape and reel.” The “*” covers all possible tape and reel options. Removed incorrect note 4 reference from “Absolute Maximum Ratings” on page5. Added “Revision History” and “Products” on page16. Updated “Package Outline Drawing” on page17. Added land pattern. Removed table and added dimensions to drawing. March 17, 2009 FN6769.1 Changed “Note 5” to “Note 6” in “VIN Operating Supply Current” on page5 November 17, 2008 FN6769.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. ©© CCooppyyrriigghhtt IInntteerrssiill AAmmeerriiccaass LLLLCC 22000088--22001177.. AAllll RRiigghhttss RReesseerrvveedd.. AAllll ttrraaddeemmaarrkkss aanndd rreeggiisstteerreedd ttrraaddeemmaarrkkss aarree tthhee pprrooppeerrttyy ooff tthheeiirr rreessppeeccttiivvee oowwnneerrss.. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6769 Rev.3.00 Page 15 of 16 Apr 14, 2017

ISL85001 Package Outline Drawing For the most recent package outline drawing, see L12.4x3. L12.4x3 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 3/15 3.30 +0.10/-0.15 4.00 A 2X 2.50 6 10X 0.50 PIN 1 PIN #1 INDEX AREA INDEX AREA B 6 1 6 12 X 0.40 ±0.10 3.00 1.70 +0.10/-0.15 (4X) 0.15 12 7 0.10MCAB TOP VIEW 4 12 x 0.23 +0.07/-0.05 BOTTOM VIEW SEE DETAIL "X" (3.30) 0.10C 6 1 1.00 MAX C SEATING PLANE 0.08C SIDE VIEW 2.80 (1.70) 0.2 REF 5 C 12 X 0.60 7 12 0. 00 MIN. (12 X 0.23) 0. 05 MAX. (10X 0.5) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on anyof the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 V4030D-4 issue E. FN6769 Rev.3.00 Page 16 of 16 Apr 14, 2017