DATASHEET ISL8483E, ISL8485E FN6048 ESD Protected to ±15kV, 5V, Low Power, High Speed or Slew Rate Limited Rev.13.00 RS-485/RS-422 Transceivers Sep 24, 2018 The ISL8483E and ISL8485E are ESD protected, BiCMOS 5V Features powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver • Pb-Free (RoHS compliant) output/receiver input is protected against ±15kV ESD strikes • Extended industrial temperature options (+125°C) without latch-up. Unlike competitive devices, this Renesas • RS-485 I/O pin ESD protection . . . . . . . . . . . . . . ±15kV HBM family is specified for 10% tolerance supplies (4.5V to 5.5V). - Class 3 ESD level on all other pins. . . . . . . . . . . >7kV HBM The ISL8483E uses slew rate limited drivers that reduce EMI and minimize reflections from improperly terminated • Specified for 10% tolerance supplies transmission lines or unterminated stubs in multidrop and • High data rate version (ISL8485E). . . . . . . . . . up to 10Mbps multipoint applications. • Slew rate limited version for error free data transmission Data rates up to 10Mbps are achievable by using the (ISL8483E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 250kbps ISL8485E, which features higher slew rates. • Single unit load allows up to 32 devices on the bus Both devices present a “single unit load” to the RS-485 bus, • 1nA low current Shutdown mode (ISL8483E) which allows up to 32 transceivers on the network. • Low quiescent current: Receiver (Rx) inputs feature a “fail-safe if open” design, which - 160µA (ISL8483E) ensures a logic high Rx output if Rx inputs are floating. - 500µA (ISL8485E) Driver (Tx) outputs are short-circuit protected even for voltages • -7V to +12V common-mode input voltage range exceeding the power supply voltage. Additionally, on-chip • Three-state Rx and Tx outputs thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. • 30ns propagation delays, 5ns skew (ISL8485E) These half duplex configurations multiplex the Rx inputs and • Operate from a single +5V supply (10% tolerance) Tx outputs to allow transceivers with Rx and Tx disable • Current limiting and thermal shutdown for driver overload functions in 8 Ld packages. protection Related Literature Applications For a full list of related documents, visit our website: • Factory automation •ISL8483E and ISL8485E product pages • Security networks • Building environmental control systems • Industrial/process control networks • Level translators (such as RS-232 to RS-422) • RS-232 “extension cords” TABLE 1. SUMMARY OF FEATURES NO. OF DEVICES PART HALF/FULL ALLOWED DATA RATE SLEW-RATE RECEIVER/DRIVER QUIESCENT ICC LOW POWER PIN NUMBER DUPLEX ON BUS (Mbps) LIMITED? ENABLE? (µA) SHUTDOWN? COUNT ISL8483E Half 32 0.25 Yes Yes 160 Yes 8 ISL8485E Half 32 10 No Yes 500 No 8 FN6048 Rev.13.00 Page 1 of 15 Sep 24, 2018

ISL8483E, ISL8485E Typical Operating Circuit 5V 5V 8 100nF 100nF 8 RPU VCC VCC RPU 1 RO RB RO 1 A/Y 6 6 A/Y 2 RE RE 2 3 DE B/Z 7 RT2 VFS RT1 7 B/Z DE 3 4 DI DI 4 RB GND GND 5 5 To calculate the resistor values, refer to TB509 Ordering Information PART NUMBER TAPE AND REEL PACKAGE (Notes3, 4) PART MARKING TEMP. RANGE (°C) (UNITS) (Note2) (RoHS COMPLIANT) PKG. DWG. # ISL8483EIBZ 8483 EIBZ -40 to +85 - 8 Ld SOIC M8.15 ISL8483EIBZ-T 8483 EIBZ -40 to +85 2.5k 8 Ld SOIC M8.15 ISL8485EABZ 8485 EABZ -40 to +125 - 8 Ld SOIC M8.15 ISL8485EABZ-T 8485 EABZ -40 to +125 2.5k 8 Ld SOIC M8.15 ISL8485ECBZ 8485 ECBZ 0 to +70 - 8 Ld SOIC M8.15 ISL8485ECBZ-T 8485 ECBZ 0 to +70 2.5k 8 Ld SOIC M8.15 ISL8485EIBZ 8485 EIBZ -40 to +85 - 8 Ld SOIC M8.15 ISL8485EIBZ-T 8485 EIBZ -40 to +85 2.5k 8 Ld SOIC M8.15 ISL8485EIPZ ISL 8485EIPZ -40 to +85 - 8 Ld PDIP (Note1) E8.3 NOTES: 1. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in reflow solder processing applications. 2. Refer to TB347 for details about reel specifications. 3. These Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), refer to the product information pages for the ISL8483E and the ISL8485E. For more information on MSL, refer to TB363. FN6048 Rev.13.00 Page 2 of 15 Sep 24, 2018

ISL8483E, ISL8485E Pin Configuration ISL8483E, ISL8485E (8 LD PDIP, SOIC) TOP VIEW RO 1 8 VCC R RE 2 7 B/Z DE 3 6 A/Y DI 4 D 5 GND Pin Descriptions PIN FUNCTION RO Receiver output: RO is high if A > B by at least 0.2V; RO is low if A < B by 0.2V or more; RO is high if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs Y and Z are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y ±15kV HBM ESD protected, RS-485, RS-422 level noninverting receiver input and noninverting driver output. Pin is an input (A) if DE=0; pin is an output (Y) if DE = 1. B/Z ±15kV HBM ESD protected, RS-485, RS-422 level inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. VCC System power supply input (4.5V to 5.5V). Truth Tables RECEIVING TRANSMITTING INPUTS OUTPUT INPUTS OUTPUTS RE DE A-B RO RE DE DI Z Y 0 0 VAB≥ 0.2V 1 X 1 1 0 1 0 0 0.2V > VAB > -0.2V Undetermined X 1 0 1 0 0 0 VAB ≤ -0.2V 0 0 0 X High-Z High-Z 0 0 Inputs Open 1 1 0 X High-Z * High-Z * 1 0 X High-Z * *Shutdown mode for ISL8483E (see Note11) 1 1 X High-Z *Shutdown mode for ISL8483E (see Note11) FN6048 Rev.13.00 Page 3 of 15 Sep 24, 2018

ISL8483E, ISL8485E Absolute Maximum Ratings Thermal Information VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Thermal Resistance (Typical, Note5) θJA (°C/W) Input Voltages 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 DI, DE, RE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) 8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Input/Output Voltages Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C A/Y, B/Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C RO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Short-Circuit Duration *Pb-free PDIPs can be used for through hole wave solder processing only. Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous They are not intended for use in reflow solder processing applications. ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See “ESD PERFORMANCE” Operating Conditions Temperature Range ISL8485ECx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL848xEIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C ISL8485EAx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. NOTE: 5. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. Refer to TB379 for details. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C, (Note6) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note16) TYP (Note16) UNIT DC CHARACTERISTICS Driver Differential VOUT (No Load) VOD1 Full - - VCC V Driver Differential VOUT (With Load) VOD2 R = 50Ω (RS-422), (Figure1 on page6) Full 2 3 - V R = 27Ω (RS-485), (Figure1 on page6) Full 1.5 2.3 5 V Change in Magnitude of Driver VOD R = 27Ω or 50Ω, (Figure1 on page6) Full - 0.01 0.2 V Differential VOUT for Complementary Output States Driver Common-Mode VOUT VOC R = 27Ω or 50Ω, (Figure1 on page6) Full - - 3 V Change in Magnitude of Driver VOC R = 27Ω or 50Ω, (Figure1 on page6) Full - 0.01 0.2 V Common-Mode VOUT for Complementary Output States Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V Logic Input Current IIN1 DE, DI, RE (ISL8483E) Full -2 - 2 µA IIN1 DI (ISL8485E) Full -2 - 2 µA IIN1 DE, RE (ISL8485E) Full -25 - 25 µA Input Current (A, B), (Note14) IIN2 DE = 0V, VCC = 0V or 4.5 to 5.5V VIN = 12V Full - - 1 mA VIN = -7V Full - - -0.8 mA Receiver Differential Threshold VTH -7V  VCM  12V Full -0.2 - 0.2 V Voltage Receiver Input Hysteresis VTH VCM = 0V +25 - 70 - mV Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full 3.5 - - V Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V Three-State (High Impedance) IOZR 0.4V  VO  2.4V Full - - ±1 µA Receiver Output Current FN6048 Rev.13.00 Page 4 of 15 Sep 24, 2018

ISL8483E, ISL8485E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C, (Note6) (Continued) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note16) TYP (Note16) UNIT Receiver Input Resistance RIN -7V  VCM  12V Full 12 - - kΩ No-Load Supply Current, (Note7) ICC ISL8485E, DI, RE = 0V or VCC DE = VCC Full - 700 900 µA DE = 0V Full - 500 565 µA ISL8483E, DI, RE = 0V or VCC DE = VCC Full - 470 650 µA DE = 0V Full - 160 250 µA Shutdown Supply Current ISHDN ISL8483E, DE = 0V, RE = VCC, DI = 0V or VCC Full - 1 50 nA Driver Short-Circuit Current, IOSD1 DE = VCC, -7V  VY or VZ  12V, (Note8) Full 35 - 250 mA VO = High or Low Receiver Short-Circuit Current IOSR 0V  VO  VCC Full 7 - 85 mA SWITCHING CHARACTERISTICS (ISL8485E) Driver Input to Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full 18 30 50 ns Driver Output Skew tSKEW RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full - 2 10 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full 3 11 25 ns Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure3 on page7) Full - 17 70 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure3 on page7) Full - 14 70 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure3 on page7) Full - 19 70 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure3 on page7) Full - 13 70 ns Receiver Input to Output Delay tPLH, tPHL (Figure4 on page7) Full 30 40 150 ns Receiver Skew | tPLH - tPHL | tSKD (Figure4 on page7) +25 - 5 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure5 on page8) Full - 9 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure5 on page8) Full - 9 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure5 on page8) Full - 9 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure5 on page8) Full - 9 50 ns Maximum Data Rate fMAX (Note15) Full 10 - - Mbps SWITCHING CHARACTERISTICS (ISL8483E) Driver Input to Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full 250 800 2000 ns Driver Output Skew tSKEW RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full - 160 800 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure2 on page7) Full 250 800 2000 νσ Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure3 on page7), Full 250 - 2000 νσ (Note9) Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure3 on page7), Full 250 - 2000 νσ (Note9) Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure3 on page7) Full 300 - 3000 νσ Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure3 on page7) Full 300 - 3000 νσ Receiver Input to Output Delay tPLH, tPHL (Figure4 on page7) Full 250 350 2000 ns Receiver Skew | tPLH - tPHL | tSKD (Figure4 on page7) +25 - 25 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure5 on page8), Full - 10 50 ns (Note10) Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure5 on page8), Full - 10 50 ns (Note10) FN6048 Rev.13.00 Page 5 of 15 Sep 24, 2018

ISL8483E, ISL8485E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C, (Note6) (Continued) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note16) TYP (Note16) UNIT Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure5 on page8) Full - 10 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure5 on page8) Full - 10 50 ns Maximum Data Rate fMAX (Note15) Full 250 - - kbps Time to Shutdown tSHDN (Note11) Full 50 200 600 ns Driver Enable from Shutdown to tZH(SHDN) CL = 100pF, SW = GND, (Figure3 on page7), Full - - 2000 νσ Output High (Notes11, 12) Driver Enable from Shutdown to tZL(SHDN) CL = 100pF, SW = VCC, (Figure5 on page8), Full - - 2000 νσ Output Low (Notes11, 12) Receiver Enable from Shutdown to tZH(SHDN) CL = 15pF, SW = GND, (Figure5 on page8), Full - - 2500 ns Output High (Notes11, 13) Receiver Enable from Shutdown to tZL(SHDN) CL = 15pF, SW = VCC, (Figure5 on page8), Full - - 2500 ns Output Low (Notes11, 13) ESD PERFORMANCE RS-485 Pins (A/Y, B/Z) Human Body Model +25 - 15 - kV All Other Pins +25 - >7 - kV NOTES: 6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 7. Supply current specification is valid for loaded drivers when DE = 0V. 8. Applies to peak current. See “Typical Performance Curves” on page10 for more information. 9. When testing the ISL8483E, keep RE = 0 to prevent the device from entering SHDN. 10. When testing the ISL8483E, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN. 11. The ISL8483E is put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are ensured not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are ensured to have entered shutdown. See “Low Power Shutdown Mode (ISL8483E Only)” on page9. 12. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN. 13. Set the RE signal high time >600ns to ensure that the device enters SHDN. 14. Devices meeting these limits are denoted as “single unit load (1 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus. . 15. Limits established by characterization and are not production tested 16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Test Circuits and Waveforms R DE VCC Z DI D VOD Y R VOC FIGURE 1. DRIVER VOD AND VOC FN6048 Rev.13.00 Page 6 of 15 Sep 24, 2018

ISL8483E, ISL8485E Test Circuits and Waveforms (Continued) 3V DI 1.5V 1.5V 0V tPLH tPHL VOH CL = 100pF OUT (Y) 50% 50% DE VCC VOL DI Z D RDIFF tPHL tPLH Y CL = 100pF VOH OUT (Z) 50% 50% SIGNAL GENERATOR VOL 90% 90% +VOD DIFF OUT (Y - Z) 10% 10% -VOD tR tF SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES DE DI Z 500Ω VCC D SIGNAL Y SW GND GENERATOR CL 3V DE Note6 1.5V 1.5V 0V (SHDN) FOR ISL8483E ONLY tZH, tZH(SHDN) tHZ Note6 OUTPUT HIGH PARAMETER OUTPUT RE DI SW CL (pF) VOH - 0.5V VOH tHZ Y/Z X 1 / 0 GND 15 OUT (Y, Z) 2.3V 0V tLZ Y/Z X 0 / 1 VCC 15 tZH Y/Z 0 (Note9) 1 / 0 GND 100 tZL, tZL(SHDN) tLZ tZL Y/Z 0 (Note9) 0 / 1 VCC 100 Note6 VCC tZH(SHDN) Y/Z 1 (Note12) 1 / 0 GND 100 OUT (Y, Z) 2.3V tZL(SHDN) Y/Z 1 (Note12) 0 / 1 VCC 100 OUTPUT LOW VOL + 0.5V VOL FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES RE 3V B 15pF A 1.5V 1.5V +1.5V RO A R 0V tPLH tPHL SIGNAL VCC GENERATOR RO 50% 50% 0V FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS FIGURE 4. RECEIVER PROPAGATION DELAY FN6048 Rev.13.00 Page 7 of 15 Sep 24, 2018

ISL8483E, ISL8485E Test Circuits and Waveforms (Continued) RE B RO 1kΩ VCC R SIGNAL SW GND Note6 GENERATOR A 3V 15pF RE 1.5V 1.5V 0V (SHDN) FOR ISL8483E ONLY tZH, tZH(SHDN) tHZ Note6 OUTPUT HIGH VOH - 0.5V VOH RO 1.5V PARAMETER DE A SW 0V tHZ 0 +1.5V GND tZL, tZL(SHDN) tLZ tLZ 0 -1.5V VCC Note6 VCC tZH (Note10) 0 +1.5V GND RO 1.5V tZL (Note10) 0 -1.5V VCC OUTPUT LOW VOL + 0.5V VOL tZH(SHDN) (Note13) 0 +1.5V GND tZL(SHDN) (Note13) 0 -1.5V VCC FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES Application Information All the receivers include a “fail-safe if open” function that ensures a high level receiver output if the receiver inputs are unconnected RS-485 and RS-422 are differential (balanced) data (floating). transmission standards for use in long haul or noisy Receivers easily meet the data rates supported by the environments. RS-422 is a subset of RS-485, so RS-485 corresponding driver. transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard that allows only one ISL8483E and ISL8485E receiver outputs are tri-statable through driver and up to 10 receivers on each bus, assuming one unit the active low RE input. load devices. RS-485 is a true multipoint standard that allows up to 32 one unit load devices (any combination of drivers and Driver Features receivers) on each bus. To allow for multipoint operation, the The RS-485 and RS-422 drivers are differential output devices RS-485 specification requires that drivers handle bus contention that deliver at least 1.5V across a 54Ω load (RS-485) and at least without sustaining any damage. 2V across a 100Ω load (RS-422). The drivers feature low Another important advantage of RS-485 is the extended propagation delay skew to maximize bit width and to minimize Common-Mode Range (CMR). The CMR specifies that the driver EMI. outputs and receiver inputs withstand signals that range from The ISL8483E and ISL8485E drivers are tri-statable using the +12V to -7V. RS-422 and RS-485 are intended for runs as long as active high DE input. 4000ft, so the wide CMR is necessary to handle ground potential differences and voltages induced in the cable by external fields. The ISL8483E driver outputs are slew rate limited to minimize EMI and to minimize reflections in unterminated or improperly Receiver Features terminated networks. The data rate on these slew rate limited versions is a maximum of 250kbps. The ISL8485E driver outputs The devices use a differential input receiver for maximum noise are not limited, so faster output transition times allow data rates immunity and common-mode rejection. Input sensitivity is of at least 10Mbps. ±200mV as required by the RS-422 and RS-485 specifications. Receiver input impedance surpasses the RS-422 spec of 4kΩ and meets the RS-485 “Unit Load” requirement of 12kΩ minimum. Receiver inputs function with common-mode voltages as high as ±7V outside the power supplies (for example, +12V and -7V), making them ideal for long networks where induced voltages are a realistic concern. FN6048 Rev.13.00 Page 8 of 15 Sep 24, 2018

ISL8483E, ISL8485E Data Rate, Cables, and Terminations Low Power Shutdown Mode (ISL8483E Only) RS-485 and RS-422 are intended for network lengths up to These CMOS transceivers all use a fraction of the power required 4000ft, but the maximum system data rate decreases as the by their bipolar counterparts, but the ISL8483E includes a transmission length increases. Devices operating at 10Mbps are shutdown feature that reduces the already low quiescent ICC to a limited to lengths less than 100 feet, and the 250kbps versions 1nA trickle. The ISL8483E enters shutdown whenever the can operate at full data rates with lengths in excess of 1000 ft. receiver and driver are simultaneously disabled (RE=VCC and DE=GND) for a period of at least 600ns. Disabling both the Twisted pair cable is the cable of choice for the RS-485 and RS- driver and the receiver for fewer than 50ns ensures that the 422 networks. Twisted pair cables tend to pick up noise and ISL8483E does not enter shutdown. other electromagnetically induced voltages as common-mode signals, which are effectively rejected by the differential receivers Note that receiver and driver enable times increase when the in these ICs. ISL8483E enables from shutdown. Refer to Notes9 through Notes12 on page6 at the end of the “Electrical Specifications” Proper termination is imperative when using the 10Mbps devices table for more information. to minimize reflections. Short networks using the 250kbps versions do not need to be terminated, but terminations are ESD Protection recommended unless power dissipation is an overriding concern. All pins on these interface devices include Class 3 Human Body In point-to-point or point-to-multipoint (single driver on bus) Model (HBM) ESD protection structures, but the RS-485 pins networks, terminate the main cable in its characteristic (driver outputs and receiver inputs) incorporate advanced impedance (typically 120Ω) at the end farthest from the driver. In structures allowing them to survive ESD events in excess of multi-receiver applications, keep stubs connecting receivers to ±15kV HBM. The RS-485 pins are particularly vulnerable to ESD the main cable as short as possible. In multipoint (multi-driver) systems, terminate the main cable in its characteristic damage because they typically connect to an exposed port on impedance at both ends. Keep stubs that are connecting a the exterior of the finished product. Simply touching the port pins transceiver to the main cable as short as possible. or connecting a cable can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device Built-In Driver Overload Protection whether or not it is powered up without either allowing any latchup mechanism to activate and without degrading the The RS-485 specification requires that drivers survive worst case RS-485 common-mode range of -7V to +12V. The built-in ESD bus contentions undamaged. The ISL848xE devices meet this protection eliminates the need for board level protection requirement through driver output short-circuit current limits and structures (such as transient suppression diodes) and the on-chip thermal shutdown circuitry. associated, undesirable capacitive load that they present. The driver output stages incorporate short-circuit current limiting Human Body Model Testing circuitry that ensures that the output current never exceeds the RS-485 specification, even at the common-mode voltage range As the name implies, the HBM test method emulates the ESD extremes. Also, these devices use a foldback circuit that reduces event delivered to an IC during human handling. The tester the short-circuit current and consequently the power dissipation delivers the charge stored on a 100pF capacitor through a 1.5kΩ when the contending voltage exceeds either supply. current limiting resistor into the pin under test. The HBM method determines an IC’s ability to withstand the ESD events typically In the event of a major short-circuit condition, the ISL848xE present during handling and manufacturing. devices perform a thermal shutdown that disables the drivers whenever the die temperature becomes excessive. This The RS-485 pin survivability on this high ESD family has been eliminates the power dissipation allowing the die to cool. The characterized to be in excess of ±15kV for discharges to GND. drivers automatically re-enable after the die temperature drops about 15°. If the contention persists, the thermal Die Characteristics shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 518 PROCESS: Si Gate CMOS FN6048 Rev.13.00 Page 9 of 15 Sep 24, 2018

ISL8483E, ISL8485E Typical Performance Curves VCC = 5V, TA = +25°C, ISL8483E and ISL8485E; unless otherwise specified. 90 3.6 80 3.4 T (mA) 70 AGE (V) 3.2 RDIFF = 100Ω N 60 T RE OL 3.0 UR 50 T V UT C 40 UTPU 2.8 UTP 30 L O 2.6 O A VER 20 ENTI 2.4 RDIFF = 54Ω RI ER D 10 F 2.2 F DI 0 0 1 2 3 4 5 2.0 -40 -25 0 25 50 75 85 DIFFERENTIAL OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs VOLTAGE TEMPERATURE 160 700 140 650 ISL8485E, DE = VCC, RE = X 120 Y OR Z = LOW 600 100 mA) 80 550 IISSLL88448855E, D, DEE = =G GNNDD, R, REE = =X X T ( 60 500 URREN 24000 (µA)CC440500 ISL8483E, DE = VCC, RE = X C I T -20 350 TPU -40 Y OR Z = HIGH 300 U O -60 250 -80 200 -100 ISL8483E, DE = GND, RE = GND -120 150 -7 -6 -4 -2 0 2 4 6 8 10 12 -40 -25 0 25 50 75 85 OUTPUT VOLTAGE (V) TEMPERATURE (oC) FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT VOLTAGE FIGURE 9. SUPPLY CURRENT vs TEMPERATURE 1200 400 1100 Y (ns)1000 tPLHY tPLHZ 300 A ON DEL 900 tPHLY W (ns) 200 |tPHLY - tPLHZ| |tPLHY - tPHLZ| GATI 800 tPHLZ SKE A P O 700 R 100 P 600 |CROSS PT. OF Y AND Z - CROSS PT. OF YAND Z| 500 0 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 10. DRIVER PROPAGATION DELAY vs TEMPERATURE FIGURE 11. DRIVER SKEW vs TEMPERATURE (ISL8483E) (ISL8483E) FN6048 Rev.13.00 Page 10 of 15 Sep 24, 2018

ISL8483E, ISL8485E Typical Performance Curves VCC = 5V, TA = +25°C, ISL8483E and ISL8485E; unless otherwise specified. (Continued) 40 3.0 ns) 35 2.5 Y ( |tPHLY - tPLHZ| LA tPHLY DE s) ON 30 tPHLZ tPLHZ W (n 2.0 |tPLHY - tPHLZ| TI E A K G S PA tPLHY O R 25 1.5 P |CROSSING PT. OF Y- AND Z¯ - CROSSING PT. OF Y¯ AND Z-| 20 1 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. DRIVER PROPAGATION DELAY vs TEMPERATURE FIGURE 13. DRIVER SKEW vs TEMPERATURE (ISL8485E) (ISL8485E) VER OUTPUT (V) 5 DI RO RDIFF = 54Ω, CL = 100pF 05 DRIVER INPUT (V) VER OUTPUT (V) 5 RDOI RDIFF = 54Ω, CL = 100pF 05 DRIVER INPUT (V) EI 0 EI 0 C C E E R R V) 4 V) 4 UT ( 3 B/Z UT ( 3 A/Y P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (400ns/DIV) TIME (400ns/DIV) FIGURE 14. DRIVER AND RECEIVER WAVEFORMS, FIGURE 15. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8483E) HIGH TO LOW (ISL8483E) OUTPUT (V) DI RDIFF = 54Ω, CL = 100pF 05 ER INPUT (V) OUTPUT (V) DI RDIFF = 54Ω, CL = 100pF 05 ER INPUT (V) VER 5 RO DRIV VER 5 RO DRIV EI 0 EI 0 C C E E R R V) 4 V) 4 T ( B/Z T ( A/Y U 3 U 3 P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (10ns/DIV) TIME (10ns/DIV) FIGURE 16. DRIVER AND RECEIVER WAVEFORMS, FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8485E) HIGH TO LOW (ISL8485E) FN6048 Rev.13.00 Page 11 of 15 Sep 24, 2018

ISL8483E, ISL8485E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure that you have the latest revision. DATE REVISION CHANGE Sept 24, 2018 FN6048.13 Updated the Ordering Information table by adding tape and reel information, removing part, and updating notes. Updated Typical Operating Circuits on page 2. Removed About Intersil section and updated disclaimer. Aug 31, 2017 FN6048.12 Updated Receiving Truth table on page 2. Applied Intersil A Renesas Company template. May 8, 2017 FN6048.11 Applied new header/footer Removed any mention of military version. Updated ordering information table on page2 as follows: Updated Note2, added Notes3, and 5. Sept 3, 2015 FN6048.10 - Ordering Information Table on page2. - Added Revision History. - Added About Intersil Verbiage. -Updated POD M8.15 to most current revision with changes as follows: -Revision 1 to Revision 2 Changes: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern -Revision 2 to Revision 3 Changes: Changed Note 1 "1982" to "1994" Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Revision 3 to Revision 4 Changes: Changed Note 1 "1982" to "1994" FN6048 Rev.13.00 Page 12 of 15 Sep 24, 2018

ISL8483E, ISL8485E Package Outline Drawings For the most recent package outline drawing, see M8.15. M8.15 8 lead narrow body small outline plastic package Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 17. Dimensioning and tolerancing per ANSI Y14.5M-1994. 18. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 19. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 20. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 21. Terminal numbers are shown for reference only. 22. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 23. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 24. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6048 Rev.13.00 Page 13 of 15 Sep 24, 2018

ISL8483E, ISL8485E For the most recent package outline drawing, see E8.3. N E1 IANRDEEAX 1 2 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE -B- INCHES MILLIMETERS -A- D E SYMBOL MIN MAX MIN MAX NOTES BASE PLANE A2 A - 0.210 - 5.33 4 -C- A SEATING A1 0.015 - 0.39 - 4 PLANE L CL A2 0.115 0.195 2.93 4.95 - D1 D1 A1 eA B 0.014 0.022 0.356 0.558 - B1 e eC C B1 0.045 0.070 1.15 1.77 8, 10 B e 0.010 (0.25) M C A B S B C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 NOTES: D1 0.005 - 0.13 - 5 1. Controlling Dimensions: INCH. In case of conflict between English E 0.300 0.325 7.62 8.25 6 and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. E1 0.240 0.280 6.10 7.11 5 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 e 0.100 BSC 2.54 BSC - of Publication No. 95. eA 0.300 BSC 7.62 BSC 6 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. eB - 0.430 - 10.92 7 5. D, D1, and E1 dimensions do not include mold flash or protrusions. L 0.115 0.150 2.93 3.81 4 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). N 8 8 9 6. E and eA are measured with the leads constrained to be Rev. 0 12/93 perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6048 Rev.13.00 Page 14 of 15 Sep 24, 2018

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