DATASHEET ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 FN6052 3.3V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers Rev.5.00 Nov 21, 2018 These Renesas RS-485/RS-422 devices are BiCMOS 3.3V Features powered, single transceivers that meet both the RS-485 and • Operate from a single +3.3V supply (10% tolerance) RS-422 standards for balanced communication. Unlike competitive devices, this Renesas family is specified for 10% • Interoperable with 5V logic tolerance supplies (3V to 3.6V). • High data rates. . . . . . . . . . . . . . . . . . . . . . up to 10Mbps The ISL83483 and ISL83488 use slew rate limited drivers • Single unit load allows up to 32 devices on the bus which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in • Slew rate limited versions for error free data transmission multidrop and multipoint applications. (ISL83483, ISL83488) . . . . . . . . . . . . . . . . .up to 250kbps • Low current Shutdown mode (ISL83483, ISL83485, Data rates up to 10Mbps are achievable by using the ISL83491). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15nA ISL83485, ISL83490, or ISL83491, which feature higher slew rates. • -7V to +12V common-mode input voltage range Logic inputs (for example, DI and DE) accept signals in • Three-state Rx and Tx outputs (except ISL83488, excess of 5.5V, making them compatible with 5V logic ISL83490) families. • 10ns propagation delay, 1ns skew (ISL83485, ISL83490, ISL83491) Receiver (Rx) inputs feature a “fail-safe if open” design, which ensures a logic high output if Rx inputs are floating. All • Full duplex and half duplex pinouts devices present a “single unit load” to the RS-485 bus, which • Current limiting and thermal shutdown for driver overload allows up to 32 transceivers on the network. protection Driver (Tx) outputs are short-circuit protected, even for • Pb-free (RoHS compliant) voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to Applications prevent damage if power dissipation becomes excessive. • Factory automation The ISL83488, ISL83490, and ISL83491 are configured for • Security networks full duplex (separate Rx input and Tx output pins) applications. The ISL83488 and ISL83490 are offered in • Building environmental control systems space saving 8Ld packages for applications not requiring Rx • Industrial/process control networks and Tx output disable functions (for example, point-to-point and RS-422). Half duplex configurations (ISL83483, • Level translators (for example, RS-232 to RS-422) ISL83485) multiplex the Rx inputs and Tx outputs to provide • RS-232 “Extension Cords” transceivers with Rx and Tx disable functions in 8 Ld packages. Related Literature For a full list of related documents, visit our website: • ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 device pages TABLE 1. SUMMARY OF FEATURES PART HALF/FULL DATA RATE SLEW-RATE RECEIVER/DRIVER QUIESCENT ICC LOW POWER NUMBER DUPLEX (Mbps) LIMITED? ENABLE? (mA) SHUTDOWN? PIN COUNT ISL83483 Half 0.25 Yes Yes 0.65 Yes 8 ISL83485 Half 10 No Yes 0.65 Yes 8 ISL83488 Full 0.25 Yes No 0.65 No 8 ISL83490 Full 10 No No 0.65 No 8 ISL83491 Full 10 No Yes 0.65 Yes 14 FN6052 Rev.5.00 Page 1 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Ordering Information PART NUMBER PART TAPE AND REEL PKG. (Notes2, 3) MARKING TEMP. RANGE (°C) (UNITS) (Note1) PACKAGE DWG. # ISL83483IBZ 83483 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IBZ-T 83483 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IBZ-T7A 83483 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IP (No longer available or supported) ISL 83483IP -40 to +85 - 8 Ld PDIP E8.3 ISL83485IBZ 83485 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83485IBZ-T 83485 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83485IBZ-T7A 83485 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15 ISL83488IBZ 83488 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83488IBZ-T 83488 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83490IBZ 83490 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83490IBZ-T 83490 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83491IBZ 83491IBZ -40 to +85 - 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IBZ-T 83491IBZ -40 to +85 2.5k 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IBZ-T7A 83491IBZ -40 to +85 250 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IP (No longer available, recommended ISL83491IP -40 to +85 - 14 Ld PDIP E14.3 replacement: ISL83491IBZ) NOTES: 1. Refer to TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), refer to the ISL83483, ISL83485, ISL83488, ISL83490, and ISL83491 device pages. For more information about MSL, refer to TB363. FN6052 Rev.5.00 Page 2 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Pinouts ISL83483, ISL83485 (PDIP, SOIC) ISL83488, ISL83490 (SOIC) ISL83491 (PDIP, SOIC) TOP VIEW TOP VIEW TOP VIEW RO 1 R 8 VCC VCC 1 R 8 A NC 1 14 VCC RE 2 7 B/Z RO 2 7 B RO 2 13 VCC R DE 3 6 A/Y DI 3 6 Z RE 3 12 A DI 4 D 5 GND GND 4 D 5 Y DE 4 11 B DI 5 D 10 Z GND 6 9 Y GND 7 8 NC NOTE: PDIP packages are no longer supported Truth Tables TRANSMITTING RECEIVING INPUTS OUTPUTS INPUTS OUTPUT RE DE DI Z Y RE DE DE A-B RO Half Duplex Full Duplex X 1 1 0 1 0 0 X ≥ +0.2V 1 X 1 0 1 0 0 0 X ≤ -0.2V 0 0 0 X High-Z High-Z 0 0 X Inputs Open 1 1 0 X High-Z * High-Z * 1 0 0 X High-Z * NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491 1 1 1 X High-Z NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491 Pin Descriptions PIN FUNCTION RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y Noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. A Noninverting receiver input. B Inverting receiver input. Y Noninverting driver output. Z Inverting driver output. VCC System power supply input (3V to 3.6V). NC No Connection. FN6052 Rev.5.00 Page 3 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Typical Operating Circuits For calculating the resistor values refer to TB509, “Detecting Bus Signals Correctly with Failsafe Biased RS-485 Receivers” 3.3V 3.3V 8 100nF 100nF 8 RPU VCC VCC RPU 1 RO RB RO 1 A/Y 6 6 A/Y 2 RE RE 2 3 DE B/Z 7 RT2 VFS RT1 7 B/Z DE 3 4 DI DI 4 RB GND GND 5 5 FIGURE 1. ISL83483, ISL83485 3.3V 3.3V 1 100nF 100nF 1 VCC VCC A 8 5 Y 2 RO DI 3 RT B 7 6 Z Z 6 7 B 3 DI RO 2 RT Y 5 8 A GND GND 4 4 FIGURE 2. ISL83488, ISL83490 3.3V 3.3V 13, 14 100nF 100nF 13,14 RPU VCC RB RB VCC RPU A 12 9 Y 2 RO DI 5 RT 3 RE B 11 10 Z DE 4 4 DE Z 10 11 B RE 3 5 DI RO 2 RT Y 9 12 A GND GND 6, 7 RB RB 6, 7 FIGURE 3. ISL83491 FN6052 Rev.5.00 Page 4 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Thermal Resistance (Typical, Note4) θJA (°C/W) Input Voltages 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . 170 DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V 8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . 140 Input/Output Voltages 14 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . 130 A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V 14 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 105 RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C Short-Circuit Duration Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Pb-Free Reflow Profile (SOIC only). . . . . . . . . . . . . . . . . see TB493 *Pb-free PDIPs can be used for through hole wave solder Operating Conditions processing only. They are not intended for use in Reflow solder Temperature Range processing applications. ISL834xxIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379. Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note5. TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT DC CHARACTERISTICS Driver Differential VOUT (no load) VOD1 Full - - VCC V Driver Differential VOUT (with load) VOD2 RL = 100Ω (RS-422) (Figure4A) Full 2 2.7 - V RL = 54Ω (RS-485) (Figure4A) Full 1.5 2.3 VCC V RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure4B) Full 1.5 2.6 - V Change in Magnitude of Driver ΔVOD RL = 54Ω or 100Ω (Figure4A) Full - 0.01 0.2 V Differential VOUT for Complementary Output States Driver Common-Mode VOUT VOC RL = 54Ω or 100Ω (Figure4A) Full - 1.8 3 V Change in Magnitude of Driver ΔVOC RL = 54Ω or 100Ω (Figure4A) Full - 0.01 0.2 V Common-Mode VOUT for Complementary Output States Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V Logic Input Current IIN1 DE, DI Full -2 - 2 µA RE Full -25 - 25 µA Input Current (A, B) IIN2 DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.6 1 mA VIN = -7V Full - -0.3 -0.8 mA Output Leakage Current (Y, Z) IIN3 RE = 0V, DE = 0V, VCC= 0V or 3.6V VIN = 12V Full - 14 20 µA (ISL83491) VIN = -7V Full -20 -11 - µA Output Leakage Current (Y, Z) IIN3 RE = VCC, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.03 1 µA in Shutdown Mode (ISL83491) VIN = -7V Full -1 -0.01 - µA Receiver Differential Threshold VTH -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V Voltage Receiver Input Hysteresis ΔVTH VCM = 0V +25 - 50 - mV Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full VCC - - - V 0.4 Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V FN6052 Rev.5.00 Page 5 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note5. (Continued) TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT Three-State (high impedance) IOZR 0.4V ≤ VO ≤ 2.4V Full -1 - 1 µA Receiver Output Current Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full 12 19 - kΩ No-Load Supply Current (Note6) ICC DI = 0V or VCC DE = VCC, Full - 0.75 1.2 mA RE = 0V or VCC DE = 0V, Full - 0.65 1 mA RE = 0V Shutdown Supply Current ISHDN DE = 0V, RE = VCC, DI = 0V or VCC Full - 15 100 nA (Except ISL83488 and ISL83490) Driver Short-Circuit Current, IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note7) Full - - 250 mA VO = High or Low Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full 8 - 60 mA DRIVER SWITCHING CHARACTERISTICS (ISL83485, ISL83490, ISL83491) Maximum Data Rate fMAX Full 12 15 - Mbps Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure5A) Full 1 10 35 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 60Ω, CL = 15pF (Figure5A) Full 3 5 20 ns Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure5C) Full 6 10 35 ns Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure5C) Full - 1 8 ns Driver Enable to Output High tZH RL = 110Ω, CL = 50pF, SW = GND (Figure6), Full - 45 90 ns (Except ISL83490) (Note8) Driver Enable to Output Low tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure6), Full - 45 90 ns (Except ISL83490) (Note8) Driver Disable from Output High tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure6) +25 - 65 80 ns (Except ISL83490) Full - - 110 ns Driver Disable from Output Low tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure6) +25 - 65 80 ns (Except ISL83490) Full - - 110 ns Driver Enable from Shutdown to tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Figure6), Full - 115 150 ns Output High (Except ISL83490) (Notes10, 11) Driver Enable from Shutdown to tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure6), Full - 115 150 ns Output Low (Except ISL83490) (Notes10, 11) DRIVER SWITCHING CHARACTERISTICS (ISL83483, ISL83488) Maximum Data Rate fMAX Full 250 - - kbps Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure5A) Full 600 930 1400 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 60Ω, CL = 15pF (Figure5A) Full 400 900 1200 ns Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure5C) +25 600 930 1500 ns Full 400 - 1500 ns Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure5C) Full - 140 - ns Driver Enable to Output High tZH RL = 110Ω, CL = 50pF, SW = GND (Figure6), Full - 385 800 ns (Except ISL83488) (Note8) Driver Enable to Output Low tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure6), Full - 55 800 ns (Except ISL83488) (Note8) Driver Disable from Output High tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure6) +25 - 63 80 ns (Except ISL83488) Full - - 110 ns FN6052 Rev.5.00 Page 6 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note5. (Continued) TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT Driver Disable from Output Low tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure6) +25 - 70 80 ns (Except ISL83488) Full - - 110 ns Driver Enable from Shutdown to tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes10, 11) Full - 450 2000 ns Output High (Except ISL83488) Driver Enable from Shutdown to tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure6), Full - 126 2000 ns Output Low (Except ISL83488) (Notes10, 11) RECEIVER SWITCHING CHARACTERISTICS (All Versions) Receiver Input to Output Delay tPLH, tPHL (Figure7) Full 25 45 90 ns Receiver Skew | tPLH - tPHL | tSKD (Figure7) +25 - 2 10 ns Full - 2 12 ns Receiver Enable to Output High tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure8), Full - 11 50 ns (Except ISL83488 and ISL83490) (Note9) Receiver Enable to Output Low tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure8), Full - 11 50 ns (Except ISL83488 and ISL83490) (Note9) Receiver Disable from Output High tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure8) Full - 7 45 ns (Except ISL83488 and ISL83490) Receiver Disable from Output Low tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure8) Full - 7 45 ns (Except ISL83488 and ISL83490) Time to Shutdown tSHDN (Note10) Full 80 190 300 ns (Except ISL83488 and ISL83490) Receiver Enable from Shutdown to tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure8), Full - 240 600 ns Output High (Notes10, 11) (Except ISL83488 and ISL83490) Receiver Enable from Shutdown to tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure8), Full - 240 600 ns Output Low (Notes10, 11) (Except ISL83488 and ISL83490) NOTES: 5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 6. Supply current specification is valid for loaded drivers when DE = 0V. 7. Applies to peak current. See “Typical Performance Curves” on page11 for more information. 8. When testing the ISL83483, ISL83485, and ISL83491, keep RE = 0 to prevent the device from entering SHDN. 9. When testing the ISL83483, ISL83485, and ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN. 10. The ISL83483, ISL83485, and ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, the parts are ensured not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are ensured to have entered shutdown. See “Low Power Shutdown Mode (ISL83483, ISL83485, ISL83491 Only)” on page11. 11. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN. 12. Set the RE signal high time >300ns to ensure that the device enters SHDN. FN6052 Rev.5.00 Page 7 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Test Circuits and Waveforms RL/2 375Ω DE DE VCC VCC DI Z DI Z VCM D VOD D VOD RL = 60Ω -7V to +12V Y Y RL/2 VOC 375Ω FIGURE 4A. VOD AND VOC FIGURE 4B. VOD WITH COMMON MODE LOAD FIGURE 4. DC DRIVER TEST CIRCUITS 3V CL = 15pF DI 1.5V 1.5V 3V DE 0V Z DI D RDIFF = 60Ω tPLH tPHL Y CL = 15pF VOH OUT (Y) 50% 50% SGIEGNNEARLATOR VOL tPHL tPLH VOH FIGURE 5A. DIFFERENTIAL TEST CIRCUIT OUT (Z) 50% 50% VOL OUT tDD tDD 3V DE 90% 90% +VOD DI Z RL = 27Ω DIFF OUT (Y - Z) 105%0% 5100%% D VOM -VOD Y tR tF CL = 15pF SIGNAL SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| GENERATOR VOH + VOL VOM = ≈1.5V 2 FIGURE 5C. SINGLE ENDED TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES FN6052 Rev.5.00 Page 8 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Test Circuits and Waveforms (Continued) DE DI Z 110Ω VCC 3V D SIGNAL Y SW GND DE 1.5V 1.5V GENERATOR CL = 50pF Note10 0V tZH, tZH(SHDN) tHZ Note10 OUTPUT HIGH PARAMETER OUTPUT RE DI SW VOH - 0.25VVOH OUT (Y, Z) 50% tHZ Y/Z X 1/0 GND 0V tLZ Y/Z X 0/1 VCC tZL, tZL(SHDN) tLZ tZH Y/Z 0 (Note8) 1/0 GND Note10 VCC tZL Y/Z 0 (Note8) 0/1 VCC OUT (Y, Z) 50% tZH(SHDN) Y/Z 1 (Note11) 1/0 GND OUTPUT LOW VOL + 0.25VVOL tZL(SHDN) Y/Z 1 (Note11) 0/1 VCC FIGURE 6B. MEASUREMENT POINTS FIGURE 6A. TEST CIRCUIT FIGURE 6. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490) RE 3V GND 15pF B A 1.5V 1.5V +1.5V RO A R 0V tPLH tPHL SIGNAL VCC GENERATOR RO 50% 50% 0V FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FIGURE 7. RECEIVER PROPAGATION DELAY RE GND B RO 1kΩ VCC Note10 A R 3V SIGNAL SW GND RE 1.5V 1.5V GENERATOR 15pF 0V tZH, tZH(SHDN) tHZ Note10 OUTPUT HIGH PARAMETER DE A SW VOH - 0.25VVOH tHZ 0 +1.5V GND RO 1.5V 0V tLZ 0 -1.5V VCC tZH (Note9) 0 +1.5V GND tZL, tZL(SHDN) tLZ Note10 tZL (Note9) 0 -1.5V VCC VCC RO 1.5V tZH(SHDN) (Note12) 0 +1.5V GND VOL + 0.25VVOL tZL(SHDN) (Note12) 0 -1.5V VCC OUTPUT LOW FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMENT POINTS FIGURE 8. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490) FN6052 Rev.5.00 Page 9 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Application Information faster output transition times allow data rates of at least 10Mbps. RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy Data Rate, Cables, and Terminations environments. RS-422 is a subset of RS-485, so RS-485 RS-485 and RS-422 are intended for network lengths up to transceivers are also RS-422 compliant. RS-422 is a 4000’, but the maximum system data rate decreases as the point-to-multipoint (multidrop) standard, which allows only one transmission length increases. Devices operating at 10Mbps driver and up to 10 (assuming one unit load devices) receivers are limited to lengths of a few hundred feet, while the 250kbps on each bus. RS-485 is a true multipoint standard, which versions can operate at full data rates with lengths in excess of allows up to 32 one unit load devices (any combination of 1000’. drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers must Twisted pair is the cable of choice for RS-485 and RS-422 handle bus contention without sustaining any damage. networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common-mode Another important advantage of RS-485 is the extended signals, which are effectively rejected by the differential Common-Mode Range (CMR), which specifies that the driver receivers in these ICs. outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long Proper termination is imperative, when using the 10Mbps as 4000’, so the wide CMR is necessary to handle ground devices, to minimize reflections. Short networks using the potential differences, as well as voltages induced in the cable 250kbps versions need not be terminated, but, terminations by external fields. are recommended unless power dissipation is an overriding concern. Receiver Features In point-to-point, or point-to-multipoint (single driver on bus) These devices use a differential input receiver for maximum networks, the main cable should be terminated in its noise immunity and common-mode rejection. Input sensitivity is characteristic impedance (typically 120Ω) at the end farthest ±200mV, as required by the RS422 and RS-485 specifications. from the driver. In multi-receiver applications, stubs connecting Receiver input impedance surpasses the RS-422 spec of 4kΩ, receivers to the main cable should be kept as short as and meets the RS-485 “Unit Load” requirement of 12kΩ possible. Multipoint (multi-driver) systems require that the main minimum. cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should Receiver inputs function with common-mode voltages as great be kept as short as possible. as +9V/-7V outside the power supplies (that is, +12V and -7V), making them ideal for long networks where induced voltages Built-In Driver Overload Protection are a realistic concern. As stated previously, the RS-485 specification requires that All the receivers include a “fail-safe if open” function that drivers survive worst case bus contentions undamaged. The ensures a high level receiver output if the receiver inputs are ISL834xx devices meet this requirement through driver output unconnected (floating). short-circuit current limits, and on-chip thermal shutdown circuitry. Receivers easily meet the data rates supported by the corresponding driver. The driver output stages incorporate short-circuit current limiting circuitry, which ensures that the output current never ISL83483, ISL83485, ISL83491 receiver outputs are tri-statable exceeds the RS-485 specification, even at the common-mode using the active low RE input. voltage range extremes. Additionally, these devices use a Driver Features foldback circuit which reduces the short-circuit current, and thus the power dissipation, whenever the contending voltage The RS-485, RS-422 driver is a differential output device that exceeds either supply. delivers at least 1.5V across a 54Ω load (RS-485), and at least 2V across a 100Ω load (RS-422) even with VCC=3V. The In the event of a major short-circuit condition, the ISL834xx drivers feature low propagation delay skew to maximize bit devices also include a thermal shutdown feature that disables width, and to minimize EMI. the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. Drivers of the ISL83483, ISL83485, and ISL83491 are The drivers automatically re-enable after the die temperature tri-statable using the active high DE input. drops about 15°. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. ISL83483 and ISL83488 driver outputs are slew rate limited to Receivers stay operational during thermal shutdown. minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Data rate on these slew rate limited versions is a maximum of 250kbps. Outputs of ISL83485, ISL83490, and ISL83491 drivers are not limited, so FN6052 Rev.5.00 Page 10 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Low Power Shutdown Mode (ISL83483, ISL83485, period of at least 300ns. Disabling both the driver and the ISL83491 Only) receiver for less than 80ns ensures that shutdown is not entered. These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but the ISL83483, Note that receiver and driver enable times increase when ISL83485, and ISL83491 include a shutdown feature that these devices enable from shutdown. For more information reduces the already low quiescent ICC to a 15nA trickle. They refer to Notes8 through 12 on page7 at the end of the enter shutdown whenever the receiver and driver are Electrical Specification table. simultaneously disabled (RE=VCC and DE=GND) for a Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified 110 2.9 100 V) A) E ( 2.8 m 90 G RDIFF = 100Ω NT ( 80 LTA 2.7 RE 70 VO 2.6 R T CU 60 PU 2.5 UT 50 UT P O 2.4 UT 40 AL R O 30 NTI 2.3 RDIFF = 54Ω VE 20 RE 2.2 RI E D 10 FF 2.1 DI 0 2 0 0.5 1 1.5 2 2.5 3 3.5 -40 -25 0 25 50 75 85 DIFFERENTIAL OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 9. DRIVER OUTPUT CURRENT vs DIFFERENTIAL FIGURE 10. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT VOLTAGE TEMPERATURE 160 800 140 120 Y OR Z = LOW ISL83483/85, DE = VCC, RE = X 100 750 A) 80 m 60 T ( EN 40 A) CURR 200 I (µCC 700 T -20 ISL83483/85, DE = RE = GND; ISL83491, DE = X, RE = GND; PU Y OR Z = HIGH ISL83488/90 UT -40 650 O -60 -80 -100 -120 600 -7 -6 -4 -2 0 2 4 6 8 10 12 -40 -25 0 25 50 75 85 OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 11. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT FIGURE 12. SUPPLY CURRENT vs TEMPERATURE VOLTAGE FN6052 Rev.5.00 Page 11 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued) 1200 300 RDIFF = 54Ω RDIFF = 54Ω |tPHLY - tPLHZ| Figure5A 250 1100 ns) tPLHZ tPLHY |tPLHY - tPHLZ| Y ( 200 A EL 1000 s) D n N W ( 150 TIO tPHLY KE A 900 S G PA tPHLZ 100 O R P 800 50 |CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑| 700 0 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 13. DRIVER PROPAGATION DELAY vs FIGURE 14. DRIVER SKEW vs TEMPERATURE TEMPERATURE (ISL83483, ISL83488) (ISL83483, ISL83488) 16 4 RDIFF = 54Ω RDIFF = 54Ω 15 Figure5A 3.5 s) 14 tPLHZ |tPHLY - tPLHZ| n 3 Y ( A 13 L E 2.5 D N 12 tPLHY s) O n ATI W ( 2 G 11 E A K OP tPHLY S 1.5 PR 10 tPHLY |CROSSING PT. OF Y↑ & Z↓ - CROSSING PT. OF Y↓ & Z↑| 9 1 tPHLZ |tPLHY - tPHLZ| 8 0.5 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 15. DRIVER PROPAGATION DELAY vs FIGURE 16. DRIVER SKEW vs TEMPERATURE TEMPERATURE (ISL83485, ISL83490, ISL83491) (ISL83485, ISL84390, ISL83491) EIVER OUTPUT (V) 05 DI RO RDIFF = 54Ω, CL = 15pF 05 DRIVER INPUT (V) EIVER OUTPUT (V) 05 DI RO RDIFF = 54Ω, CL = 15pF 05 DRIVER INPUT (V) C C E E R R V) 3 V) 3 PUT (2.25 B/Z PUT (2.25 A/Y T T U1.5 U1.5 O O ER 1 A/Y ER 1 B/Z V0.5 V0.5 DRI 0 DRI 0 TIME (400ns/DIV) TIME (400ns/DIV) FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, FIGURE 18. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83483, ISL83488) HIGH TO LOW (ISL83483, ISL83488) FN6052 Rev.5.00 Page 12 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued) CEIVER OUTPUT (V) 05 DI RO RDIFF = 54Ω, CL = 15pF 05 DRIVER INPUT (V) CEIVER OUTPUT (V) 05 DI RDIFF = 5R4OΩ, CL = 15pF 05 DRIVER INPUT (V) E E R R V) 3 V) 3 PUT (2.25 B/Z PUT (2.25 A/Y UT1.5 UT1.5 O O VER 0.15 A/Y VER 0.15 B/Z DRI 0 DRI 0 TIME (10ns/DIV) TIME (10ns/DIV) FIGURE 19. DRIVER AND RECEIVER WAVEFORMS, FIGURE 20. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83485, ISL83490, ISL83491) HIGH TO LOW (ISL83485, ISL83490, ISL83491) Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 528 PROCESS: Si Gate CMOS FN6052 Rev.5.00 Page 13 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Nov 21, 2018 FN6052.5 Updated part marking in the ordering information table to represent what the brand has been on the products. Added PDIP note in the thermal information section and specified the Pb-free reflow note is applicable to SOIC pages only. Updated disclaimer. Jul 27, 2018 FN6052.4 Added Related Literature on page 1. Updated Ordering Information table. Removed Retired parts, added tape and reel quantity column, and added MSL note. Updated Typical Operating Circuits on page 4. Thermal Information on page 5: Removed Maximum Lead Temperature (Soldering 10s)+300°C (SOIC - Lead Tips Only) Added Pb-Free Reflow information Updated POD M8.15 from rev 0 to rev 4. Changes since rev 0: Removed "u" symbol from drawing (overlaps the "a" on Side View). Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Changed Note 1 "1982" to "1994" Updated POD M14.15 from rev 0 to rev 1. Changes since rev 0: Added land pattern and moved dimensions from table onto drawing Added Revision History. Updated disclaimer. FN6052 Rev.5.00 Page 14 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Package Outline Drawings For the most recent package outline drawing, see E8.3. E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 13. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 14. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 15. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 16. Dimensions A, A1 and L are measured with the package seated N 8 8 9 in JEDEC seating plane gauge GS-3. Rev. 0 12/93 17. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 18. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 19. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 20. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 21. N is the maximum number of terminal positions. 22. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6052 Rev.5.00 Page 15 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 For the most recent package outline drawing, see E14.3. N E1 E14.3 (JEDEC MS-001-AA ISSUE D) INDEX 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE AREA 1 2 3 N/2 INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES -A- D E A - 0.210 - 5.33 4 BASE A1 0.015 - 0.39 - 4 PLANE A2 -C- A A2 0.115 0.195 2.93 4.95 - SEATING PLANE L CL B 0.014 0.022 0.356 0.558 - D1 D1 A1 eA B1 0.045 0.070 1.15 1.77 8 B1 e eC C C 0.008 0.014 0.204 0.355 - B eB D 0.735 0.775 18.66 19.68 5 0.010 (0.25) M C A B S D1 0.005 - 0.13 - 5 NOTES: E 0.300 0.325 7.62 8.25 6 1. Controlling Dimensions: INCH. In case of conflict between English E1 0.240 0.280 6.10 7.11 5 and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. e 0.100 BSC 2.54 BSC - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eA 0.300 BSC 7.62 BSC 6 Publication No. 95. eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in L 0.115 0.150 2.93 3.81 4 JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. N 14 14 9 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). Rev. 0 12/93 6. E and eA are measured with the leads constrained to be perpen- dicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6052 Rev.5.00 Page 16 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 M8.15 For the most recent package outline drawing, see M8.15. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6052 Rev.5.00 Page 17 of 19 Nov 21, 2018

ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 M14.15 For the most recent package outline drawing, see M14.15. 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 4 0.10CA-B2X 8.65 A 3 6 DETAIL"A" 0.22±0.03 14 8 D 6.0 3.9 4 0.10CD2X PIN NO.1 7 0.20C2X ID MARK (0.35) x 45° 4° ± 4° 5 0.31-0.51 B 3 6 0.25MCA-B D TOP VIEW 0.10C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C 1.27 0.10-0.25 SEATING PLANE 0.10C SIDE VIEW DETAIL "A" (1.27) (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. 6. Does not include dambar protrusion. Allowable dambar protrusion (1.50) shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN FN6052 Rev.5.00 Page 18 of 19 Nov 21, 2018

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