DATASHEET ISL83080E/82E/83E/84E/85E/86E/88E FN6085 ±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers Rev 10.00 February 15, 2016 The ISL8308xE are BiCMOS, ESD protected, 5V powered, Features single transceivers that meet both the RS-485 and RS-422 • Pb-Free Available (RoHS Compliant) standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strikes • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM without latch-up, and unlike competitive products, this Intersil Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV family is specified for 10% tolerance supplies (4.5V to 5.5V). • Tiny MSOP Packages Save 50% Board Space These devices have very low bus currents (+125µA/-75µA), • Full Fail-Safe (Open, Short, Terminated and Floating) so they present a true “1/8 unit load” to the RS-485 bus. This Receivers allows up to 256 transceivers on the network without violating • Hot Plug Circuitry (ISL83080E, ISL83082E, ISL83083E, the RS-485 specification’s 32 unit load maximum, and without ISL83085E) using repeaters. For example, in a remote utility meter reading - Tx and Rx Outputs Remain Three-state During system, individual meter readings are routed to a concentrator Power-up/Power-down via an RS-485 network, so the high allowed node count minimizes the number of repeaters required. Data for all • True 1/8 Unit Load Allows up to 256 Devices on the Bus meters is then read out from the concentrator via a single • Specified for Single 5V, 10% Tolerance, Supplies access port, or a wireless link. • High Data Rates. . . . . . . . . . . . . . . . . . . . . up to 10Mbps Receiver (Rx) inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, • Low Quiescent Supply Current . . . . . . . . . . . . . . . 530µA Ultra Low Shutdown Supply Current . . . . . . . . . . . . 70nA shorted, or terminated but undriven. • -7V to +12V Common Mode Input Voltage Range The ISL83080E, ISL83082E, ISL83083E, ISL83084E, ISL83085E utilize slew rate limited drivers which reduce EMI, • Half and Full Duplex Pinouts and minimize reflections from improperly terminated • Three-State Rx and Tx Outputs (Except ISL83084E) transmission lines, or unterminated stubs in multidrop and multipoint applications. Slew rate limited versions also include • Current Limiting and Thermal Shutdown for driver receiver input filtering to enhance noise immunity in the Overload Protection presence of slow input signals. Applications Hot Plug circuitry ensures that the Tx and Rx outputs remain • Automated Utility Meter Reading Systems in a high impedance state until the power supply has stabilized, and the Tx outputs are fully short circuit protected. • High Node Count Systems The ISL83080E, ISL83083E, ISL83084E, ISL83086E are • Factory Automation configured for full duplex (separate Rx input and Tx output • Field Bus Networks pins) applications. The half duplex versions multiplex the Rx inputs and Tx outputs to allow transceivers with output • Security Camera Networks disable functions in 8 Ld packages. • Building Environmental Control Systems • Industrial/Process Control Networks FN6085 Rev 10.00 Page 1 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E TABLE 1. SUMMARY OF FEATURES DATA SLEW- # HALF/FULL RATE RATE HOT DEVICES Rx/Tx QUIESCEN LOW POWER PIN PART NUMBER DUPLEX (Mbps) LIMITED? PLUG ON BUS ENABLE? T ICC (µA) SHUTDOWN? COUNT ISL83080E Full 0.115 Yes Yes 256 Yes 530 Yes 10, 14 ISL83082E Half 0.115 Yes Yes 256 Yes 530 Yes 8 ISL83083E Full 0.5 Yes Yes 256 Yes 530 Yes 10, 14 ISL83084E Full 0.5 Yes No 256 No 530 No 8 (No longer available orsupported) ISL83085E Half 0.5 Yes Yes 256 Yes 530 Yes 8 ISL83086E Full 10 No No 256 Yes 530 Yes 10, 14 ISL83088E Half 10 No No 256 Yes 530 Yes 8 Pinouts ISL83082E, ISL83085E, ISL83088E ISL83084E (8 LD MSOP, SOIC) (8 LD SOIC) TOP VIEW TOP VIEW RRDDOEEI 1234 DR 8765 VBAGC//NZYCD NO LONGVGRNCDODCEIR1234 AVAILDRABLE OR 8765SUABZYPPORTED ISL83080E, ISL83083E, ISL83086E ISL83080E, ISL83083E, ISL83086E (10 LD MSOP) (14 LD SOIC) TOP VIEW TOP VIEW RO 1 10 VCC NC 1 14 VCC R RE 2 9 A RO 2 13 NC R DE 3 8 B RE 3 12 A DI 4 D 7 Z DE 4 11 B GND 5 6 Y DI 5 D 10 Z GND 6 9 Y GND 7 8 NC FN6085 Rev 10.00 Page 2 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Ordering Information PACKAGE PART NUMBER (Note 1) PART MARKING TEMP. RANGE (°C) (RoHS Compliant) PKG. DWG. # ISL83080EIBZ (Note 2) 83080EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83080EIUZ (Note 2) 3080Z -40 to +85 10 Ld MSOP M10.118 ISL83082EIBZ (Note 2) 83082 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83082EIUZ (Note 2) 3082Z -40 to +85 8 Ld MSOP M8.118 ISL83083EIBZ (Note 2) 83083EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83083EIUZ (Note 2) 3083Z -40 to +85 10 Ld MSOP M10.118 ISL83084EIBZ (Note 2) 83084 EIBZ -40 to +85 8 Ld SOIC M8.15 (No longer available or supported, Recommended Replacements ISL83080EIBZ or ISL83088EIBZ) ISL83085EIBZ (Note 2) 83085 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83085EIUZ (Note 2) 3085Z -40 to +85 8 Ld MSOP M8.118 ISL83086EIBZ (Note 2) 83086EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83086EIUZ (Note 2) 3086Z -40 to +85 10 Ld MSOP M10.118 ISL83088EIBZ (Note 2) 83088 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83088EIUZ (Note 2) 3088Z -40 to +85 8 Ld MSOP M8.118 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. Truth Tables RECEIVING TRANSMITTING INPUTS OUTPUT INPUTS OUTPUTS RE DE DE A-B RO Half Duplex Full Duplex RE DE DI Z Y 0 0 X  -0.05V 1 X 1 1 0 1 0 0 X  -0.2V 0 X 1 0 1 0 0 0 X Inputs 1 0 0 X High-Z High-Z Open/Shorted 1 0 X High-Z * High-Z* 1 0 0 X High-Z* NOTE: *Shutdown Mode (See Notes 10 and 13). 1 1 1 X High-Z NOTE: *Shutdown Mode (See Notes 10 and 13). Pin Descriptions PIN FUNCTION RO Receiver output: If A - B  -50mV, RO is high; If A - B  -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted. RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. FN6085 Rev 10.00 Page 3 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Pin Descriptions (Continued) PIN FUNCTION DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. B/Z ±15kV HBM ESD Protected RS-485/RS-422 level, Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE=1. A ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input. B ±15kV HBM ESD Protected RS-485/RS-422 level, inverting receiver input. Y ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting driver output. Z ±15kV HBM ESD Protected RS-485/RS-422 level, inverting driver output. VCC System power supply input (4.5V to 5.5V). NC No Connection. Typical Operating Circuit ISL83082E, ISL83085E, ISL83088E +5V +5V + + 0.1µF 0.1µF 8 8 VCC VCC 1 RO R D DI 4 2 RE B/Z 7 RT RT 7 B/Z DE 3 3 DE A/Y 6 6 A/Y RE 2 4 DI RO 1 D R GND GND 5 5 FN6085 Rev 10.00 Page 4 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Typical Operating Circuit (Continued) ISL83080E, ISL83083E, ISL83086E +5V +5V + + 0.1µF 0.1µF 14 14 VCC A 12 RT 9 Y VCC 2 RO DI 5 R B 11 10 Z D 3 RE DE 4 4 DE RE 3 Z 10 RT 11 B 5 DI RO 2 D Y 9 12 A R GND GND 6, 7 6, 7 ISL83084E +5V +5V + + 0.1µF 0.1µF 1 1 VCC VCC A 8 RT 5 Y 2 RO DI 3 R B 7 6 Z D Z 6 RT 7 B 3 DI RO 2 D Y 5 8 A R GND GND 4 4 FN6085 Rev 10.00 Page 5 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Thermal Resistance (Typical, Note 3) JA (°C/W) Input Voltages 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . 105 DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 140 Input/Output Voltages 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 190 A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V to +13V 14 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . 128 A, B, Y, Z (Transient Pulse Through 100, Note 14) . . . . . . ±75V Maximum Junction Temperature (Plastic Package) . . . . . . +150°C RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Short Circuit Duration Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous http://www.intersil.com/pbfree/Pb-FreeReflow.asp ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note5). TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note 4) TYP (Note 4) UNITS DC CHARACTERISTICS Driver Differential VOUT (no load) VOD1 Full - - VCC V Driver Differential VOUT (with load) VOD2 RL = 100 (RS-422) (Figure 1A) Full 2 2.9 - V RL = 54 (RS-485) (Figure 1A) Full 1.5 2.4 VCC V RL = 60, -7V  VCM  12V (Figure 1B) Full 1.5 2.6 - V Change in Magnitude of Driver VOD RL = 54 or 100 (Figure 1A) Full - 0.01 0.2 V Differential VOUT for Complementary Output States Driver Common-Mode VOUT VOC RL = 54 or 100 (Figure 1A) Full - 2.85 3 V Change in Magnitude of Driver VOC RL = 54 or 100 (Figure 1A) Full - 0.01 0.1 V Common-Mode VOUT for Complementary Output States Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V DI Input Hysteresis Voltage VHYS 25 - 100 - mV Logic Input Current IIN1 DE, DI, RE Full -2 - 2 µA Input Current (A, B) IIN2 DE = 0V, VCC = 0V or 5.5V VIN = 12V Full - 70 125 µA VIN = -7V Full -75 55 - µA Output Leakage Current (Y, Z) (Full IIN3 RE = 0V, DE = 0V, VCC = 0V VIN = 12V Full - 7 125 µA Duplex Versions Only) or 5.5V (Note 13) VIN = -7V Full -75 11 - µA Output Leakage Current (Y, Z) IIN3 RE = VCC, DE = 0V, VIN = 12V Full - 0 20 µA in Shutdown Mode (Full Duplex) VCC=0V or 5.5V (Note 13) VIN = -7V Full -20 9 - µA Driver Short-Circuit Current, IOSD1 DE = VCC, -7V  VY or VZ  12V (Note 7) Full - - 250 mA VO = High or Low FN6085 Rev 10.00 Page 6 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note5). (Continued) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note 4) TYP (Note 4) UNITS Receiver Differential Threshold VTH -7V  VCM  12V Full -200 -90 -50 mV Voltage Receiver Input Hysteresis VTH VCM = 0V 25 - 20 - mV Receiver Output High Voltage VOH IO = -4mA, VID = -50mV Full VCC - 1 4.6 - V Receiver Output Low Voltage VOL IO = -4mA, VID = -200mV Full - 0.2 0.4 V Three-State (high impedance) IOZR 0.4V  VO  2.4V (Note 13) Full -1 0.03 1 µA Receiver Output Current Receiver Input Resistance RIN -7V  VCM  12V Full 96 160 - k Receiver Short-Circuit Current IOSR 0V  VO  VCC Full ±7 - ±85 mA SUPPLY CURRENT No-Load Supply Current (Note 6) ICC Half Duplex Versions, DE = VCC, RE = X, Full - 560 700 µA DI = 0V or VCC All Versions, DE = 0V, RE = 0V, or Full Duplex Full - 530 650 µA Versions, DE = VCC, RE = X. DI = 0V or VCC Shutdown Supply Current ISHDN DE = 0V, RE = VCC, DI = 0V or VCC (Note 13) Full - 0.07 2 µA ESD PERFORMANCE RS-485 Pins (A, Y, B, Z) Human Body Model (HBM), Pin to GND 25 - ±15 - kV All Other Pins HBM, per MIL-STD-883 Method 3015 25 - ±7 - kV Machine Model 25 - ±250 - V DRIVER SWITCHING CHARACTERISTICS (115kbps Versions; ISL83080E, ISL83082E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full 500 780 1300 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 40 100 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full 667 1000 1500 ns Maximum Data Rate fMAX CD = 820pF (Figure 4) (Note 15) Full 115 666 - kbps Driver Enable to Output High tZH RL = 500, CL = 100pF, SW = GND (Figure 3), Full - 278 1500 ns (Note 8) Driver Enable to Output Low tZL RL = 500, CL = 100pF, SW = VCC (Figure 3) Full - 35 1500 ns (Note 8) Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3) Full - 67 100 ns Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns Time to Shutdown tSHDN (Note 10) Full 60 160 600 ns Driver Enable from Shutdown to tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3) Full - 400 2000 ns Output High (Notes 10, 11) Driver Enable from Shutdown to tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3) Full - 155 2000 ns Output Low (Notes 10, 11) DRIVER SWITCHING CHARACTERISTICS (500kbps Versions; ISL83083E, ISL83084E, ISL83085E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full 250 360 1000 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 20 100 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full 200 475 750 ns Maximum Data Rate fMAX CD = 820pF (Figure 4) (Note 15) Full 500 1000 - kbps FN6085 Rev 10.00 Page 7 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note5). (Continued) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note 4) TYP (Note 4) UNITS Driver Enable to Output High tZH RL = 500, CL = 100pF, SW = GND (Figure 3), Full - 137 1000 ns (Notes 8, 13) Driver Enable to Output Low tZL RL = 500, CL = 100pF, SW = VCC (Figure 3), Full - 35 1000 ns (Notes 8, 13) Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3), Full - 65 100 ns (Note 13) Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3), Full - 38 100 ns (Note 13) Time to Shutdown tSHDN (Note 10) Full 60 160 600 ns Driver Enable from Shutdown to tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3), Full - 260 1500 ns Output High (Notes 10, 11, 13) Driver Enable from Shutdown to tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3), Full - 155 1500 ns Output Low (Notes 10, 11, 13) DRIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full - 20 60 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 1 10 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full - 13 25 ns Maximum Data Rate fMAX CD = 470pF (Figure 4) (Note 15) Full 10 15 - Mbps Driver Enable to Output High tZH RL = 500, CL = 100pF, SW = GND (Figure 3), Full - 35 150 ns (Note 8) Driver Enable to Output Low tZL RL = 500, CL = 100pF, SW = VCC (Figure 3), Full - 30 150 ns (Note 8) Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3) Full - 66 100 ns Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns Time to Shutdown tSHDN (Note 10) Full 60 160 600 ns Driver Enable from Shutdown to tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3), Full - 115 250 ns Output High (Notes 10, 11) Driver Enable from Shutdown to tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3), Full - 84 250 ns Output Low (Notes 10, 11) RECEIVER SWITCHING CHARACTERISTICS (115kbps and 500kbps Versions; ISL83080E THRU ISL83085E) Maximum Data Rate fMAX (Figure 5) (Note 15) Full 0.5 10 - Mbps Receiver Input to Output Delay tPLH, tPHL (Figure 5) Full - 100 150 ns Receiver Skew | tPLH - tPHL | tSKD (Figure 5) Full - 7 10 ns Receiver Enable to Output Low tZL RL = 1k, CL = 15pF, SW = VCC (Figure 6), Full - 10 50 ns (Notes 9, 13) Receiver Enable to Output High tZH RL = 1k, CL = 15pF, SW = GND (Figure 6), Full - 10 50 ns (Notes 9, 13) Receiver Disable from Output Low tLZ RL = 1k, CL = 15pF, SW = VCC (Figure 6), Full - 10 50 ns (Note 13) Receiver Disable from Output High tHZ RL = 1k, CL = 15pF, SW = GND (Figure 6), Full - 10 50 ns (Note 13) Time to Shutdown tSHDN (Notes 10, 13) Full 60 160 600 ns FN6085 Rev 10.00 Page 8 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note5). (Continued) TEMP MIN MAX PARAMETER SYMBOL TEST CONDITIONS (°C) (Note 4) TYP (Note 4) UNITS Receiver Enable from Shutdown to tZH(SHDN) RL = 1k, CL = 15pF, SW = GND (Figure 6), Full - 150 2000 ns Output High (Notes 10, 12, 13) Receiver Enable from Shutdown to tZL(SHDN) RL = 1k, CL = 15pF, SW = VCC (Figure 6), Full - 150 2000 ns Output Low (Notes 10, 12, 13) RECEIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E) Maximum Data Rate fMAX (Figure 5) (Note 15) Full 10 15 - Mbps Receiver Input to Output Delay tPLH, tPHL (Figure 5) Full - 70 125 ns Receiver Skew | tPLH - tPHL | tSKD (Figure 5) Full - 0 10 ns Receiver Enable to Output Low tZL RL = 1k, CL = 15pF, SW = VCC (Figure 6) Full - 10 30 ns (Note 9) Receiver Enable to Output High tZH RL = 1k, CL = 15pF, SW = GND (Figure 6) Full - 10 30 ns (Note 9) Receiver Disable from Output Low tLZ RL = 1k, CL = 15pF, SW = VCC (Figure 6) Full - 10 30 ns Receiver Disable from Output High tHZ RL = 1k, CL = 15pF, SW = GND (Figure 6) Full - 10 30 ns Time to Shutdown tSHDN (Note 10) Full 60 160 600 ns Receiver Enable from Shutdown to tZH(SHDN) RL = 1k, CL = 15pF, SW = GND (Figure 6) Full - 150 2000 ns Output High (Notes 10, 12) Receiver Enable from Shutdown to tZL(SHDN) RL = 1k, CL = 15pF, SW = VCC (Figure 6) Full - 150 2000 ns Output Low (Notes 10, 12) NOTES: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 6. Supply current specification is valid for loaded drivers when DE = 0V. 7. Applies to peak current. See “Typical Performance Curves” beginning on page13 for more information. 8. Keep RE = 0 to prevent the device from entering SHDN. 9. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN. 10. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low Power Shutdown Mode” on page13. 11. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN. 12. Set the RE signal high time >600ns to ensure that the device enters SHDN. 13. Does not apply to the ISL83084E. 14. Tested according to TIA/EIA-485-A, section 4.2.6 (±75V for 15µs at a 1% duty cycle). 15. Limits established by characterization and are not production tested. FN6085 Rev 10.00 Page 9 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Test Circuits and Waveforms RL/2 375 DE DE VCC VCC DI Z DI Z VCM D VOD D VOD RL = 60 -7V TO +12V Y Y RL/2 VOC 375 FIGURE 1A. VOD AND VOC FIGURE 1B. VOD WITH COMMON MODE LOAD FIGURE 1. DC DRIVER TEST CIRCUITS 3V DI 1.5V 1.5V 0V CL = 100pF DE tPLH tPHL VCC DI Z OUT (Z) VOH D RDIFF Y CL = 100pF OUT (Y) VOL SIGNAL GENERATOR 90% 90% +VOD DIFF OUT (Y - Z) 10% 10% -VOD tR tF SKEW = |tPLH - tPHL| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES DE 3V DI Z 500 VCC DE 1.5V 1.5V D NOTE 10 SIGNAL Y SW GND 0V GENERATOR CL tZH, tZH(SHDN) tHZ NOTES 8, 11 OUTPUT HIGH VOH - 0.5V VOH OUT (Y, Z) 2.3V PARAMETER OUTPUT RE DI SW CL (pF) 0V tHZ Y/Z X 1/0 GND 15 tZL, tZL(SHDN) tLZ tLZ Y/Z X 0/1 VCC 15 NOTES 8, 11 VCC tZH Y/Z 0 (Note 8) 1/0 GND 100 OUT (Y, Z) 2.3V tZL Y/Z 0 (Note 8) 0/1 VCC 100 OUTPUT LOW VOL + 0.5V VOL tZH(SHDN) Y/Z 1 (Note 11) 1/0 GND 100 tZL(SHDN) Y/Z 1 (Note 11) 0/1 VCC 100 FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (DOES NOT APPLY TO THE ISL83084E) FN6085 Rev 10.00 Page 10 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Test Circuits and Waveforms (Continued) 3V DE VCC + DI DI Z 0V D 60 CD VOD Y - SIGNAL DIFF OUT (Y - Z) +VOD 0V GENERATOR -VOD FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS FIGURE 4. DRIVER DATA RATE RE +1.5V B 15pF A 0V 0V 0V RO A R -1.5V tPLH tPHL SIGNAL VCC GENERATOR RO 1.5V 1.5V 0V FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER PROPAGATION DELAY AND DATA RATE RE NOTE 10 GND B RO 1k VCC 3V A R RE 1.5V 1.5V SIGNAL SW GND 0V GENERATOR 15pF tZH, tZH(SHDN) tHZ NOTES 9, 12 OUTPUT HIGH VOH - 0.5V VOH PARAMETER DE A SW RO 1.5V tHZ 0 +1.5V GND 0V tLZ 0 -1.5V VCC tZL, tZL(SHDN) tLZ NOTES 9, 12 tZH (Note 9) 0 +1.5V GND VCC RO 1.5V tZL (Note 9) 0 -1.5V VCC VOL + 0.5V VOL OUTPUT LOW tZH(SHDN) (Note 12) 0 +1.5V GND tZL(SHDN) (Note 12) 0 -1.5V VCC FIGURE 6A. TEST CIRCUIT FIGURE 6B. MEASUREMENT POINTS FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES (DOES NOT APPLY TO THE ISL83084E) Application Information one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, RS-485 and RS-422 are differential (balanced) data which allows up to 32 one unit load devices (any transmission standards for use in long haul or noisy combination of drivers and receivers) on each bus. To allow environments. RS-422 is a subset of RS-485, so RS-485 for multipoint operation, the RS-485 specification requires transceivers are also RS-422 compliant. RS-422 is a that drivers must handle bus contention without sustaining point-to-multipoint (multidrop) standard, which allows only any damage. FN6085 Rev 10.00 Page 11 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Another important advantage of RS-485 is the extended power-up and power-down, the Tx and Rx outputs remain common mode range (CMR), which specifies that the driver disabled, regardless of the state of DE and RE, if VCC is less outputs and receiver inputs withstand signals that range from than ~3.4V. This gives the processor/ASIC a chance to stabilize +12V to -7V. RS-422 and RS-485 are intended for runs as and drive the RS-485 control lines to the proper states. long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in DI = VCC the cable by external fields. 5.0 Receiver Features VCC 3.4V 3.2V 2.5 (V)C C V These devices utilize a differential input receiver for maximum V) 0 noise immunity and common mode rejection. Input sensitivity T ( U5.0 is ±200mV, as required by the RS-422 and RS-485 TP A/Y RL = 1k specifications. OU2.5 Receiver input resistance of 96k surpasses the RS-422 ER Y 0 ISL83080E T (V) V U Lspoeacdi f(icUaLt)io” nre oqfu 4irkem, eanntd o ifs 1 e2ikght mtimineims uthme. RTShu-4s8, 5th “eUsnei t DRI RO RL = 1k 5.0OUTP 2.5R products are known as “one-eighth UL” transceivers, and ISL83080E E there can be up to 256 of these devices on a network while 0 EIV C still complying with the RS-485 loading specification. RE TIME (40µs/DIV) Receiver inputs function with common mode voltages as FIGURE 7. HOT PLUG PERFORMANCE (ISL83080E) vs great as ±7V outside the power supplies (i.e., +12V and DEVICE WITHOUT HOT PLUG CIRCUITRY -7V), making them ideal for long networks where induced (ISL83086E) voltages are a realistic concern. ESD Protection All the receivers include a “full fail-safe” function that All pins on these devices include class 3 Human Body guarantees a high level receiver output if the receiver inputs Model (HBM) ESD protection structures, but the RS-485 are unconnected (floating) or shorted. pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events Receivers easily meet the data rates supported by the in excess of ±15kV HBM. The RS-485 pins are particularly corresponding driver, and all receiver outputs are vulnerable to ESD damage because they typically connect three-statable via the active low RE input (except for the to an exposed port on the exterior of the finished product. ISL83084E). Simply touching the port pins, or connecting a cable, can Driver Features cause an ESD event that might destroy unprotected ICs. The RS-485/RS-422 driver is a differential output device that These new ESD structures protect the device whether or delivers at least 1.5V across a 54 load (RS-485), and at not it is powered up, protect without allowing any latchup least 2V across a 100 load (RS-422). The drivers feature mechanism to activate, and without degrading the RS-485 low propagation delay skew to maximize bit width, and to common mode range of -7V to +12V. This built-in ESD minimize EMI. protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the All drivers are three-statable via the active high DE input associated, undesirable capacitive load they present. (except for the ISL83084E). Data Rate, Cables, and Terminations The 115kbps and 500kbps driver outputs are slew rate limited to minimize EMI, and to minimize reflections in RS-485/RS-422 are intended for network lengths up to unterminated or improperly terminated networks. Outputs of 4000’, but the maximum system data rate decreases as the the ISL83086E, ISL83088E drivers are not limited, so faster transmission length increases. Devices operating at 10Mbps output transition times allow data rates of at least 10Mbps. are limited to lengths less than 100’, while the 115kbps versions can operate at full data rates with lengths of several Hot Plug Function 1000’. When apiece of equipment powers up, there is a period of Twisted pair is the cable of choice for RS-485/RS-422 time where the processor or ASIC driving the RS-485 control networks. Twisted pair cables tend to pick up noise and lines (DE, RE) is unable to ensure that the RS-485 Tx and other electromagnetically induced voltages as common Rx outputs are kept disabled. If the equipment is connected mode signals, which are effectively rejected by the to the bus, a driver activating prematurely during power-up differential receivers in these ICs. may crash the bus. To avoid this scenario, the ISL83080, ISL83082, ISL83083, ISL83085 versions incorporate a “Hot Proper termination is imperative (when using the 10Mbps Plug” function. Circuitry monitoring VCC ensures that, during devices) to minimize reflections. Short networks using the FN6085 Rev 10.00 Page 12 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E 115kbps versions need not be terminated, but, terminations In the event of a major short circuit condition, devices also are recommended unless power dissipation is an overriding include a thermal shutdown feature that disables the drivers concern. whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The In point-to-point, or point-to-multipoint (single driver on bus) drivers automatically re-enable after the die temperature networks, the main cable should be terminated in its drops about +15°C. If the contention persists, the thermal characteristic impedance (typically 120) at the end farthest shutdown/re-enable cycle repeats until the fault is cleared. from the driver. In multi-receiver applications, stubs Receivers stay operational during thermal shutdown. connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require Low Power Shutdown Mode that the main cable be terminated in its characteristic These CMOS transceivers all use a fraction of the power impedance at both ends. Stubs connecting a transceiver to required by their bipolar counterparts, but they also include a the main cable should be kept as short as possible. shutdown feature (except for the ISL83084E) that reduces Built-In Driver Overload Protection the already low quiescent ICC to a 70nA trickle. These devices enter shutdown whenever the receiver and driver As stated previously, the RS-485 specification requires that are simultaneously disabled (RE=VCC and DE=GND) for drivers survive worst case bus contentions undamaged. a period of at least 600ns. Disabling both the driver and the These devices meet this requirement via driver output short receiver for less than 60ns guarantees that the transceiver circuit current limits, and on-chip thermal shutdown circuitry. will not enter shutdown. The driver output stages incorporate short circuit current Note that receiver and driver enable times increase when limiting circuitry which ensures that the output current never the transceiver enables from shutdown. Refer to Notes 8 exceeds the RS-485 specification, even at the common thru 12, at the end of the “Electrical Specification Table” on mode voltage range extremes. Additionally, these devices page9, for more information. utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified 90 3.4 80 V) mA) 70 GE ( 3.2 RDIFF = 100 NT ( LTA 3.0 E 60 O R V UR 50 UT 2.8 C P T T PU 40 OU 2.6 R OUT 30 NTIAL 2.4 RDIFF = 54 E E V 20 R RI E D F 2.2 10 F DI 0 2.0 0 1 2 3 4 5 -40 -25 0 25 50 75 85 DIFFERENTIAL OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 8. DRIVER OUTPUT CURRENT vs DIFFERENTIAL FIGURE 9. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT VOLTAGE TEMPERATURE FN6085 Rev 10.00 Page 13 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) 200 560 ISL83086E/ISL83088E 150 550 Y OR Z = LOW HALF DUPLEX, DE = VCC, RE = X A)100 m 540 T ( ISL83080E thru ISL83085E EN 50 A) R µ 530 T CUR 0 I (CC U 520 TP -50 HALF DUPLEX, DE = GND, RE = GND U O Y OR Z = HIGH FULL DUPLEX, DE = X, RE = GND 510 -100 ISL8308xE -150 500 -7 -6 -4 -2 0 2 4 6 8 10 12 -40 -25 0 25 50 75 85 OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 10. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT FIGURE 11. SUPPLY CURRENT vs TEMPERATURE VOLTAGE 880 60 860 55 s) Y (n 840 50 N DELA 820 tPHL W (ns) 45 O E TI 800 K A S G A 40 P O 780 R P tPLH 35 760 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 740 30 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. DRIVER DIFFERENTIAL PROPAGATION DELAY FIGURE 13. DRIVER DIFFERENTIAL SKEW vs vs TEMPERATURE (ISL83080E, ISL83082E) TEMPERATURE (ISL83080E, ISL83082E) 400 27 26 390 25 s) n LAY ( 380 tPHL 24 E s) 23 D n ON 370 W ( 22 GATI SKE 21 OPA 360 20 R P 350 tPLH 19 18 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 340 17 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 14. DRIVER DIFFERENTIAL PROPAGATION DELAY FIGURE 15. DRIVER DIFFERENTIAL SKEW vs vs TEMPERATURE (ISL83083E, ISL83084E, TEMPERATURE (ISL83083E, ISL83084E, ISL83085E) ISL83085E) FN6085 Rev 10.00 Page 14 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) 20 0.70 19 Y (ns) tPHL 0.65 A EL 18 s) D n GATION 17 tPLH SKEW (0.60 A P O R 0.55 P 16 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 15 0.50 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 16. DRIVER DIFFERENTIAL PROPAGATION DELAY FIGURE 17. DRIVER DIFFERENTIAL SKEW vs vs TEMPERATURE (ISL83086E, ISL83088E) TEMPERATURE (ISL83086E, ISL83088E) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) VER 5 RO DRIV VER 5 RO DRIV EI 0 EI 0 C C E E R R V) 4 V) 4 UT ( 3 B/Z UT ( 3 A/Y P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (400ns/DIV) TIME (400ns/DIV) FIGURE 18. DRIVER AND RECEIVER WAVEFORMS, FIGURE 19. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83080E, ISL83082E) HIGH TO LOW (ISL83080E, ISL83082E) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) RECEIVER 05 RO DRIV RECEIVER 05 RO DRIV V) 4 V) 4 UT ( 3 B/Z UT ( 3 A/Y P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (200ns/DIV) TIME (200ns/DIV) FIGURE 20. DRIVER AND RECEIVER WAVEFORMS, FIGURE 21. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83083E, ISL83084E, HIGH TO LOW (ISL83083E, ISL83084E, ISL83085E) ISL83085E) FN6085 Rev 10.00 Page 15 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) OUTPUT (V) DI RDIFF = 54, CL = 100pF 05 ER INPUT (V) EIVER 05 RO DRIV EIVER 05 RO DRIV C C E E R R V) 4 V) 4 T ( B/Z T ( A/Y U 3 U 3 P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (20ns/DIV) TIME (20ns/DIV) FIGURE 22. DRIVER AND RECEIVER WAVEFORMS, FIGURE 23. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83086E, ISL83088E) HIGH TO LOW (ISL83086E, ISL83088E) 40 mA) 35 VOL, +25°C Die Characteristics NT ( 30 VOL, +85°C SUBSTRATE POTENTIAL (POWERED UP): E R UR 25 GND C T VOH, +25°C U 20 TRANSISTOR COUNT: P T OU 15 VOH, +85°C 525 R VE 10 PROCESS: EI C Si Gate BiCMOS E 5 R 0 0 1 2 3 4 5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 24. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FN6085 Rev 10.00 Page 16 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE February 15, 2016 FN6085.10 Added Rev History and About Intersil verbiage. Updated “Ordering Information” on page3. Updated POD M8.118 to current version with following changes: Updated to new Intersil format by adding land pattern and moving dimensions from table onto drawing Corrected lead width dimension in side view 1 from “0.25 - 0.036" to “0.25 - 0.36" Updated POD M10.118 to current version with following change: Updated to new POD template. Added land pattern Updated POD M14.15 to current version with following change: Added land pattern and moved dimensions from table onto drawing. Updated POD M8.15 to current version with following changes: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern. Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Changed Note 1 “1982” to “1994” About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2004-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6085 Rev 10.00 Page 17 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.65) 4. Plastic interlead protrusions of 0.15mm max per side are not (0.40) included. (1.40) 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 Page 18 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 Page 19 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 4 0.10CA-B2X 8.65 A 3 6 DETAIL"A" 0.22±0.03 14 8 D 6.0 3.9 4 0.10CD2X PIN NO.1 7 0.20C2X ID MARK (0.35) x 45° 4° ± 4° 5 0.31-0.51 B 3 6 0.25MCA-B D TOP VIEW 0.10C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C 1.27 0.10-0.25 SEATING PLANE 0.10C SIDE VIEW DETAIL "A" (1.27) (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. 6. Does not include dambar protrusion. Allowable dambar protrusion (1.50) shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 Page 20 of 21 February 15, 2016

ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6085 Rev 10.00 Page 21 of 21 February 15, 2016