DATASHEET ISL8201M FN6657 10A, High Efficiency DC/DC Module Rev 3.00 October 28, 2014 The ISL8201M is a 20V, 10A output current, variable output Features step-down power supply. Included in the 15mmx15mm • Complete Switch Mode Power Supply package is a high performance PWM controller switching at 600kHz, power MOSFETs, an inductor, and all the passive • Bias Voltage Range from +4.5 to +14.4V components required for complete DC/DC power solution. - Wide Input Voltage Range from 1V up to 20V (see The ISL8201M operates over an input voltage range of 1V to “Input Voltage Considerations” on page11) 20V and supports an output voltage range of 0.6V to 5V, • 10A DC Output Current, 17A Peak Output Current which is set by a single dividing resistor. This high efficiency • Adjustable +0.6V to +5V Output Range power module is capable of delivering 10A (17A peak) output with up to 95% efficiency, needing no heat sinks or airflow to • Up to 95% Efficiency meet power specifications. Only bulk input and output • Simple Voltage Mode Control capacitors are needed to finish the design. Utilizing voltage-mode control, the output voltage can be precisely • Fixed 600kHz Switching Frequency regulated to as low as 0.6V with up to ±1% output voltage • Fast Transient Response regulation. The ISL8201M also features internal • Enable Function Option compensation, internal soft-start, auto-recovery overcurrent protection, an enable option, and pre-biased output start-up • Pre-biased Output Start-up Capability capability. • Internal Soft-Start The ISL8201M is packaged in a thermally enhanced, compact • Overcurrent Protection by Low-Side MOSFET r DS(ON) (15mmx15mm) and low profile (3.5mm) overmolded QFN Sensing (Non-Latching, Auto-Recovery) Package Module suitable for automated assembly by standard surface mount equipment. The ISL8201M is RoHS • Small Footprint, Low Profile Surface Mount QFN Package (15mmx15mmx3.5mm) compliant. • RoHS Compliant Typical Schematic Applications (+5V/+12V) OR PVCC • Servers (+6.5V TO 14.4V) CPVCC P • Industrial Equipment VCC (+5V / +V12V) • Point of Load Regulation V COMP/EN PVCC VIN 1V.OIN8UVT (+4.I5NV TO +20V) C 10A • Other General Purpose Step-Down DC/DC VINISL8201M VOUT IN CINFB PHASE COUT • Telecom and Datacom Applications ISL8201M V OUT RFB ISEN PGPNDGNDVOUT FB COUT RFB 4.87k FN6657 Rev 3.00 Page 1 of 16 October 28, 2014

ISL8201M Ordering Information PART NUMBER PACKAGE (Notes1, 2, 3) PART MARKING (RoHS Compliant) PKG. DWG.# ISL8201MIRZ ISL8201M 15 Ld QFN L15.15x15 ISL8201MEVAL1Z Evaluation Board 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3) termination finish which is compatible with both SnPb and Pb-free soldering operations. Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb- free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL8201M. For more information on MSL please see techbrief TB363. Simplified Block Diagram PVCC VIN SAMPLE POR PGND AND AND LDO HOLD SOFT-START - INHIBIT DRIVER + 21.5µA VOUT ISET 0.6V + GATE FB - +- PWM COLNOTGRICOL PVCC 0.4V + DIS - DRIVER COMP/EN OSCILLATOR RSET-IN PGND PWM Controller RFB-TI ISET PHASE FIGURE 1. INTERNAL BLOCK DIAGRAM FN6657 Rev 3.00 Page 2 of 16 October 28, 2014

ISL8201M Pinout ISL8201M (15 LD QFN) TOP AND 3D VIEW 9 8 7 6 5 4 3 2 1 1 15 14 13 10 12 11 Pin Descriptions PIN SYMBOL DESCRIPTION 1, 2, 3, 4, 11 PGND Power ground. Connect to ground plane directly. 5 PVCC Supply voltage. Connect 1µF ceramic capacitor to ground plane directly. 6, 8, 15 NC Do not connect. Overcurrent protection. Integrated internal 3.57k resistor. Connect additional resistor between this 7 ISET pin and PGND pin can change initial setting. 9 VIN Power input. Connect to input. 10 PHASE Phase node. Node of high-side and low-side MOSFETs and output inductor connection. 12 VOUT Power output. Connect to output. 13 COMP/EN Compensation and enable. 14 FB Feedback input. Connect resistor between this pin and ground for adjusting output voltage. FN6657 Rev 3.00 Page 3 of 16 October 28, 2014

ISL8201M Absolute Maximum Ratings Thermal Information C to P . . . . . . . . . . . . . . . . . . . . . . . . P - 0.3V to +6V Thermal Resistance (Typical)  (°C/W)  (°C/W) OMP/EN GND GND JA JC ISET to PGND. . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to PVCC + 0.3V 15 Ld QFN (Notes5, 6) . . . . . . . . . . . . 13 2 PVCC to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to +15V Junction Temperature TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C PHASE to PGND. . . . . . . . . . . . . . . . . . . . . . . . -1.2V ~ +30V (Note4) Storage Temperature Range TSTG . . . . . . . . . . . . .-55°C to +125°C VIN to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . -1.2V ~ +30V (Note4) Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Ratings Input Supply Voltage (V ). . . . . . . . . . . . . . . . . . . . . . +1V to +20V IN Output Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . . +0.6V to +5V OUT P VCC Fixed Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . +5V or +12V Wide Range Supply. . . . . . . . . . . . . . . . . . . . . . +6.5V to +14.4V Ambient Temperature Range (T ). . . . . . . . . . . . . . -40°C to +85°C A CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. V (Drain-to-Source) specification for internal high-side and low-side MOSFET. DS 5.  is measured in free air with the component mounted on a high effective thermal conductivity test board (i.e. 4-layer type without thermal vias JA – see tech brief TB379) per JEDEC standards except that the top and bottom layers assume solid planes. 6. For  , the “case temp” location is the center of the exposed metal pad on the package underside. JC Electrical Specifications T = +25°C. V = 12V, V = 1.5V. C = 220µFx1, 10µF/Ceramicx2, C = 330µF (ESR = 10m), A IN OUT IN OUT 22µF/Ceramicx3. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Supply Bias Current I I = 0A, V = 1.5V, V = 12V, P = 12V - 10 - mA Q(VIN) OUT OUT IN VCC Input In-rush Current I I = 0A, V = 1.5V, V = 12V, P = 12V - 140 - mA inRush OUT OUT IN VCC Input Supply Current I I = 10A, V = 1.5V, V = 12V, P = 12V - 1.48 - A S(VIN) OUT OUT IN VCC OUTPUT CHARACTERISTICS Output Continuous Current Range I V = 12V, V = 1.5V 0 - 10 A OUT(DC) IN OUT Line Regulation Accuracy V /V V = 1.5V, I = 0A, V =3.3V to 20V, P = 12V - 0.1 - % OUT IN OUT OUT IN VCC Load Regulation Accuracy V /I I = 0A to 10A, V = 1.5V, V = 12V, P = 12V - 0.5 - % OUT OUT OUT OUT IN VCC Peak-to-Peak Output Ripple Voltage V I = 10A, V = 1.5V, V = 12V, P = 12V - 20 - mV OUT OUT OUT IN VCC DYNAMIC CHARACTERISTICS Voltage Change For Positive Load Step V I = 0A to 5A. Current slew rate=2.5A/µs, V = 12V, - 36 - mV OUT-DP OUT IN V = 1.5V, P =12V OUT VCC Voltage Change For Negative Load Step V I = 0A to 5A. Current slew rate=2.5A/µs, V = 12V, - 39 - mV OUT-DN OUT IN V = 1.5V, P =12V OUT VCC CONTROLLER Shutdown PVCC Supply Current I P = 12V; Disabled (Note7) 4 5.2 7 mA PVCC_S VCC Supply Voltage P Fixed 5V supply 4.5 5.0 5.5 V VCC Wide range supply 6.5 12.0 14.4 V P Operating Current I I = 10A, V = 1.5V V =12V VCC PVCC OUT OUT IN 5V supply - 22 - mA 12V supply - 47 - mA Rising P Threshold V (Note7) 3.9 4.1 4.3 V VCC PORR P Power-On-Reset Threshold Hysteresis V (Note7) 0.30 0.35 0.40 V VCC PORH Oscillator Frequency F (Note7) 510 600 660 kHz OSC FN6657 Rev 3.00 Page 4 of 16 October 28, 2014

ISL8201M Electrical Specifications T = +25°C. V = 12V, V = 1.5V. C = 220µFx1, 10µF/Ceramicx2, C = 330µF (ESR = 10m), A IN OUT IN OUT 22µF/Ceramicx3. (Continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Internal Resistor Between V and FB Pins R 9.66 9.76 9.85 k OUT FB-TI Disabled Threshold Voltage (COMP/EN) V (Note7) 0.375 0.4 0.425 V ENDIS Reference Voltage V (Note7) - 0.6 - V REF Reference Voltage Tolerance 0°C to +70°C (Note7) -1.0 - +1.0 % -40°C to +85°C (Note7) -1.5 - +1.5 % FAULT PROTECTION Internal Resistor Between I and P Pins R - 3.57 - k SET GND SET-IN I Current Source I (Note7) 18.0 21.5 23.5 µA SET SET NOTE: 7. Parameters are 100% tested for internal IC prior to module assembly. Typical Performance Characteristics Efficiency Performance T = +25°C, V = P (P = 5V for 18V ), C = 220µFx1, 10µF/Ceramicx2, C = 330µF (ESR = 10m), A IN VCC VCC IN IN OUT 22µF/Ceramicx3. Theefficiency equation is: Efficiency = O------u---t---p---u----t-- --P-----o----w-----e----r = P-----O----U----T--- = ---V----O-----U----T----x---I--O----U-----T---- Input Power P V xI  IN IN IN 100 100 90 90 %) 80 %) 80 EFFICIENCY ( 567000 3.3V 2.5V 1.5V 1.2V EFFICIENCY ( 567000 5.0V 3.3V 2.5V 1.5V 1.2V 0.8V 0.8V 40 40 30 30 0 2 4 6 8 10 0 2 4 6 8 10 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 2. EFFICIENCY vs LOAD CURRENT (5V ) FIGURE 3. EFFICIENCY vs LOAD CURRENT (12V ) IN IN 100 VIN = 12V VOUT = 1.2V 90 IOUT = 0A to 5A %) 80 NCY ( 70 5.0V 3.3V E 2.5V CI 60 FI 1.5V F E 50 1.2V 40 30 0 2 4 6 8 10 LOAD CURRENT (A) FIGURE 4. EFFICIENCY vs LOAD CURRENT (18V ) FIGURE 5. 1.2V TRANSIENT RESPONSE IN FN6657 Rev 3.00 Page 5 of 16 October 28, 2014

ISL8201M Typical Performance Characteristics (Continued) Transient Response Performance T = +25°C, V = 12V, V = 1.5V, P = 12V, C =220µFx1, 10µF/Ceramicx2, C =330µF A IN OUT VCC IN OUT (ESR = 10m), 22µF/Ceramicx3 I = 0-5A (10A), Current slew rate = 2.5A/µs OUT VIN = 12V VIN = 12V VOUT = 1.5V VOUT = 1.8V IOUT = 0A to 5A IOUT = 0A to 5A FIGURE 6. 1.5V TRANSIENT RESPONSE FIGURE 7. 1.8V TRANSIENT RESPONSE VIN = 12V VIN = 12V VOUT = 2.5V VOUT = 3.3V IOUT = 0A to 5A IOUT = 0A to 5A FIGURE 8. 2.5V TRANSIENT RESPONSE FIGURE 9. 3.3V TRANSIENT RESPONSE C PVCC PVCC V OUT V IN 1.8V (+5V/+12V) 10A VIN VOUT CIN (BULK) CIN (CER) ISL8201M COUT1 COUT2 220µF 10µF 22µF 330µF PHASE COMP/EN 25V 6.3V x2 x3 ISET FB PGND R FB 4.87k FIGURE 10. TYPICAL APPLICATION FN6657 Rev 3.00 Page 6 of 16 October 28, 2014

ISL8201M Pin Functions the MOSFETs outputs to be held low. The external pull-down device will initially need to overcome a maximum of 5mA of PGND (Pins 1, 2, 3, 4, 11) COMP/EN output current. However, once the controller is Power ground pin for signal, input, and output return path. PGND disabled, the COMP/EN output will also be disabled, thus only needs to connect to one (or more) ground plane(s) immediately, a 20µA current source will continue to draw current. which is recommended to minimize the effect of switching noise, FB (Pin 14) copper losses, and maximize heat dissipation. The FB pin is the output voltage adjustment of the ISL8201M. It PVCC (Pin 5) will regulate to 0.6V at the FB pin with respect to the PGND pin. This pin provides the bias supply for ISL8201M, as well as the The ISL8201M has an integrated voltage dividing resistor. This low-side MOSFET’s gate and high-side MOSFET’s gate. If is a precision 9.76k resistor (R ) between the VOUT and FB-TI PVCC rises above 6.5V, an internal 5V regulator will supply to FB pins. Different output voltages can be programmed with the internal logics bias (but high-side and low-side MOSFET additional resistors between FB to PGND. gate will still be sourced by PVCC). Connect a well decoupled +5V or +12V supply to this pin. Reference Circuitry For General Applications NC (Pins 6, 8, 15) Typical Application with Single Power Supply These pins have no function; do not connect. Figure11 shows the ISL8201M application schematic for input voltage +5V or +12V. The PVCC pin can connect to the input ISET (Pin 7) supply directly. The ISET pin is the input for the overcurrent protection (OCP) setting, which compares the r of the low-side MOSFET CPVCC DS(ON) to set the overcurrent threshold. The ISL8201M has an initial protect overcurrent limit. It has an integrated internal 3.57k resistor (R ) between the ISET and PGND pins, which PVCC SET-IN can prevent significant overcurrent impact to the module. One (+5V/+12V) can also connect an additional resistor R between the COMP/EN VIN VIN SET-EX ISL8201M CIN ISET pin and the PGND pin in order to reduce the current limit FB PHASE point by paralleling. VOUT VIN (Pin 9) ISET VOUT RFB RSET-EX PGND COUT Power input pin. Apply input voltage between the VIN pin and PGND pin. It is recommended to place an input decoupling capacitor directly between the VIN pin and the PGND pin. The FIGURE 11. TYPICAL APPLICATION SCHEMATIC input capacitor should be placed as closely as possible to the module. Typical Application with Separated Power Supply Figure12 shows the ISL8201M application schematic for wide PHASE (Pin 10) input voltages from +1V to +20V. The P supply can source VCC The PHASE pin is the switching node between the high and +5V/+12V or +6.5V to 14.4V. low-side MOSFET. It also returns the current path for the high- side MOSFET driver and detects the low-side MOSFET drain (+5V/+12V) or PVCC voltage for the overcurrent limits point. (+6.5V TO 14.4V) CPVCC VOUT (Pin 12) Power output pin. Apply output load between this pin and the PGND pin. It is recommended to place a high frequency output PVCC (+1V TO +20V) decoupling capacitor directly between the VOUT pin and the PGND pin. The output capacitor should be placed as closely COMP/EN VIN VIN ISL8201M CIN as possible to the module. FB PHASE COMP/EN (Pin 13) V OUT ISET VOUT This is the multiplexed pin of the ISL8201M. During soft-start RFB RSET-EX PGND COUT and normal converter operation, this pin represents the output of the error amplifier. Use COMP/EN in combination with the FB pin to compensate for the voltage control feedback loop of FIGURE 12. WIDE INPUT VOLTAGE APPLICATION SCHEMATIC the converter. Pulling COMP/EN low (V = 0.4V nominal) ENDIS will disable (shut-down) the controller, which causes the oscillator to stop, and the high-side gate and low-side gate of FN6657 Rev 3.00 Page 7 of 16 October 28, 2014

ISL8201M Applications Information If the COMP/EN pin is held low during power-up, the initialization will be delayed until the COMP/EN is released and The typical ISL8201M application schematic for input voltage its voltage rises above the V trip point. +5V or +12V is shown in Figure11. External component ENDIS selection is primarily determined by the maximum load current Figures14 and 15 show a typical power-up sequence in more and input/output voltage. detail. The initialization starts at t , when either P rises 0 VCC above V , or the COMP/EN pin is released (after POR). Programming the Output Voltage PORR The COMP/EN will be pulled up by an internal 20µA current The ISL8201M has an internal 0.6V ±1.5% reference voltage. source, however, the timing will not begin until the COMP/EN Programming the output voltage requires a dividing resistor exceeds the V trip point (at t ). The external capacitance ENDIS 1 (R ). The output voltage can be calculated as shown in FB of the disabling device, as well as the compensation Equation1: capacitors, will determine how quickly the 20µA current source V = 0.61+9----.--7---6----k-- (EQ. 1) will charge the COMP/EN pin. With typical values, it should OUT  R  FB add a small delay compared to the soft-start times. The COMP/EN will continue to ramp to ~1V. Note: ISL8201M has integrated 9.76k resistance into the module (dividing resistor for top side). The resistance From t , there is a nominal 6.8ms delay, which allows the 1 corresponding to different output voltages is as shown in PVCC pin to exceed 6.5V (if rising up towards 12V), so that the Table1: internal bias regulator can turn on cleanly. At the same time, the ISET pin is initialized by disabling the low-side gate driver TABLE 1. RESISTANCE TO OUTPUT VOLTAGES and drawing I (nominal 21.5µA) through R . This sets up SET SETI V 0.6V 1.05V 1.2V 1.5V OUT a voltage that will represent the I trip point. At t , there is a SET 2 R open 13k 9.76k 6.49k variable time period for the OCP sample and hold operation FB (0.0ms to 3.4ms nominal; the longer time occurs with the V 1.8V 2.5V 3.3V 5V OUT higher overcurrent setting). The sample and hold uses a digital R 4.87k 3.09k 2.16k 1.33k FB counter and DAC to save the voltage, so the stored value does not degrade, as long as the P is above V (See VCC PORR Initialization (POR and OCP Sampling) “Overcurrent Protection (OCP)” on page10 for more details on Figure13 shows a start-up waveform of ISL8201M. The the equations and variables). Upon the completion of sample power-on-reset (POR) function continually monitors the bias and hold at t3, the soft-start operation is initiated, and the voltage at the PVCC pin. Once the rising POR threshold has output voltage ramps up between t4 and t5. exceeded 4V (V nominal), the POR function initiates the PORR overcurrent protection (OCP) sample and hold operation (while COCMOMPP/E/ENN COMP/EN is ~1V). When the sampling is complete, V OUT begins the soft-start ramp. T0t0 Tt11 PVCC ISETISET VOUTVOUT VOUT ~4V COMP/EN FIGURE 14. I AND SOFT-START OPERATION SET FIGURE 13. POR AND SOFT-START OPERATION FN6657 Rev 3.00 Page 8 of 16 October 28, 2014

ISL8201M If the output is pre-biased to a voltage above the expected value (as shown Figure18), neither MOSFET will turn on until the end of the soft-start, at which time it will pull the output voltage down to the final value. Any resistive load connected to the output will help pull down the voltage (at the RC rate of the R of the load and the C of the output capacitance). t1 t2 t3 t4 t5 COMP/EN IISSEETT VOUT VOUT 3.4ms 3.4ms t2 FIGURE 15. I AND SOFT-START OPERATION SET Soft-Start and Pre-Biased Outputs The soft-start internally ramps the reference on the t0 t1 non-inverting terminal of the error amp from 0V to 0.6V in a nominal 6.8ms. The output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp FIGURE 16. NORMAL START-UP seen on the V will be less than the nominal time), due to OUT some initialization timing, between t and t . 3 4 The ramp is created digitally, so there will be 64 small discrete steps. There is no simple way to change this ramp rate externally. After an initialization period (t to t ), the error amplifier VOUT 3 4 (COMP/EN pin) is enabled and begins to regulate the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitors. When the internally generated soft-start voltage exceeds the reference voltage (0.6V), the soft-start is complete and the output should be in regulation at the expected voltage. This method provides a rapid and controlled output voltage rise; there is no large in-rush current charging the output capacitors. The entire start-up sequence from POR typically takes up to 17ms; up to 10.2ms for the delay and OCP sample and 6.8ms for the soft-start ramp. Figure16 shows the normal curve for start-up; initialization FIGURE 17. PRE-BIASED START-UP begins at t , and the output ramps between t and t . If the 0 1 2 output is pre-biased to a voltage less than the expected value (as shown Figure17), the ISL8201M will detect that condition. Neither internal MOSFET will turn on until the soft-start ramp voltage exceeds the output; V starts seamlessly ramping OUT from there. FN6657 Rev 3.00 Page 9 of 16 October 28, 2014

ISL8201M side gate driver is disabled to allow an internal 21.5µA current source to develop a voltage across R . The ISL8201M SET samples this voltage (which is referenced to the PGND pin) at VOUT the ISET pin, and holds it in a counter and DAC combination. This sampled voltage is held internally as the overcurrent set point, for as long as power is applied, or until a new sample is taken after coming out of a shut-down. The actual monitoring of the low-side MOSFET ON-resistance starts 200ns (nominal) after the edge of the internal PWM logic signal (that creates the rising external low-side gate signal). This is done to allow the gate transition noise and ringing on the PHASE pin to settle out before monitoring. The monitoring ends when the internal PWM edge (and thus low-side gate signal) goes low. The OCP can be detected anywhere within the above window. 500mV/DIV If the converter is running at high duty cycles around 75% for 600kHz operation, then the low-side gate pulse width may not FIGURE 18. PRE-BIASED START-UP - OVERCHARGED be wide enough for the OCP to properly sample the r . DS(ON) For those cases, if the low-side gate signal is too narrow (or If the V for the synchronous buck converter is from a different not there at all) for 3 consecutive pulses, then the third pulse IN supply that comes up after P , the soft-start will go through will be stretched and/or inserted to the 425ns minimum width. VCC its cycle, but with no output voltage ramp. When V turns on, This allows for OCP monitoring every third pulse under this IN the output will follow the ramp of the V from zero up to the condition. This can introduce a small pulse-width error on the IN final expected voltage (at close to 100% duty cycle, with output voltage, which will be corrected on the next pulse; and COMP/EN pin >4V). If V is too fast, there may be excessive the output ripple voltage will have an unusual 3-clock pattern, IN in-rush current charging the output capacitors (only the which may look like jitter. beginning of the ramp, from zero to V matters here). If this OUT The overcurrent function will trip at a peak inductor current is not acceptable, then consider changing the sequencing of (I ) determined by Equation2: PEAK the power supplies, sharing the same supply, or adding 2I R SET SET sequencing logic to the COMP/EN pin to delay the soft-start I = -------------------------------------------- (EQ. 2) PEAK r until the V supply is ready (see “Input Voltage DSON IN Considerations” on page11). where: If ISL8201M is disabled after soft-start (by pulling COMP/EN I is the internal I current source (21.5µA typical). SET SET pin low), and afterwards enabled (by releasing the COMP/EN R is equivalent resistance between ISET and PGND pins. pin), then the full initialization (including OCP sample) will take SET place. However, there is no new OCP sampling during r is typically 6.1m at (V = V = 10V, I = 30A) DS(ON) PVCC GS DS overcurrent retries. If the output is shorted to GND during soft- and 9m at (V = V = 4.5V, I = 30A). PVCC GS DS start, the OCP will handle it, as described in the next section. Note: ISL8201M has integrated 3.57k resistance (R ). SET-IN Overcurrent Protection (OCP) Therefore, the equivalent resistance of R can be expressed SET The overcurrent function protects the converter from a shorted in Equation3: output by using the low-side MOSFET ON-resistance, rDS(ON), RSET-EXRSET-IN to monitor the current. A resistor (RSET) programs the RSET = R-----S----E----T-------E----X-----+----R-----S----E----T-------I-N--- (EQ. 3) overcurrent trip level. The scale factor of 2 doubles the trip point of the MOSFET This method enhances the converter's efficiency and reduces voltage drop, compared to the setting on the R resistor. The SET cost by eliminating a current sensing resistor. If overcurrent is OC trip point varies in a system mainly due to the MOSFET detected, the output immediately shuts off. It cycles the soft- r variations (i.e. over process, current and temperature). DS(ON) start function in a hiccup mode (2 dummy soft-start time-outs, To avoid overcurrent tripping in the normal operating load then up to one real one) to provide fault protection. If the range, find the R resistor from Equation4, and with Steps 1 SET shorted condition is not removed, this cycle will continue to 3: indefinitely. 1. The maximum r at the highest junction temperature DS(ON) Following POR (and 6.8ms delay), the ISL8201M initiates the 2. The minimum I from the “Electrical Specifications” table overcurrent protection sample and hold operation. The low- SET on page3. FN6657 Rev 3.00 Page 10 of 16 October 28, 2014

ISL8201M 3. Determine I for: retry at an acceptable level. At time t , the output starts a PEAK 2 I  normal soft-start cycle, and the output tries to ramp. If the short L IPEAKIOUTMAX+------2------- (EQ. 4) is still applied and the current reaches the ISET trip point any time during the soft-start ramp period, the output will shut off where I is the output inductor ripple current. In a high input L and return to time t for another delay cycle. The retry period is voltage, high output voltage application, such as 20V input to 0 thus two dummy soft-start cycles plus one variable one (which 5V output, the inductor ripple becomes excessive due to the depends on how long it takes to trip the sensor each time). fixed internal inductor value. In such applications, the output Figure19 shows an example where the output gets about half- current will be limited from the rating to approximately 70% of way up before shutting down; therefore, the retry (or hiccup) the module’s rated current. time will be around 17ms. The minimum should be nominally The relationships between the external R values and the 13.6ms and the maximum 20.4ms. If the short condition is SET typical output current I OCP levels are as follows: finally removed, the output should ramp up normally on the OUT(MAX) next t cycle. TABLE 2. 2 R OCP (A) AT V = 12V, OCP (A) AT V = 12V SET IN IN () PVCC = 5V PVCC = 12V OPEN 13.3 17.3 50k 12.6 16.6 20k 11.4 14.9 t0 t1 t2 10k 10.2 13.3 5k 7.6 10.3 3k 6.3 8.3 2k 4.9 6.7 VOUT The range of allowable voltages detected (2 x I x R ) is SET SET 0mV to 475mV. If the voltage drop across R is set too low, SET then this can cause almost continuous OCP tripping and retry. It will also be very sensitive to system noise and in-rush current FIGURE 19. OVERCURRENT RETRY OPERATION spikes, so it should be avoided. The maximum usable setting is around 0.2V across RSET (0.4V across the MOSFET); values Starting up into a shorted load looks the same as a retry into above this might disable the protection. Any voltage drop that same shorted load. In both cases, OCP is always enabled across RSET that is greater than 0.3V (0.6V MOSFET trip during soft-start; once it trips, it will go into retry (hiccup) mode. point) will disable the OCP. Note that conditions during power- The retry cycle will always have two dummy time-outs, plus up or during a retry may look different than normal operation. whatever fraction of the real soft-start time passes before the During power-up in a 12V system, the ISL8201M starts detection and shutoff. At that point, the logic immediately starts operation just above 4V; if the supply ramp is slow, the soft- a new two dummy cycle time-out. start ramp might be over well before 12V is reached. Input Voltage Considerations Therefore, with low-side gate drive voltages, the r of the DS(ON) MOSFET will be higher during power-up, effectively lowering Figure12 shows a standard configuration where P is either VCC the OCP trip. In addition, the ripple current will likely be 5V (±10%) or 12V (±20%). In each case, the gate drivers use different at a lower input voltage. Another factor is the digital the P voltage for low-side gate and high-side gate driver. In VCC nature of the soft-start ramp. On each discrete voltage step, addition, P is allowed to work anywhere from 6.5V up to the VCC there is in effect, a small load transient and a current spike to 14.4V maximum. The P range between 5.5V and 6.5V is VCC charge the output capacitors. The height of the current spike is not allowed for long-term reliability reasons, but transitions not controlled, however, it is affected by the step size of the through it to voltages above 6.5V are acceptable. output and the value of the output capacitors, as well as the There is an internal 5V regulator for bias, which turns on internal error amp compensation. Therefore, it is possible to between 5.5V and 6.5V. Some of the delay after POR is there to trip the overcurrent with in-rush current, in addition to the allow a typical power supply to ramp-up past 6.5V before the normal load and ripple considerations. soft-start ramps begins. This prevents a disturbance on the Figure19 shows the output response during a retry of an output, due to the internal regulator turning on or off. If the output shorted to PGND. At time t , the output has been turned transition is slow (not a step change), the disturbance should be 0 off due to sensing an overcurrent condition. There are two minimal. Thus, while the recommendation is to not have the internal soft-start delay cycles (t and t ) to allow the MOSFETs output enabled during the transition through this region, it may 1 2 to cool down in order to keep the average power dissipation in be acceptable. The user should monitor the output for their FN6657 Rev 3.00 Page 11 of 16 October 28, 2014

ISL8201M application to see if there is any problem. If P powers up first Where: VCC and the V is not present by the time the initialization is done, IN C is the input capacitance (µF) then the soft-start will not be able to ramp the output, and the IN output will later follow part of the V ramp when it is applied. If I is the input current (A) IN IN this is not desired, then change the sequencing of the supplies, t is the turn on time of the high-side switch (µs) or use the COMP/EN pin to disable V until both supplies are OUT ready. V is the allowable peak-to-peak voltage (V) Figure20 shows a simple sequencer for this situation. If P In addition to the bulk capacitance, some low Equivalent Series VCC powers up first, Q will be off, and R pulling to P will turn Inductance (ESL) ceramic capacitance is recommended to 1 3 VCC Q on, keeping the ISL8201M in shut-down. When V turns decouple between the drain terminal of the high-side MOSFET 2 IN on, the resistor divider R and R determines when Q turns and the source terminal of the low-side MOSFET. This is used 1 2 1 on, which will turn off Q and release the shut-down. If V to reduce the voltage ringing created by the switching current 2 IN powers up first, Q will be on, turning Q off; so the ISL8201M across parasitic circuit elements. 1 2 will start-up as soon as P comes up. The V trip point VCC ENDIS Output Capacitors is 0.4V nominal, so a wide variety of N-MOSFET or NPN BJT or even some logic IC's can be used as Q or Q . However, Q The ISL8201M is designed for low output voltage ripple. The 1 2 2 must be low leakage when off (open-drain or open-collector) so output voltage ripple and transient requirements can be met as not to interfere with the COMP output. Q2 should also be with bulk output capacitors (COUT) with low enough Equivalent placed near the COMP/EN pin. Series Resistance (ESR). COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or a ceramic capacitor. VIN PVCC The typical capacitance is 330µF and decoupled ceramic output capacitors are used. The internally optimized loop compensation provides sufficient stability margins for all R1 R3 ceramic capacitor applications with a recommended total value of 400µF. Additional output filtering may be needed if further TO COMP/EN reduction of output ripple or dynamic transient spike is required. Layout Guide R2 Q1 Q2 To achieve stable operation, low losses, and good thermal performance some layout considerations are necessary. FIGURE 20. SEQUENCE CIRCUIT CPVCC PGND The V range can be as low as ~1V (for V as low as the IN OUT 0.6V reference) and as high as 20V. There are some restrictions for running high VIN voltage. The maximum PHASE VIN voltage is 30V. The VIN + P + any ringing or other RFB VCC transients on the PHASE pin must be less than 30V. If V is IN 20V, it is recommended to limit P to 5V. VCC VOUT Switching Frequency CIN The switching frequency is a fixed 600kHz clock, which is determined by the internal oscillator. However, all of the other COUT1 (DECOUPLE) timing mentioned (POR delay, OCP sample, soft-start, etc.) is independent of the clock frequency (unless otherwise noted). PGND Selection of the Input Capacitor The input filter capacitor should be based on how much ripple FIGURE 21. RECOMMENDED LAYOUT the supply can tolerate on the DC input line. The larger the capacitor, the less ripple expected but consideration should be • The ground connection between pin 11 and pins 1 to 4 should be a solid ground plane under the module. taken for the higher surge current during power-up. The ISL8201M provides the soft-start function that controls and • Place a high frequency ceramic capacitor between (1) VIN limits the current surge. The value of the input capacitor can be and PGND (pin 11) and (2) PVCC and PGND (pins 1 to 4) as calculated by Equation5: I t IN C = ------------------- (EQ. 5) IN V FN6657 Rev 3.00 Page 12 of 16 October 28, 2014

ISL8201M close to the module as possible to minimize high frequency Thermal Considerations noise. Experimental power loss curves along with  from thermal JA • Use large copper areas for power path (VIN, PGND, VOUT) modeling analysis can be used to evaluate the thermal to minimize conduction loss and thermal stress. Also, use consideration for the module. The derating curves are derived multiple vias to connect the power planes in different layers. from the maximum power allowed while maintaining the temperature below the maximum junction temperature of • Keep the trace connection to the feedback resistor short. +125°C. In actual application, other heat sources and design • Avoid routing any sensitive signal traces near the PHASE margin should be considered. node. 3.5 12 23..50 1.5V 3.3V T (A) 10 EN 8 W) 2.0 0.6V URR 3.3V 1.5V OSS ( 1.5 AD C 6 0.6V L LO 4 1.0 X. A M 2 0.5 0.0 0 0 2 4 6 8 10 60 70 80 90 100 110 LOAD CURRENT (A) AMBIENT TEMPERATURE (°C) FIGURE 22. POWER LOSS vs LOAD CURRENT (5V ) FIGURE 23. DERATING CURVE (5V ) IN IN 4.0 12 1.5V 3.5 5.0V A) 10 0.6V 3.0 3.3V T ( W) 2.5 2.5V RREN 8 5.0V S ( 2.0 1.5V CU 6 LOS 1.5 0.6V OAD 2.5V L 4 1.0 AX. 3.3V M 2 0.5 0.0 0 0 2 4 6 8 10 60 70 80 90 100 110 LOAD CURRENT (A) AMBIENT TEMPERATURE (°C) FIGURE 24. POWER LOSS vs LOAD CURRENT (12V ) FIGURE 25. DERATING CURVE (12V ) IN IN © Copyright Intersil Americas LLC 2009-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6657 Rev 3.00 Page 13 of 16 October 28, 2014

ISL8201M Package Description Stencil Pattern Design The structure of ISL8201M belongs to the Quad Flat-pack Reflowed solder joints on the perimeter I/O lands should have No-lead package (QFN). This kind of package has advantages, about a 50µm to 75µm (2mil to 3mil) standoff height. The solder such as good thermal and electrical conductivity, low weight and paste stencil design is the first step in developing optimized, small size. The QFN package is applicable for surface mounting reliable solder joins. Stencil aperture size to land size ratio should technology and is being more readily used in the industry. The typically be 1:1. The aperture width may be reduced slightly to ISL8201M contains several types of devices, including resistors, help prevent solder bridging between adjacent I/O lands. To capacitors, inductors and control ICs. The ISL8201M is a copper reduce solder paste volume on the larger thermal lands, it is leadframe based package with exposed copper thermal pads, recommended that an array of smaller apertures be used instead which have good electrical and thermal conductivity. The copper of one large aperture. It is recommended that the stencil printing leadframe and multi component assembly is overmolded with area cover 50% to 80% of the PCB layout pattern. A typical solder polymer mold compound to protect these devices. stencil pattern is shown in the Package Outline Drawing L15.15x15 on page15. The gap width between pad to pad is The package outline and typical PCB layout pattern design and 0.6mm. The user should consider the symmetry of the whole typical stencil pattern design are shown in the package outline stencil pattern when designing its pads. A laser cut, stainless steel drawing L15.15x15 on page15. The module has a small size stencil with electropolished trapezoidal walls is recommended. of 15mmx15mm x 3.5mm. Figure26 shows typical reflow Electropolishing "smoothes" the aperture walls resulting in profile parameters. These guidelines are general design rules. reduced surface friction and better paste release which reduces Users could modify parameters according to their application. voids. Using a trapezoidal section aperture (TSA) also promotes paste release and forms a "brick like" paste deposit that assists in PCB Layout Pattern Design firm component placement. A 0.1mm to 0.15mm stencil thickness The bottom of ISL8201M is leadframe footprint, which is is recommended for this large pitch (1.3mm) QFN. attached to PCB by surface mounting process. The PCB layout Reflow Parameters pattern is shown in the Package Outline Drawing L15.15x15 on page15. The PCB layout pattern is essentially 1:1 with the Due to the low mount height of the QFN, "No Clean" Type 3 QFN exposed pad and I/O termination dimensions, except for solder paste per ANSI/J-STD-005 is recommended. Nitrogen the PCB lands being a slightly extended distance of 0.2mm purge is also recommended during reflow. A system board (0.4mm max) longer than the QFN terminations, which allows reflow profile depends on the thermal mass of the entire for solder filleting around the periphery of the package. This populated board, so it is not practical to define a specific ensures a more complete and inspectable solder joint. The soldering profile just for the QFN. The profile given in Figure26 thermal lands on the PCB layout should match 1:1 with the is provided as a guideline, to be customized for varying package exposed die pads. manufacturing practices and applications. 300 PEAK TEMPERATURE +230°C~+245°C; Thermal Vias TYPICALLY 60s-70s ABOVE +220°C A grid of 1.0mm to 1.2mm pitch thermal vias, which drops 250 KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP. down and connects to buried copper plane(s), should be p0l.a3cmemd uton d0e.3r 3thmem th ienr dmiaaml laentedr. wTihthe tvhiea sb sahrroeul lpdl abtee da btoo uatb out E (°C) 200 SALNODW S ORAAKM PFR (3O°MC/ s+ 1M0A0°XC) R 1.0 ounce copper. Although adding more vias (by decreasing U TO +180°C FOR 90s~120s T 150 A via pitch) will improve the thermal performance, diminishing R E returns will be seen as more and more vias are added. Simply P use as many vias as practical for the thermal land size and TEM 100 your board design rules allow. RAMP RATE 1.5°C FROM +70°C TO +90°C 50 0 0 100 150 200 250 300 350 DURATION (s) FIGURE 26. TYPICAL REFLOW PROFILE FN6657 Rev 3.00 Page 14 of 16 October 28, 2014

OctoFN6 Package Outline Drawing ISL8 b6 L15.15x15 2 e5 0 r7 1 2R 15 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) M 8 , 2ev Rev 3, 8/10 0 3 14.0 0 2X 7.70 23X 1.30 5.90 7x 1.70 INDEPXIN A 1REA 1151413 12 X40.2SAB1.30 12 131415 1 4X 11.9.800 2 3.80 2 11X 0.80 3 3.10 3 6.90 4 4 5.10 5 5 0.90 1.90 11 6 15.0±0.2 15.8±0.2 6 7 11 2.10 13.80 7 9.0 8 8 2.10 6.0000 5.0 9 9 0.30 2.90 45° 10 (33x0.4) 0.05MSAB 33x 0.5 10 2X 1 .125 15.0±0.2 5.80 3.0 21X 1.0 15.8±0.2 4.60 4.80 TOP VIEW 2.20 4X 7.90 BOTTOM VIEW 5° ALL AROUND 0.2S 3.5±0.2 S 0.5 NOTES: 0.05 S 1. Dimensions are in millimeters. 2. Unless otherwise specified, tolerance : Decimal ± 0.05; SIDE VIEW Body Tolerance ±0.1mm P a 3. The configuration of the pin #1 identifier is optional, but must be g e located within the zone indicated. The pin #1 identifier may be 1 either a mold or mark feature. 5 o f 1 6

OctobFN66 86..3100 7.00 6.20 5.70 4.90 4.40 3.60 3.10 2.30 1.30 4.60 5.60 8.30 8.29 8.30 6.92 6.28 5.62 4.98 4.32 3.683.02 2.38 0.420.00 0.22 0.88 1.52 2.18 2.82 3.48 4.12 ISL82 er 257R 45..8600 66..1088 8.29 01M 8, 20ev 3 34..5300 54..5827 65..9592 14.0 3.00 Package Boundary 4.22 4.22 0 3.57 3.58 2.20 8.30 2.92 2.92 1.70 6.00 2.27 2.28 0.90 5.10 1.62 1.62 0.40 0.97 0.98 3.10 0.0 0.0 0.32 0.32 0.00 0.00 0.40 2.10 0.33 0.32 0.90 0.98 0.98 1.70 0.90 1.63 1.63 2.20 1.90 2.28 2.28 3.00 8.30 2.93 2.93 4.00 4.88 3.58 4.23 8.30 5.53 4.88 5.53 7.01 0 0 0 0 0 0 0 0 8.3 5.2 3.1 2.2 1.2 0.0 4.6 5.6 8.3 8.31 0 0 7 3 5 0 2 8 20 2 8 2828 2 7 20 0 TYPICAL RECOMMENDED LAND PATTERN 8.3 7.0 5.2 4.6 4.1 3.5 3.0 2.3 0.40.0 0.2 0.8 1.52.12.83.4 4.1 6.0 6.77.0 8.3 STENCIL PATTERN WITH SQUARE PADS-2 0 0 0 0 5 8 0 0 0 9 8 6 0 3 1 3 9 6 4. 2. 1. 1. 1. 2. 4. 5. 6. 0 0 0. 6.60 6.60 4.80 3.75 3.40 3.15 1.80 0.30 0.00 0.00 0.60 0.30 3.15 1.20 3.60 2.20 P 3.75 a 3.70 g e 4.30 4.20 1 6.60 6 6.60 o f 1 6 0 0 0 0 0 0 0 0 0 7 9 3 5 9 0 4 0 3 6. 4. 4. 2. 0. 0. 1. 2. 4. STENCIL PATTERN WITH SQUARE PADS-1