DATASHEET ISL8487E, ISL81487L, ISL81487E FN6051 ±15kV ESD Protected, 1/8 Unit Load, 5V, Low Power, High Speed or Slew Rate Rev.8.00 Limited RS-485/RS-422 Transceivers Sep 20, 2018 The ISL8487E, ISL81487L, and ISL81487E RS-485/RS-422 Features devices are ESD protected, fractional unit load (UL), • RS-485 I/O pin ESD protection . . . . . . . . . . . ±15kV HBM BiCMOS, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced - Class 3 ESD level on all other pins . . . . . . . >7kV HBM communication. Each driver output/receiver input is • Fractional unit load allows up to 256 devices on the bus protected against ±15kV ESD strikes without latch-up. Unlike • Specified for 10% tolerance supplies competitive devices, this device family is specified for 10% tolerance supplies (4.5V to 5.5V). • High data rate version (ISL81487E). . . . . . . up to 5Mbps All devices present a 1/8 unit load to the RS-485 bus, which • Slew rate limited versions for error free data allows up to 256 transceivers on the network for large node transmission (ISL8487E, ISL81487L) . . . . .up to 250kbps count systems (for example, process automation and remote • Low current shutdown mode (except ISL81487E) . . . 0.5µA meter reading systems). In a remote utility meter reading • Low quiescent supply current: system, individual utility meter readings (in apartments, for example) are routed to a concentrator with an RS-485 - ISL8487E, ISL81487L . . . . . . . . . . . 145µA (maximum) network, so the high allowed node count minimizes the - ISL81487E . . . . . . . . . . . . . . . . . . . . 420µA (maximum) number of repeaters required to network all the meters. Data • -7V to +12V common mode input voltage range for all meters is then read out from the concentrator from a • Three state Rx and Tx outputs single access port or a wireless link. • 30ns propagation delays, 5ns skew (ISL81487E) Slew rate limited drivers on the ISL8487E and ISL81487L reduce EMI and minimize reflections from improperly • Half duplex pinouts terminated transmission lines or unterminated stubs in • Operate from a single +5V supply (10% tolerance) multidrop and multipoint applications. Data rates up to 250kbps are achievable with these devices. • Current limiting and thermal shutdown for driver overload protection Data rates up to 5Mbps are achievable by using the • Pin compatible replacements for: MAX487E, (ISL8487E); ISL81487E, which features higher slew rates. LTC1487, ADM1487 (ISL81487L); MAX1487E, ST485ER The receiver (Rx) inputs feature a “fail-safe if open” design, (ISL81487E) which ensures a logic high Rx output if Rx inputs are floating. • Pb-free plus anneal available (RoHS compliant) The driver (Tx) outputs are short-circuit protected, even for Applications voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to • High node count networks prevent damage if power dissipation becomes excessive. • Automated utility meter reading systems The half duplex devices multiplex the Rx inputs and Tx • Factory automation outputs to allow transceivers with Rx and Tx disable functions in 8 lead packages. • Security networks • Building environmental control systems Related Literature • Industrial/process control networks For a full list of related documents, visit our website: • ISL8487E, ISL81487L, and ISL81487E product pages TABLE 1. SUMMARY OF FEATURES PART HALF/FULL NO. OF DEVICES DATA RATE SLEW RATE RECEIVER/ QUIESCENT LOW POWER PIN NUMBER DUPLEX ALLOWED ON BUS (Mbps) LIMITED? DRIVER ENABLE? ICC (A) SHUTDOWN? COUNT ISL8487E Half 256 0.25 Yes Yes 120 Yes 8 ISL81487L Half 256 0.25 Yes Yes 120 Yes 8 ISL81487E Half 256 5 No Yes 350 No 8 FN6051 Rev.8.00 Page 1 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Typical Operating Circuits (cid:24)(cid:57) (cid:24)(cid:57) (cid:27) (cid:20)(cid:19)(cid:19)(cid:81)(cid:41) (cid:20)(cid:19)(cid:19)(cid:81)(cid:41) (cid:27) (cid:53)(cid:51)(cid:56) (cid:57)(cid:38)(cid:38) (cid:57)(cid:38)(cid:38) (cid:53)(cid:51)(cid:56) (cid:20) (cid:53)(cid:50) (cid:53)(cid:37) (cid:53)(cid:50) (cid:20) (cid:36)(cid:18)(cid:60) (cid:25) (cid:25) (cid:36)(cid:18)(cid:60) (cid:21) (cid:53)(cid:40) (cid:53)(cid:40) (cid:21) (cid:22) (cid:39)(cid:40) (cid:37)(cid:18)(cid:61) (cid:26) (cid:53)(cid:55)(cid:21) (cid:57)(cid:41)(cid:54) (cid:53)(cid:55)(cid:20) (cid:26) (cid:37)(cid:18)(cid:61) (cid:39)(cid:40) (cid:22) (cid:23) (cid:39)(cid:44) (cid:39)(cid:44) (cid:23) (cid:53)(cid:37) (cid:42)(cid:49)(cid:39) (cid:42)(cid:49)(cid:39) (cid:24) (cid:24) To calculate the resistor values, refer to TB509. Ordering Information TAPE AND REEL PART NUMBER () PART MARKING TEMP. RANGE (°C) (UNITS) (Note1) PACKAGE PKG. DWG. # ISL8487EIBZ 8487EIBZ -40 to +85 - 8 Ld SOIC M8.15 (Pb-free) ISL8487EIBZ-T 8487EIBZ -40 to +85 2.5k 8 Ld SOIC M8.15 (Pb-free) ISL8487EIPZ (not 8487EIPZ -40 to +85 - 8 Ld PDIP E8.3 recommended for new designs, (Pb-free, Note4) recommended replacement ISL81487LIPZ) ISL81487LIBZ 81487LIBZ -40 to +85 - 8 Ld SOIC M8.15 (Pb-free) ISL81487LIBZ-T 81487LIBZ -40 to +85 2.5k 8 Ld SOIC M8.15 (Pb-free) ISL81487LIPZ 81487LIPZ -40 to +85 - 8 Ld PDIP E8.3 (Pb-free, Note4) ISL81487EIBZ 81487EIBZ -40 to +85 - 8 Ld SOIC M8.15 (Pb-free) ISL81487EIBZ-T 81487EIBZ -40 to +85 2.5k 8 Ld SOIC M8.15 (Pb-free) ISL81487EIPZ ISL81487EIPZ -40 to +85 - 8 Ld PDIP E8.3 (Pb-free, Note4) NOTES: 1. Refer to TB347 for details about reel specifications. 2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 3. For Moisture Sensitivity Level (MSL), see the ISL8487E, ISL81487L, and ISL81487E product information pages. For more information about MSL, see TB363. 4. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN6051 Rev.8.00 Page 2 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Pinout PDIP, SOIC TOP VIEW RO 1 8 VCC R RE 2 7 B/Z DE 3 6 A/Y DI 4 D 5 GND Pin Descriptions PIN FUNCTION RO Receiver output. RO is high if A > B by at least 0.2V; RO is low if A < B by 0.2V or more; RO is high if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs Y and Z are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y 15kV HBM ESD protected, RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input (A) if DE=0; pin is an output (Y) if DE = 1. B/Z 15kV HBM ESD protected, RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. VCC System power supply input (4.5V to 5.5V). Truth Tables TRANSMITTING RECEIVING INPUTS OUTPUTS INPUTS OUTPUT RE DE DI Z Y RE DE A-B RO X 1 1 0 1 0 X ≥ +0.2V 1 X 1 0 1 0 0 X ≤ -0.2V 0 0 0 X High-Z High-Z 0 X Inputs Open 1 1 0 X High-Z High-Z 1 X X High-Z (Note12) (Note12) (Note12) 1 0 X High-Z FN6051 Rev.8.00 Page 3 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Thermal Resistance (Typical, Note5) JA (°C/W) Input Voltages 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . 170 DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) 8 Ld PDIP Package (Note6) . . . . . . . . . . . . . . . . . . 140 Input/Output Voltages Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Short-Circuit Duration (SOIC - Lead Tips Only) Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . See “Electrical Specifications” Operating Conditions Temperature Range ISL8XXXIX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can permanently damage the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. JA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379 for details. 6. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. (Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note7 TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT DC CHARACTERISTICS Driver Differential VOUT (No Load) VOD1 Full - - VCC V Driver Differential VOUT (with Load) VOD2 R = 50Ω (RS-422), (Figure1) Full 2 3 - V R = 27Ω (RS-485), (Figure1) Full 1.5 2.3 5 V Change in Magnitude of Driver VOD R = 27Ω or 50Ω, (Figure1) Full - 0.01 0.2 V Differential VOUT for Complementary Output States Driver Common-Mode VOUT VOC R = 27Ω or 50Ω, (Figure1) Full - - 3 V Change in Magnitude of Driver VOC R = 27Ω or 50Ω, (Figure1) Full - 0.01 0.2 V Common-Mode VOUT for Complementary Output States Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V Logic Input Current IIN1 DE, DI, RE Full -2 - 2 µA Input Current (A/Y, B/Z), (Note15) IIN2 DE = 0V, VCC = 4.5 to VIN = 12V Full - - 140 µA 5.5V VIN = -7V Full - - -120 µA IIN2 DE = 0V, VCC = 0V VIN = 12V Full - - 180 µA VIN = -7V Full - - -100 µA Receiver Differential Threshold VTH -7V  VCM  12V Full -0.2 - 0.2 V Voltage Receiver Input Hysteresis VTH VCM = 0V 25 - 70 - mV Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full 3.5 - - V Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V Three-State (High Impedance) IOZR 0.4V  VO  2.4V Full - - 1 µA Receiver Output Current Receiver Input Resistance RIN -7V  VCM  12V Full 96 - - kΩ FN6051 Rev.8.00 Page 4 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note7 (Continued) TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT No-Load Supply Current, (Note8) ICC ISL81487E, DI, RE = 0V DE = VCC Full - 400 500 µA or VCC DE = 0V Full - 350 420 µA ISL8487E, ISL81487L, DE = VCC Full - 160 200 µA DI, RE = 0V or VCC DE = 0V Full - 120 145 µA Shutdown Supply Current ISHDN (Note12), DE = 0V, RE = VCC, DI = 0V or VCC Full - 0.5 8 µA Driver Short-Circuit Current, IOSD1 DE = VCC, -7V  VY or VZ  12V, (Note9) Full 35 - 250 mA VO = High or Low Receiver Short-Circuit Current IOSR 0V  VO  VCC Full 7 - 85 mA SWITCHING CHARACTERISTICS (ISL81487E) Driver Input to Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure2) Full 15 24 50 ns Driver Output Skew tSKEW RDIFF = 54Ω, CL = 100pF, (Figure2) Full - 3 10 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure2) Full 3 12 25 ns Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure2) Full - 14 70 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure2) Full - 14 70 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure2) Full - 44 70 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure2) Full - 21 70 ns Receiver Input to Output Delay tPLH, tPHL (Figure4) Full 30 90 150 ns Receiver Skew | tPLH - tPHL | tSKD (Figure4) 25 - 5 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure5) Full - 9 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure5) Full - 9 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure5) Full - 9 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure5) Full - 9 50 ns Maximum Data Rate fMAX Full 5 - - Mbps SWITCHING CHARACTERISTICS (ISL8487E) Driver Input to Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure2) Full 250 650 2000 ns Driver Output Skew tSKEW RDIFF = 54Ω, CL = 100pF, (Figure2) Full - 160 800 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure2) Full 250 900 2000 ns Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure3, Note10) Full 250 1000 2000 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure3, Note10) Full 250 860 2000 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure3) Full 300 660 3000 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure3) Full 300 640 3000 ns Receiver Input to Output Delay tPLH, tPHL (Figure4) Full 250 500 2000 ns Receiver Skew | tPLH - tPHL | tSKD (Figure4) 25 - 60 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure5, Note11) Full - 10 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure5, Note11) Full - 10 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure5) Full - 10 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure5) Full - 10 50 ns Maximum Data Rate fMAX Full 250 - - kbps Time to Shutdown tSHDN (Note12) Full 50 120 600 ns Driver Enable from Shutdown to tZH(SHDN) CL = 100pF, SW = GND, (Figure3, Notes12 and Full - 1000 2000 ns Output High 13) Driver Enable from Shutdown to tZL(SHDN) CL = 100pF, SW = VCC, (Figure3, Notes12 and Full - 1000 2000 ns Output Low 13) FN6051 Rev.8.00 Page 5 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note7 (Continued) TEMP PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNIT Receiver Enable from Shutdown to tZH(SHDN) CL = 15pF, SW = GND, (Figure5, Notes12 and Full - 800 2500 ns Output High 14) Receiver Enable from Shutdown to tZL(SHDN) CL = 15pF, SW = VCC, (Figure5, Notes12 and Full - 800 2500 ns Output Low 14) SWITCHING CHARACTERISTICS (ISL81487L) Driver Input to Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure2) Full 150 650 1200 ns Driver Output Skew tSKEW RDIFF = 54Ω, CL = 100pF, (Figure2) Full - 160 600 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure2) Full 250 900 1200 ns Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure3, Note10) Full 100 1000 1500 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure3, Note10) Full 100 1000 1500 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure3) Full 150 750 1500 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure3) Full 150 750 1500 ns Receiver Input to Output Delay tPLH, tPHL (Figure4) Full 30 175 250 ns Receiver Skew | tPLH - tPHL | tSKD (Figure4) 25 - 13 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure5, Note11) Full - 10 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure5, Note11) Full - 10 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure5) Full - 10 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure5) Full - 10 50 ns Maximum Data Rate fMAX Full 250 - - kbps Time to Shutdown tSHDN (Note12) Full 50 140 600 ns Driver Enable from Shutdown to tZH(SHDN) CL = 100pF, SW = GND, (Figure3, Notes12 and Full - 1100 2000 ns Output High 13) Driver Enable from Shutdown to tZL(SHDN) CL = 100pF, SW = VCC, (Figure3, Notes12 and Full - 1000 2000 ns Output Low 13) Receiver Enable from Shutdown to tZH(SHDN) CL = 15pF, SW = GND, (Figure3, Notes12 and Full - 900 2000 ns Output High 14) Receiver Enable from Shutdown to tZL(SHDN) CL = 15pF, SW = VCC, (Figure3, Notes12 and Full - 900 2000 ns Output Low 14) ESD PERFORMANCE RS-485 Pins (A/Y, B/Z) Human Body Model 25 - 15 - kV All Other Pins 25 - >7 - kV NOTES: 7. Currents into device pins are positive; currents out of device pins are negative. Voltages are referenced to ground unless otherwise specified. 8. Supply current specification is valid for loaded drivers when DE = 0V. 9. Applies to peak current. See “Typical Performance Curves” for more information. 10. When testing the ISL8487E and ISL81487L, keep RE = 0 to prevent the device from entering shutdown (SHDN). 11. When testing the ISL8487E and ISL81487L, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN. 12. The ISL8487E and ISL81487L go into SHDN by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are specified not to enter SHDN. If the inputs are in this state for at least 600ns, the parts are specified to enter SHDN. See “Low Power Shutdown Mode (Excluding ISL81487E)” for more information. 13. Keep RE = VCC and set the DE signal low time >600ns to ensure that the device enters SHDN. 14. Set the RE signal high time >600ns to ensure that the device enters SHDN. 15. Devices meeting these limits are denoted as 1/8 unit load (1/8 UL) transceivers. The RS-485 standard allows up to 32 UL on the bus, so there can be 256 1/8 UL devices on a bus. FN6051 Rev.8.00 Page 6 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Test Circuits and Waveforms R DE VCC Z DI D VOD Y R VOC FIGURE 1. DRIVER VOD AND VOC 3V DI 1.5V 1.5V 0V tPLH tPHL VOH OUT (Y) 50% 50% VOL tPHL tPLH VOH OUT (Z) 50% 50% CL = 100pF DE VOL VCC DI Z D RDIFF 90% 90% +VOD Y CL = 100pF DIFF OUT (Y - Z) 10% 10% -VOD SIGNAL GENERATOR tR tF SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES FN6051 Rev.8.00 Page 7 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Test Circuits and Waveforms (Continued) DE DI Z 500 VCC D SIGNAL Y SW GND GENERATOR CL (SHDN) for ISL8487E and ISL81487L only. 3V PARAMETER OUTPUT RE DI SW CL (pF) DE NOTE 7 1.5V 1.5V 0V tHZ Y/Z X 1/0 GND 15 tLZ Y/Z X 0/1 VCC 15 tZH, tZH(SHDN) tHZ NOTE 7 OUTPUT HIGH tZH Y/Z 0 1/0 GND 100 VOH - 0.5V VOH (Note10) OUT (Y, Z) 2.3V tZL Y/Z 0 0/1 VCC 100 0V (Note10) tZH(SHDN) Y/Z 1 1/0 GND 100 tZLN, tOZTL(ES H7DN) tLZ (Note12) VCC OUT (Y, Z) tZLSHDN) Y/Z (Not1e 12) 0/1 VCC 100 2.3V VOL + 0.5V VOL OUTPUT LOW FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES RE 3V 15pF B A 1.5V 1.5V +1.5V RO A R 0V tPLH tPHL SIGNAL VCC GENERATOR RO 50% 50% 0V FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS FIGURE 4. RECEIVER PROPAGATION DELAY RE B RO 1k VCC R NOTE 7 SIGNAL A SW GND 3V GENERATOR 15pF RE 1.5V 1.5V 0V (SHDN) for ISL8487E and ISL81487L only. tZH, tZH(SHDN) tHZ NOTE 7 OUTPUT HIGH PARAMETER DE A SW VOH - 0.5V VOH tHZ 0 +1.5V GND RO 1.5V 0V tLZ 0 -1.5V VCC tZH (Note11) 0 +1.5V GND tZL, tZL(SHDN) tLZ NOTE 7 tZL (Note11) 0 -1.5V VCC VCC RO tZH(SHDN) (Note12) 0 +1.5V GND 1.5V VOL + 0.5V VOL tZL(SHDN) (Note12) 0 -1.5V VCC OUTPUT LOW FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES FN6051 Rev.8.00 Page 8 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Application Information maximum data rate on these slew rate limited versions is 250kbps. The ISL81487E drivers are not limited, so faster RS-485 and RS-422 are differential (balanced) data output transition times allow data rates of at least 5Mbps. transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 Data Rate, Cables, and Terminations transceivers are also RS-422 compliant. RS-422 is a RS-485/422 are intended for network lengths up to 4000ft, point-to-multipoint (multidrop) standard that allows only one but the maximum system data rate decreases as the driver and up to 10 receivers on each bus (assuming one transmission length increases. Devices operating at 5Mbps unit load devices). RS-485 is a true multipoint standard that are limited to lengths less than a few hundred feet, while the allows up to 32 one unit load devices (any combination of 250kbps versions can operate at full data rates with lengths drivers and receivers) on each bus. To allow for multipoint in excess of 1000ft. operation, the RS-485 specification requires that drivers handle bus contention without sustaining any damage. Twisted pair cable is the cable of choice for RS-485/422 networks. Twisted pair cables tend to pick up noise and An important advantage of RS-485 is the extended other electromagnetically induced voltages as Common-Mode Range (CMR), which specifies that the common-mode signals that are effectively rejected by the driver outputs and receiver inputs withstand signals ranging differential receivers in these ICs. from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000ft, so the wide CMR is necessary to handle Proper termination is imperative to minimize reflections ground potential differences and voltages induced in the when using the 5Mbps device. Short networks using the cable by external fields. 250kbps versions do not need to be terminated, but terminations are recommended unless power dissipation is Receiver Features an overriding concern. These devices use a differential input receiver for maximum In point-to-point or point-to-multipoint (single driver on bus) noise immunity and common-mode rejection. Input sensitivity networks, terminate the main cable in its characteristic is 200mV, as required by the RS-422 and RS-485 impedance (typically 120Ω) at the end farthest from the specifications. driver. In multi-receiver applications, keep stubs connecting The receiver input resistance of 96kΩ surpasses the RS-422 receivers to the main cable as short as possible. In specification of 4kΩ and is eight times the RS-485 Unit Load multipoint (multi-driver) systems, terminate the main cable in (UL) requirement of 12kΩ minimum. Thus, these products its characteristic impedance at both ends. Keep stubs are known as one-eighth UL transceivers. A network can connecting a transceiver to the main cable as short as host up to 256 of these devices still complying with the possible. RS-485 loading specification. Built-In Driver Overload Protection The receiver inputs function with common-mode voltages as The RS-485 specification requires that drivers survive worst great as 7V outside the power supplies (that is, +12V and case bus contentions undamaged. These devices meet this -7V), making them ideal for long networks in which induced requirement with driver output short-circuit current limits and voltages are a realistic concern. on-chip thermal shutdown circuitry. All the receivers include a “fail-safe if open” function that The driver output stages incorporate short-circuit current guarantees a high level receiver output if the receiver inputs limiting circuitry that ensures the output current never are unconnected (floating). exceeds the RS-485 specification, even at the Receivers easily meet the data rates supported by the common-mode voltage range extremes. These devices also corresponding driver. The receiver outputs are three-statable use a foldback circuit that reduces the short-circuit current using the active low RE input. and as a result, the power dissipation when the contending voltage exceeds either supply. Driver Features In the event of a major short-circuit condition, the thermal The RS-485/422 driver is a differential output device that shutdown feature disables the drivers when the die delivers at least 1.5V across a 54Ω load (RS-485) and at temperature becomes excessive. This eliminates the power least 2V across a 100Ω load (RS-422). The drivers feature dissipation, allowing the die to cool. The drivers low propagation delay skew to maximize bit width and to automatically re-enable after the die temperature drops minimize EMI. about 15°C. If the condition persists, the thermal Driver outputs are three-statable using the active high DE shutdown/re-enable cycle repeats until the fault is cleared. input. Receivers stay operational during thermal shutdown. The ISL8487E and ISL81487L driver outputs are slew rate limited to minimize EMI and to minimize reflections in unterminated or improperly terminated networks. The FN6051 Rev.8.00 Page 9 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Low Power Shutdown Mode (Excluding ISL81487E) ESD damage because they typically connect to an exposed port on the exterior of the finished product. Touching the port These CMOS transceivers all use a fraction of the power pins or connecting a cable can cause an ESD event that required by their bipolar counterparts, but the ISL8487E and destroys unprotected ICs. The ESD structures protect the ISL81487L include a shutdown feature that reduces the device whether or not it is powered up, protect without already low quiescent ICC to a 500nA trickle. They enter allowing any latchup mechanism to activate, and without shutdown whenever the receiver and driver are degrading the RS-485 common-mode range of -7V to +12V. simultaneously disabled (RE=VCC and DE=GND) for a This built-in ESD protection eliminates the need for board period of at least 600ns. Disabling both the driver and the level protection structures (for example, transient receiver for less than 50ns guarantees that shutdown is not suppression diodes), and the associated undesirable entered. capacitive load they present. Note that receiver and driver enable times increase when Human Body Model Testing enabling from shutdown. Refer to Note10 through 14 at the end of the “Electrical Specifications” table for more information. This test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge stored ESD Protection on a 100pF capacitor through a 1.5k current limiting resistor All pins on the interface devices include Class 3 Human Body into the pin under test. The HBM method determines an IC’s Model (HBM) ESD protection structures, but the RS-485 pins ability to withstand the ESD events typically present during (driver outputs and receiver inputs) incorporate advanced handling and manufacturing. The RS-485 pin survivability on structures allowing them to survive ESD events in excess of this high ESD family has been characterized to be in excess of 15kV HBM. The RS-485 pins are particularly vulnerable to 15kV for discharges to GND. Typical Performance Curves VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified 90 3.6 80 3.4 V) mA) 70 GE ( 3.2 RDIFF = 100Ω NT ( 60 LTA E O 3 R V CUR 50 PUT 2.8 UT 40 UT UTP 30 AL O 2.6 ER O 20 ENTI 2.4 RDIFF = 54Ω V R RI E D 10 F 2.2 F DI 0 2 0 1 2 3 4 5 -40 -25 0 25 50 75 85 DIFFERENTIAL OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT VOLTAGE TEMPERATURE FN6051 Rev.8.00 Page 10 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Typical Performance Curves VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified 400 160 140 ISL81487E, DE = VCC, RE = X ISL81487E 120 350 Y OR Z = LOW 100 ISL81487E, DE = GND, RE = X A) 80 ISL8487E, ISL81487L 300 m T ( 60 RREN 2400 (µA)C250 CU 0 IC PUT -20 Y OR Z = HIGH 200 T -40 OU -60 ISL8487E, ISL81487L, DE = VCC, RE = X ISL81487E 150 -80 ISL8487E, ISL81487L -100 ISL8487E, ISL81487L, DE = GND, RE = GND -120 100 -7 -6 -4 -2 0 2 4 6 8 10 12 -40 -25 0 25 50 75 OUTPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT FIGURE 9. SUPPLY CURRENT vs TEMPERATURE VOLTAGE 750 250 700 s) tPLHY 200 AY (n 650 tPLHZ |tPLHY - tPHLZ| L 150 E D ROPAGATION 565000 tPtHPLHYLZ SKEW (ns) 100 |tPHLY - tPLHZ| P 50 500 |CROSS PT. OF Y & Z - CROSS PT. OF Y & Z| 450 0 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 10. DRIVER PROPAGATION DELAY vs FIGURE 11. DRIVER SKEW vs TEMPERATURE TEMPERATURE (ISL8487E and ISL81487L) (ISL8487E and ISL81487L) 30 5 28 4 Y (ns) 26 |tPHLY - tPLHZ| A L E 3 D 24 N PAGATIO 22 tPtPLLHHYZ tPHLZ KEW (ns) 2 |tPLHY - tPHLZ| O 20 S R P 1 18 |CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z| tPHLY 16 0 -40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. DRIVER PROPAGATION DELAY vs FIGURE 13. DRIVER SKEW vs TEMPERATURE TEMPERATURE (ISL81487E) (ISL81487E) FN6051 Rev.8.00 Page 11 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Typical Performance Curves VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified 5 RECEIVER OUTPUT (V) 0505 DI RROO ISL81I4S8L78L487ERDIFF = 54Ω, CL = 100pF 05 DRIVER INPUT (V) RECEIVER OUTPUT (V) 0505 RRDOOI ISL81IS48L78L487ERDIFF = 54Ω, CL = 100pF 0 DRIVER INPUT (V) T (V) 4 B/Z UT (V) 34 A/Y U 3 P P T ER OUT 12 A/Y VER OU 12 B/Z DRIV 0 DRI 0 TIME (400ns/DIV) TIME (400ns/DIV) FIGURE 14. DRIVER AND RECEIVER WAVEFORMS, FIGURE 15. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8487E and ISL81487L) HIGH TO LOW (ISL8487E and ISL81487L) EIVER OUTPUT (V) 05 DI RO RDIFF = 54Ω, CL = 100pF 05 DRIVER INPUT (V) EIVER OUTPUT (V) 05 RDOI RDIFF = 54Ω, CL = 100pF 05 DRIVER INPUT (V) C C E E R R V) 4 V) 4 T ( B/Z T ( A/Y U 3 U 3 P P T T OU 2 A/Y OU 2 B/Z R R E 1 E 1 V V RI RI D 0 D 0 TIME (20ns/DIV) TIME (20ns/DIV) FIGURE 16. DRIVER AND RECEIVER WAVEFORMS, FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL81487E) HIGH TO LOW (ISL81487E) Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 518 PROCESS: Si Gate CMOS FN6051 Rev.8.00 Page 12 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Sep 20, 2018 FN6051.8 Applied Renesas Header/Footer. Added Related Literature section. Updated Ordering Information table by removing retired parts ISL8487EIB, ISL81487LIB, ISL81487LIP, and ISL81487EIP, adding Notes 1 and 3, and adding tape and reel parts and column. Updated the Typical Operating Circuit diagram on page 2. Added Revision History section. Updated POD M8.15 to the latest revision. Changes are as follows: -Revision 1: Initial revision -Revision 1 to revision 2: Updated to new package outline drawing format by removing table, moving dimensions onto drawing, and adding land pattern -Revision 2 to revision 3: Changed the following values in Typical Recommended Landing Pattern: 2.41(0.095) to 2.20 (0.087) 0.76(0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Revision 3 to revision 4: Changed text in Note 1 from “1982” to “1994” FN6051 Rev.8.00 Page 13 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E Package Outline Drawings E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE N INCHES MILLIMETERS E1 INDEX SYMBOL MIN MAX MIN MAX NOTES AREA 1 2 3 N/2 A - 0.210 - 5.33 4 -B- A1 0.015 - 0.39 - 4 -A- D E A2 0.115 0.195 2.93 4.95 - BASE B 0.014 0.022 0.356 0.558 - PLANE A2 -C- A B1 0.045 0.070 1.15 1.77 8, 10 SEATING PLANE L CL C 0.008 0.014 0.204 0.355 - D1 D1 A1 eA D 0.355 0.400 9.01 10.16 5 B1 e eC C D1 0.005 - 0.13 - 5 B e E 0.300 0.325 7.62 8.25 6 B 0.010 (0.25) M C A B S E1 0.240 0.280 6.10 7.11 5 NOTES: e 0.100 BSC 2.54 BSC - 1. Controlling Dimensions: INCH. In case of conflict between eA 0.300 BSC 7.62 BSC 6 English and Metric dimensions, the inch dimensions control. eB - 0.430 - 10.92 7 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. L 0.115 0.150 2.93 3.81 4 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. N 8 8 9 4. Dimensions A, A1 and L are measured with the package seated Rev. 0 12/93 in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- For the most recent package outline drawing, see E8.3. sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6051 Rev.8.00 Page 14 of 16 Sep 20, 2018

ISL8487E, ISL81487L, ISL81487E M8.15 For the most recent package outline drawing, see M8.15. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6051 Rev.8.00 Page 15 of 16 Sep 20, 2018

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