DATASHEET ISL8105, ISL8105A FN6306 +5V or +12V Single-Phase Synchronous Buck Converter PWM Controller with Rev 5.00 Integrated MOSFET Gate Drivers April 15, 2010 The ISL8105, ISL8105A is a simple single-phase PWM Features controller for a synchronous buck converter. It operates from • Operates from +5V or +12V Bias Supply Voltage +5V or +12V bias supply voltage. With integrated linear - 1.0V to 12V Input Voltage Range (up to 20V possible regulator, boot diode, and N-Channel MOSFET gate drivers, with restrictions; see “Input Voltage Considerations” on the ISL8105, ISL8105A reduces external component count and page9) board space requirements. These make the IC suitable for a - 0.6V to VIN Output Voltage Range wide range of applications. • 0.6V Internal Reference Voltage Utilizing voltage-mode control, the output voltage can be - ±1.0% Tolerance Over the Commercial Temperature precisely regulated to as low as 0.6V. The 0.6V internal Range (0°C to +70°C) reference features a maximum tolerance of ±1.0% over the - ±1.5% Tolerance Over the Industrial Temperature commercial temperature range, and ±1.5% over the Range (-40°C to +85°C). industrial temperature range. Two fixed oscillator frequency • Integrated MOSFET Gate Drivers that Operate from versions are available; 300kHz (ISL8105 for high efficiency applications) and 600kHz (ISL8105A for fast transient VBIAS (+5V to +12V) - Bootstrapped High-side Gate Driver with Integrated applications). Boot Diode The ISL8105, ISL8105A features the capability of safe - Drives N-Channel MOSFETs start-up with pre-biased load. It also provides overcurrent • Simple Voltage-Mode PWM Control protection by monitoring the ON-resistance of the - Traditional Dual Edge Modulation bottom-side MOSFET to inhibit PWM operation appropriately. During start-up interval, the resistor connected • Fast Transient Response to BGATE/BSOC pin is employed to program overcurrent - High-Bandwidth Error Amplifier protection condition. This approach simplifies the - Full 0% to 100% Duty Cycle implementation and does not deteriorate converter • Fixed Operating Frequency efficiency. - 300kHz for ISL8105 Pinouts - 600kHz for ISL8105A ISL8105, ISL8105A (10 LD 3X3 DFN) • Fixed Internal Soft-Start with Pre-biased Load Capability TOP VIEW • Lossless, Programmable Overcurrent Protection - Uses Bottom-side MOSFET’s rDS(ON) BOOT 1 10 LX • Enable/Disable Function Using COMP/EN Pin TGATE 2 9 COMP/EN N/C 3 GND 8 FB • Output Current Sourcing and Sinking Currents GND 4 7 N/C • Pb-Free (RoHS Compliant) BGATE/BSOC 5 6 VBIAS Applications ISL8105, ISL8105A • 5V or 12V DC/DC Regulators (8 LD SOIC) TOP VIEW • Industrial Power Systems • Telecom and Datacom Applications BOOT 1 8 LX • Test and Measurement Instruments TGATE 2 7 COMP/EN • Distributed DC/DC Power Architecture GND 3 6 FB • Point of Load Modules BGATE/BSOC 4 5 VBIAS FN6306 Rev 5.00 Page 1 of 16 April 15, 2010

ISL8105, ISL8105A Ordering Information SWITCHING TEMPERATURE PART NUMBER PART FREQUENCY RANGE PACKAGE PKG. (Note) MARKING (kHz) (°C) (Pb-Free) DWG. # ISL8105CRZ* 5CRZ 300 0 to +70 10 Ld DFN L10.3x3C ISL8105IBZ* 8105 IBZ 300 -40 to +85 8 Ld SOIC M8.15 ISL8105IRZ* 5IRZ 300 -40 to +85 10 Ld DFN L10.3x3C ISL8105ACRZ* 05AZ 600 0 to +70 10 Ld DFN L10.3x3C ISL8105AIBZ* 8105 AIBZ 600 -40 to +85 8 Ld SOIC M8.15 ISL8105AIRZ* 5AIZ 600 -40 to +85 10 Ld DFN L10.3x3C ISL8105AEVAL1Z Evaluation Board *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Typical Application Diagram VIN +1V TO +12V VBIAS CHF CBULK +5V OR +12V CDCPL VBIAS BOOT COMP/EN CBOOT Q1 C1 TGATE LOUT C2 ISL8105 VOUT R2 LX COUT FB Q2 BGATE/BSOC GND RBSOC C3 R3 R1 R0 FN6306 Rev 5.00 Page 2 of 16 April 15, 2010

ApFN Block Diagram IS ril 15, 20106306Rev 5.0 L8105, ISL810 0 VBIAS 5 A DBOOT POR AND INTERNAL BOOT SOFT-START REGULATOR + SAMPLE AND - HOLD OC TGATE COMPARATOR 5V INT. 21.5A LX 20k PWM TO COMPARATOR INHIBIT BGATE/BSOC 0.6V + GATE - + CONTROL LOGIC ERROR - PWM VBIAS FB AMP DIS 5V INT. BGATE/BSOC 0.4V + DIS 20A - OSCILLATOR COMP/EN FIXED 300kHZ OR 600kHz GND P a g e 3 o f 1 6

ISL8105, ISL8105A Absolute Maximum Ratings Thermal Information Bias Voltage, VBIAS. . . . . . . . . . . . . . . . . . . . GND - 0.3V to +15.0V Thermal Resistance JA (°C/W) JC (°C/W) Boot Voltage, VBOOT. . . . . . . . . . . . . . . . . . . GND - 0.3V to +36.0V SOIC Package (Note 1). . . . . . . . . . . . 95 N/A TGATE Voltage, VTGATE. . . . . . . . . . . VLX - 0.3V to VBOOT + 0.3V DFN Package (Notes 1, 2). . . . . . . . . . 44 5.5 BGATE/BSOC Voltage, VBGATE/BSOC . .GND - 0.3 to VBIAS + 0.3V Maximum Junction Temperature LX Voltage, VLX. . . . . . . . . . . . . . . . . .GND - 0.3V to VBOOT + 0.3V (Plastic Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Upper Driver Supply Voltage, VBOOT - VLX . . . . . . . . . . . . . . . .15V Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Clamp Voltage, VBOOT - VBIAS. . . . . . . . . . . . . . . . . . . . . . . . . .24V Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below FB, COMP/EN Voltage . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6V http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Bias Voltage, VBIAS. . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V Ambient Temperature Range ISL8105C, ISL8105AC. . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL8105I, ISL8105AI. . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. E lectrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS INPUT SUPPLY CURRENTS Shutdown VBIAS Supply Current IVBIAS_S VBIAS=12V; Disabled 4 5.2 7 mA DISABLE Disable Threshold (COMP/EN pin) VDISABLE 0.375 0.4 0.425 V OSCILLATOR Nominal Frequency Range fOSC ISL8105C 270 300 330 kHz ISL8105I 240 300 330 kHz fOSC ISL8105AC 540 600 660 kHz ISL8105AI 510 600 660 kHz Ramp Amplitude (Note 3) VOSC 1.5 VP-P POWER-ON RESET Rising VBIAS Threshold VPOR_R 3.9 4.1 4.3 V VBIAS POR Threshold Hysteresis VPOR_H 0.30 0.35 0.40 V REFERENCE Nominal Reference Voltage VREF 0.6 V Reference Voltage Tolerance ISL8105C (0°C to +70°C) -1.0 +1.0 % ISL8105I (-40°C to +85°C) -1.5 +1.5 % ERROR AMPLIFIER DC Gain (Note 3) GAINDC 96 dB Unity Gain-Bandwidth (Note 3) UGBW 20 MHz Slew Rate (Note 3) SR 9 V/µs GATE DRIVERS TGATE Source Resistance RTG-SRCh VBIAS = 14.5V, 50mA Source Current 3.0  FN6306 Rev 5.00 Page 4 of 16 April 15, 2010

ISL8105, ISL8105A Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TGATE Source Resistance RTG-SRCl VBIAS = 4.25V, 50mA Source Current 3.5  TGATE Sink Resistance RTG-SNKh VBIAS = 14.5V, 50mA Source Current 2.7  TGATE Sink Resistance RTG-SNKl VBIAS = 4.25V, 50mA Source Current 2.7  BGATE Source Resistance RBG-SRCh VBIAS = 14.5V, 50mA Source Current 2.4  BGATE Source Resistance RBG-SRCl VBIAS = 4.25V, 50mA Source Current 2.75  BGATE Sink Resistance RBG-SNKh VBIAS = 14.5V, 50mA Source Current 2.0  BGATE Sink Resistance RBG-SNKl VBIAS = 4.25V, 50mA Source Current 2.1  OVERCURRENT PROTECTION (OCP) BSOC Current Source IBSOC ISL8105C; BGATE/BSOC Disabled 19.5 21.5 23.5 µA ISL8105I; BGATE/BSOC Disabled 18.0 21.5 23.5 µA NOTE: 3. Limits established by characterization and are not production tested. Functional Pin Description (SOIC, DFN) VBIAS (SOIC Pin 5, DFN Pin 6) This pin provides the bias supply for the ISL8105, as well as BOOT (SOIC Pin 1, DFN Pin 1) the bottom-side MOSFET's gate and the BOOT voltage for This pin provides ground referenced bias voltage to the the top-side MOSFET's gate. An internal 5V regulator will top-side MOSFET driver. A bootstrap circuit is used to create supply bias if VBIAS rises above 6.5V (but the BGATE/BSOC a voltage suitable to drive an N-Channel MOSFET (equal to and BOOT will still be sourced by VBIAS). Connect a well VBIAS minus the on-chip BOOT diode voltage drop), with decoupled +5V or +12V supply to this pin. respect to LX. FB (SOIC Pin 6, DFN Pin 8) TGATE (SOIC Pin 2, DFN Pin 2) This pin is the inverting input of the internal error amplifier. Connect this pin to the gate of top-side MOSFET; it provides Use FB, in combination with the COMP/EN pin, to the PWM-controlled gate drive. It is also monitored by the compensate the voltage-control feedback loop of the adaptive shoot-through protection circuitry to determine converter. A resistor divider from the output to GND is used when the top-side MOSFET has turned off. to set the regulation voltage. GND (SOIC Pin 3, DFN Pin 4) COMP/EN (SOIC Pin 7, DFN Pin 9) This pin represents the signal and power ground for the IC. This is a multiplexed pin. During soft-start and normal converter Tie this pin to the ground island/plane through the lowest operation, this pin represents the output of the error amplifier. impedance connection available. Use COMP/EN, in combination with the FB pin, to compensate BGATE/BSOC (SOIC Pin 4, DFN Pin 5) the voltage-control feedback loop of the converter. Connect this pin to the gate of the bottom-side MOSFET; it Pulling COMP/EN low (VDISABLE = 0.4V nominal) will provides the PWM-controlled gate drive (from VBIAS). This disable (shut-down) the controller, which causes the pin is also monitored by the adaptive shoot-through oscillator to stop, the BGATE and TGATE outputs to be held protection circuitry to determine when the lower MOSFET low, and the soft-start circuitry to re-arm. The external has turned off. pull-down device will initially need to overcome maximum of 5mA of COMP/EN output current. However, once the IC is During a short period of time following Power-On Reset disabled, the COMP output will also be disabled, so only a (POR) or shut-down release, this pin is also used to 20µA current source will continue to draw current. determine the current limit threshold of the converter. Connect a resistor (RBSOC) from this pin to GND. See When the pull-down device is released, the COMP/EN pin “Overcurrent Protection (OCP)” on page7 for equations. An will start to rise at a rate determined by the 20µA charging up overcurrent trip cycles the soft-start function, after two the capacitance on the COMP/EN pin. When the COMP/EN dummy soft-start time-outs. Some of the text describing the pin rises above the VDISABLE trip point, the ISL8105 will BGATE function may leave off the BSOC part of the name, begin a new initialization and soft-start cycle. when it is not relevant to the discussion. FN6306 Rev 5.00 Page 5 of 16 April 15, 2010

ISL8105, ISL8105A LX (SOIC Pin 8, DFN Pin 10) time, the BGATE/BSOC pin is initialized by disabling the BGATE driver and drawing BSOC (nominal 21.5µA) through Connect this pin to the source of the top-side MOSFET and the drain of the bottom-side MOSFET. It is used as the sink RBSOC. This sets up a voltage that will represent the BSOC for the TGATE driver and to monitor the voltage drop across trip point. At t2, there is a variable time period for the OCP the bottom-side MOSFET for overcurrent protection. This pin sample and hold operation (0ms to 3.4ms nominal; the is also monitored by the adaptive shoot-through protection longer time occurs with the higher overcurrent setting). The circuitry to determine when the top-side MOSFET has turned sample and hold uses a digital counter and DAC to save the off. voltage, so the stored value does not degrade, for as long as the VBIAS is above VPOR. See “Overcurrent Protection N/C (DFN Only; Pin3, Pin 7) (OCP)” on page7 for more details on the equations and These two pins in the DFN package are No Connect. variables. Upon the completion of sample and hold at t3, the soft-start operation is initiated, and the output voltage ramps Functional Description up between t4 and t5. Initialization (POR and OCP Sampling) BGATE Figure 1 shows a start-up waveform of ISL8105. The STARTS Power-ON-Reset (POR) function continually monitors the SWITCHING bias voltage at the VBIAS pin. Once the rising POR threshold is exceeded 4V (VPOR nominal), the POR function initiates the Overcurrent Protection (OCP) sample and hold operation (while COMP/EN is ~1V). When the sampling is COMP/EN complete, VOUT begins the soft-start ramp. VOUT BGATE/BSOC VBIAS 3.4ms 3.4ms 0ms to 3.4ms t0t1 t2t3 t4 t5 VOUT ~4V POR FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION VCOMP/EN Soft-Start and Pre-Biased Outputs Functionally, the soft-start internally ramps the reference on the non-inverting terminal of the error amp from 0V to 0.6V in a nominal 6.8ms. The output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the VOUT will be less than the nominal time), FIGURE 1. POR AND SOFT-START OPERATION due to some initialization timing, between t3 and t4). If the COMP/EN pin is held low during power-up, the The ramp is created digitally, so there will be 64 small initialization will be delayed until the COMP/EN is released discrete steps. There is no simple way to change this ramp and its voltage rises above the VDISABLE trip point. rate externally, and it is the same for either frequency version of the IC (300kHz or 600kHz). Figure 2 shows a typical power-up sequence in more detail. The initialization starts at t0, when either VBIAS rises above After an initialization period (t3 to t4), the error amplifier VPOR, or the COMP/EN pin is released (after POR). The (COMP/EN pin) is enabled, and begins to regulate the COMP/EN will be pulled up by an internal 20µA current converter's output voltage during soft-start. The oscillator's source, but the timing will not begin until the COMP/EN triangular waveform is compared to the ramping error exceeds the VDISABLE trip point (at t1). The external amplifier voltage. This generates LX pulses of increasing capacitance of the disabling device, as well as the width that charge the output capacitors. When the internally compensation capacitors, will determine how quickly the generated soft-start voltage exceeds the reference voltage 20µA current source will charge the COMP/EN pin. With (0.6V), the soft-start is complete and the output should be in typical values, it should add a small delay compared to the regulation at the expected voltage. This method provides a soft-start times. The COMP/EN will continue to ramp to ~1V. rapid and controlled output voltage rise; there is no large inrush current charging the output capacitors. The entire From t1, there is a nominal 6.8ms delay, which allows the start-up sequence from POR typically takes up to 17ms; up VBIAS pin to exceed 6.5V (if rising up towards 12V), so that the internal bias regulator can turn on cleanly. At the same FN6306 Rev 5.00 Page 6 of 16 April 15, 2010

ISL8105, ISL8105A Overcurrent Protection (OCP) The overcurrent function protects the converter from a shorted output by using the bottom-side MOSFET's VOUT OVER-CHARGED on-resistance, rDS(ON), to monitor the current. A resistor (RBSOC) programs the overcurrent trip level (see “Typical Application Diagram” on page2). This method enhances the VVOOUUTT P PRREE--BBIAIASSEEDD converter's efficiency and reduces cost by eliminating a current sensing resistor. If overcurrent is detected, the output VVOOUUT TN NOORRMMAALL immediately shuts off, it cycles the soft-start function in a hiccup mode (2dummy soft-start time-outs, then up to one real one) to provide fault protection. If the shorted condition t0 t1t1 tt22 is not removed, this cycle will continue indefinitely. Following POR (and 6.8ms delay), the ISL8105, ISL8105A initiates the Overcurrent Protection sample and hold FIGURE 3. SOFT-START WITH PRE-BIAS operation. The BGATE driver is disabled to allow an internal 21.5µA current source to develop a voltage across RBSOC. to 10.2ms for the delay and OCP sample and 6.8ms for the The ISL8105, ISL8105A samples this voltage (which is soft-start ramp. referenced to the GND pin) at the BGATE/BSOC pin, and Figure 3 shows the normal curve in blue; initialization begins holds it in a counter and DAC combination. This sampled at t0, and the output ramps between t1 and t2. If the output is voltage is held internally as the Overcurrent Set Point, for as pre-biased to a voltage less than the expected value, as long as power is applied, or until a new sample is taken after shown by the red curve, the ISL8105, ISL8105A will detect coming out of a shut-down. that condition. Neither MOSFET will turn on until the The actual monitoring of the bottom-side MOSFET's soft-start ramp voltage exceeds the output; VOUT starts on-resistance starts 200ns (nominal) after the edge of the seamlessly ramping from there. If the output is pre-biased to internal PWM logic signal (that creates the rising external a voltage above the expected value, as in the gray curve, BGATE signal). This is done to allow the gate transition neither MOSFET will turn on until the end of the soft-start, at noise and ringing on the LX pin to settle out before which time it will pull the output voltage down to the final monitoring. The monitoring ends when the internal PWM value. Any resistive load connected to the output will help edge (and thus BGATE) goes low. The OCP can be detected pull down the voltage (at the RC rate of the R of the load and anywhere within the above window. the C of the output capacitance). If the regulator is running at high TGATE duty cycles (around If the VIN for the synchronous buck converter is from a 75% for 600kHz or 87% for 300kHz operation), then the different supply that comes up after VBIAS, the soft-start BGATE pulse width may not be wide enough for the OCP to would go through its cycle, but with no output voltage ramp. properly sample the rDS(ON). For those cases, if the BGATE When VIN turns on, the output would follow the ramp of the is too narrow (or not there at all) for 3 consecutive pulses, VIN from zero up to the final expected voltage (at close to then the third pulse will be stretched and/or inserted to the 100% duty cycle, with COMP/EN pin >4V). If VIN is too fast, 425ns minimum width. This allows for OCP monitoring every there may be excessive inrush current charging the output third pulse under this condition. This can introduce a small capacitors (only the beginning of the ramp, from zero to pulse-width error on the output voltage, which will be VOUT matters here). If this is not acceptable, then consider corrected on the next pulse; and the output ripple voltage will changing the sequencing of the power supplies, or sharing have an unusual 3-clock pattern, which may look like jitter. If the same supply, or adding sequencing logic to the the OCP is disabled (by choosing a too-high value of COMP/EN pin to delay the soft-start until the VIN supply is RBSOC, or no resistor at all), then the pulse stretching ready (see “Input Voltage Considerations” on page9). feature is also disabled. Figure 4 illustrates the BGATE pulse If the IC is disabled after soft-start (by pulling COMP/EN pin width stretching, as the width gets smaller. low), and then enabled (by releasing the COMP/EN pin), then the full initialization (including OCP sample) will take place. However, there is no new OCP sampling during overcurrent retries. If the output is shorted to GND during soft-start, the OCP will handle it, as described in the next section. If the output is shorted to GND during soft-start, the OCP will handle it, as described in the next section. FN6306 Rev 5.00 Page 7 of 16 April 15, 2010

ISL8105, ISL8105A MOSFETs is typically in the 20mV to 120mV ballpark (500to 3000). If the voltage drop across RBSOC is set too low, that can cause almost continuous OCP tripping and BGATE > 425ns retry. It would also be very sensitive to system noise and inrush current spikes, so it should be avoided. The maximum usable setting is around 0.2V across RBSOC (0.4V across the MOSFET); values above that might disable the protection. Any voltage drop across RBSOC that is greater than 0.3V (0.6V MOSFET trip point) will disable the OCP. The preferred method to disable OCP is simply to remove the resistor, which will be detected as no OCP. BGATE = 425ns Note that conditions during power-up or during a retry may look different than normal operation. During power-up in a 12V system, the IC starts operation just above 4V; if the supply ramp is slow, the soft-start ramp might be over well before 12V is reached. So with bottom-side gate drive voltages, the rDS(ON) of the MOSFETs will be higher during BGATE < 425ns power-up, effectively lowering the OCP trip. In addition, the ripple current will likely be different at lower input voltage. Another factor is the digital nature of the soft-start ramp. On each discrete voltage step, there is in effect a small load transient, and a current spike to charge the output capacitors. The height of the current spike is not controlled; it BGATE << 425ns is affected by the step size of the output, the value of the output capacitors, as well as the IC error amp compensation. So it is possible to trip the overcurrent with inrush current, in addition to the normal load and ripple considerations. Figure 5 shows the output response during a retry of an FIGURE 4. BGATE PULSE STRETCHING output shorted to GND. At time t0, the output has been turned off, due to sensing an overcurrent condition. There The overcurrent function will trip at a peak inductor current are two internal soft-start delay cycles (t1 and t2) to allow the (IPEAK) determined by Equation 1: MOSFETs to cool down, to keep the average power 2IBSOCRBSOC (EQ. 1) dissipation in retry at an acceptable level. At time t2, the IPEAK = ----------------r-------------------------------------- output starts a normal soft-start cycle, and the output tries to DSON ramp. If the short is still applied, and the current reaches the BSOC trip point any time during soft-start ramp period, the where IBSOC is the internal BSOC current source (21.5µA typical). The scale factor of 2 doubles the trip point of the output will shut off and return to time t0 for another delay cycle. Thus, the retry period is two dummy soft-start cycles MOSFET voltage drop, compared to the setting on the plus one variable one (which depends on how long it takes to RBSOC resistor. The OC trip point varies in a system mainly trip the sensor each time). Figure 5 also shows an example due to the MOSFET's rDS(ON) variations (over process, where the output gets about half-way up before shutting current and temperature). To avoid overcurrent tripping in down; therefore, the retry (or hiccup) time will be around the normal operating load range, find the RBSOC resistor 17ms. The minimum should be nominally 13.6ms and the from Equation 1 with: maximum 20.4ms. If the short condition is finally removed, 1. The maximum rDS(ON) at the highest junction the output should ramp up normally on the next t2 cycle. temperature Starting up into a shorted load looks the same as a retry into 2. The minimum IBSOC from the specification table that same shorted load. In both cases, OCP is always I 3. Determine IPEAK for IPEAK > IOUT(MAX) + ----2------, where enabled during soft-start; once it trips, it will go into retry I is the output inductor ripple current. (hiccup) mode. The retry cycle will always have two dummy For an equation for the ripple current, see “Output Inductor time-outs, plus whatever fraction of the real soft-start time Selection” on page13. passes before the detection and shutoff; at that point, the logic immediately starts a new two dummy cycle time-out. The range of allowable voltages detected (2*IBSOC*RBSOC) is 0mV to 475mV; but the practical range for typical FN6306 Rev 5.00 Page 8 of 16 April 15, 2010

ISL8105, ISL8105A There is an internal 5V regulator for bias; it turns on between INTERNAL SOFT-START RAMP 5.5 and 6.5V. Some of the delay after POR is there to allow a typical power supply to ramp-up past 6.5V before the soft-start ramps begins. This prevents a disturbance on the output, due to the internal regulator turning on or off. If the transition is slow (not a step change), the disturbance should be minimal. So while the recommendation is to not have the VOUT output enabled during the transition through this region, it may be acceptable. The user should monitor the output for their application to see if there is any problem. 6.8ms 66..88mmss The VIN to the top-side MOSFET can share the same supply 0ms TO 6.8ms as VBIAS but can also run off a separate supply or other t0 tt11 tt22 sources, such as outputs of other regulators. If VBIAS powers up first, and the VIN is not present by the time the initialization is done, then the soft-start will not be able to FIGURE 5. OVERCURRENT RETRY OPERATION ramp the output, and the output will later follow part of the Output Voltage Selection VIN ramp when it is applied. If this is not desired, then change the sequencing of the supplies, or use the The output voltage can be programmed to any level between the 0.6V internal reference, up to the VBIAS supply. The COMP/EN pin to disable VOUT until both supplies are ready. ISL8105, ISL8105A can run at near 100% duty cycle at zero Figure 6 shows a simple sequencer for this situation. If load, but the rDS(ON) of the top-side MOSFET will effectively VBIAS powers up first, Q1 will be off, and R3 pulling to VBIAS limit it to something less as the load current increases. In will turn Q2 on, keeping the ISL8105, ISL8105A in shutdown. addition, the OCP (if enabled) will also limit the maximum When VIN turns on, the resistor divider R1 and R2 effective duty cycle. determines when Q1 turns on, which will turn off Q2 and An external resistor divider is used to scale the output release the shut-down. If VIN powers up first, Q1 will be on, voltage relative to the internal reference voltage, and feed it turning Q2 off; so the ISL8105, ISL8105A will start-up as back to the inverting input of the error amp. See “Typical soon as VBIAS comes up. The VDISABLE trip point is 0.4V nominal, so a wide variety of NFET's or NPN's or even some Application Diagram” on page2 for more detail; R1 is the upper resistor; ROFFSET (shortened to R0 below) is the logic IC's can be used as Q1 or Q2; but Q2 must be low leakage when off (open-drain or open-collector) so as not to lower one. The recommended value for R1 is 1k to 5k (±1% for accuracy) and then ROFFSET is chosen according interfere with the COMP output. Q2 should also be placed near the COMP/EN pin. to Equations 2 and 3. Since R1 is part of the compensation circuit (see “Feedback Compensation” on page11), it is The VIN range can be as low as ~1V (for VOUT as low as the often easier to change ROFFSET to change the output 0.6V reference). It can be as high as 20V (for VOUT just voltage; that way the compensation calculations do not need below VIN). There are some restrictions for running high VIN to be repeated. If VOUT = 0.6V, then ROFFSET can be left voltage. open. Output voltages less than 0.6V are not available. The first consideration for high VIN is the maximum BOOT V = 0.6V---R----1-----+-----R----0----- (EQ. 2) voltage of 36V. The VIN (as seen on LX)+VBIAS (boot OUT R voltage-the diode drop) + any ringing (or other transients) 0 on the BOOT pin must be less than 36V. If VIN is 20V, that R = -----R-----1--------0----.-6----V------- (EQ. 3) limits VBIAS + ringing to 16V. 0 V –0.6V OUT The second consideration for high VIN is the maximum Input Voltage Considerations (BOOT - VBIAS) voltage; this must be less than 24V. Since BOOT = VIN + VBIAS + ringing, that reduces to (VIN + ringing) The “Typical Application Diagram” on page2 shows a standard configuration where VBIAS is either 5V (±10%) or VIN VBIAS 12V (±20%); in each case, the gate drivers use the VBIAS voltage for BGATE and BOOT/TGATE. In addition, VBIAS is R3 allowed to work anywhere from 6.5V up to the 14.4V R1 TO COMP/EN maximum. The VBIAS range between 5.5V and 6.5V is NtraOnTs iatiollnosw tehdro fuogr hlo itn tgo- tveorltmag reesli aabboilvitey 6re.5aVs oanres ,a bcucet ptable. R2 Q1 Q2 FIGURE 6. SEQUENCER CIRCUIT FN6306 Rev 5.00 Page 9 of 16 April 15, 2010

ISL8105, ISL8105A must be <24V. So based on typical circuits, a 20V maximum Application Guidelines VIN is a good starting assumption; the user should verify the Layout Considerations ringing in their particular application. As in any high-frequency switching converter, layout is very Another consideration for high VIN is duty cycle. Very low important. Switching current from one power device to duty cycles (such as 20V in to 1.0V out, for 5% duty cycle) another can generate voltage transients across the require component selection compatible with that choice impedances of the interconnecting bond wires and circuit (such as low rDS(ON) bottom-side MOSFET, and a good LC traces. These interconnecting impedances should be output filter). At the other extreme (for example, 20V in to minimized by using wide, short printed circuit traces. The 12V out), the top-side MOSFET needs to be low rDS(ON). In critical components should be located as close together as addition, if the duty cycle gets too high, it can affect the possible using ground plane construction or single point overcurrent sample time. In all cases, the input and output grounding. capacitors and both MOSFETs must be rated for the voltages present. VIN Switching Frequency The switching frequency is either a fixed 300kHz or 600kHz, ISL8105 depending on the part number chosen (ISL8105 is 300kHz; ISL8105A is 600kHz; the generic name “ISL8105” may apply TGATE Q1 LO to either in the rest of this document, except when choosing LX VOUT the frequency). However, all of the other timing mentioned (POR delay, OCP sample, soft-start, etc.) is independent of CIN D the clock frequency (unless otherwise noted). BGATE Q2 CO OA L PGND BOOT Refresh In the event that the TGATE is on for an extended period of time, the charge on the boot capacitor can start to sag, RETURN raising the rDS(ON) of the top-side MOSFET. The ISL8105 has a circuit that detects a long TGATE on-time (nominal FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS 100µs), and forces the BGATE to go higher for one clock cycle, which will allow the boot capacitor some time to recharge. Separately, the OCP circuit has a BGATE pulse Figure 7 shows the critical power components of the stretcher (to be sure the sample time is long enough), which converter. To minimize the voltage overshoot/undershoot, can also help refresh the boot. But if OCP is disabled (no the interconnecting wires indicated by heavy lines should be current sense resistor), the regular boot refresh circuit will part of ground or power plane in a printed circuit board. The still be active. components shown in Figure 8 should be located as close Current Sinking together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. The ISL8105 incorporates a MOSFET shoot-through Locate the ISL8105 within three inches of the MOSFETs, Q1 protection method which allows a converter to sink current and Q2. The circuit traces for the MOSFETs’ gate and as well as source current. Care should be exercised when source connections from the ISL8105 must be sized to designing a converter with the ISL8105 when it is known that handle up to 1A peak current. the converter may sink current. Proper grounding of the IC is important for correct operation When the converter is sinking current, it is behaving as a in noisy environments. The GND pin should be connected to boost converter that is regulating its input voltage. This a large copper fill under the IC which is subsequently means that the converter is boosting current into the VIN rail. connected to board ground at a quiet location on the board, If there is nowhere for this current to go, such as to other typically found at an input or output bulk (electrolytic) distributed loads on the VIN rail, through a voltage limiting capacitor. protection device, or other methods, the capacitance on the VIN bus will absorb the current. This situation will allow Figure 8 shows the circuit traces that require additional voltage level of the VIN rail (also LX) to increase. If the layout consideration. Use single point and ground plane voltage level of the LX is increased to a level that exceeds construction for the circuits shown. Locate the resistor, the maximum voltage rating of the ISL8105, then the IC will RBSOC, close to the BGATE/BSOC pin as the internal BSOC experience an irreversible failure and the converter will no current source is only 21.5µA. longer be operational. Ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. FN6306 Rev 5.00 Page 10 of 16 April 15, 2010

ISL8105, ISL8105A BOOT +VIN C2 CBOOT Q1 LO VOUT LX R3 C3 ISL8105 D COMP R2 C1 +VBIAS Q2 CO OA L - C BGATE/BSOC VBIAS CVBIAS E/A + FB R1 O BS GND GND R VREF FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES OSCILLATOR VOUT Minimize the loop from any pulldown transistor connected to VIN COMP/EN pin to reduce antenna effect. Provide local PWM VOSC decoupling between VBIAS and GND pins as described CIRCUIT earlier. Locate the capacitor, CBOOT, as close as practical to L TGATE DCR the BOOT and LX pins. All components used for feedback HALF-BRIDGE compensation (not shown) should be located as close to the DRIVE IC as practical. LX C Feedback Compensation ESR BGATE This section highlights the design considerations for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback ISL8105 EXTERNAL CIRCUIT network is recommended (see Figure 9). FIGURE 9. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN Figure 9 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the Equations 5 through 8 that relate the compensation network’s ISL8105 circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output poles, zeros and gain to the components (R1, R2, R3, C1, C2, (COMP pin voltage) is compared with the oscillator (OSC) and C3) in Figure 9. Use the following guidelines for locating the poles and zeros of the compensation network: triangle wave to provide a pulse-width modulated wave with an amplitude of VIN at the LX node. The PWM wave is 1. Select a value for R1 (1k to 10k, typically). Calculate smoothed by the output filter (Land C). The output filter value for R2 for desired converter bandwidth (F0). If capacitor bank’s equivalent series resistance is represented setting the output voltage to be equal to the reference set by the series resistor ESR. voltage as shown in Figure 9, the design procedure can be followed as presented in Equation 5. The modulator transfer function is the small-signal transfer V R F function of VOUT/VCOMP. This function is dominated by a DC R2 = d--------O----S----C-----V--------1------F-----0----- (EQ. 5) gain, given by dMAXVIN/VOSC, and shaped by the output filter, MAX IN LC with a double pole break frequency at FLC and a zero at FCE. 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, For the purpose of this analysis, C and ESR represent the total at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to output capacitance and its equivalent series resistance. desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 1 1 FLC = 2----------------L--------C--- FCE = 2------------C---------E----S-----R--- (EQ. 4) frequency (to maximize phase boost at FLC). 1 C = ----------------------------------------------- The compensation network consists of the error amplifier 1 2R20.5FLC (EQ. 6) (internal to the ISL8105) and the external R1 to R3, C1 to C3 3. Calculate C2 such that FP1 is placed at FCE. components. The goal of the compensation network is to C provide a closed loop transfer function with high 0dB crossing C = ------------------------------1-------------------------- frequency (F0; typically 0.1 to 0.3 of fSW) and adequate phase 2 2R2C1FCE–1 (EQ. 7) margin (better than +45°). 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below fSW (typically, 0.5 to 1.0 Phase margin is the difference between the closed loop times fSW). fSW represents the regulator’s switching phase at F0dB and +180°. frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in FN6306 Rev 5.00 Page 11 of 16 April 15, 2010

ISL8105, ISL8105A frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple FZ1FZ2 FP1 MODULATOR GAIN component at the COMP pin and minimizing resultant duty N COMPENSATION GAIN AI CLOSED LOOP GAIN cycle jitter. G OPEN LOOP E/A GAIN R FP2 1 R = -------------------- 3 f SW -----------–1 F (EQ. 8) LC C3 = 2------------R-----3-----1--0---.--7--------f--S----W---- 20logRR-----21--- 20logd-----M-----A-----X---------V----I--N--- 0 VOSC GFB It is recommended that a mathematical model is used to plot the loop response. Check the loop gain against the error GCL amplifier’s open-loop gain. Verify phase margin results and OG GMOD adjust as necessary. The equations in Equation 9, describe the L LOG frequency response of the modulator (GMOD), feedback fLC fCE f0 FREQUENCY compensation (GFB) and closed-loop response (GCL): FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN G f = d----M-----A----X--------V----I--N----------------------------------1-----+-----s------f--------E-----S----R---------C---------------------------------- frequencies approaching or exceeding half the switching MOD V 2 frequency. When designing compensation networks, select OSC 1+sfESR+DCRC+s fLC target crossover frequencies in the range of 10% to 30% of the G f = -----1-----+-----s------f--------R-----2-------C-----1------ switching frequency, fSW. FB sfR C +C  1 1 2 Component Selection Guidelines 1+sfR +R C -------------------------------------------------------------1--------------3---------------3-------------------------------  C1C2 Output Capacitor Selection 1+sfR C 1+sfR --------------------- 3 3  2 C1+C2 An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a GCLf = GMODfGFBf wheresf = 2fj function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (EQ. 9) (di/dt) and the magnitude of the transient load current. These COMPENSATION BREAK FREQUENCY EQUATIONS requirements are generally met with a mix of capacitors and careful layout. FZ1 = 2------------R--1---2-------C-----1-- FP1 = 2------------R---------1-----C----------1--------------C----------2------ Modern microprocessors produce transient load rates above 2 C1+C2 1A/ns. High frequency capacitors initially supply the transient F = ------------------------1------------------------- F = --------------1----------------- and slow the current load rate seen by the bulk capacitors. The Z2 2R +R C P2 2R C 1 3 3 3 3 bulk filter capacitor values are generally determined by the (EQ. 10) ESR (effective series resistance) and voltage rating Figure 10 shows an asymptotic plot of the DC/DC converter’s requirements rather than actual capacitance requirements. gain vs frequency. The actual modulator gain has a high gain High frequency decoupling capacitors should be placed as peak dependent on the quality factor (Q) of the output filter, which close to the power pins of the load as physically possible. Be is not shown. Using the above guidelines should yield a careful not to add inductance in the circuit board wiring that compensation gain similar to the curve plotted. The open loop could cancel the usefulness of these low inductance error amplifier gain bounds the compensation gain. Check the components. Consult with the manufacturer of the load on compensation gain at FP2 against the capabilities of the error specific decoupling requirements. For example, Intel amplifier. The closed loop gain, GCL, is constructed on the log- recommends that the high frequency decoupling for the log graph of Figure 10 by adding the modulator gain, GMOD (in Pentium Pro be composed of at least forty (40) 1.0mF ceramic dB), to the feedback compensation gain, GFB (in dB). This is capacitors in the 1206 surface-mount package. Follow on equivalent to multiplying the modulator transfer function and specifications have only increased the number and quality of the compensation transfer function and then plotting the required ceramic decoupling capacitors. resulting gain. Use only specialized low-ESR capacitors intended for switching- A stable control loop has a gain crossing with close to a regulator applications for the bulk capacitors. The bulk -20dB/decade slope and a phase margin greater than +45°. capacitor’s ESR will determine the output ripple voltage and the Include worst case component variations when determining initial voltage drop after a high slew-rate transient. An aluminum phase margin. The mathematical model presented makes a electrolytic capacitor's ESR value is related to the case size with number of approximations and is generally not accurate at lower ESR available in larger case sizes. However, the FN6306 Rev 5.00 Page 12 of 16 April 15, 2010

ISL8105, ISL8105A equivalent series inductance (ESL) of these capacitors 0.60 increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL 0.50 is not a specified parameter. Work with your capacitor supplier 0.5Io and measure the capacitor’s impedance with frequency to select 0.40 a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large CM 0.30 case capacitor. KI 0.25Io Output Inductor Selection 0.20 I = 0Io The output inductor is selected to meet the output voltage 0.10 ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the 0.00 converter’s ripple current and the ripple voltage is a function of 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 the ripple current. The ripple voltage and current are DUTY CYCLE (D) approximated by Equation 11: FIGURE 11. INPUT-CAPACITOR CURRENT MULTIPLIER FOR SINGLE-PHASE BUCK CONVERTER V - V V I = -----I--N-F-------- -x--- -O-L---U-----T------V-O----U----T--- VOUT= I x ESR (EQ. 11) current needed each time Q1 turns on. Place the small ceramic S IN capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the The important parameters for the bulk input capacitor are the converter’s response time to a load transient. voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current One of the parameters limiting the converter’s response to a load ratings above the maximum input voltage and largest RMS transient is the time required to change the inductor current. current required by the circuit. The capacitor voltage rating Given a sufficiently fast control loop design, the ISL8105 will should be at least 1.25x greater than the maximum input provide either 0% or 100% duty cycle in response to a load voltage and a voltage rating of 1.5x is a conservative guideline. transient. The response time is the time required to slew the The RMS current rating requirement for the input capacitor of a inductor current from an initial current value to the transient buck regulator is approximately as shown in Equation 13.. current level. During this interval the difference between the inductor current and the transient current level must be supplied I = I2D–D2+----I--2--D D = --V----O---- by the output capacitor. Minimizing the response time can INRMS O 12 VIN minimize the output capacitance required. OR (EQ. 13) The response time to a transient is different for the application I = K I INRMS ICM O of load and the removal of load. Equation 12 gives the approximate response time interval for application and removal For a through-hole design, several electrolytic capacitors of a transient load: (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX L I L I or equivalent) may be needed. For surface mount designs, t = ----O-------------T---R-----A---N---- t = ----O------------T----R----A----N--- (EQ. 12) RISE V –V FALL V solid tantalum capacitors can be used, but caution must be IN OUT OUT exercised with regard to the capacitor surge current rating. where: These capacitors must be capable of handling the surge- ITRAN is the transient load current step current at power-up. The TPS series, available from AVX, and tRISE is the response time to the application of load the 593D, available series from Sprague, are both surge tFALL is the response time to the removal of load current tested. With a lower input source such as 1.8V or 3.3V, the worst case MOSFET Selection/Considerations response time can be either at the application or removal of The ISL8105 requires 2 N-Channel power MOSFETs. These load and dependent upon the output voltage setting. Be sure to should be selected based upon rDS(ON), gate supply check both of these equations at the minimum and maximum requirements, and thermal management requirements. output levels for the worst case response time. In high-current applications, the MOSFET power dissipation, Input Capacitor Selection package selection and heatsink are the dominant design Use a mix of input bypass capacitors to control the voltage factors. The power dissipation includes two loss components: overshoot across the MOSFETs. Use small ceramic capacitors conduction loss and switching loss. The conduction losses are for high frequency decoupling and bulk capacitors to supply the the largest component of power dissipation for both the top and FN6306 Rev 5.00 Page 13 of 16 April 15, 2010

ISL8105, ISL8105A the bottom-side MOSFETs. These losses are distributed Bootstrap Considerations between the two MOSFETs according to duty factor. The Figure 12 shows the top-side gate drive (BOOT pin) supplied switching losses seen when sourcing current will be different by a bootstrap circuit from VBIAS. The boot capacitor, CBOOT, from the switching losses seen when sinking current. When develops a floating supply voltage referenced to the LX pin. sourcing current, the top-side MOSFET realizes most of the The supply is refreshed to a voltage of VBIAS less the boot switching losses. The bottom-side switch realizes most of the diode drop (VD) each time the lower MOSFET, Q2, turns on. switching losses when the converter is sinking current (see Check that the voltage rating of the capacitor is above the Equation 14). These equations assume linear voltage current maximum VBIAS voltage in the system. A 16V rating should be transitions and do not adequately model power loss due to the sufficient for a 12V system. A value of 0.1µF is typical for many reverse recovery of the upper and lower MOSFET’s body systems driving single MOSFETs. diode. The gate-charge losses are dissipated by the ISL8105 and do not heat the MOSFETs. However, large gate charge +VBIAS +1V TO +12V increases the switching interval, tSW, which increases the MOSFET switching losses. Ensure that both MOSFETs are + within their maximum junction temperature at high ambient -VD BOOT temperature by calculating the temperature rise according to ISL8105 CBOOT Q1 package thermal-resistance specifications. A separate TGATE heatsink may be necessary depending upon MOSFET power, VG-S VBIAS - VD package type, ambient temperature and air flow. LX Losses while Sourcing Current +VBIAS 22 11 PP == IIoo rr DD++------IIooVV tt f TTOOPP DDSSOONN 22 IINN SSWW S Q2 BGATE PBOTTOM = Io2 x rDS(ON) x (1 - D) +- NOTE: VG-S  VBIAS Losses while Sinking Current PTOP = Io2 x rDS(ON) x D GND 2 1 PBOTTOM = Io rDSON1–D+2---IoVINtSWfS FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION (EQ. 14) If VBIAS is 12V, but VIN is lower (such as 5V), then another Where: option is to connect the BOOT pin to 12V and remove the D is the duty cycle=VOUT/VIN, BOOT capacitor (although, you may want to add a local tSW is the combined switch ON and OFF time, and capacitor from BOOT to GND). This will make the TGATE VGS fS is the switching frequency. voltage equal to (12V - 5V = 7V). That should be high enough to drive most MOSFETs, and low enough to improve the When operating with a 12V power supply for VBIAS (or down to efficiency slightly. Do NOT leave the BOOT pin open, and try to a minimum supply voltage of 6.5V), a wide variety of NMOSFETs can be used. Check the absolute maximum VGS get the same effect by driving BOOT through VBIAS and the internal diode; this path is not designed for the high current rating for both MOSFETs; it needs to be above the highest pulses that will result. VBIAS voltage allowed in the system; that usually means a 20V VGS rating (which typically correlates with a 30V VDS For low VBIAS voltage applications where efficiency is very maximum rating). Low threshold transistors (around 1V or important, an external BOOT diode (in parallel with the internal below) are not recommended for the reasons explained in the one) may be considered. The external diode drop has to be next paragraph. lower than the internal one. The resulting higher VG-S of the For 5V-only operation, given the reduced available gate bias top-side FET will lower its rDS(ON). The modest gain in efficiency should be balanced against the extra cost and area voltage (5V), logic-level transistors should be used for both N- of the external diode. MOSFETs. Look for rDS(ON) ratings at 4.5V. Caution should be exercised with devices exhibiting very low VGS(ON) For information on the Application circuit, including a complete characteristics. The shoot-through protection present aboard Bill-of-Materials and circuit board description, can be found in the ISL8105 may be circumvented by these MOSFETs if they Application Note AN1258. have large parasitic impedances and/or capacitances that http://www.intersil.com/data/an/AN1258.pdf would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Also avoid MOSFETs with excessive switching times; the circuitry is expecting transitions to occur in under 50ns or so. FN6306 Rev 5.00 Page 14 of 16 April 15, 2010

ISL8105, ISL8105A Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 2X 0.10 C A 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE A D 2X MILLIMETERS 0.10 C B SYMBOL MIN NOMINAL MAX NOTES A 0.85 0.90 0.95 - A1 - - 0.05 - E 6 A3 0.20 REF - INDEX b 0.20 0.25 0.30 5, 8 AREA D 3.00 BSC - TOP VIEW B D2 2.33 2.38 2.43 7, 8 E 3.00 BSC - // 0.10 C E2 1.59 1.64 1.69 7, 8 A 0.08 C e 0.50 BSC - C SIDE VIEW A3 k 0.20 - - - SEATING PLANE L 0.35 0.40 0.45 8 N 10 2 D2 7 8 (DATUM B) Nd 5 3 D2/2 Rev. 1 4/06 1 2 6 NOTES: INDEX AREA NX k 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. (DATUM A) E2 3. Nd refers to the number of terminals on D. E2/2 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured NX L between 0.15mm and 0.30mm from the terminal tip. N N-1 6. The configuration of the pin #1 identifier is optional, but must be NX b 8 e 5 located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. (Nd-1)Xe 0.10 M C AB REF. 7. Dimensions D2 and E2 are for the exposed pads which provide BOTTOM VIEW improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land CL Pattern Design efforts, see Intersil Technical Brief TB389. (A1) 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for NX (b) dimensions E2 & D2. 5 9 L e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE FN6306 Rev 5.00 Page 15 of 16 April 15, 2010

ISL8105, ISL8105A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - 1 2 3 L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0075 0.0098 0.19 0.25 - -A- D 0.1890 0.1968 4.80 5.00 3 D A h x 45° E 0.1497 0.1574 3.80 4.00 4 -C- e 0.050 BSC 1.27 BSC -  H 0.2284 0.2440 5.80 6.20 - e A1 C h 0.0099 0.0196 0.25 0.50 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 8 8 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2005-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6306 Rev 5.00 Page 16 of 16 April 15, 2010