DATASHEET ISL8013A FN7526 3A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator Rev 2.00 November 17, 2014 The ISL8013A is a high efficiency, monolithic, synchronous Features step-down DC/DC converter that can deliver up to 3A continuous output current from a 2.8V to 5.5V input supply. It • High efficiency synchronous buck regulator with up to 97% efficiency uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response • Power-good (PG) output with a 1ms delay and excellent loop stability. • 2.8V to 5.5V supply voltage The ISL8013A integrates a pair of low ON-resistance • 3% output accuracy over temperature, load, line P-Channel and N-Channel internal MOSFETs to maximize • 3A output current efficiency and minimize external component count. The 100% duty-cycle operation allows less than 300mV dropout voltage • Start-up with prebiased output at 3A output current. High 1MHz pulse-width modulation • Internal soft-start - 1ms (PWM) switching frequency allows for the use of small external • Soft-stop output discharge during disable components and the SYNC input enables multiple ICs to • 35µA quiescent supply current in PFM mode synchronize out-of-phase to reduce ripple and eliminate beat frequencies. • Selectable forced PWM mode and PFM mode The ISL8013A can be configured for discontinuous or forced • External synchronization up to 4MHz continuous operation at light load. Forced continuous • Less than 1µA logic controlled shutdown current operation reduces noise and RF interference while • 100% maximum duty cycle discontinuous mode provides high efficiency by reducing switching losses at light loads. • Internal current mode compensation • Peak current limiting and hiccup mode short-circuit Fault protection is provided by internal hiccup mode current protection limiting during short circuit and overcurrent conditions, an output overvoltage comparator and over-temperature monitor • Over-temperature protection circuit. A power-good output voltage monitor indicates when • Small 16 Ld 4mmx4mm QFN the output is in regulation. • Pb-Free (RoHS compliant) The ISL8013A is offered in a space saving 4mmx4mm, Pb-free Applications QFN package with exposed pad leadframes for low thermal resistance. • DC/DC POL modules The ISL8013A includes a pair of low ON-resistance P-Channel • µC/µP, FPGA and DSP power and N-Channel internal MOSFETs to maximize efficiency and • Plug-in DC/DC modules for routers and switchers minimize external component count. The 100% duty-cycle operation allows less than 300mV dropout voltage at 3A. • Portable instruments • Test and measurement systems The ISL8013A offers a 1ms Power-Good (PG) timer at power-up. When shut down, ISL8013A discharges the output • Li-ion battery powered devices capacitor. Other features include internal soft-start, internal • Small form factor (SFP) modules compensation, overcurrent protection, and thermal shutdown. • Barcode readers The ISL8013A is offered in a 4mmx4mm 16 Ld QFN package with 1mm maximum height. The complete converter occupies less than 0.4in2 area. FN7526 Rev 2.00 Page 1 of 16 November 17, 2014

ISL8013A Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes1, 2, 3) MARKING (°C) (Pb-Free) DWG. # ISL8013AIRZ 80 13AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4 ISL8013AEVAL2Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8013A. For more information on MSL please see techbrief TB363. Pin Configuration ISL8013A (16 LD QFN) TOP VIEW C X X X N L L L 16 15 14 13 VIN 1 12 PGND VIN 2 11 PGND PAD VDD 3 10 SGND SYNCH 4 9 SGND 5 6 7 8 N C G B E N P F V REFER TO APPLICATION NOTE AN1365 FOR MORE LAYOUT SUGGESTIONS. Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2 VIN Input supply voltage. Connect a 10µF ceramic capacitor to power ground. 3 VDD Input supply voltage for the analog circuitry. Connect to VIN pin. 5 EN Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do not leave this pin floating. 7 PG 1ms timer output. At power-up or EN HI, this output is a 1ms delayed power-good signal for the output voltage. 4 SYNCH Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the negative edge trigger. Do not leave this pin floating. 13, 14, 15 LX Switching node connection. Connect to one terminal of the inductor. 11, 12 PGND Power ground 9, 10 SGND Signal ground 8 VFB Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage. For 0.8V output voltage, connect this pin to the output. 6, 16 NC No connect - Exposed Pad The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to SGND plane for optimal thermal performance. FN7526 Rev 2.00 Page 2 of 16 November 17, 2014

ISL8013A Typical Application L OUTPUT INPUT 2.8V TO 5.5V 1.5µH 1.8V VIN LX C2 2 x 22µF C1 VDD R2 C3 2 x 22µF PGND 124k 47pF ISL8013A EN R1 VFB 100k PG 10R0k3 SYNCH SGND FIGURE 1. TYPICAL APPLICATION DIAGRAM Block Diagram SYNCH SOSFoTft- 27pF SHUTDOWN START SHUTDOWN 390k - EN BANDGAP 0.8V + EAMP + OSCILLATOR VIN COMP PWM/PFM - - LOGIC CONTROLLER LX 3pF PROTECTION DRIVER + PGND VFB SLSOloPpEe 6k COMP ++ CSA - + OCP 1.4V - + 0.736V - + SKIP- 0.5V PG 1ms DELAY ZERO-CROSS SGND SENSING - SCP 0.2V + FIGURE 2. FUNCTIONAL BLOCK DIAGRAM FN7526 Rev 2.00 Page 3 of 16 November 17, 2014

ISL8013A Absolute Maximum Ratings ( ) Thermal Information Reference to GND VIN, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms) Thermal Resistance (Typical, Notes4, 5) JA (°C/W) JC (°C/W) EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V 16 Ld 4x4 QFN Package . . . . . . . . . . . . . 39 3 LX . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms) Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C VFB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.8V to 5.5V Load Current Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are at TA= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note7) TYP (Note7) UNITS INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load - 2.6 2.8 V Falling, no load 2.15 2.35 - V Quiescent Supply Current IVIN SYNCH = GND, no load at the output - 35 - µA SYNCH = GND, no load at the output and no switches - 30 45 µA switching SYNCH = VDD, FS = 1MHz, no load at the output - 6.5 10 mA Shut Down Supply Current ISD VIN = 5.5V, EN = low - 0.1 2 µA OUTPUT REGULATION Reference Voltage VREF 0.790 0.8 0.810 V VFB Bias Current IVFB VFB = 0.75V - 0.1 - µA Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.8V) - 0.2 - %/V Soft-Start Ramp Time Cycle - 1 - ms OVERCURRENT PROTECTION Current Limit Blanking Time tOCON - 17 - Clock pulses Overcurrent and Auto Restart Period tOCOFF - 4 - SS cycle Switch Current Limit ILIMIT (Note6) 4.0 4.8 5.9 A Peak Skip Limit ISKIP (Note6) - 1.2 - A COMPENSATION Error Amplifier Transconductance - 20 - µA/V Trans-Resistance RT 0.213 0.25 0.287 Ω LX P-Channel MOSFET ON-resistance VIN = 5V, IO = 200mA - 50 75 mΩ VIN = 2.8V, IO = 200mA - 70 100 mΩ FN7526 Rev 2.00 Page 4 of 16 November 17, 2014

ISL8013A Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are at TA= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note7) TYP (Note7) UNITS N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA - 50 75 mΩ VIN = 2.8V, IO = 200mA - 70 100 mΩ LX Maximum Duty Cycle - 100 -  PWM Switching Frequency fS 0.80 1.00 1.20 MHz LX Minimum On-Time SYNCH = High - - 140 ns PG Output Low Voltage Sinking 1mA - - 0.3 V Delay Time (Rising Edge) 0.65 1 1.35 ms PG Pin Leakage Current PG = VIN = 3.6V - 0.01 0.1 µA PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 % PGOOD Falling Threshold Percentage of regulation voltage 85 88 91.5 % PGOOD Delay Time (Falling Edge) - 15 - µs EN, SYNCH Logic Input Low - - 0.4 V Logic Input High 1.4 - - V Synch Logic Input Leakage Current ISYNCH Pulled up to 5.5V - 0.1 1 µA Enable Logic Input Leakage Current IEN - 0.1 1 µA Thermal Shutdown - 140 - °C Thermal Shutdown Hysteresis - 25 - °C NOTES: 6. Limits established by characterization and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN7526 Rev 2.00 Page 5 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. 100 100 90 90 NCY (%) 7800 2.5VOUT-PWM1.8VOUT-PWM1.5VOUT-PWM NCY (%) 7800 2.5VOUT-PFM 1.8VOUT-PFM 1.5VOUT-PFM1.2VOUT-PFM CIE 1.2VOUT-PWM CIE EFFI 60 EFFI 60 50 50 40 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM) 100 1.0 90 0.9 %) 80 %) 0.8 2.5VOUT-PFM 3.3VOUT-PFM CY ( 2.5VOUT-PWM1.8VOUT-PWM 1.5VOUT-PWM CY ( 1.5VOUT-PFM EN 70 3.3VOUT-PWM 1.2VOUT-PWM EN 0.7 1.8VOUT-PFM 1.2VOUT-PFM CI CI FFI 60 FFI 0.6 E E 50 0.5 40 0.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM) FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM) 2.00 125 W) 1.75 mW) 100 DISSIPATION ( 0111....70255050 3.3VIN-PFM DISSIPATION ( 5705 R 5VIN-PWM R OWE 0.50 3.3VIN-PWM5VIN-PFM OWE 25 P 0.25 P 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) VIN (V) FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 8. POWER DISSIPATION WITH NO LOAD vs VIN (PWM VOUT = 1.8V) FN7526 Rev 2.00 Page 6 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued) 1.24 1.55 1.23 1.54 V) 1.22 3.3VIN-PFM V)1.53 3.3VIN-PFM E ( E ( G 1.21 G1.52 A A T T OL 1.20 OL1.51 V V OUTPUT 11..1189 5VIN-PFM 5VIN-PWM 3.3VIN-PWM OUTPUT 11..4590 5VIN-PFM 5VIN-PWM 3.3VIN-PWM 1.17 1.48 1.16 1.47 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) 1.83 2.52 1.82 2.51 V) 1.81 3.3VIN-PFM 5VIN-PWM V) 2.50 3.3VIN-PFM 3.3VIN-PWM E ( E ( AG 1.80 AG 2.49 T T OL 1.79 OL 2.48 V V PUT 1.78 3.3VIN-PWM PUT 2.47 5VIN-PWM UT 1.77 5VIN-PFM UT 2.46 O O 5VIN-PFM 1.76 2.45 1.75 2.44 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) 3.36 3.35 4.5VIN-PWM 5VIN-PWM V) 3.34 E ( G 3.33 A T L O 3.32 V UT 3.31 OUTP 3.30 5VIN-PFM 4.5VIN-PFM 3.29 3.28 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) FN7526 Rev 2.00 Page 7 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued) 1.830 1.830 1.820 1.820 V)1.810 3A LOAD PWM 0A LOAD PWM V) 1.810 3A LOAD E ( E ( 0A LOAD AG1.800 AG 1.800 T T L L O1.790 O 1.790 V V UT 1.780 UT 1.780 P P T T U1.770 U 1.770 O O 1.760 1.760 1.750 1.750 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN (PWM VOUT = 1.8) (PFM VOUT = 1.8V) LX 2V/DIV LX 2V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 0.5A/DIV FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM) FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM) LX 2V/DIV LX 2V/DIV IL 1A/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV VOUT RIPPLE 20mV/DIV FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD FIGURE 19. MODE TRANSITION CCM TO DCM FN7526 Rev 2.00 Page 8 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued) LX 2V/DIV VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV FIGURE 20. MODE TRANSITION DCM TO CCM FIGURE 21. LOAD TRANSIENT (PWM) LX 2V/DIV EN 5V/DIV VOUT 0.5V/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV FIGURE 22. LOAD TRANSIENT (PFM) FIGURE 23. SOFT-START WITH NO LOAD (PWM) EN 5V/DIV EN 5V/DIV VOUT 0.5V/DIV VOUT 0.5V/DIV IL 5A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 24. SOFT-START AT NO LOAD (PFM) FIGURE 25. SOFT-START WITH PREBIASED 1V FN7526 Rev 2.00 Page 9 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued) EN 5V/DIV EN 5V/DIV VOUT 0.5V/DIV VOUT 0.5V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 26. SOFT-START AT FULL LOAD FIGURE 27. SOFT-DISCHARGE SHUTDOWN LX 2V/DIV LX 2V/DIV IL 1A/DIV SYNCH 2V/DIV VOUT RIPPLE 20mV/DIV SYNCH 2V/DIV IL 1A/DIV VOUT RIPPLE 20mV/DIV FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH FIGURE 29. STEADY STATE OPERATION AT FULL LOAD WITH FREQUENCY = 2MHz FREQUENCY = 2MHz LX 2V/DIV LX 2V/DIV IL 1A/DIV SYNCH 2V/DIV SYNCH 2V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV FIGURE 30. STEADY STATE OPERATION AT NO LOAD WITH FIGURE 31. STEADY STATE OPERATION AT FULL LOAD (PWM) FREQUENCY = 4MHz WITH FREQUENCY = 4MHz FN7526 Rev 2.00 Page 10 of 16 November 17, 2014

ISL8013A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.5V to 5.5V, EN=VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued) LX 2V/DIV PHASE 2V/DIV VOUT 1V/DIV VOUT 0.5V/DIV IL 2A/DIV IL 2A/DIV PG 5V/DIV PG 5V/DIV FIGURE 32. OUTPUT SHORT-CIRCUIT FIGURE 33. OUTPUT SHORT-CIRCUIT RECOVERY 5.000 4.875 A)4.750 T ( OCP_3.3VIN EN4.625 R UR4.500 C T 4.375 U P OCP_5VIN UT4.250 O 4.125 4.000 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 34. OUTPUT CURRENT LIMIT vs TEMPERATURE Theory of Operation The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM The ISL8013A is a step-down switching regulator optimized for cycle and the current in the MOSFET starts to ramp up. When the battery-powered handheld applications. The regulator operates at sum of the current amplifier CSA and the slope compensation 1MHz fixed switching frequency under heavy load conditions to (237mV/µs) reaches the control reference of the current loop, the allow smaller external inductors and capacitors to be used for PWM comparator COMP sends a signal to the PWM logic to turn minimal printed-circuit board (PCB) area. At light load, the regulator off the P-MOSFET and turn on the N-Channel MOSFET. The reduces the switching frequency, unless forced to the fixed N-MOSFET stays on until the end of the PWM cycle. Figure35 frequency, to minimize the switching loss and to maximize the shows the typical operating waveforms during the PWM operation. battery life. The quiescent current, when the output is not loaded, is The dotted lines illustrate the sum of the slope compensation typically only 35µA. The supply current is typically only 0.1µA when ramp and the current-sense amplifier’s CSA output. the regulator is shut down. The output voltage is regulated by controlling the VEAMP voltage PWM Control Scheme to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage loop. The feedback signal comes from the Pulling the SYNCH pin HI (>2.5V) forces the converter into PWM VFB pin. The soft-start block only affects the operation during the mode, regardless of output current. The ISL8013A employs the start-up and will be discussed separately. The error amplifier is a current-mode pulse-width modulation (PWM) control scheme for transconductance amplifier that converts the voltage error signal fast transient response and pulse-by-pulse current limiting. Figure2 to a current output. The voltage loop is internally compensated shows the block diagram. The current loop consists of the oscillator, with the 27pF and 390kΩ RC network. The maximum EAMP the PWM comparator, current sensing circuit and the slope voltage output is precisely clamped to 1.6V. compensation for the current loop stability. The gain for the current sensing circuit is typically 250mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output. FN7526 Rev 2.00 Page 11 of 16 November 17, 2014

ISL8013A Synchronization Control VEAMP The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNCH pin. The falling edge on the VCSA SYNCH triggers the rising edge of the LX pulse. Make sure that the minimum on time of the LX node is greater than 140ns. DUTY CYCLE Overcurrent Protection The overcurrent protection is realized by monitoring the CSA IL output with the OCP comparator, as shown in Figure2. The current sensing circuit has a gain of 250mV/A, from the P-MOSFET current to the CSA output. When the CSA output reaches 1.4V, which is VOUT equivalent to 4.8A for the switch current, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent FIGURE 35. PWM OPERATION WAVEFORMS function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. SKIP Mode Upon detection of an overcurrent condition, the upper MOSFET Pulling the SYNCH pin LO (<0.4V) forces the converter into PFM will be immediately turned off and will not be turned on again mode. The ISL8013A enters a pulse-skipping mode at light load until the next switching cycle. Upon detection of the initial to minimize the switching loss by reducing the switching overcurrent condition, the overcurrent fault counter is set to 1. If, frequency. Figure36 illustrates the skip-mode operation. A on the subsequent cycle, another overcurrent condition is zero-cross sensing circuit shown in Figure2 monitors the detected, the OC fault counter will be incremented. If there are N-MOSFET current for zero crossing. When 8 consecutive cycles 17 sequential OC fault detections, the regulator will be shut down of the inductor current crossing zero are detected, the regulator under an overcurrent fault condition. An overcurrent fault enters the skip mode. During the eight detecting cycles, the condition will result in the regulator attempting to restart in a current in the inductor is allowed to become negative. The hiccup mode within the delay of four soft-start periods. At the counter is reset to zero when the current in any cycle does not end of the fourth soft-start wait period, the fault counters are cross zero. reset and soft-start is attempted again. If the overcurrent Once the skip mode is entered, the pulse modulation starts being condition goes away during the delay of four soft-start periods, controlled by the SKIP comparator shown in Figure2. Each pulse the output will resume back into regulation point after hiccup cycle is still synchronized by the PWM clock. The P-MOSFET is mode expires. turned on at the clock's rising edge and turned off when the Short-Circuit Protection output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. Then the The short-circuit protection SCP comparator monitors the VFB pin inductor current is discharging to 0A and stays at zero. The voltage for output short-circuit protection. When the VFB is lower internal clock is disabled. The output voltage reduces gradually than 0.2V, the SCP comparator forces the PWM oscillator due to the load current discharging the output capacitor. When frequency to drop to 1/3 of the normal operation value. This the output voltage drops to the nominal voltage, the P-MOSFET comparator is effective during start-up or an output short-circuit will be turned on again at the rising edge of the internal clock as event. it repeats the previous operations. . The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. PWM PFM CLOCK 8 CYCLES PFM CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL FIGURE 36. SKIP MODE OPERATION WAVEFORMS FN7526 Rev 2.00 Page 12 of 16 November 17, 2014

ISL8013A PG threshold) when VIN is equal to or greater than 2.5V. Set R5 between 10kΩ to 100kΩ, and use Equation1 to determine R4: During power-up, the open-drain power-good output holds low for about 1ms after VOUT reaches the regulation voltage. The PG R = -R----5----------V----I--N-----–-----1---.--4----V----- (EQ. 1) output also serves as a 1ms delayed the power-good signal when 4 1.4V the pull-up resistor R1 is installed. Where VIN is greater than or equal to 2.5V. UVLO Then select C such that the equivalent time constant is at least When the input voltage is below the undervoltage lockout (UVLO) 2x the rise time, T. This will delay the EN voltage enough so that threshold, the regulator is disabled. To adjust the voltage level of the overall EN voltage is less than 400mV by the time VIN power on and UVLO, use a resistive divider across EN. The input reaches 2.5V. Use Equation2 to get C: voltage programming resistor R4 will depend on the bottom 2T resistor R5, as referred to in Figure37. The value of R5 is typically CR-------------R------- (EQ. 2) between 10kΩ and 100kΩ. 4 5 VIN Where T is the rise time of VIN As an example, let VIN = 5V with rise time, T = 10ms. Then R4 R4=56.2kΩ, R5 = 71.5kΩ, and C = 0.68µF are used to insure EN + that VIN was >2.5V and the EN voltage was <400mV. 1V - R5 C Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100Ω FIGURE 37. EXTERNAL RESISTOR DIVIDER switch. Soft Start-up Power MOSFETs The soft start-up reduces the in-rush current during the start-up. The power MOSFETs are optimized for best efficiency. The The soft-start block outputs a ramp reference to the input of the ON-resistance for the P-MOSFET is typically 50mΩ and the error amplifier. This voltage ramp limits the inductor current as ON-resistance for the N-MOSFET is typically 50mΩ. well as the output voltage speed so that the output voltage rises 100% Duty Cycle in a controlled fashion. When VFB is less than 0.2V at the beginning of the soft-start, the switching frequency is reduced to The ISL8013A features 100% duty cycle operation to maximize 1/3 of the nominal value so that the output can start-up the battery life. When the battery voltage drops to a level that the smoothly at light load condition. During soft-start, the IC operates ISL8013A can no longer maintain the regulation at the output, in the SKIP mode to support prebiased output conditions. the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the Enable product of the load current and the ON-resistance of the The enable (EN) input allows the user to control the turning on or P-MOSFET. off the regulator for purposes such as power-up sequencing. Thermal Shutdown When the regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference and then the soft-start-up The ISL8013A has built-in thermal protection. When the internal begins. It is recommended that the EN voltage should be kept temperature reaches +140°C, the regulator is completely shut logic low (less than 400mV), until VIN reaches 2.5V. Refer to down. As the temperature drops to +115°C, the ISL8013A Figures37 and 38 for suggested circuit implementation with VIN resumes operation by stepping through the soft-start. slew rate. VIN S) T L O EN V 2.5V V ( <400mV T t (TIME) FIGURE 38. CIRCUIT IMPLEMENTATION WITH VIN SLEW RATE Let T equal the rise time of VIN. Select the ratio of R5 and R4 such that the voltage is 1.4V (minimum enable logic high FN7526 Rev 2.00 Page 13 of 16 November 17, 2014

ISL8013A Applications Information TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT Output Inductor and Capacitor Selection VOUT (V) COUT (µF) L (µH) 0.8 2 x 22 1.0~2.2 To consider steady state and transient operations, ISL8013A typically uses a 1.5µH output inductor. The higher or lower 1.2 2 x 22 1.0~2.2 inductor value can be used to optimize the total converter system 1.5 2 x 22 1.5~3.3 performance. For example, for higher output voltage 3.3V 1.8 2 x 22 1.5~3.3 application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. 2.5 2 x 22 1.5~3.3 It is recommended to set the ripple inductor current 3.3 2 x 22 2.2~4.7 approximately 30% of the maximum output current for optimized 3.6 2 x 22 2.2~4.7 performance. The inductor ripple current can be expressed as shown in Equation3: Output Voltage Selection  VO The output voltage of the regulator can be programmed via an VO1–V-----I--N-- (EQ. 3) external resistor divider that is used to scale the output voltage I = -------------L--------f---------------- relative to the internal reference voltage and feed it back to the S inverting input of the error amplifier (see Figure1). The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL8013A protects the typical The output voltage programming resistor, R3, will depend on the value chosen for the feedback resistor and the desired output peak current 4.8A. The saturation current needs be over 5.5A for voltage of the regulator. The value for the feedback resistor is maximum output current applications. typically between 10kΩ and 100kΩas shown in Equation4. ISL8013A uses an internal compensation network and the R 0.8V output capacitor value is dependent on the output voltage. The R = ----------2------------------------ (EQ. 4) 3 V –0.8V ceramic capacitor is recommended to be X5R or X7R. The OUT recommended X5R or X7R minimum output capacitor values are If the output voltage desired is 0.8V, then R3 is left unpopulated shown in Table1. In Table1, the minimum output capacitor value and R2 is shorted. There is a leakage current from VIN to LX. It is is given for the different output voltage to make sure that the recommended to preload the output with 10µA minimum. For whole converter system is stable. Additional output capacitance better performance, add 47pF in parallel with R2 (100kΩ should be added for better performances in applications where Input Capacitor Selection high load transient or low output ripple is required. It is recommended to check the system level performance along with The main functions for the input capacitor are to provide the simulation model. decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. Two 22µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. FN7526 Rev 2.00 Page 14 of 16 November 17, 2014

ISL8013A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE November 17, 2014 FN7526.2 Added more information to section “Enable” on page13. Added more information to section “UVLO” on page13. July 24, 2014 FN7526.1 Converted to new datasheet template. Updated Tape & Reel note in “Ordering Information” on page2 from "Add “-T” suffix for tape and reel." to new standard "Add “-T*” suffix for tape and reel." The "*" covers all possible tape and reel options. Added Evaluation board information to the Ordering Information on page2. Replaced Figure6 on page6, Figure7 on page6 and Figure11 on page7 with the new data curves. Removed Figure 9 (POWER DISSIPATION WITH NO LOAD vs VIN (PFM VOUT = 1.8V). November 25, 2009 FN7526.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2009-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7526 Rev 2.00 Page 15 of 16 November 17, 2014

ISL8013A Package Outline Drawing L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 6, 02/08 4X 1.95 4.00 A 12X 0.65 B 6 13 16 PIN #1 INDEX AREA 6 PIN 1 INDEX AREA 1 12 0 0 2 . 10 ± 0 . 15 4. 9 4 (4X) 0.15 8 5 TOP VIEW +0.15 0.10M C AB 16X 0 . 60 -0.10 4 0.28 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 1.00 MAX BASE PLANE ( 3 . 6 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 10 ) ( 12X 0 . 65 ) ( 16X 0 . 28 ) C 0 . 2 REF 5 ( 16 X 0 . 8 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7526 Rev 2.00 Page 16 of 16 November 17, 2014