DATASHEET ISL8002, ISL8002A, ISL80019, ISL80019A FN7888 Compact Synchronous Buck Regulators Rev 4.00 July 31, 2014 The ISL8002, ISL8002A, ISL80019 and ISL80019A are highly Features efficient, monolithic, synchronous step-down DC/DC converters that can deliver up to 2A of continuous output current from a 2.7V • VIN range 2.7V to 5.5V to 5.5V input supply. They use peak current mode control • VOUT range is 0.6V to VIN architecture to allow very low duty cycle operation. They operate at either 1MHz or 2MHz switching frequency, thereby providing • IOUT maximum is 1.5A or 2A (see Table1 on page3) superior transient response and allowing for the use of small • Switching frequency is 1MHz or 2MHz (see Table1 on page3) inductors. They also have excellent stability and provide both • Internal or external compensation option internal and external compensation options. • Selectable PFM or PWM operation option The ISL8002, ISL8002A, ISL80019 and ISL80019A integrate • Overcurrent and short circuit protection very low rDS(ON) MOSFETs in order to maximize efficiency. In addition, since the high-side MOSFET is a PMOS, the need for a • Over-temperature/thermal protection Boot capacitor is eliminated, thereby reducing external • VIN Undervoltage Lockout and VOUT Overvoltage Protection component count. They can operate at 100% duty cycle (at 1MHz) with a dropout of 200mV at 2A output current. • Up to 95% peak efficiency These devices can be configured for either PFM (discontinuous Applications conduction) or PWM (continuous conduction) operation at light • General purpose point of load DC/DC load. PFM provides high efficiency by reducing switching losses at light loads and PWM reduces noise susceptibility and RF • Set-top boxes and cable modems interference. • FPGA power These devices are offered in a space saving 8 pin 2mmx2mm • DVD, HDD drives, LCD panels, TV TDFN lead free package with exposed pad for improved thermal performance. The complete converter occupies less than Related Literature 0.10in2 area. • See AN1803, “1.5A/2A Low Quiescent Current High Efficiency Synchronous Buck Regulator” ISL8002 L1 100 VIN +2.7V …+5.5V 1 VIN PHASE 8 1.2μH +1.8V/2A VOUT C1 C5 C6 22μF 22μF 22μF 90 GND 2 EN PGND 7 GND %) 80 EN 3 MODE FB 6 +0.6V 200Rk1 1% NCY ( 70 1R020k 1% CIE 2.5VOUT PG 4 PG PAD COMP 5 FFI 60 1.8VOUT E 1.5VOUT 9 1.2VOUT 50 0.9VOUT 0.8VOUT R = R ---V----O-----–1 (EQ. 1) 400 .0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 2VFB  OUTPUT LOAD (A) FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION FIGURE 2. EFFICIENCY vs LOAD (INTERNAL COMPENSATION OPTION) FSW = 1MHz, VIN = 3.3V, MODE=PFM, TA = +25°C FN7888 Rev 4.00 Page 1 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM Control Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PFM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Negative Current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Enable, Disable, and Soft-Start Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 100% Duty Cycle (1MHz Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal ShutDown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Derating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loop Compensation Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FN7888 Rev 4.00 Page 2 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A TABLE 1. SUMMARY OF KEY DIFFERENCES IOUT (MAX) FSW VIN RANGE VOUT RANGE PACKAGE PART# (A) (MHz) (V) (V) SIZE ISL80019 1.5 1 ISL80019A 1.5 2 2.7 to 5.5 0.6 to 5.5 8 pin 2mmx2mm TDFN ISL8002 2 1 ISL8002A 2 2 NOTE: In this datasheet, the parts in the table above are collectively called "device". TABLE 2. COMPONENT VALUE SELECTION TABLE VOUT C1 C5, C6 C4 L1 R1 R2 (V) (µF) (µF) (pF) (µH) (kΩ) (kΩ) 0.8 22 22 22 1.0~2.2 33 100 1.2 22 22 22 1.0~2.2 100 100 1.5 22 22 22 1.0~2.2 150 100 1.8 22 22 22 1.0~3.3 200 100 2.5 22 22 22 1.5~3.3 316 100 3.3 22 22 22 1.5~4.7 450 100 FN7888 Rev 4.00 Page 3 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Pin Configuration ISL8002, ISL8002A, ISL80019, ISL80019A (8 LD 2x2 TDFN) TOP VIEW VIN 1 8 PHASE EN 2 THERMAL 7 PGND PAD (GPANDD) MODE 3 PIN 9 6 FB PG 4 5 COMP Pin Descriptions PIN # PIN NAME PIN DESCRIPTION 1 VIN The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for decoupling. 2 EN Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin. See Figure3, “FUNCTIONAL BLOCK DIAGRAM” on page5 for details. 3 MODE Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left floating, however, it is not recommended to leave this pin floating. 4 PG Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation limits. There is an internal 5MΩ internal pull-up resistor on this pin. 5 COMP COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is connected with a series resistor and capacitor to GND, compensation is external. See “Loop Compensation Design” on page20 for more detail. 6 FB Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage protection circuits use FB to monitor the output voltage. 7 PGND Power and analog ground connections. Connect directly to the board GROUND plane. 8 PHASE Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an 100Ω resistor when the device is disabled. See Figure3, “FUNCTIONAL BLOCK DIAGRAM” on page5 for details. 9 THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as-well-as a thermal (T-PAD) path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad. FN7888 Rev 4.00 Page 4 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Functional Block Diagram COMP MODE 27pF SOSoFfTt- * SHUTDOWN START 200kΩ + VIN EN VREF OSCILLATOR BANDGAP + EAMP + COMP - - PWM/PFM P SHUTDOWN LOGIC PHASE 3pF CONTROLLER PROTECTION N + HS DRIVER PGND FB 1.15*VREF SSLlOoPpEe 6kΩ COMP ++ - CSA - + OV + OCP - - 0.85*VREF + UV + VIN SKIP - 5MΩ PG 1ms DELAY NEG CURRENT SENSING ZERO-CROSS - SENSING SCP 0.3V + 100Ω SHUTDOWN *By default, when COMP is tied to VIN, the voltage loop is internally compensated with the 27pF and 200kΩ RC network. Please see "COMP" pin in the “Pin Descriptions” table on Page 4 for more details. FIGURE 3. FUNCTIONAL BLOCK DIAGRAM FN7888 Rev 4.00 Page 5 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Ordering Information PACKAGE PART NUMBER TAPE AND REEL PART TECHNICAL TEMP. RANGE Tape and Reel PKG. (Notes 1, 2, 3) QUANTITY MARKING SPECIFICATIONS (°C) (Pb-Free) DWG. # ISL8002IRZ-T 1000 002 2A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002IRZ-T7A 250 002 2A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002AIRZ-T 1000 02A 2A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002AIRZ-T7A 250 02A 2A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019IRZ-T 1000 019 1.5A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019IRZ-T7A 250 019 1.5A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019AIRZ-T 1000 19A 1.5A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019AIRZ-T7A 250 19A 1.5A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002FRZ-T 1000 02F 2A, 1MHz -40 to +125 8 Ld TDFN L8.2x2C ISL8002FRZ-T7A 250 02F 2A, 1MHz -40 to +125 8 Ld TDFN L8.2x2C ISL8002AFRZ-T 1000 2AF 2A, 2MHz -40 to +125 8 Ld TDFN L8.2x2C ISL8002AFRZ-T7A 250 2AF 2A, 2MHz -40 to +125 8 Ld TDFN L8.2x2C ISL80019FRZ-T 1000 19F 1.5A, 1MHz -40 to +125 8 Ld TDFN L8.2x2C ISL80019FRZ-T7A 250 19F 1.5A, 1MHz -40 to +125 8 Ld TDFN L8.2x2C ISL80019AFRZ-T 1000 9AF 1.5A, 2MHz -40 to +125 8 Ld TDFN L8.2x2C ISL80019AFRZ-T7A 250 9AF 1.5A, 2MHz -40 to +125 8 Ld TDFN L8.2x2C ISL8002EVAL1Z Evaluation Board ISL8002AEVAL1Z Evaluation Board ISL80019AEVAL1Z Evaluation Board ISL80019EVAL1Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8002, ISL8002A, ISL80019, ISL80019A. For more information on MSL please see techbrief TB363. FN7888 Rev 4.00 Page 6 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Absolute Maximum Ratings Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms) Thermal Resistance (Typical, Notes4, 5) JA (°C/W) JC (°C/W) PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms) 2x2 TDFN Package . . . . . . . . . . . . . . . . . . . 71 7 EN, COMP, PG, MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V Load Current Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA=+25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note6) TYP (Note6) UNITS INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load 2.5 2.7 V Falling, no load 2.2 2.4 V Quiescent Supply Current IVIN MODE = PFM (GND), FSW = 2MHz, no load at 35 60 µA the output MODE = PWM (VIN), FSW = 1MHz, no load at 7 15 mA the output MODE = PWM (VIN), FSW = 2MHz, no load at 10 22 mA the output Shut Down Supply Current ISD MODE = PFM (GND), VIN = 5.5V, EN = low 5 10 µA OUTPUT REGULATION Feedback Voltage VFB 0.595 0.600 0.605 V TJ = -40°C to +125°C 0.589 0.605 V VFB Bias Current IVFB VFB = 2.7V. TJ = -40°C to +125°C -120 50 350 nA Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) -0.2 -0.05 0.1 %/V TJ = -40°C to +125°C Load Regulation See Note7 < -0.2 %/A Soft-Start Ramp Time Cycle 1 ms PROTECTIONS Positive Peak Current Limit IPLIMIT 2A application 3 3.5 4 A 1.5A application 2.1 2.5 2.9 A Peak Skip Limit ISKIP VIN = 3.6, VOUT = 1.8V (See “Applications 450 mA Information” on page19 for more detail) Zero Cross Threshold -170 -70 30 mA Negative Current Limit INLIMIT -2.3 -1.5 -1 A Thermal Shutdown Temperature rising 150 °C FN7888 Rev 4.00 Page 7 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA=+25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note6) TYP (Note6) UNITS Thermal Shutdown Hysteresis Temperature falling 25 °C COMPENSATION Error Amplifier Trans-Conductance COMP tied VIN 40 µA/V COMP with RC 120 µA/V Trans-Resistance RT 0.24 0.3 0.40 Ω LX P-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA 117 mΩ N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA 86 mΩ LX Maximum Duty Cycle 100  LX Minimum On-Time MODE = PWM (High) 1MHz 60 80 ns OSCILLATOR Nominal Switching Frequency FSW ISL8002, ISL80019 850 1000 1150 kHz ISL8002A, ISL80019A 1700 2000 2300 kHz PG Output Low Voltage 1mA sinking current 0.3 V Delay Time (Rising Edge) 0.5 1 2 ms PGOOD Delay Time (Falling Edge) 15 µs PG Pin Leakage Current PG = VIN 0.01 0.1 µA OVP PG Rising Threshold 110 115 120 % OVP PG Hysteresis 5 % UVP PG Rising Threshold 80 85 90 % UVP PG Hysteresis 5 % EN AND MODE LOGIC Logic Input Low 0.4 V Logic Input High 1.4 V Logic Input Leakage Current IMODE Pulled up to 5.5V 5.5 8 µA NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Not tested in production. Characterized using evaluation board. Refer to Figures12 through 14 load regulation diagrams. +105°C TA represents near worst case operating point. FN7888 Rev 4.00 Page 8 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves 100 100 90 90 %) 80 %) 80 Y ( Y ( C C N 70 N 70 CIE 2.5VOUT CIE 2.5VOUT FFI 60 1.8VOUT FFI 60 1.8VOUT E 1.5VOUT E 1.5VOUT 1.2VOUT 1.2VOUT 50 50 0.9VOUT 0.9VOUT 0.8VOUT 0.8VOUT 40 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 4. EFFICIENCY vs LOAD FIGURE 5. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 3.3V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 3.3V, MODE=PWM, TA = +25°C 100 100 90 90 CIENCY (%) 7800 2.5VOUT ENCY (%) 7800 2.5VOUT EFFI 60 11..58VVOOUUTT EFFICI 60 11..58VVOOUUTT 50 1.2VOUT 50 1.2VOUT 0.9VOUT 0.9VOUT 0.8VOUT 0.8VOUT 40 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 6. EFFICIENCY vs LOAD FIGURE 7. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 3.3V, MODE=PFM, TA = +25°C FSW = 1MHz, VIN = 3.3V, MODE=PWM, TA = +25°C 100 100 90 90 %) 80 %) 80 Y ( Y ( C C N 70 N 70 E E CI 3.3VOUT CI 3.3VOUT FFI 60 2.5VOUT FFI 60 2.5VOUT E 1.8VOUT E 1.8VOUT 50 1.5VOUT 50 1.5VOUT 1.2VOUT 1.2VOUT 0.9VOUT 0.9VOUT 40 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 8. EFFICIENCY vs LOAD FIGURE 9. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FN7888 Rev 4.00 Page 9 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) 100 100 90 90 %) 80 %) 80 CIENCY ( 70 23..53VVOOUUTT CIENCY ( 70 23..53VVOOUUTT EFFI 60 11..58VVOOUUTT EFFI 60 11..85VVOOUUTT 50 1.2VOUT 50 1.2VOUT 0.9VOUT 0.9VOUT 0.8VOUT 0.8VOUT 40 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 10. EFFICIENCY vs LOAD FIGURE 11. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 1MHz, VIN = 5V, MODE=PWM, TA = +25°C 0.1 0.1 0.0 0.0 %) %) N ( -0.1 N ( -0.1 O O ATI -0.2 ATI -0.2 L L U U REG -0.3 AVERAGE REG -0.3 AVERAGE AD -0.4 HIGH AD -0.4 HIGH O O L LOW L LOW -0.5 -0.5 6 SIGMA 6 SIGMA -0.6 -0.6 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 LOAD CURRENT LOAD CURRENT FIGURE 12. LOAD REGULATION, TA = +105°C, 2.7VIN, 0.6VOUT, 1MHz FIGURE 13. LOAD REGULATION, TA = +105°C, 3.3VIN, 0.6VOUT, 1MHz 0.0 -0.1 %) N (-0.2 O TI A UL-0.3 G RE AVERAGE D -0.4 A HIGH O L LOW -0.5 6 SIGMA -0.6 0 0.5 1.0 1.5 2.0 LOAD CURRENT FIGURE 14. LOAD REGULATION, TA = +105°, 5.5VIN, 0.6VOUT, 1MHz FN7888 Rev 4.00 Page 10 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) 0.925 1.230 5VIN PFM 5VIN PFM 0.920 5VIN PWM 1.225 5VIN PWM E (V) 0.915 33..33VVIINN PPWFMM E (V) 1.220 33..33VVIINN PPWFMM G G A A T T OL 0.910 OL 1.215 V V T T U U P 0.905 P 1.210 T T U U O O 0.900 1.205 0.895 1.200 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 15. VOUT REGULATION vs LOAD, FIGURE 16. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 0.9V, TA = +25°C FSW = 2MHz, VOUT = 1.2V, TA = +25°C 1.520 1.810 5VIN PFM 5VIN PFM 1.515 5VIN PWM 1.805 5VIN PWM E (V) 1.510 33..33VVIINN PPWFMM )V( E 1.800 33..33VVIINN PPWFMM G G A A T T OL 1.505 LO1.795 V V T T U U P 1.500 P1.790 T T U U O O 1.495 1.785 1.490 1.780 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 17. VOUT REGULATION vs LOAD, FIGURE 18. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 1.5V, TA = +25°C FSW = 2MHz, VOUT = 1.8V, TA = +25°C 2.505 3.335 5VIN PFM 5VIN PFM MODE 2.500 5VIN PWM 3.330 5VIN PWM MODE E (V) 2.495 33..33VVIINN PPWFMM E (V) 3.325 G G A A T T OL2.490 OL 3.320 V V T T U U P2.485 P 3.315 T T U U O O 2.480 3.310 2.475 3.305 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 19. VOUT REGULATION vs LOAD, FIGURE 20. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 2.5V, TA = +25°C FSW = 2MHz, VOUT = 3.3V, TA = +25°C FN7888 Rev 4.00 Page 11 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 1V/DIV VEN 2V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 21. START-UP AT NO LOAD FIGURE 22. START-UP AT NO LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV VEN 2V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 23. SHUTDOWN AT NO LOAD FIGURE 24. SHUTDOWN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV PG 5V/DIV VEN 2V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 25. START-UP AT 2A LOAD FIGURE 26. SHUTDOWN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FN7888 Rev 4.00 Page 12 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV PG 5V/DIV VEN 2V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 27. START-UP AT 2A LOAD FIGURE 28. SHUTDOWN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C VEN 5V/DIV VEN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV PG 5V/DIV IL 1A/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 29. START-UP AT 1.5A LOAD FIGURE 30. SHUTDOWN AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C VEN 5V/DIV VEN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV PLACEHOLDERPG 5V/DIV IL 1A/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 31. START-UP AT 1.5A LOAD FIGURE 32. SHUTDOWN AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FN7888 Rev 4.00 Page 13 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) VIN 5V/DIV VIN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 33. START-UP VIN AT 2A LOAD FIGURE 34. START-UP VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C VIN 5V/DIV VIN 5V/DIV IL 1A/DIV IL 1A/DIV VOUT 1V/DIV VOUT 1V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 35. SHUTDOWN VIN AT 2A LOAD FIGURE 36. SHUTDOWN VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 37. START-UP VIN AT NO LOAD FIGURE 38. START-UP VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FN7888 Rev 4.00 Page 14 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 100ms/DIV 50ms/DIV FIGURE 39. SHUTDOWN VIN AT NO LOAD FIGURE 40. SHUTDOWN VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 1V/DIV LX 1V/DIV 10ns/DIV 10ns/DIV FIGURE 41. JITTER AT NO LOAD FIGURE 42. JITTER AT FULL LOAD FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 20mV/DIV VOUT 10mV/DIV IL 0.5A/DIV IL 0.5A/DIV 50ms/DIV 500ns/DIV FIGURE 43. STEADY STATE AT NO LOAD FIGURE 44. STEADY STATE AT NO LOAD FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FN7888 Rev 4.00 Page 15 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV 200µs/DIV 200µs/DIV FIGURE 45. LOAD TRANSIENT FIGURE 46. LOAD TRANSIENT FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV VOUT 0.5V/DIV IL 2A/DIV IL 1A/DIV VOUT 1V/DIV PG 5V/DIV PG 5V/DIV 5µs/DIV 500µs/DIV FIGURE 47. OUTPUT SHORT-CIRCUIT FIGURE 48. OVERCURRENT PROTECTION FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C LX 5V/DIV LX 5V/DIV 675mA MODE TRANSITION, COMPLETELY ENTER TO PWM AT 770mA BACK TO PFM AT 121mA VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 2A/DIV IL 1A/DIV 2µs/DIV 2µs/DIV FIGURE 49. PFM TO PWM TRANSITION FIGURE 50. PWM TO PFM TRANSITION FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +25°C FN7888 Rev 4.00 Page 16 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV IL 2A/DIV VOUT 0.5V/DIV VOUT 2V/DIV PG 2V/DIV PG 5V/DIV 10µs/DIV 1ms/DIV FIGURE 51. OVERVOLTAGE PROTECTION FIGURE 52. OVER-TEMPERATURE PROTECTION FSW = 2MHz, VIN = 5V, MODE=PFM, TA = +25°C FSW = 2MHz, VIN = 5V, MODE=PWM, TA = +163°C Theory of Operation VEAMP The device is a step-down switching regulator optimized for battery powered applications. It operates at high switching frequency (1MHz VCSA or 2MHz), which enables the use of smaller inductors resulting in small form factor, while also providing excellent efficiency. Further, DUTY at light loads while in PFM mode, the regulator reduces the CYCLE switching frequency, thereby minimizing the switching loss and maximizing battery life. The quiescent current when the output is not loaded is typically only 35µA. The supply current is typically only IL 5µA when the regulator is shut down. PWM Control Scheme VOUT Pulling the MODE pin HI (>2.5V) forces the converter into PWM mode, regardless of output current. The device employs the FIGURE 53. PWM OPERATION WAVEFORMS current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. See The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference “Functional Block Diagram” on page5. The current loop consists of voltage to the voltage loop. The feedback signal comes from the the oscillator, the PWM comparator, current sensing circuit and the VFB pin. The soft-start block only affects the operation during the slope compensation for the current loop stability. The slope start-up and will be discussed separately. The error amplifier is a compensation is 900mV/Ts, which changes with frequency. The transconductance amplifier that converts the voltage error signal gain for the current sensing circuit is typically 300mV/A. The control to a current output. The voltage loop is internally compensated reference for the current loops comes from the error amplifier's with the 27pF and 200kΩ RC network. The maximum EAMP (EAMP) output. voltage output is precisely clamped to 1.6V. The PWM operation is initialized by the clock from the oscillator. PFM Mode The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the Pulling the MODE pin LO (<0.4V) forces the converter into PFM sum of the current amplifier CSA and the slope compensation mode. The device enters a pulse-skipping mode at light load to reaches the control reference of the current loop, the PWM minimize the switching loss by reducing the switching frequency. comparator COMP sends a signal to the PWM logic to turn off the Figure54 illustrates the skip-mode operation. A zero-cross P-FET and turn on the N-Channel MOSFET. The N-FET stays on until sensing circuit shown in Figure54 monitors the N-FET current for the end of the PWM cycle. Figure53 shows the typical operating zero crossing. When 16 consecutive cycles of the inductor current waveforms during the PWM operation. The dotted lines illustrate crossing zero are detected, the regulator enters the skip mode. the sum of the slope compensation ramp and the current-sense During the eight detecting cycles, the current in the inductor is amplifier’s CSA output. allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. FN7888 Rev 4.00 Page 17 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A PWM PFM PWM CLOCK 16 CYCLES PFM CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL NOMINAL -1.5% FIGURE 54. SKIP MODE OPERATION WAVEFORMS Once the skip mode is entered, the pulse modulation starts being cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the controlled by the SKIP comparator as shown in the “Functional N-FET will activate discharging the output into regulation. The Block Diagram” on page5. Each pulse cycle is still synchronized control will begin to switch when output is within regulation. The by the PWM clock. The P-FET is turned on at the clock's rising regulator will be in PFM for 20µs before switching to PWM if edge and turned off when the output is higher than 1.5% of the necessary. nominal regulation or when its current reaches the peak Skip PG current limit value. Then the inductor current is discharges to 0A and stays at zero. The internal clock is disabled. The output PG is an output of a window comparator that continuously monitors voltage reduces gradually due to the load current discharging the the buck regulator output voltage. PG is actively held low when EN is output capacitor. When the output voltage drops to the nominal low and during the buck regulator soft-start period. After 1ms delay voltage, the P-FET will be turned on again at the rising edge of of the soft-start period, PG becomes high impedance as-long-as the the internal clock as it repeats the previous operations. output voltage is within nominal regulation voltage set by VFB. The regulator resumes normal PWM mode operation when the When VFB drops 15% below or raises 15% above the nominal output voltage drops 1.5% below the nominal voltage. regulation voltage, the device pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. Overcurrent Protection There is an internal 5MΩ pull-up resistor to fit most applications. An external resistor can be added from PG to VIN for more pull-up The overcurrent protection is realized by monitoring the CSA strength. output with the OCP comparator, as shown in the “Functional Block Diagram” on page5. The current sensing circuit has a gain UVLO of 300mV/A, from the P-FET current to the CSA output. When the CSA output reaches a threshold, the OCP comparator is tripped to When the input voltage is below the undervoltage lock-out (UVLO) turn off the P-FET immediately. The overcurrent function protects threshold, the regulator is disabled. the switching converter from a shorted output by monitoring the Enable, Disable, and Soft-Start Up current flowing through the upper MOSFET. After the VIN pin exceeds its rising POR trip point (nominal 2.7V), Upon detection of overcurrent condition, the upper MOSFET will the device begins operation. If the EN pin is held low externally, be immediately turned off and will not be turned on again until nothing happens until this pin is released. Once the EN is the next switching cycle. If the overcurrent condition goes away, released and above the logic threshold, the internal default the output will resume back into regulation point. soft-start time is 1ms. Short-Circuit Protection Discharge Mode (Soft-Stop) The short-circuit protection (SCP) comparator monitors the VFB When a transition to shutdown mode occurs or the VIN UVLO is set, pin voltage for output short-circuit protection. When the VFB is the outputs discharge to GND through an internal 100Ω switch. lower than 0.3V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This 100% Duty Cycle (1MHz Version) comparator is effective during start-up or an output short-circuit The device features 100% duty cycle operation to maximize the event. battery life. When the battery voltage drops to a level that the Negative Current Protection device can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout Similar to the overcurrent, the negative current protection is voltage under the 100% duty cycle operation is the product of the realized by monitoring the current across the low-side N-FET, as load current and the ON-resistance of the P-FET. shown in the “Functional Block Diagram” on page5. When the valley point of the inductor current reaches -1.5A for 2 consecutive FN7888 Rev 4.00 Page 18 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Thermal ShutDown voltage 3.3V application, in order to decrease the inductor ripple current and output voltage ripple, the output inductor value can The device has built-in thermal protection. When the internal be increased. It is recommended to set the inductor ripple temperature reaches +150°C, the regulator is completely current to be approximately 30% of the maximum output current shutdown. As the temperature drops to +125°C, the device for optimized performance. The inductor ripple current can be resumes operation by stepping through the soft-start. expressed as shown in Equation4: Power Derating Characteristics V 1–-V-----O--- To prevent the ISL8002 from exceeding the maximum junction I = -----O----------------------V----I--N------ (EQ. 4) temperature, some thermal analysis is required. The LFSW temperature rise is given by Equation2: The inductor’s saturation current rating needs to be at least T = PD  (EQ. 2) larger than the peak current. RISE JA The device uses internal compensation network and the output where PD is the power dissipated by the regulator and θJA is the capacitor value is dependent on the output voltage. The ceramic thermal resistance from the junction of the die to the ambient capacitor is recommended to be X5R or X7R. temperature. The junction temperature, TJ, is given by Equation3: Output Voltage Selection T = T +T  (EQ. 3) The output voltage of the regulator can be programmed via an RISE A RISE external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the where TA is the ambient temperature. For the DFN package, the inverting input of the error amplifier (see Figure35). θJA is +71°C/W. The actual junction temperature should not exceed the absolute The output voltage programming resistor, R2, will depend on the value chosen for the feedback resistor and the desired output maximum junction temperature of +125°C when considering voltage of the regulator. The value for the feedback resistor is the thermal design. typically between 10kΩ and 100kΩas shown in Equation5. The ISL8002 delivers full current at ambient temperatures up to V +85°C; if the thermal impedance from the thermal pad R = R -------O-----–1 (EQ. 5) 1 2VFB  maintains the junction temperature below the thermal shutdown level, depending on the input voltage/output voltage If the output voltage desired is 0.6V, then R2 is left unpopulated combination and the switching frequency. The device power and R1 is shorted. There is a leakage current from VIN to LX. It is dissipation must be reduced to maintain the junction recommended to preload the output with 10µA minimum. For temperature at or below the thermal shutdown level. Figure55 better performance, add 22pF in parallel with R1Check loop illustrates the approximate output current derating versus analysis before use in application. ambient temperature for the ISL8002 EVAL1Z kit. Input Capacitor Selection 2.5 The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering T (V) 2.0 function to prevent the switching current flowing back to the N battery rail. At least two 22µF X5R or X7R ceramic capacitors are RE 1.5 1V a good starting point for the input capacitor selection. R U 1.5V C T 1.0 2.5V Output Capacitor Selection U P UT 3.3V An output capacitor is required to filter the inductor current. O 0.5 Output ripple voltage and transient response are 2 critical factors VIN = 5V, OLFM when considering output capacitance choice. The current mode 0 control loop allows for the usage of low ESR ceramic capacitors 50 60 70 80 90 100 110 120 130 and thus smaller board layout. Electrolytic and polymer TEMPERATURE (°C) capacitors may also be used. FIGURE 55. DERATING CURVE vs TEMPERATURE Additional consideration applies to ceramic capacitors. While Applications Information they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. Ceramic capacitors Output Inductor and Capacitor Selection are rated using large peak-to-peak voltage swings and with no DC bias. In the DC/DC converter application, these conditions do not To consider steady state and transient operations, reflect reality. As a result, the actual capacitance may be ISL8002A/ISL80019A typically requires a 1.2µH and considerably lower than the advertised value. Consult the ISL8002/ISL80019 typically requires a 2.2µH output inductor. manufacturers data sheet to determine the actual in-application Higher or lower inductor value can be used to optimize the total capacitance. Most manufacturers publish capacitance vs DC bias converter system performance. For example, for higher output so this effect can be easily accommodated. The effects of AC FN7888 Rev 4.00 Page 19 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. The result of these ^iin ^iL LLP RLP voo^ considerations can easily result in an effective capacitance 50% ++ lcohwoeicre t hina nm tahney r aaptepdli cvaatluioen. sN dounee tthoe tlheesisr, rtehleiayb ailriety aa nvedr ey xgtoreomd ely V^in IILd^ 11::DD Vind^ RRcc low ESR. ++ RRTT The following equations allow calculation of the required S(fi)) Co Ro capacitance to meet a desired ripple voltage level. Additional P ( capacitance may be used. OO For the ceramic capacitors (low ESR) = N (VL d^ TTii((SS)) KK V = ---------------------I------------------ (EQ. 6) GAI FFmm OUTripple 8F C SW OUT where I is the inductor’s peak-to-peak ripple current, FSW is the + HHee((SS)) TTv((SS)) switching frequency and COUT is the output capacitor. v^comp If using electrolytic capacitors then: --AAvv((SS)) V = I*ESR (EQ. 7) FIGURE 56. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK OUTripple REGULATOR Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be VOUT transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. The following equation R1 C4 determines the required output capacitor value in order to VFB achieve a desired overshoot relative to the regulated voltage. -- VCOMP GM COUT = -V----O----U----T----2----*-----V----O-----IU--O--T--U--M--T--A--2--X--*---L---V----O-----U----T------2-----–----1----- (EQ. 8) R2 VREF ++ R14 C8 where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. For an overshoot of 5%, C7 the equation becomes as follows: IOUT2*L C = ----------------------------------------------------- (EQ. 9) OUT 2 2 VOUT *1.05 –1 FIGURE 57. TYPE II COMPENSATOR Loop Compensation Design Figure57 shows the type II compensator and its transfer function When COMP is not connected to VDD, the COMP pin is active for is expressed as Equation10: external loop compensation. The ISL8002, ISL8002A, ISL80019, and ISL80019A use constant frequency peak current mode vˆ GMR 1+-----S--------1+-----S-------- control architecture to achieve fast loop transient response. An A S= ----c---o---m-----p--= -------------------------------------2------------------- --------------------c---z---1-----------------------c---z---2-------- accurate current sensing pilot device in parallel with the upper v vˆFB C7+C8R1+R2 S1+-----S--------1+-----S--------      MOSFET is used for peak current control signal and overcurrent cp1 cp2 (EQ. 10) protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes a where, single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage  = --------1----------,  =-------1-------- = ---C-----7----+-----C----8----- = -R-----1-----+----R-----2--- mode control. Peak current mode control has an inherent input cz1 R14C7 cz2 R1C4 cp1 R14C7C8 cp2 C4R1R2 voltage feed-forward function to achieve good line regulation. Figure56 shows the small signal model of the synchronous buck regulator. FN7888 Rev 4.00 Page 20 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A COMPENSATOR DESIGN GOAL 60 • High DC gain • Choose Loop bandwidth fc less than 100kHz 45 • Gain margin: >10dB 30 • Phase margin: >50° B) d The compensator design procedure is as follows: N ( 15 AI G The loop gain at crossover frequency of fc has unity gain. 0 Therefore, the compensator resistance R14 is determined by Equation11. -15 2fcVoCoRt 3 (EQ. 11) R = ---------------------------------- = 2610 f V C 14 GMVFB c o o -30 100 1k 10k 100k 1M Where GM is the trans-conductance of the voltage error FREQUENCY (Hz) amplifier. Compensator capacitors C7 and C8 are then given by 180 Equations12 and 13. 150 R C V C C = -----o--------o--= -----o--------o-- (EQ. 12) 7 R I R 14 o 14 120 E (°) C = max(R-----c---C-----o--,--------1-----------) HAS 90 8 R f R (EQ. 13) P 14 s 14 60 An optional zero can boost the phase margin.  is a zero due CZ2 to R1 and C4 30 Put compensator zero 2 to 5 times fc: 0 1 100 1k 10k 100k 1M C = ---------------- (EQ. 14) 4 f R FREQUENCY (Hz) c 1 FIGURE 58. SIMULATED LOOP GAIN Example: VIN = 5V, VOUT = 1.8V, IO = 2A, FSW = 1MHz, Layout Considerations R1=200k, R2=100k, COUT=2x22µF/3mΩ, L = 2.2µH, The PCB layout is a very important converter design step to make fc=100kHz, then compensator resistance R14: sure the designed converter works well. The power loop is R14 = 26103100kHz1.8V44F = 205k (EQ. 15) composed of the output inductor L’s, the output capacitor COUT, the PHASE’s pins, and the PGND pin. It is necessary to make the Using the closest standard value for R14 value is fine (200k. power loop as small as possible and the connecting traces C = 1----.-8----V---------4---4--------F---= 198pF (EQ. 16) among them should be direct, short and wide. The switching 7 2A200k node of the converter, the PHASE pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace C = max(-3---m---------------4---4--------F---,-----------------------1-------------------------)= (1pF,2.3pF) (EQ. 17) away from these noisy traces. The input capacitor should be 8 200k 1MHz200k placed as closely as possible to the VIN pin and the ground of the input and output capacitors should be connected as closely as The closest standard values for C7 and C8 are also fine. There is possible. The heat of the IC is mainly dissipated through the approximately 3pF parasitic capacitance from VCOMP to GND; thermal pad. Maximizing the copper area connected to the Therefore, C8 is optional. Use C7=220pF and C8=OPEN. thermal pad is preferable. In addition, a solid ground plane is 1 helpful for better EMI performance. It is recommended to add at C = ------------------------------------------------ = 16pF (EQ. 18) 4 100kHz200k least 4 vias ground connection within the pad for the best thermal relief. Use C4=15pF. Note that C4 may increase the loop bandwidth from previously estimated value. Figure58 shows the simulated voltage loop gain. It is shown that it has 114kHz loop bandwidth with 52° phase margin and 10dB gain margin. It may be more desirable to achieve more phase margin. This can be accomplished by lowering R14 by 20% to 50%. FN7888 Rev 4.00 Page 21 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE July 31, 2014 FN7888.4 Page18 under overcurrent protection: removed a text, which read “after the hiccup mode expires”. Added ISL80019AEVAL1Z and ISL80019EVAL1Z to ordering information table on Page6. November 26, 2013 FN7888.3 Added Eval boards to “Ordering Information” on Page6. Added Curve and “Power Derating Characteristics” on page19. July 30, 2013 FN7888.2 Updated ordering information table on Page6. Added Figures 12, 13 and 14 to “Typical Performance Curves” on page9. Electrical Specifications on Page7 under output regulation section removed duplicate of "TJ = -40°C to +125°C" from VFB Bias Current to in place Line Regulation. June 13, 2013 Functional Block Diagram on page 5 - changed VFB to VREF Changed part number in ordering information on page 6 from ISL80019FRZ-T TO ISL80019FZ-T Changed on page 7 Recommend Operating Conditions the word "Ambient" to "Junction" Changed in Electrical Spec on page 7 conditions from TA -40 to +85 to TJ -40 to +125 VFB Bias Current under Output Regulation Test condition from 0.75V and TYP from 0.1 to 2.7V MIN -120 TYP 50 MAX 350 Type II Compensator graphic on page 20 - changed VFB to VREF May 10, 2013 Pin Descriptions on Page4: EN section, changed pin rises from 0.6V to 1.4V. January 7, 2013 FN7888.1 Initial release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2013-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7888 Rev 4.00 Page 22 of 23 July 31, 2014

ISL8002, ISL8002A, ISL80019, ISL80019A Package Outline Drawing L8.2x2C 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD Rev 0, 07/08 2.00 A 6 PIN #1 INDEX AREA 6 B PIN 1 INDEX AREA 8 1 0.50 2.00 1E.4x5p±.D0.A0P50 (4X) 0.15 0.10M CAB 0.25 ( 8x0.30 ) TOP VIEW 0.80±0.050 Exp.DAP BOTTOM VIEW Package Outline ( 8x0.20 ) ( 8x0.30 ) SEE DETAIL "X" ( 6x0.50 ) 0.10 C C 0 . 75 ( 0 . 80 max) 1.45 2.00 BASE PLANE SEATING PLANE 0.08 C SIDE VIEW ( 8x0.25 ) 0.80 2.00 TYPICAL RECOMMENDED LAND PATTERN C 0 . 2 REF 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7888 Rev 4.00 Page 23 of 23 July 31, 2014