DATASHEET ISL6563 FN9126 Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers Rev 8.00 Jun 10, 2010 The ISL6563 two-phase PWM control IC provides a Features precision voltage regulation system for advanced microprocessors. Multiphase power conversion is a marked • Integrated Two-Phase Power Conversion departure from single phase converter configurations • Both 5V and 12V Conversion employed to satisfy the increasing current demands of • Precision Channel Current Sharing modern microprocessors and other electronic circuits. By distributing the power and load current, implementation of - Loss Less Current Sampling - Uses rDS(ON) multiphase converters utilize smaller and lower cost • Precision Output Voltage Regulation transistors with fewer input and output capacitors. These - 1% System Accuracy Over-Temperature (Commercial) reductions accrue from the higher effective conversion frequency with higher frequency ripple current due to the • Microprocessor Voltage Identification Inputs phase interleaving process of this topology. - Up to a 6-Bit DAC Outstanding features of this controller IC include - Selectable between Intel’s VRM9, VRM10, or AMD’s programmable VID codes compatible with Intel VRM9, Hammer DAC codes VRM10, as well as AMD’s Hammer microprocessors, along - Resistor-Programmable Droop Voltage with a system regulation accuracy of 1%. The droop • Fast Transient Recovery Time characteristic, used to reduce the overshoot or undershoot of the output voltage, is easily programmed with a single resistor. • Overcurrent Protection Important features of this controller IC include a set of • Improved, Multi-tiered Overvoltage Protection sophisticated overvoltage and overcurrent protection. • Capable of Start-up into a Pre-Charged Output Overvoltage results in the converter turning the lower MOSFETs ON to clamp the rising output voltage and protect • QFN Package: the microprocessor. Like other Intersil multiphase - Compliant to JEDEC PUB95 MO-220 controllers, the ISL6563 uses cost and space-saving QFN - Quad Flat No Leads - Package Outline rDS(ON) sensing for channel current balance, dynamic - Near Chip Scale Package Footprint, which Improves voltage positioning, and overcurrent protection. Channel PCB Efficiency and has a Thinner Profile current balancing is automatic and accurate with the integrated current-balance control system. Overcurrent • Pb-Free (RoHS Compliant) protection can be tailored to any application with no need for additional parts. These features provide advanced protection Pinout for the microprocessor and power system. ISL6563 Ordering Information (24 LD QFN) TOP VIEW TEMP. 1 PAR(TN oNtUe M2)BER MAPRAKRITNG RA(°NCG)E P(APCb-KfrAeGe)E DPWKGG.. # D2 D3 D4 NLL OOT1 GATE VI VI VI E B U ISL6563CRZ 65 63CRZ 0 to +70 24 Ld 4x4 QFN L24.4x4B 24 23 22 21 20 19 ISL6563CRZ-T (Note 1) 65 63CRZ 0 to +70 24 Ld 4x4 QFN L24.4x4B VID1 1 18 PHASE1 ISL6563CRZ-TK (Note 1) 65 63CRZ 0 to +70 24 Ld 4x4 QFN L24.4x4B VID0 2 17 LGATE1 ISL6563IRZ 65 63IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4B ISL6563IRZ-T (Note 1) 65 63IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4B DACSEL/VID5 3 16 PVCC 25 ISL6563EVAL1 Evaluation Platform VRM10 4 GND 15 LGATE2 NOTES: COMP 5 14 PGND 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free FB 6 13 PHASE2 material sets, molding compounds/die attach materials, and 100% matte 7 8 9 10 11 12 tin plate plus anneal (e3 termination finish, which is RoHS compliant and N C S D 2 2 compatible with both SnPb and Pb-free soldering operations). Intersil E C F N T E Pb-free products are MSL classified at Pb-free peak reflow temperatures IS V O SE OO AT S B G that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. U FN9126 Rev 8.00 Page 1 of 20 Jun 10, 2010

JuFN Block Diagram IS n 191 L65 02 6 , 26 SSEND ENLL VCC PVCC BOOT1 3 0R 1e 0v OVP WHILE 8 DISABLED .0 0 1.65V/1.95V + - POWER-ON UGATE1 OVP OSCILLATOR RESET (POR) GATE PHASE1 + CONTROL 200mV - COMP LGATE1 VID0 VID1 PWM1 SOFT-START PGND VID2 TTL D/A AND FAULT LOGIC CONVERTER VID3 (VID DAC) CONTROL VID4 EA LOGIC DACSEL/VID5 + BOOT2 OC  PWM2 VRM10 -  UGATE2 FB GATE PHASE2 CONTROL  CURRENT CORRECTION DROOP LGATE2 SOURCE OFFSET SOURCE GND  2 P a g e 2 o OFS ISEN f 2 0

ISL6563 Simplified Power System Diagram +5VIN Q1 CHANNEL1 Q2 5-6 VID DAC VOUT Q3 CHANNEL2 Q4 ISL6563 Typical Application +12VIN LIN +5VIN CHFIN1 CBIN1 CF2 CF1 VCC PVCC BOOT1 CBOOT1 DACSEL/VID12 VID4 UGATE1 Q1 VID3 VID2 PHASE1 LOUT1 VID1 VID0 VRM10 Q2 LGATE1 RISEN ISEN BOOT2 VOUT SSEND R’OFS ENLL ISL6563 CBOOT2 OFS CHFIN2 CBIN2 CHFOUT CBOUT ROFS UGATE2 Q3 PHASE2 COMP C2 C1 LOUT2 LGATE2 Q4 R2 PGND FB GND R1 FN9126 Rev 8.00 Page 3 of 20 Jun 10, 2010

ISL6563 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC, PVCC. . . . . . . . . . . . . . . . . . -0.3V to +6.25V Thermal Resistance JA (°C/W) JC (°C/W) Absolute Boot Voltage, VBOOT . . . . . PGND - 0.3V to PGND + 27V QFN Package (Notes 3, 4). . . . . . . . . . 43 7 Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C Upper Gate Voltage, VUGATE . . . .VPHASE - 0.3V to VBOOT + 0.3V Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Lower Gate Voltage, VLGATE. . . . . . . . PGND - 0.3V to VCC + 0.3V Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp ESD Classification. . . . . . . . . . . . . . . . . .HBM Class 1 JEDEC STD Recommended Operating Conditions Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VCC = 5V, TJ = 0°C to +85°C, Unless Otherwise Specified. MIN MAX PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS BIAS SUPPLY AND INTERNAL OSCILLATOR Input Bias Supply Current IVCC; ENLL = high - 4 6 mA VCC POR (Power-On Reset) Threshold VCC Rising 4.2 4.4 4.6 V VCC Falling 3.7 3.9 4.1 V PVCC POR (Power-On Reset) Threshold PVCC Rising - 4.2 - V PVCC Falling - 3.3 - V Switching Frequency (per Channel) TJ = +25°C to +85°C 189 222 255 kHz (Note 5) TJ = -40°C 166 205 241 kHz Oscillator Ramp Amplitude (Note 6) VPP - 1.33 - V Maximum Duty Cycle (Note 6) - 66 - % CONTROL THRESHOLDS ENLL Rising Threshold - 0.61 - V ENLL Hysteresis (Note 6) - 60 - mV COMP Shutdown Threshold 0.23 0.36 0.49 V COMP Shutdown Maximum Pull-Down Impedance - - 15  REFERENCE AND DAC System Accuracy -1 - 1 % TJ = -40°C to +85°C -1.5 - 1.5 % DAC Input Low Voltage - - 0.4 V DAC Input High Voltage 0.8 - - V DAC Input Pull-Up Current VIDx = 0V - 45 - µA ERROR AMPLIFIER DC Gain (Note 5) RL = 10k to ground - 96 - dB Gain-Bandwidth Product (Note 6) CL = 100pF, RL = 10k to ground - 20 - MHz Slew Rate (Note 6) CL = 100pF, Load = 400µA - 8 - V/µs Maximum Output Voltage Load = 1mA 3.90 4.20 - V Minimum Output Voltage Load = -1mA - 0.80 0.90 V FN9126 Rev 8.00 Page 4 of 20 Jun 10, 2010

ISL6563 Electrical Specifications Test Conditions: VCC = 5V, TJ = 0°C to +85°C, Unless Otherwise Specified. (Continued) MIN MAX PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS OVERCURRENT PROTECTION Overcurrent Trip Level - 95 - µA PROTECTION Overvoltage Threshold while IC Disabled VRM9.0 configuration 1.90 1.95 2.00 V Hammer and VRM10.0 configurations 1.60 1.65 1.70 V Overvoltage Threshold FB Rising - VID +200mV - V Overvoltage Hysteresis - 100 - mV SWITCHING TIME UGATE Rise Time (Note 6) tRUGATE; VVCC = 5V, 3nF Load - 8 - ns LGATE Rise Time (Note 6) tRLGATE; VVCC = 5V, 3nF Load - 8 - ns UGATE Fall Time (Note 6) tFUGATE; VVCC = 5V, 3nF Load - 8 - ns LGATE Fall Time (Note 6) tFLGATE; VVCC = 5V, 3nF Load - 4 - ns UGATE Turn-On Non-overlap (Note 6) tPDHUGATE; VVCC = 5V, 3nF Load - 8 - ns LGATE Turn-On Non-overlap (Note 6) tPDHLGATE; VVCC = 5V, 3nF Load - 8 - ns OUTPUT Upper Drive Source Resistance 100mA Source Current - 0.5 1.3  Upper Drive Sink Resistance 100mA Sink Current - 0.4 1.0  Lower Drive Source Resistance 100mA Source Current - 0.5 1.3  Lower Drive Sink Resistance 100mA Sink Current - 0.3 1.0  NOTES: 5. Parameter magnitude at TJ = -40°C determined through characterization. 6. Limits should be considered typical and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Timing Diagram tPDHUGATE tRUGATE tFUGATE UGATE LGATE tFLGATE tRLGATE tPDHLGATE FN9126 Rev 8.00 Page 5 of 20 Jun 10, 2010

ISL6563 Functional Pin Description ISEN (Pin 7) This pin is used to close the current-feedback loop and set the VCC (Pin 8) overcurrent protection threshold. A resistor connected between Bias supply for the IC’s small-signal circuitry. Connect this this pin and VCC has a voltage drop forced across it equal to pin to a 5V supply and locally decouple using a quality 0.1µF that sampled across the lower MOSFET’s rDS(ON) during ceramic capacitor. approximately the middle of its conduction interval. The PVCC (Pin 16) resulting current through this resistor is used for channel current balancing, overcurrent protection and is sourced to the Power supply pin for the MOSFET drives. Connect this pin to a 5V supply and locally decouple using a quality 1µF FB pin for load-line regulation. The voltage across the RISEN resistor is time multiplexed between the two channels. ceramic capacitor. GND and PGND (Pins 25 and 14) Use Equation 1 to select the proper RISEN resistor: r I Connect these pins to the circuit ground using the shortest RISEN = ---D----S------O-5---N-0--------A------O----U----T-- (EQ. 1) possible paths. All internal small-signal circuitry is referenced to the GND pin. LGATE drive is referenced to the where: PGND pin. rDS(ON) = lower MOSFET drain-source ON-resistance () VID0-4 (Pins 2, 1, 24-22) IOUT = channel maximum output current (A) Voltage identification inputs from microprocessor. These pins Read ‘Current Feedback’ paragraph for more information. respond to TTL logic thresholds. The ISL6563 decodes the VID inputs to establish the output voltage; see VID Tables for UGATE1, 2 (Pins 19, 12) correspondence between DAC codes and output voltage Connect these pins to the upper MOSFETs’ gates. These settings. These pins are internally pulled high, to pins are used to control the upper MOSFETs and are approximately 1.2V, by 40µA (typically) internal current monitored for shoot-through prevention purposes. Maximum sources; the internal pull-up current decrease to 0 as the VID individual channel duty cycle is limited to 66%. voltage approaches the internal pull-up voltage. All VID pins BOOT1, 2 (Pins 20, 11) are compatible with external pull-up voltages not exceeding the IC’s bias voltage. These pins provide the bias voltage for the upper MOSFETs’ drives. Connect these pins to appropriately-chosen external DACSEL/VID5 (Pin 3) bootstrap capacitors. Internal bootstrap diodes connected to If VRM10 pin is grounded, DACSEL/VID5 represents the 6th the PVCC pins provide the necessary bootstrap charge. voltage identification input from the VRM10-compliant PHASE1, 2 (Pins 18, 13) microprocessor, otherwise known as VID5. If VRM10 pin is open or pulled high, DACSEL/VID5 selects the compliance Connect these pins to the sources of the upper MOSFETs. standard for the internal DAC: pulled to ground it encodes the These pins are the return path for the upper MOSFETs’ drives. DAC with AMD Hammer VID codes, while left open or pulled LGATE1, 2 (Pins 17, 15) high, it encodes the DAC with Intel VRM9.0 codes. These pins are used to control the lower MOSFETs and are VRM10 (Pin 4) monitored for shoot-through prevention purposes. Connect This pin selects VRM10.0 DAC compliance when grounded. these pins to the lower MOSFETs’ gates. Left open, it allows selection of either VRM9.0 or Hammer OFS (Pin 9) DAC compliance via DACSEL pin. This pin is used to create an adjustable output voltage offset. ENLL (Pin 21) For no offset, leave this pin open. For negative offset, connect This pin is a precision-threshold (approximately 0.6V) enable an R’OFS resistor from this pin to VCC and size it according to pin. Held low, this pin disables controller operation. Pulled Equation 2: high, the pin enables the controller for operation. 1500 R = R -------------------------- (EQ. 2) OFS 1 V OFFSET FB and COMP (Pins 6, 5) The internal error amplifier’s inverting input and output where: respectively. These pins are connected to the external VOFFSET = desired output voltage offset magnitude (mV) network used to compensate the regulator’s feedback loop. For positive output voltage offset, connect an ROFS resistor An internal current source injects the average current from this pin to GND, sizing it according to Equation 3: sampled through RISEN into the FB pin. Pulling COMP to ground through an impedance lower than 15 disables the R = R ---------5---0----0---------- (EQ. 3) OFS 1 V controller (same effect as ENLL pulled low). OFFSET FN9126 Rev 8.00 Page 6 of 20 Jun 10, 2010

ISL6563 For more information, refer to the ‘Output Voltage Offset through the output drivers with no phase reversal to drive the Programming’ paragraph. external upper MOSFETs. Increased duty cycle or ON time for the upper MOSFET transistors results in increased SSEND (Pin 10) output voltage to compensate for the low output voltage This pin is an end of Soft-Start (SS) indicator; open drain sensed. output device stays ON during soft-start, and goes open when Current Loop soft-start ends. The current control loop works in a similar fashion to the Operation voltage control loop, but with current control information Figure 1 shows a simplified diagram of the voltage regulation applied individually to each channel’s Comparator. The and current control loops. Both voltage and current feedback information used for this control is the voltage that is are used to precisely regulate the output voltage and tightly developed across the rDS(ON) of each lower MOSFET, while control the output currents, IL1 and IL2, of the two power they are conducting. A single resistor converts and scales channels. the voltage across the MOSFETs to a current that is applied to the Current Sensing circuit within the ISL6563. Output Voltage Loop from these sensing circuits is applied to the current averaging circuit. Each PWM channel receives the Feedback from the output voltage is applied via resistor R1 difference current signal from the summing circuit that to the inverting input of the Error Amplifier. This signal can compares the average sensed current to the individual drive the Error Amplifier output either high or low, depending channel current. When a power channel’s current is greater upon the output voltage. Low output voltage makes the than the average current, the signal applied via the summing amplifier output move towards a higher output voltage level. Correction circuit to the Comparator, reduces the output Amplifier output voltage is applied to the positive inputs of pulse width of the Comparator to compensate for the the PWM Circuit comparators via the correction summing detected “above average” current in that channel. networks. Out-of-phase sawtooth signals are applied to the two PWM comparators inverting inputs. Increasing Error Droop Implementation Amplifier voltage results in increased Comparator output In addition to controlling each channel’s output current, the duty cycle. This increased duty cycle signal is passed average channel current is used to implement an output DAC OSCILLATOR VIN & REFERENCE UGATE1 ERROR AMP PWM HALF-BRIDGE  CIRCUIT DRIVE COMP LGATE1 L1 R2 PWM HALF-BRIDGE  CIRCUIT DRIVE C2 PHASE1 VOUT FB  CURRENT VIN SENSE L2 COUT R1 UGATE2 AVERAGE DROOP SOURCE, IFB CURRENT LGATE2  SENSE PHASE2 ISEN VCC RISEN FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6563 VOLTAGE AND CURRENT CONTROL LOOPS FN9126 Rev 8.00 Page 7 of 20 Jun 10, 2010

ISL6563 voltage droop characteristic. Internal average channel To understand the reduction of ripple current amplitude in the current is fed into the FB pin; the voltage thus developed multiphase circuit, examine Equation 5, which represents an across R1 is equal to the droop voltage. individual channel’s peak-to-peak inductor current. Assuming identical power switch selection on the two V –V V ILPP= -------I--N--------------O-----U----T---------------O----U-----T-- (EQ. 5) channels, Equation 4 determines the current fed out the FB Lf  V S IN pin for output voltage droop generation: IFB = r---D----S------O---R-N-----------I--P----H----A----S----E-- (EQ. 4) VreIsNp aencdtiv VeOlyU, LT iasr eth teh esi ningpleu-tc ahnadn noeult pinudt uvcotlotar gveaslu, e, and fS is ISEN the switching frequency. where, rDS(ON) - lower MOSFET/s’ ON resistance (@5V) The output capacitors conduct the ripple component of the IPHASE - average phase current inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each Multiphase Power Conversion of the individual channels. Peak-to-peak ripple current, IPP, Multiphase power conversion provides a cost-effective decreases by an amount proportional to the number of power solution when load currents are no longer easily channels. Output-voltage ripple is a function of capacitance, supported by single-phase converters. Although its greater capacitor equivalent series resistance (ESR), and inductor complexity presents additional technical challenges, the ripple current. Reducing the inductor ripple current allows multiphase approach offers cost-saving advantages with the designer to use fewer or less costly output capacitors improved response time, superior ripple cancellation, and (should output ripple be an important design parameter). thermal distribution. V –N V  V INTERLEAVING IPP= -------I--N-----------L---------f----O-----U-V---T---------------O----U-----T-- (EQ. 6) S IN The switching of each channel in an ISL6563-based converter is timed to be symmetrically out of phase with the CIN CURRENT other channel. As a result, the two-phase converter has a combined ripple frequency twice the frequency of one of its phases. In addition, the peak-to-peak amplitude of the combined inductor currents is proportionately reduced. Increased ripple frequency and lower ripple amplitude generally translate to lower per-channel inductance and lower total output capacitance for a given set of performance Q1 D-S CURRENT specifications. Q3 D-S CURRENT IL1 + IL2 FIGURE 3. INPUT CAPACITOR CURRENT AND INDIVIDUAL IL2 CHANNEL CURRENTS IN A 2-PHASE CONVERTER PWM2 Another benefit of interleaving is the reduction of input ripple IL1 current. Input capacitance is determined in a large part by the maximum input ripple current. Multiphase topologies can PWM1 improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 3 illustrates input FIGURE 2. PWM AND INDUCTOR-CURRENT WAVEFORMS currents from a two-phase converter combining to reduce FOR 2-PHASE CONVERTER the total input ripple current. Figure 2 illustrates the additive effect on output ripple Figure 11, part of “Input Capacitor Selection” on page18, frequency. The two channel currents (IL1 and IL2), combine can be used to determine the input-capacitor RMS current to form the AC ripple current and the DC load current. The based on load current and duty cycle. The figure is provided ripple component has two times the ripple frequency of each as an aid in determining the optimal input capacitor solution. individual channel current. FN9126 Rev 8.00 Page 8 of 20 Jun 10, 2010

ISL6563 PWM OPERATION current. If both channels’ currents exceed, at any time, the reference current, the overcurrent comparator triggers an One switching cycle for the ISL6563 is defined as the time overcurrent event. Similarly, an OC event is also triggered if between consecutive PWM pulse terminations (turn-off of either channel’s current exceeds the 95µA reference for 7 the upper MOSFET on a channel). Each cycle begins when consecutive switching cycles. a switching clock signal commands the upper MOSFET to go off. The other channel’s upper MOSFET conduction is As a result of an OC event, output drives on both channels terminated 1/2 of a cycle later. turn off both upper and lower MOSFETs. The system then waits in this state for a period of 4096 switching clock cycles. Once a channel’s upper MOSFET is turned off, the lower MOSFET remains on for a minimum of 1/3 cycle. This forced The wait period is followed by a soft-start attempt. If the soft- off time is required to assure an accurate current sample. start attempt is successful, operation continues as normal. Following the 1/3-cycle forced off time, the controller enables Should the soft-start attempt fail, the ISL6563 repeats the the upper MOSFET output. Once enabled, the upper 2048-cycle wait period and follows with another soft-start MOSFET output transitions high when the sawtooth signal attempt. This hiccup mode of operation continues indefinitely crosses the adjusted error-amplifier output signal, as (as depicted in Figure 4) for as long as the controller is illustrated in the ISL6563’s block diagram. Just prior to the enabled or until the overcurrent condition is removed. upper drive turning the MOSFET on, the lower MOSFET drive turns the freewheeling element off. The upper MOSFET is kept on until the clock signals the beginning of the next switching cycle and the PWM pulse is terminated. OUTPUT CURRENT CURRENT SENSING ISL6563 senses current by sampling the voltage across the lower MOSFET during its conduction interval. MOSFET rDS(ON) sensing is a no-added-cost method to sense current for load line regulation, channel current balance, module current sharing, and overcurrent protection. OUTPUT VOLTAGE The PHASE pins are used as inputs for each channel. Internal circuitry samples the lower MOSFETs’ rDS(ON) voltage, once each cycle, during their conduction periods and time multiplexes the sampled voltages across the ISEN FIGURE 4. OVERCURRENT BEHAVIOR IN HICCUP MODE resistor. The current that is thus developed through the ISEN resistor is duplicated and fed back through the FB pin to OUTPUT VOLTAGE SETTING create droop, as well as used for channel current balancing. The ISL6563 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the CHANNEL-CURRENT BALANCE VID pins. The DAC decodes the 5 or 6-bit logic signals into one Another benefit of multiphase operation is the thermal of the discrete voltages shown in Tables 1 through 3. Each VID advantage gained by distributing the dissipated heat over pin is pulled up to an internal 1.2V voltage by weak current multiple devices and greater area. By doing this, the sources (about 45µA current, decreasing to 0 as the voltage at designer avoids the complexity of driving multiple parallel the VID pins varies from 0 to the internal 1.2V pull-up voltage). MOSFETs and the expense of using expensive heat sinks External pull-up resistors or active-high output stages can and exotic magnetic materials. augment the pull-up current sources, up to a voltage of 5V. In order to fully realize the thermal advantage, it is important .The ISL6563 accommodates three different DAC ranges: that each channel in a multiphase converter be controlled to Intel VRM9.0, AMD Hammer, or Intel VRM10.0 - see deliver about the same current at any load level. Intersil “Functional Pin Description” on page6 for proper multiphase controllers ensure current balance by comparing connections for DAC range compatibility. each channel’s current to the average current delivered by all channels and making appropriate adjustments to each TABLE 1. AMD HAMMER VOLTAGE IDENTIFICATION channel’s pulse width based on the error. The error signal CODES modifies the pulse width to correct any unbalance and force VID4 VID3 VID2 VID1 VID0 VDAC the error toward zero. 1 1 1 1 1 Off OVERCURRENT PROTECTION 1 1 1 1 0 0.800 The individual channel currents, as sensed via the PHASE 1 1 1 0 1 0.825 pins and scaled via the ISEN resistor, are continuously 1 1 1 0 0 0.850 monitored and compared with an internal 95µA reference FN9126 Rev 8.00 Page 9 of 20 Jun 10, 2010

ISL6563 TABLE 1. AMD HAMMER VOLTAGE IDENTIFICATION TABLE 2. VRM9 VOLTAGE IDENTIFICATION CODES CODES (Continued) VID4 VID3 VID2 VID1 VID0 VDAC VID4 VID3 VID2 VID1 VID0 VDAC 1 1 1 1 1 Off 1 1 0 1 1 0.875 1 1 1 1 0 1.100 1 1 0 1 0 0.900 1 1 1 0 1 1.125 1 1 0 0 1 0.925 1 1 1 0 0 1.150 1 1 0 0 0 0.950 1 1 0 1 1 1.175 1 0 1 1 1 0.975 1 1 0 1 0 1.200 1 0 1 1 0 1.000 1 1 0 0 1 1.225 1 0 1 0 1 1.025 1 1 0 0 0 1.250 1 0 1 0 0 1.050 1 0 1 1 1 1.275 1 0 0 1 1 1.075 1 0 1 1 0 1.300 1 0 0 1 0 1.100 1 0 1 0 1 1.325 1 0 0 0 1 1.125 1 0 1 0 0 1.350 1 0 0 0 0 1.150 1 0 0 1 1 1.375 0 1 1 1 1 1.175 1 0 0 1 0 1.400 0 1 1 1 0 1.200 1 0 0 0 1 1.425 0 1 1 0 1 1.225 1 0 0 0 0 1.450 0 1 1 0 0 1.250 0 1 1 1 1 1.475 0 1 0 1 1 1.275 0 1 1 1 0 1.500 0 1 0 1 0 1.300 0 1 1 0 1 1.525 0 1 0 0 1 1.325 0 1 1 0 0 1.550 0 1 0 0 0 1.350 0 1 0 1 1 1.575 0 0 1 1 1 1.375 0 1 0 1 0 1.600 0 0 1 1 0 1.400 0 1 0 0 1 1.625 0 0 1 0 1 1.425 0 1 0 0 0 1.650 0 0 1 0 0 1.450 0 0 1 1 1 1.675 0 0 0 1 1 1.475 0 0 1 1 0 1.700 0 0 0 1 0 1.500 0 0 1 0 1 1.725 0 0 0 0 1 1.525 0 0 1 0 0 1.750 0 0 0 0 0 1.550 0 0 0 1 1 1.775 0 0 0 1 0 1.800 0 0 0 0 1 1.825 0 0 0 0 0 1.850 FN9126 Rev 8.00 Page 10 of 20 Jun 10, 2010

ISL6563 TABLE 3. VRM10 VOLTAGE IDENTIFICATION TABLE 3. VRM10 VOLTAGE IDENTIFICATION CODES CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 VDAC VID4 VID3 VID2 VID1 VID0 VID5 VDAC 1 1 1 1 1 1 Off 1 0 0 1 1 1 1.3750 1 1 1 1 1 0 Off 1 0 0 1 1 0 1.3875 0 1 0 1 0 0 0.8375 1 0 0 1 0 1 1.4000 0 1 0 0\ 1 1 0.8500 1 0 0 1 0 0 1.4125 0 1 0 0 1 0 0.8625 1 0 0 0 1 1 1.4250 0 1 0 0 0 1 0.8750 1 0 0 0 1 0 1.4375 0 1 0 0 0 0 0.8875 1 0 0 0 0 1 1.4500 0 0 1 1 1 1 0.9000 1 0 0 0 0 0 1.4625 0 0 1 1 1 0 0.9125 0 1 1 1 1 1 1.4750 0 0 1 1 0 1 0.9250 0 1 1 1 1 0 1.4875 0 0 1 1 0 0 0.9375 0 1 1 1 0 1 1.5000 0 0 1 0 1 1 0.9500 0 1 1 1 0 0 1.5125 0 0 1 0 1 0 0.9625 0 1 1 0 1 1 1.5250 0 0 1 0 0 1 0.9750 0 1 1 0 1 0 1.5375 0 0 1 0 0 0 0.9875 0 1 1 0 0 1 1.5500 0 0 0 1 1 1 1.0000 0 1 1 0 0 0 1.5625 0 0 0 1 1 0 1.0125 0 1 0 1 1 1 1.5750 0 0 0 1 0 1 1.0250 0 1 0 1 1 0 1.5875 0 0 0 1 0 0 1.0375 0 1 0 1 0 1 1.6000 0 0 0 0 1 1 1.0500 DYNAMIC VID (VID-ON-THE-FLY) 0 0 0 0 1 0 1.0625 The ISL6563 is capable of executing on-the-fly output 0 0 0 0 0 1 1.0750 voltage changes. The way the ISL6563 reacts to a change in 0 0 0 0 0 0 1.0875 the VID code is dependent on the VID configuration. In 1 1 1 1 0 1 1.1000 VRM9 or AMD Hammer settings, the ISL6563 checks for a 1 1 1 1 0 0 1.1125 change in the VID code four times each switching cycle. The 1 1 1 0 1 1 1.1250 VID code is the bit pattern present at pins VID4-VID0. If a new code is established and it stays the same for 12 1 1 1 0 1 0 1.1375 switching cycles, the ISL6563 begins changing the reference 1 1 1 0 0 1 1.1500 by making one step change every four switching cycles until 1 1 1 0 0 0 1.1625 it reaches the new VID code. Figure 5 depicts such a 1 1 0 1 1 1 1.1750 transition, from 1.5V to 1.7V 1 1 0 1 1 0 1.1875 01110 00110 VVID 1 1 0 1 0 1 1.2000 1 1 0 1 0 0 1.2125 VID CHANGE OCCURS HERE 1 1 0 0 1 1 1.2250 1 1 0 0 1 0 1.2375 1 1 0 0 0 1 1.2500 VREF (100mV/DIV) 1.5V 1 1 0 0 0 0 1.2625 1 0 1 1 1 1 1.2750 1 0 1 1 1 0 1.2875 VOUT (100mV/DIV) 1.5V 1 0 1 1 0 1 1.300 1 0 1 1 0 0 1.3125 1 0 1 0 1 1 1.3250 1 0 1 0 1 0 1.3375 FIGURE 5. TYPICAL DYNAMIC-VID OPERATION, VRM9 DAC 1 0 1 0 0 1 1.3500 SETTING 1 0 1 0 0 0 1.3625 FN9126 Rev 8.00 Page 11 of 20 Jun 10, 2010

ISL6563 In VRM10 setting, the ISL6563 checks for a change in the VID drops below the OV comparator’s hysteretic threshold. The code six times each switching cycle. If a new code is OVP process repeats if the voltage rises back above the established and it stays the same for 3 consecutive readings, designated threshold. The occurrence of an OVP event does the ISL6563 recognizes the change and increments the not latch the controller; should the phenomenon be reference. Specific to VRM10, the processor controls the VID transitory, the controller resumes normal operation following transitions and is responsible for incrementing or decrementing such an event. one VID step at a time. In VRM10 setting, the ISL6563 will LOAD-LINE REGULATION immediately change the reference to the new requested value In applications with high transient current slew rates, the as soon as the request is validated; in cases where the lowest-cost solution for maintaining regulation often requires reference step is too large, the sudden change can trigger some kind of controlled output impedance. The FB pin of the overcurrent or overvoltage events. ISL6563 carries a current proportional to the average output In non-VRM10 settings, due to the way the ISL6563 current of the converter. The current is equivalent to IFB in recognizes VID code changes, up to one full switching Figure 1. Forcing IFB into the summing node of the error period may pass before a VID change registers. Thus, the amplifier produces a voltage drop across the feedback resistor, total time required for a VID change, tDVID, is dependent on RFB, proportional to the output current. Assuming the current is the switching frequency (fS), the size of the change (VID), shared equally by both phases, the steady-state value of and the time required to register the VID change. The VDROOP is simply: approximate time required for an ISL6563-based converter V = I  R in VRM9 configuration running at typical fS (222kHz) to DROOP FB FB perform a 1.5V-to-1.7V reference voltage change is about (EQ. 8) I r 196s, as calculated using Equation 7 (this example is also V = --O-----U----T----------D----S------O-----N------L---M-----O-----S--R DROOP 2R FB illustrated in Figure5). ISEN t  -1----4--------V----V----I--D---+13 (EQ. 7) ON/OFF CONTROL DVID fS 0.025  The internal power-on reset circuit (POR) prevents the OVERVOLTAGE PROTECTION ISL6563 from starting before the bias voltage at VCC and PVCC reach the rising POR thresholds, as defined in The ISL6563 benefits from a multi-tiered approach to “Electrical Specifications” table on page4. The POR levels overvoltage protection. are sufficiently high to guarantee that all parts of the ISL6563 A pre-POR mechanism is at work while the chip does not can perform their functions properly once bias is applied to have sufficient bias voltage to initiate an active response to the part. While bias is below the rising POR thresholds, the an OV situation. Thus, while VCC is below its POR level, the controlled MOSFETs are kept in an off state. lower drives are tristated and internal 5k (typically) ISL6563 EXTERNAL CIRCUIT resistors are connected from PHASE to their respective LGATE pins. As a result, output voltage, duplicated at the +5V PHASE nodes via the output inductors, is effectively +12V clamped at the lower MOSFETs’ threshold level. This approach ensures no catastrophic output voltage can be VCC ENABLE 15k developed at the output of an ISL6563-based regulator (for COMPARATOR most typical applications). POR + The pre-POR mechanism is removed once the bias is above CIRCUIT ENLL - OFF the POR level, and a fixed-threshold OVP goes into effect. 1k Based on the specific chip configuration, the OVP goes into 0.61V ON effect once the voltage sensed at the FB pin exceeds about 1.65V (Hammer/VR10) or 1.95V (VR9 configuration). Should the output voltage exceed these thresholds, the lower FIGURE 6. START-UP COORDINATION USING THRESHOLD- MOSFETs are turned on. SENSITIVE ENABLE (ENLL) PIN During soft-start, the OVP threshold changes to the higher of A secondary disablement feature is available via the the fixed threshold (1.65V/1.95V) or the DAC setting plus threshold-sensitive enable input (ENLL). This optional 200mV. At the end of the soft-start, the OVP threshold feature prevents the ISL6563 from operating until a certain changes to the DAC setting plus 200mV. other voltage rail is available and above some selectable In any of the described post-POR functionality, OVP results threshold. For example, when down-converting off a 12V in the turn-on of the lower MOSFETs. Once turned on, the input, it may be desirable the ISL6563-based converter does lower MOSFETs are only turned off when the output voltage not start up until the power input is sufficiently high. The FN9126 Rev 8.00 Page 12 of 20 Jun 10, 2010

ISL6563 schematic in Figure 6 demonstrates coordination of the example board layouts for all common microprocessor ISL6563 with such a rail; the resistor components are applications. chosen to enable the ISL6563 as the 12V input exceeds approximately 9.75V. Additionally, an open-drain or open- OUTPUT PRECHARGED ABOVE DAC LEVEL collector device can be used to wire-AND a second (or multiple) control signal, as shown in Figure 6. To defeat the threshold-sensitive enable, connect ENLL to VCC directly or OUTPUT PRECHARGED via a pull-up resistor. BELOW DAC LEVEL The ‘11111’ VID code is reserved as a signal to the controller that no load is present. The controller is disabled while receiving this VID code and will subsequently start up upon GND> VOUT (0.5V/DIV) receiving any other code. In summary, for the ISL6563 to operate, the following GND> ENLL (5V/DIV) conditions need be met: VCC and PVCC must be greater than their respective POR thresholds, the voltage at ENLL must be greater than 0.61V, and VID has to be different than T1T2 T3 ‘11111’. Once all these conditions are met, the controller FIGURE 7. SOFT-START WAVEFORMS FOR ISL6563-BASED immediately initiates a soft start sequence. MULTIPHASE CONVERTER SOFT-START MOSFETs The soft-start function allows the converter to bring up the Given the fixed switching frequency of the ISL6563 and the output voltage in a controlled fashion, resulting in a linear integrated output drives, the selection of MOSFETs revolves ramp-up. Following a delay of 16 PHASE clock cycles (about closely around the current each MOSFET is required to 70s) between enabling the chip and the start of the ramp, conduct, the capability of the devices to dissipate heat, as well the output voltage progresses at a fixed rate of 12.5mV per as the characteristics of available heat sinking. Since the 16 PHASE clock cycles. ISL6563 drives the MOSFETs with 5V, the selection of Thus, the soft-start period (not including the 70µs wait) up to appropriate MOSFETs should be done by comparing and a given voltage, VDAC, can be approximated by Equation 9: evaluating their characteristics at this specific VGS bias T = V-----D----A----C--------1---2----8---0-- (EQ. 9) voltage. SS f S LOWER MOSFET POWER CALCULATION where VDAC is the DAC-set VID voltage, and fS is the Since virtually all of the heat loss in the lower MOSFET is switching frequency (typically 222kHz). conduction loss (due to current conducted through the channel The ISL6563 also has the ability to start up into a pre-charged resistance, rDS(ON)), a quick approximation for heat dissipated output, without causing any unnecessary disturbance. The FB in the lower MOSFET can be found in Equation 10: pthine iesq muiovnailteonret idn tdeurnrinalg r asomftp-sintagr rt,e afenrde nscheo uvlodl tiat gbee, hthigeh oeur ttphuatn PLMOS1 = rDSON I--O----2-U----T--21–D+-I-L----,-P----P2---1---21-----–-----D----- (EQ. 10) drives hold both MOSFETs off. Once the internal ramping reference exceeds the FB pin potential, the output drives are where: IM is the maximum continuous output current, IL,PP is enabled, allowing the output to ramp from the pre-charged level the peak-to-peak inductor current, and D is the duty cycle to the final level dictated by the DAC setting. Should the output (approximately VOUT/VIN). be pre-charged to a level exceeding the DAC setting, the output An additional term can be added to the lower-MOSFET loss drives are enabled at the end of the soft-start period, leading to equation to account for additional loss accrued during the an abrupt correction in the output voltage down to the DAC-set dead time when inductor current is flowing through the level. lower-MOSFET body diode. This term is dependent on the General Application Design Guide diode forward voltage at IM, VD(ON); the switching frequency, fS; and the length of dead times, td1 and td2, at This design guide is intended to provide a high-level the beginning and the end of the lower-MOSFET conduction explanation of the steps necessary to create a multiphase interval, respectively. power converter. It is assumed that the reader is familiar with madadnityio onf ttoh eth bisa sgiuci dseki,l lIsn taenrdsi lt epcrohvniidqeuse sc oremfeprleetnec eredf ebreelnocwe. In PLMOS2 = VDONfS I--O-----U----T--+I--P----P--- td1 +I--O-----U----T--–I--P----P---td2 2 2  2 2  designs that include schematics, bills of materials, and (EQ. 11) FN9126 Rev 8.00 Page 13 of 20 Jun 10, 2010

ISL6563 The above equation assumes the current through the lower Since the power equations depend on MOSFET parameters, MOSFET is always positive; if so, the total power dissipated choosing the correct MOSFETs can be an iterative process in each lower MOSFET is approximated by the summation of that involves repetitively solving the loss equations for PLMOS1 and PLMOS2. different MOSFETs and different switching frequencies until converging upon the best solution. UPPER MOSFET POWER CALCULATION Current Sensing In addition to rDS(ON) losses, a large portion of the upper- MOSFET losses are switching losses, due to currents The resistor connected between the ISEN and VCC pins conducted through the device while the input voltage is determines the gain in the load-line regulation and the present as VDS. Upper MOSFET losses can be divided into channel-current balance loop. Select the value for this separate components, separating the upper-MOSFET resistor based on the room temperature rDS(ON) of the lower switching losses, the lower-MOSFET body diode reverse MOSFETs and the full-load total output current, IFL. recovery charge loss, and the upper MOSFET rDS(ON) R = -r--D----S------O-----N-----I--F----L-- (EQ. 16) conduction loss. ISEN 5010–6 2 In most typical circuits, when the upper MOSFET turns off, it Load Line Regulation Resistor continues to conduct the inductor current until the voltage at The load-line regulation resistor is labeled, R1 in Figure 1, the phase node falls below ground. Once the lower depends on the desired full-load droop voltage. At full load, MOSFET begins conducting (via its body diode or enhancement channel), the current in the upper MOSFET the current determined by RISEN is fed into the FB pin and creates the output voltage droop across R1. Thus, the load falls to zero. In Equation 12, the required time for this line regulation resistor can be computed using Equation 17: commutation is t1and the associated power loss is PUMOS,1. V 2R P V I--O-----U----T--+I--L----,-P----P--t--1--f (EQ. 12) R1 = -----D----R-r---O-----O----P----------------I-----I-S----E----N--- (EQ. 17) UMOS,1 IN 2 2 2 S DSON FL Frequency Compensation Similarly, the upper MOSFET begins conducting as soon as it begins turning on. Assuming the inductor current is in the The load-line regulated converter behaves in a similar positive domain, the upper MOSFET sees approximately the manner to a peak-current mode controller because the two input voltage applied across its drain and source terminals, poles at the output filter LC resonant frequency split with the while it turns on and starts conducting the inductor current. introduction of current information into the control loop. The This transition occurs over a time t2, and the approximate final location of these poles is determined by the system the power loss is PUMOS,2. function, the gain of the current signal, and the value of the I I t  compensation components, R2 and C2. P V --O-----U----T--–--L----,-P----P----2--f (EQ. 13) UMOS,2 IN 2 2 2 S The solution to the system equations can be fairly complicated. Fortunately, there is a simple approximation A third component involves the lower MOSFET’s reverse- that comes very close to an optimal solution. Treating the recovery charge, QRR. Since the lower MOSFET’s body system as though it were a voltage mode regulator by diode conducts the full inductor current before it has fully compensating the LC poles and the ESR zero of the voltage switched to the upper MOSFET, the upper MOSFET has to mode approximation yields a solution that is always stable provide the charge required to turn off the lower MOSFET’s with very close to ideal transient performance. body diode. This charge is conducted through the upper MOSFET across VIN, the power dissipated as a result, C1 PUMOS,3 can be approximated using Equation 14: PUMOS,3 = VINQrrfS (EQ. 14) R2 C2 COMP 63 5 6 Lastly, the conduction loss part of the upper MOSFET’s L S power dissipation, PUMOS,4, can be calculated using FB I Equation 15: 2 2 + I  I PUMOS,4 = rDSON --O----2-U----T-- d+--P1----2P---- (EQ. 15) R1 VDROOP - In this case, of course, rDS(ON) is the ON-resistance of the VOUT upper MOSFET. FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563 The total power dissipated by the upper MOSFET at full load CIRCUIT can be approximated as the summation of these results. FN9126 Rev 8.00 Page 14 of 20 Jun 10, 2010

ISL6563 The feedback resistor, R1, has already been chosen as fast transient load during the short interval of time required outlined in “Load Line Regulation Resistor” on page14. by the controller and power train to respond. Because it has Select a target bandwidth for the compensated system, f0. a low bandwidth compared to the switching frequency, the The target bandwidth must be large enough to ensure output filter limits the system transient response leaving the adequate transient performance, but smaller than 1/3 of the output capacitor bank to supply the load current or sink the per-channel switching frequency (75kHz in this case). The inductor currents, all while the current in the output inductors values of the compensation components depend on the increases or decreases to meet the load demand. relationships of f0 to the output filter, LC, double pole In high-speed converters, the output capacitor bank is frequency and the ESR zero frequency of the bulk output amongst the costlier (and often the physically largest) parts capacitor bank. For each of the three cases defined in the of the circuit. Output filter design begins with consideration following, there is a separate set of equations for the of the critical load parameters: maximum size of the load compensation components. step, I, the load-current slew rate, di/dt, and the maximum Case 1: -----------1------------f allowable output voltage deviation under transient loading, 0 2 LC VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). 2f V  LC R = R --------------0------------P----P------------------- (EQ. 18) 2 1 0.66V At the beginning of the load transient, the output capacitors IN supply all of the transient current. The output voltage will 0.66V C = --------------------------------I--N-------------- initially deviate by an amount approximated by the voltage 2 2V R f PP FB 0 drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load 1 1 Case 2: 2----------------L----C---f02------------C---------E----S-----R--- current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output- V 22f2LC voltage deviation is less than the allowable maximum. PP 0 R2 = R1--------------0---.--6---6--------V----------------------- (EQ. 19) Neglecting the contribution of inductor current and regulator IN response, the output voltage initially deviates according to C = ----------------------0---.--6----6-------V-----I-N------------------------- Equation 21: 2 2 2 di 2 f0VPPR1 LC VESLd-----t+ESRI (EQ. 21) Case 3: f ----------------1----------------- The filter capacitor must have sufficiently low ESL and ESR 0 2CESR so that V < VMAX. 2f V L R2 = R10----.--6---6-------0-V----------P----EP-----S----R--- (EQ. 20) Most capacitor solutions rely on a mixture of high-frequency IN capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited 0.66V ESR C C = ---------------------I--N--------------------------------- high-frequency performance. Minimizing the ESL of the 2 2V R f  L PP 1 0 high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the In the previous equations, L is the per-channel filter bulk capacitors allows them to supply the increased current inductance divided by the number of active channels, C is with less output voltage deviation. the total bulk output capacitance, ESR is the equivalent series resistance of the bulk output filter capacitance, and The ESR of the bulk capacitors is also responsible for the VPP is the peak-to-peak sawtooth signal amplitude (see majority of the output-voltage ripple. As the bulk capacitors “Electrical Specifications” table on page4). sink and source the inductor ac ripple current, a voltage Once selected, the compensation values assure a stable develops across the bulk-capacitor ESR equal to IPP. Thus, once the output capacitors are selected and a maximum converter with reasonable transient performance. C1 is needed to cut down the high frequency error amplifier gain allowable ripple voltage, VPP(MAX), is determined from an analysis of the available output voltage budget, Equation 22 and reduce the noise the PWM comparator sees. Keep a can be used to determine a lower limit on the output position available for C1, and install a 10pF to 47pF in case inductance. jitter is noted. V –2V V Output Filter Design LESR-------fI--N--------V--------------OV----U-----T--------------O----U-----T-- (EQ. 22) S IN PPMAX The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the Since the capacitors are supplying a decreasing portion of square wave voltage at the phase nodes. Additionally, the the load current while the regulator recovers from the output capacitors must also provide the energy required by a transient, the capacitor voltage becomes slightly depleted. FN9126 Rev 8.00 Page 15 of 20 Jun 10, 2010

ISL6563 The output inductors must be capable of assuming the entire The power components should be placed first. Locate the load current before the output voltage decreases more than input capacitors close to the power switches. Minimize the VMAX. This places an upper limit on inductance. length of the connections between the input capacitors, CIN, 4CV and the power switches. Locate the output inductors and L---------------------O-----U----T--V –IESR (EQ. 23) 2 MAX output capacitors between the MOSFETs and the load. I Locate the high-frequency decoupling capacitors (ceramic) While the previous equation addresses the leading edge, as close as practicable to the decoupling target, making use Equation 24 gives the upper limit on L for cases where the of the shortest connection paths to any internal planes, such trailing edge of the current transient causes a greater output as vias to GND immediately next, or even onto the capacitor voltage deviation than the leading edge. solder pad. L2----.--5-------2C----VMAX–IESRVIN–VO (EQ. 24) The critical small components include the bypass capacitors I for VCC and PVCC. Locate the bypass capacitors, CBP, Normally, the trailing edge dictates the selection of L, since close to the device. It is especially important to locate the duty cycles are usually less than 50%. Nevertheless, both components associated with the feedback circuit close to inequalities should be evaluated, and L should be selected their respective controller pins, since they belong to a high- based on the lower of the two results. In all equations in this impedance circuit loop, sensitive to EMI pick-up. It is paragraph, L is the per-channel inductance and C is the total important to place the RISEN resistor close to the respective output bulk capacitance. terminal of the ISL6563. A multi-layer printed circuit board is recommended. Figure 9 Layout Considerations shows the connections of the critical components for one MOSFETs switch very fast and efficiently. The speed with output channel of the converter. Note that capacitors CxxIN which the current transitions from one device to another and CxxOUT could each represent numerous physical causes voltage spikes across the interconnecting capacitors. Dedicate one solid layer, usually the one impedances and parasitic circuit elements. These voltage underneath the component side of the board, for a ground spikes can degrade efficiency, radiate noise into the circuit plane and make all critical component ground connections and lead to device overvoltage stress. Careful component with vias to this layer. Dedicate another solid layer as a power layout and printed circuit design minimizes the voltage plane and break this plane into smaller islands of common spikes in the converter. Consider, as an example, the turnoff voltage levels. Keep the metal runs from the PHASE terminal transition of the upper PWM MOSFET. Prior to turnoff, the to inductor LOUT short. The power plane should support the upper MOSFET was carrying channel current. During the input power and output power nodes. Use copper filled turnoff, current stops flowing in the upper MOSFET and is polygons on the top and bottom circuit layers for the phase picked up by the lower MOSFET. Any inductance in the nodes. Use the remaining printed circuit layers for small signal switched current path generates a large voltage spike during wiring. The wiring traces from the IC to the MOSFETs’ gates the switching interval. Careful component selection, tight and sources should be sized to carry at least one ampere of layout of the critical components, and short, wide circuit current (0.02” to 0.05”). traces minimize the magnitude of voltage spikes. Component Selection Guidelines There are two sets of critical components in a DC-DC converter using an ISL6563 controller. The power Output Capacitor Selection components are the most critical because they switch large The output capacitor is selected to meet both the dynamic amounts of energy. Next are small signal components that load requirements and the voltage ripple requirements. The connect to sensitive nodes or supply critical bypassing load transient a microprocessor impresses is characterized current and signal coupling. by high slew rate (di/dt) current demands. In general, multiple high quality capacitors of different size and dielectric Note that as the ISL6563 does not allow external adjustment are paralleled to meet the design constraints. of the channel-to-channel current balancing (current information is multiplexed across a single RISEN resistor), it Should the load be characterized by high slew rates, attention is important to have a symmetrical layout, preferably with the should be particularly paid to the selection and placement of controller equidistantly located from the two power trains it high-frequency decoupling capacitors (MLCCs, typically controls. Equally important are the gate drive lines (UGATE, multi-layer ceramic capacitors). High frequency capacitors LGATE, PHASE): since they drive the power train MOSFETs supply the initially transient current and slow the load using short, high current pulses, it is important to size them rate-of-change seen by the bulk capacitors. The bulk filter accordingly and reduce their overall impedance. Equidistant capacitor values are generally determined by the ESR placement of the controller to the two power trains also helps (effective series resistance) and capacitance requirements. keeping these traces equally long (equal impedances, resulting in similar driving of both sets of MOSFETs). FN9126 Rev 8.00 Page 16 of 20 Jun 10, 2010

ISL6563 High frequency decoupling capacitors should be placed as electrolytic capacitor’s ESR value is related to the case size close to the power pins of the load, or for that reason, to any with lower ESR available in larger case sizes. However, the decoupling target they are meant for, as physically possible. equivalent series inductance (ESL) of these capacitors Attention should be paid as not to add inductance in the increases with case size and can reduce the usefulness of the circuit board wiring that could cancel the usefulness of these capacitor to high slew-rate transient loading. Unfortunately, low inductance components. Consult with the manufacturer ESL is not a specified parameter. Consult the capacitor of the load on specific decoupling requirements. manufacturer and/or measure the capacitor’s impedance with frequency to help select a suitable component. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The Output Inductor Selection bulk capacitor’s ESR determines the output ripple voltage One of the parameters limiting the converter’s response to a and the initial voltage drop following a high slew-rate load transient is the time required to change the inductor transient’s edge. In most cases, multiple capacitors of small current. In a multiphase converter, small inductors reduce case size perform better than a single large case capacitor. the response time with less impact to the total output ripple Bulk capacitor choices include aluminum electrolytic, OS-Con, current (as compared to single-phase converters). Tantalum and even ceramic dielectrics. An aluminum +12VIN LIN +5VIN (CHFIN1) CBIN1 (CF2) (CF1) VCC PVCC BOOT1 DACSEL/VID12 CBOOT1 VID4 UGATE1 Q1 VID3 VID2 LOUT1 PHASE1 VID1 VID0 VRM10 Q2 LGATE1 RISEN ISEN BOOT2 VOUT SSEND R’OFS ENLL ISL6563 CBOOT2 OFS CBIN2 CBOUT (CHFOUT) ROFS UGATE2 Q3 (CHFIN2) PHASE2 COMP C2 C1 LOUT2 LGATE2 Q4 LOCATE NEAR LOAD; RR22 (MINIMIZE CONNECTION PATH) PGND FB R1 GND LOCATE NEAR SWITCHING TRANSISTORS; (MINIMIZE CONNECTION PATH) LOCATE CLOSE TO IC KEY (MINIMIZE CONNECTION PATH) HEAVY TRACE ON CIRCUIT PLANE LAYER ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 9. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN9126 Rev 8.00 Page 17 of 20 Jun 10, 2010

ISL6563 The output inductor of each power channel controls the ripple 0.3 current. The control IC is stable for channel ripple current (peak- to-peak) up to twice the average current. A single channel’s ripple ) O current is approximated using Equation25: /IS M V –V V R ILPP = -----I-F-N---S----W-------O---L-U----T-------V-O---I-U-N---T--- (EQ. 25) ENT (I 0.2 R R The current from multiple channels tend to cancel each other U C and reduce the total ripple current. The total output ripple R O current can be determined using the curve in Figure 10; it CIT provides the total ripple current as a function of duty cycle and PA 0.1 A number of active channels, normalized to the parameter C IL,PP = 0 T KNORM at zero duty cycle. PU IL,PP = 0.5 x IO K = ---V----O----U-----T---- (EQ. 26) IN IL,PP = 0.75 x IO NORM LFSW 0 0 0.1 0.2 0.3 0.4 0.5 where L is the channel inductor value. DUTY CYCLE (VO /VIN) Find the intersection of the active channel curve and duty cycle FIGURE 11. NORMALIZED INPUT RMS CURRENT vs DUTY CYCLE FOR A 2-PHASE CONVERTER for your particular application. The resulting ripple current multiplier from the y-axis is then multiplied by the normalization As the input capacitors are responsible for sourcing the AC factor, KNORM, to determine the total output ripple current for component of the input current flowing into the upper MOSFETs, the given application. their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs. Figure I = K K (EQ. 27) TOTAL NORM CM 11 can be used to determine the input capacitor RMS current 1.0 function of duty cycle, maximum sustained output current (IO), and the ratio of the peak-to-peak inductor current (IL,PP) to the CM 0.8 maximum sustained load current, IO. Figure 11 can also be used K as a reference demonstrating the dramatic reduction in input R, E capacitor RMS current in a 2-phase DC/DC converter, as LI 0.6 P compared to a single-phase regulator. TI L U M Use a mix of input bypass capacitors to control the input T 0.4 N voltage ripple. Use ceramic capacitance for the high E R frequency decoupling and bulk capacitors to supply the RMS R U 0.2 C current. Minimize the connection path inductance of the high frequency decoupling ceramic capacitors (from drain of upper 0 MOSFET to source of lower MOSFET). 0 0.1 0.2 0.3 0.4 0.5 DUTY CYCLE (VO/VIN) For bulk capacitance, several electrolytic or high-capacity MLC FIGURE 10. RIPPLE CURRENT vs DUTY CYCLE capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised Input Capacitor Selection with regard to the capacitor surge current rating. These capacitors The important parameters for the bulk input capacitors are must be capable of handling the surge-current at power-up. the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. The input RMS current required for a multiphase converter can be approximated with the aid of Figure 11. FN9126 Rev 8.00 Page 18 of 20 Jun 10, 2010

ISL6563 © Copyright Intersil Americas LLC 2003-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9126 Rev 8.00 Page 19 of 20 Jun 10, 2010

ISL6563 Package Outline Drawing L24.4x4B 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 4/10 4X 2.5 4.00 A 20X 0.50 B PIN #1 CORNER 19 24 (C 0 . 25) PIN 1 INDEX AREA 18 1 00 2 . 34 ± 0 . 15 4. 13 (4X) 0.15 12 7 TOP VIEW 24X 0 . 4 ± 0 . 1 0.10 M C A B 24X 0 . 23 +- 00 .. 0057 4 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 C BASE PLANE ( 3 . 8 TYP ) SEATING PLANE SIDE VIEW 0.08 C ( 2 . 34 ) ( 20X 0 . 5 ) C 0 . 2 REF 5 ( 24X 0 . 25 ) 0 . 00 MIN. ( 24X 0 . 6 ) 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. FN9126 Rev 8.00 Page 20 of 20 Jun 10, 2010