DATASHEET ISL65426 FN6340 6A Dual Synchronous Buck Regulator with Integrated MOSFETs Rev 3.00 March 25, 2008 The ISL65426 is a high efficiency dual output monolithic Features synchronous buck converter operating over an input • High Efficiency: Up to 95% voltage range of 3V to 5.5V. This single chip power solution provides two output voltages, which are selectable or • Fixed Frequency: 1MHz externally adjustable from 1V to 80% of the supply voltage • Operates From 3V to 5.5V Supply while delivering up to 6A of total output current. The two • ±1% Reference PWMs are synchronized 180° out-of-phase, reducing the RMS input current and ripple voltage. • Flexible Output Voltage Options - Programmable 2-Bit VID Input The ISL65426 switches at a fixed frequency of 1MHz and - Adjustable Output From 1V to 4.0V utilizes current-mode control with integrated compensation to minimize the size and number of external components • User-Partitioned Power Blocks and provide excellent transient response. The internal • Ultra-Compact DC/DC Converter Design synchronous power switches are optimized for good • PWMs Synchronized 180° Out-of-Phase thermal performance and high efficiency. • Independent Enable Inputs and System Enable A unique power block architecture allows partitioning of six • Stable All Ceramic Solutions 1A blocks to support one of four configuration options. One master power block is associated with each synchronous • Excellent Dynamic Response converter channel. Four floating slave power blocks allow • Independent Output Digital Soft-Start the user to assign them to either channel. Proper external • Power-Good Output Voltage Monitor configuration of the power blocks is verified internally prior to soft-start initialization. • Thermal-Overload Protection Independent enable inputs allow for synchronization or • Overcurrent and Undervoltage Protection sequencing soft-start intervals of the two converter • Pb-Free (RoHS Compliant) channels. A third enable input allows additional sequencing for multi-input bias supply designs. Individual power-good Applications indicators (PG1, PG2) signal when output voltage is within • FPGA, CPLD, DSP, and CPU Core and I/O Voltages the regulation window. - Xilinx Spartan IIITM, Virtex IITM, Virtex II ProTM, The ISL65426 integrates protection for both synchronous Virtex 4TM buck regulator channels. The fault conditions include - Altera StratixTM, Stratix IITM, CycloneTM, Cyclone IITM overcurrent, undervoltage, and IC thermal monitor. - Actel FusionTM, LatticeSCTM, LatticeECTM High integration contained in a thin Quad Flat No-lead • Low-Voltage, High-Density Distributed Power Systems (QFN) package makes the ISL65426 an ideal choice to • Point-of-Load Regulation power many of today’s small form factor applications. A • Distributed Power Systems single chip solution for large scale digital ICs, like field programmable gate arrays (FPGA), requiring separate core • Set-Top Boxes and I/O voltages. Ordering Information PART TEMP. NUMBER PART RANGE PACKAGE PKG. (Note) MARKING (°C) (Pb-free) DWG. # ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10 QFN L50.5x10 ISL65426IRZA* ISL65426 IRZ -40 to +85 50 Ld 5x10 QFN L50.5x10 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6340 Rev 3.00 Page 1 of 22 March 25, 2008

ISL65426 Pinout ISL65426 (50 LD QFN) TOP VIEW 2 FB1 EN1 EN2 EN ISET PG1 PG2 FB2 50 49 48 47 46 45 44 43 PGND 1 42 PGND PGND 2 41 PGND PGND 3 40 PGND PGND 4 39 PGND LX1 5 38 LX6 LX1 6 37 LX6 PVIN1 7 36 PVIN6 PVIN2 8 35 PVIN5 LX2 9 PGND 34 LX5 PGND 10 33 PGND PGND 11 32 PGND LX3 12 31 LX4 PVIN3 13 30 PVIN4 VCC 14 29 PGND VCC 15 28 PGND VCC 16 27 GND PGND 17 26 GND 18 19 20 21 22 23 24 25 D 1 2 1 1 2 D D N T T T T T N N PG 1SE 1SE ISE 2SE 2SE PG PG V V V V FN6340 Rev 3.00 Page 2 of 22 March 25, 2008

ISL65426 Typical Application Schematics SINGLE INPUT SUPPLY 3.3V 1 2 G G P P 3.3V 1 2 N N N E E E PVIN1 PVIN6 3.3V 3.3V PVIN2 PVIN5 C1 C4 PVIN4 PVIN3 LX1 LX6 L1 L2 1.2V LX2 LX5 2.5V 3A 3A C2 ISL65426 C3 LX3 LX4 FB1 FB2 VCC 3.3V C5 GND PGND 1 1 2 2 2 1 T T T T T T E E E E E E S S S S S S 1 I I 2 1 2 V V V V 3.3V FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION FN6340 Rev 3.00 Page 3 of 22 March 25, 2008

ISL65426 Typical Application Schematics (Continued) DUAL INPUT SUPPLY 3.3V 1 2 G G P P 5.0V 1 2 N N N E E E PVIN1 PVIN6 PVIN2 3.3V 5.0V PVIN3 PVIN5 C4 C1 PVIN4 LX6 L2 LX5 1.8V 2A ISL65426 C3 LX1 LX2 FB2 L1 1.5V LX3 4A C2 LX4 VCC 5.0V C5 FB1 GND PGND 1 2 1 2 1 2 T T T T T T E E E E E E S S S S S S I 1 2 I 1 2 V V V V 3.3V FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION FN6340 Rev 3.00 Page 4 of 22 March 25, 2008

ISL65426 Typical Application Schematics (Continued) 5.0V 1 2 G G P P 5.0V 1 2 N N N E E E PVIN1 PVIN2 PVIN5 5.0V 5.0V PVIN3 C4 C2 C1 PVIN4 PVIN6 L2 LX5 3.3V 1A LX1 ISL65426 C3 LX2 LX3 FB2 L1 LX4 C2 LX6 VCC 5.0V 2.5V C5 5A FB1 GND PGND 2 1 2 1 1 2 T T T T T T E E E E E E S S S S S S I 2 2 I 1 1 V V V V 5.0V FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION FN6340 Rev 3.00 Page 5 of 22 March 25, 2008

ISL65426 Functional Block Diagram EN2 EN VCC GND EN1 POWER-ON RESET (POR) PVINx PVINx CURRENT SENSE SOFT-START SLOPE COMPENSATION PWM EA GM CONTROL GATE LXx FB1 DRIVE LOGIC V1SET1 OUTPUT COMPENSATION VOLTAGE V1SET2 CONFIG EPAD GND UV PGOOD1 POWER-GOOD POWER ISET1 SOFT DEVICE START CONFIG ISET2 PWM THERMAL REFERENCE MONITOR 0.60V PVINx POR CURRENT SENSE SOFT-START SLOPE COMPENSATION PWM EA GM CONTROL GATE LXx FB2 DRIVE LOGIC V2SET1 OUTPUT VOLTAGE COMPENSATION V2SET2 CONFIG EPAD GND OV UV POWER-GOOD PGOOD2 FN6340 Rev 3.00 Page 6 of 22 March 25, 2008

ISL65426 Absolute Maximum Ratings Thermal Information VCC, PVINx, LXx. . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +6V Thermal Resistance JA (°C/W) JC (°C/W) FBx, ENx, VxSETx, ISETx, PGOODx . . . . . . . -0.3V to VCC + 0.3V 50 Ld QFN Package (Notes 1, 2). . . . . 23 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C Recommended Operating Input Range Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Ambient Temperature Range (ISL65426HRZ). . . . .-10°C to +100°C VCC, PVINx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to +5.5V Ambient Temperature Range (ISL65426IRZA) . . . . .-40°C to +85°C Operating Junction Temperature Range . . . . . . . . .-10°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details. Electrical Specifications Recommended operating conditions, unless otherwise noted. VCC = PVIN = 5.0V, TA = -10°C to +100°C for ISL65426HRZ and TA = -40°C to +85°C for ISL65426IRZA. (Note 5) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Quiescent Supply Current EN1 = EN2 = EN = VCC = 5V, IOUT1 = IOUT2 = 0mA 30 mA Shutdown Supply Current EN1 = EN2 = EN = GND, VCC = PVIN = 5.5V 5.4 7 mA EN1 = EN2 = EN = GND, VCC = PVIN = 3.3V 2.8 3.2 mA PHASE CONFIGURATION LX Pull-Down LX1, LX3, LX4, LX5, LX6 Only - Configuration Only 1 mA LX Output Leakage Low Level, Single LX Output -5 5 µA High Level, Single LX Output -5 5 µA Minimum Controllable ON-time (Note 3) 125 ns OUTPUT VOLTAGE TOLERANCE Reference Voltage Tolerance TJ = -40°C to +100°C 0.594 0.6 0.606 V TJ = 100°C to +125°C 0.591 0.6 0.609 V Programmed Output Voltage Tolerance TJ = -40°C to +125°C; No Load -2 +2 % TJ = -40°C to +125°C (Note 4); Full Load ±5 % OSCILLATOR Accuracy 0.8 1 1.2 MHz Maximum LX Pulse Width 950 ns Minimum LX Pulse Width 50 ns OUTPUT VOLTAGE SELECTION VxSETx Input High Threshold 0.4 1.2 1.5 V VxSETx Pull-down 7 10 15 µA POWER BLOCKS ISETx Input High Threshold 0.4 1.2 1.5 V ISETx Pull-up 7 10 15 µA Output Current Per Block; VCC = PVIN = 5.0V; VOUT = 1.8V (Note 3) 1 A Per Block; VCC = PVIN = 3V; VOUT = 1.2V (Note 3) 0.7 A Peak Output Current Limit Per Block 2.0 A FN6340 Rev 3.00 Page 7 of 22 March 25, 2008

ISL65426 Electrical Specifications Recommended operating conditions, unless otherwise noted. VCC = PVIN = 5.0V, TA = -10°C to +100°C for ISL65426HRZ and TA = -40°C to +85°C for ISL65426IRZA. (Note 5) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Upper Device rDS(ON) 0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V 60 100 140 m Lower Device rDS(ON) 0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V 30 55 85 m Efficiency 0.5A Per Block, VCC = PVIN = 3.3V, VOUT = 1.1V 90 % 0.5A Per Block, VCC = PVIN = 5V, VOUT = 2.5V 95 % POWER-ON RESET AND ENABLE PINS VCC POR Threshold VCC Rising; No Load 2.15 2.25 2.35 V VCC Falling; No Load 2.05 2.15 2.25 V PVIN POR Threshold PVIN Rising; No Load 1.9 2.05 2.15 V PVIN Falling; No Load 1.75 1.90 2.00 V PVIN Bias Output Voltage Enable Threshold VOUT2 = 3.3V; VCC = PVIN 4.1 4.3 4.5 V VOUT2 = 2.5V; VCC = PVIN 2.8 2.9 3.0 V EN1/EN2 Threshold Rising Threshold; VCC = 5V 1.0 1.2 1.45 V Hysteresis 280 mV Rising Threshold; VCC = 3.3V 0.75 0.98 1.20 V Hysteresis 200 mV Rising Threshold; VCC = 3V 0.55 0.82 1.05 V Hysteresis 185 mV EN1/EN2 Pull-up 7 10 15 µA EN Threshold 0.57 0.6 0.63 V EN Sink Current EN = GND 7 11 15 µA Soft-Start Time 4 ms POWER-GOOD SIGNAL Rising Threshold As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V 110 115 120 % Rising Hysteresis As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V 5 7 9 % Falling Threshold As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V 80 85 90 % Falling Hysteresis As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V 4 7 9 % Power-Good Drive VCC = 5V; PG1 = PG2 = 0.4V 1 mA Power-Good Leakage 1 µA PROTECTION FEATURES Undervoltage Monitor Undervoltage Trip Threshold As % of VREF 70 75 80 % Undervoltage Recovery Threshold As % of VREF 82 89 95 % THERMAL MONITOR Thermal Shutdown Temperature (Note 3) 150 °C NOTES: 3. Limits should be considered typical and are not production tested. 4. Accounts for output variations due to jitter, which is a function of the input voltage and output loading. 5. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. FN6340 Rev 3.00 Page 8 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. 100 100 90 90 80 80 Y (%) 6700 3.3VIN 5.5VIN 2.5VIN Y (%) 6700 3.3VIN 5.5VIN 2.5VIN C C EN 50 EN 50 FICI 40 FICI 40 F F E 30 E 30 20 20 10 10 0 0 0.1 1.0 2.0 3.0 4.0 0.1 1.0 2.0 3.0 4.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 4. VOUT1 = 1.2V EFFICIENCY vs LOAD FIGURE 5. VOUT1 = 1.5V EFFICIENCY vs LOAD 100 100 90 90 80 80 2.5VIN Y (%) 6700 5.5VIN Y (%) 6700 2.5VIN C C EN 50 3.3VIN EN 50 FICI 40 FICI 40 5.5VIN F F E 30 E 30 3.3VIN 20 20 10 10 0 0 0.1 1.0 2.0 3.0 4.0 0.1 0.5 1.0 1.5 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 6. VOUT1 = 1.8V EFFICIENCY vs LOAD FIGURE 7. VOUT2 = 1.8V EFFICIENCY vs LOAD 100 100 90 90 80 80 %) 70 4VIN %) 70 4.5VIN Y ( 60 Y ( 60 ENC 50 5.5VIN ENC 50 5.5VIN EFFICI 3400 3VIN EFFICI 3400 5VIN 20 20 10 10 0 0 0.1 0.5 1.0 1.5 2.0 0.1 0.5 1.0 1.5 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 8. VOUT2 = 2.5V EFFICIENCY VS LOAD FIGURE 9. VOUT2 = 3.3V EFFICIENCY vs LOAD FN6340 Rev 3.00 Page 9 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) 1.235 1.235 1.225 1.225 V) V) 2A LOAD GE (1.215 5.5VIN GE ( 1.215 NO LOAD TA1.205 TA 1.205 L L O O T V1.195 T V 1.195 U U P P OUT1.185 2.5VIN 3.3VIN OUT 1.185 4A LOAD 1.175 1.175 1.165 1.165 0.1 1.0 2.0 3.0 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 10. VOUT1 = 1.2V REGULATION vs LOAD FIGURE 11. VOUT1 = 1.2V REGULATION vs VIN 1.545 1.545 1.535 1.535 V) 1.525 1.525 AGE ( 1.515 5.5VIN GE (V) 1.515 NO LOAD 2A LOAD OLT 1.505 LTA 1.505 V O T 1.495 V 1.495 OUTPU 11..447855 2.5VIN OUTPUT 11..447855 1.465 3.3VIN 1.465 4A LOAD 1.455 1.455 0.1 1.0 2.0 3.0 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 12. VOUT1 = 1.5V REGULATION vs LOAD FIGURE 13. VOUT1 = 1.5V REGULATION vs VIN 1.845 1.845 1.825 1.825 V) V) 2A LOAD E ( 5.5VIN E ( OLTAG 1.805 OLTAG 1.805 NO LOAD V V UT 1.785 UT 1.785 UTP 2.5VIN UTP O 1.765 3.3VIN O 1.765 4A LOAD 1.745 1.745 0.1 1.0 2.0 3.0 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 14. VOUT1 = 1.8V REGULATION vs LOAD FIGURE 15. VOUT1 = 1.8V REGULATION vs VIN FN6340 Rev 3.00 Page 10 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) 1.845 1.845 GE (V)1.825 E (V) 1.825 1A LOAD A G OLT1.805 2.5VIN LTA 1.805 NO LOAD V O T V U1.785 T 1.785 P U T P U T O1.765 5.5VIN 3.3VIN OU 1.765 2A LOAD 1.745 1.745 0.1 0.5 1.0 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 16. VOUT2 = 1.8V REGULATION vs LOAD FIGURE 17. VOUT2 = 1.8V REGULATION vs VIN 2.565 2.565 2.545 2.545 OLTAGE (V)22..550255 4VIN 3.3VIN OLTAGE (V) 22..550255 NO LOAD 1A LOAD UT V2.485 UT V 2.485 OUTP2.465 OUTP 2.465 2A LOAD 5.5VIN 2.445 2.445 2.425 2.425 0.1 0.5 1.0 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 18. VOUT2 = 2.5V REGULATION vs LOAD FIGURE 19. VOUT2 = 2.5V REGULATION vs VIN 3.40 3.40 3.38 3.38 3.36 3.36 GE (V) 3.34 E (V) 3.34 TA 3.32 5.5VIN AG 3.32 VOL 3.30 4.5VIN OLT 3.30 NO LOAD UT 3.28 T V 3.28 P U UT 3.26 TP 3.26 O U 3.24 5VIN O 3.24 2A LOAD 1A LOAD 3.22 3.22 3.20 3.20 0.1 0.5 1.0 1.5 2.0 4.0 4.25 4.5 4.75 5.0 5.25 5.5 OUTPUT LOAD (A) INPUT VOLTAGE (V) FIGURE 20. VOUT2 = 3.3V REGULATION vs LOAD FIGURE 21. VOUT2 = 3.3V REGULATION vs VIN FN6340 Rev 3.00 Page 11 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) EN1 5V/DIV EN1 5V/DIV VOUT1 500mV/DIV VOUT1 500mV/DIV IL1 1A/DIV IL1 1A/DIV PG1 5V/DIV PG1 5V/DIV FIGURE 22. START-UP VOUT1 = 1.2V (NO LOAD) FIGURE 23. START-UP VOUT1 = 1.2V (UNDER PRE-BIASED) EN1 5V/DIV EN1 5V/DIV VOUT1 500mV/DIV VOUT1 500mV/DIV IL1 2A/DIV IL1 1A/DIV PG1 5V/DIV POK1 5V/DIV FIGURE 24. START-UP VOUT1 = 1.2V (FULL LOAD) FIGURE 25. SHUTDOWN VOUT1 = 1.2V EN2 5V/DIV EN2 5V/DIV VOUT2 1V/DIV VOUT2 1V/DIV IL2 1A/DIV IL2 1A/DIV PG2 5V/DIV PG2 5V/DIV FIGURE 26. START-UP VOUT2 = 3.3V (NO LOAD) FIGURE 27. START-UP VOUT2 = 3.3V (UNDER PRE-BIASED) FN6340 Rev 3.00 Page 12 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) EN2 5V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 1V/DIV IOUT1 1A/DIV IL2 1A/DIV VOUT2 RIPPLE 20mV/DIV PG2 5V/DIV FIGURE 28. START-UP VOUT2 = 3.3V (FULL-LOAD) FIGURE 29. VOUT1 = 1.2V LOAD TRANSIENT VOUT1 RIPPLE 20mV/DIV LX1 5V/DIV IOUT1 500mA/DIV VOUT1 500mV/DIV VOUT2 RIPPLE 50mV/DIV IL1 5A/DIV PG1 5V/DIV FIGURE 30. VOUT1 = 1.2V LOAD TRANSIENT FIGURE 31. VOUT1 = 1.2V OUTPUT OVERCURRENT LX1 5V/DIV LX2 5V/DIV VOUT1 500mV/DIV VOUT2 1V/DIV IL2 5A/DIV IL1 5A/DIV PG1 5V/DIV PG2 5V/DIV FIGURE 32. VOUT1 = 1.2V OUTPUT OVERCURRENT FIGURE 33. VOUT2 = 3.3V OUTPUT OVERCURRENT RECOVERY FN6340 Rev 3.00 Page 13 of 22 March 25, 2008

ISL65426 Typical Performance Curves Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) LX2 5V/DIV VOUT2 1V/DIV IL2 5A/DIV PG2 5V/DIV FIGURE 34. VOUT2 = 3.3V OUTPUT OVERCURRENT RECOVERY Pin Descriptions 2 FB1 EN1 EN2 EN ISET PG1 PG2 FB2 VCC 50 49 48 47 46 45 44 43 The bias supply input for the small signal circuitry. Connect this PGND 1 42 PGND pin to the highest supply voltage available if two or more PGND 2 41 PGND options are available. Locally filter this pin using a low ESL PGND 3 40 PGND ceramic capacitor of 1µF or larger, and a 10 resistor. PGND 4 39 PGND PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6 LX1 5 38 LX6 These pins are the power supply pins for the corresponding LX1 6 37 LX6 PWM power blocks. Associated power blocks must all tie to the PVIN1 7 PGND 36 PVIN6 same power supply. The power supply must fall in the range of PVIN2 8 35 PVIN5 3V to 5.5V. LX2 9 34 LX5 GND PGND 10 33 PGND Signal ground. All small signal components connect to this PGND 11 32 PGND ground, which in turn connects to PGND at one point. LX3 12 31 LX4 PGND PVIN3 13 30 PVIN4 VCC 14 29 PGND Power ground for the PWM power blocks and thermal relief for the package. The exposed pad must be connected to PGND VCC 15 28 PGND and soldered to the PCB. Connect these pins closely to the VCC 16 27 GND negative terminal of input and output capacitors. PGND 17 26 GND FB1, FB2 18 19 20 21 22 23 24 25 D 1 2 1 1 2 D D Voltage feedback input. Depending on the voltage selection pin N T T T T T N N PG 1SE 1SE ISE 2SE 2SE PG PG settings, connect an optional resistor divider between VOUT V V V V and GND for selection of a variable output voltage. LX1, LX2, LX3, LX4, LX5, LX6 Switch node connection to inductor. This pin connects to the internal synchronous power MOSFET switches. The average voltage of this node is equal to the regulator output voltage. FN6340 Rev 3.00 Page 14 of 22 March 25, 2008

ISL65426 EN outlined in Table 1. The controller detects the programmed configuration based on the state of logic signals at pins ISET1 System enable for voltage monitoring with programmable and ISET2. The controller checks the power block hysteresis. This pin has a POR rising threshold of 0.6V. This configuration versus the programmed configuration before the enable is intended for applications where two or more input either converter can soft-start. power supplies are used and bias rise time is an issue. Each power block has a separate power supply connection pin, EN1, EN2 PVINx, and common channels must join these inputs to one These pins are threshold-sensitive enable inputs for the input power supply. Common synchronous power switch individual PWM converters. These pins have low current connection points for each channel must be tied together and (10µA) internal pull-ups to VCC. This pin disables the to an external inductor. See the “Typical Application respective converter until pulled above a 1V rising threshold. Schematics” for pin connection guidance. ISET1, ISET2 TABLE 1. POWER BLOCK CONFIGURATION Power block configuration inputs. Select the proper state for CHANNEL 1 CHANNEL 2 each pin according to Table 1. ISET1 ISET2 IOUT1 CONNECTIONS IOUT2 CONNECTIONS V1SET1, V1SET2, V2SET1, V2SET2 1 1 3A LX1,LX2,LX3 3A LX4,LX5,LX6 Output voltage configuration inputs. Select the proper state of 1 0 4A LX1,LX2,LX3,LX4 2A LX5,LX6 each pin per the “Electrical Specifications” table. 0 1 5A LX1,LX2,LX3, 1A LX5 PG1, PG2 LX4,LX6 Power-good output. Open drain logic output that is pulled to 0 0 2A LX1,LX2 4A LX3,LX4,LX5,LX6 ground when the output voltage is outside regulation limits. Invalid LX Configurations: SS Prevented Functional Description X X 1A LX2 5A LX1,LX3,LX4, LX5,LX6 The ISL65426 is a monolithic, constant frequency, current- mode dual output buck converter controller with user Each power block has a scaled pilot device providing current configurable power blocks. Designed to provide a total DC/DC feedback. The configuration pin settling determines how the solution for FPGAs, CPLDs, core processors, and ASICs. controller handles separation and summing of the individual current feedback signals. PVIN1 PVIN6 POWER BLOCK 1 POWER BLOCK 6 Main Control Loop LX1 LX6 The ISL65426 is a monolithic, constant frequency, currentmode step-down DC/DC converter. During normal PVIN2 PVIN5 POWER BLOCK 2 POWER BLOCK 5 operation, the internal top power switch is turned on at the LX2 LX5 beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top PVIN3 PVIN4 power MOSFET. The bottom power MOSFET turns on and the POWER BLOCK 3 POWER BLOCK 4 inductor current ramps down for the rest of the cycle. LX3 LX4 The current comparator compares the output current at the ripple current peak to a current pilot. The error amplifier MASTER POWER BLOCK monitors VOUT and compares it with the internal voltage reference. The error amplifier’s output voltage drives a FLOATING POWER BLOCK proportional current to the pilot. If VOUT is low the pilot’s FIGURE 35. POWER BLOCK DIAGRAM current level is increased and the trip off current level of the output is increased. The increased current works to raise the Power Blocks VOUT level into agreement with the voltage reference. A unique power block architecture allows partitioning of six 1A capable modules to support one of four power block Output Voltage Programming configuration options. The block diagram in Figure 3 provides a The feedback voltage applied to the inverting input of the error top level view of the power block layout. One master power amplifier is scaled internally relative to the 0.6V internal block is assigned to each converter output channel. Power reference voltage based on the state of logic signals at pins Block 2 is allotted to converter Channel 1 and Power Block 5 to V1SET1, V1SET2, V2SET1 and V2SET2. The output voltage Channel 2. The master power blocks must not be tied together configuration logic decodes the 2-bit voltage identification or the controller will not soft-start. The remaining four floating codes into one of the discrete voltages shown in Table 2. When power blocks can be partitioned in one of four valid states each pin is pulled to GND by an internal 10µA pull-down, this FN6340 Rev 3.00 Page 15 of 22 March 25, 2008

ISL65426 default condition programs the output voltage to the lowest channel changes state from low to high indicating proper level. The pull-down prevents situations where a pin could be operation initialization. left floating for example (cold solder joint) from causing the Power-On Reset output voltage to rise above the programmed level and damage a sensitive load device. The POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at vital power supply TABLE 2. OUTPUT VOLTAGE PROGRAMMING input pins. These include the VCC and PVINx pins. VOUT1 V1SET1 V1SET2 VOUT2 V2SET1 V2SET2 The VCC pins have a variable POR threshold based on the 1.8V 1 1 3.3V 1 1 output voltage configuration pin configuration of VOUT2. If the configuration pins are set for 2.5V, the VCC POR rising 1.5V 0 1 2.5V 0 1 threshold is typically 2.9V. The 3.3V configuration increases 1.2V 1 0 1.8V 1 0 the VCC POR level to 4.3V. This variable rising threshold guarantees that the controller can properly switch the internal power blocks at the assigned output voltage levels. ISL65426 EXTERNAL CONDITIONS The PVINx pins have a set POR rising threshold for all output LX LOUT V1.O4UVT vboelltoawg eth ciso nthfirgeusrhaotilodn (sa. sW dheiflien ethde i nv othltea g“eE loenc ttrhiceasl e pins are COUT Specifications” table), the controller inhibits switching of the internal power MOSFETs. R1 13.3k Built-in hysteresis between the rising and falling thresholds FB insures that once enabled, the controller will not inadvertently R2 toggle turn off unless the bias voltage drops substantially. 10k While these pins are below the POR rising threshold, the synchronous power switch LX pins are held in a high- FIGURE 36. EXTERNAL OUTPUT VOLTAGE SELECTION impedance state. For designers requiring an output voltage level outside those If additional POR control is required, a system enable input can shown in Table 2, the ISL65426 allows user programming with be used to govern initialization, as described in the following an external resistor divider (see Figure 36). First, both channel section. selection pins associated with that output channel must be tied to GND to set the internal reference to 0.6V. Next, the output Enable and Disable voltage is set by an external resistive divider according to If the POR input requirements are met, the ISL65426 remains Equation 1. R2 is selected arbitrarily, but 5k or 10k is usually in shutdown until the voltage at the enable inputs rise above a good starting point. The designer can configure the output their enable thresholds. Independent enable inputs, EN1 and voltage from 1V to 4V from a 5V power supply. Lower input EN2, allow initialization of either buck converter channel supply voltages reduce the maximum programmable output separately, sequenced, or simultaneously. Both pins feature a voltage to 80% of the input voltage level. 10µA pull-up, which will initialize both sides once the voltage at V –0.6V their respective pins exceeds the rising enable threshold, as R1 = R2-----O----U---0-T--.--6---V-------------- (EQ. 1) defined in the “Electrical Specifications” table. Switching Frequency Both converters are governed by the presence of a system enable, EN. When two separate input supplies are used for The controller features an internal oscillator running at a fixed each channel of power blocks or an external signal needs to frequency of 1MHz. The oscillator tolerance is +20% over input govern the power-up sequence, the system enable provides a bias and load range. start-up sequencing mechanism. Operation Initialization The system enable features an internal 11µA pull-down, which The ISL65426 initializes based on the state of three enable is only active when the voltage on the EN pin is below the inputs (EN, EN1, EN2) and power-on reset (POR) monitors on enable threshold. The current sink pulls the EN pin low. As VCC and PVINx inputs. Successful initialization of the VCC2 rises, the enable level is not set exclusively by the controller prompts a one time power block configuration check. resistor divider from VCC2. With the current sink active, the Verification of proper phase connections lead to a soft-start enable level is defined in Equation 2. R1 is the resistor EN to interval. The controller begins slowly ramping the output VCC2 and R2 is the resistor from EN to GND. voltages based on the enable input states. Once the 0.6V V = R  ------------+10A +0.6V (EQ. 2) commanded output voltage is within the proper window of ENABLE 1 R 2 operation, the power-good signal corresponding to the active FN6340 Rev 3.00 Page 16 of 22 March 25, 2008

ISL65426 Once the voltage at the EN pin reaches the enable threshold, power block has a pull-down active only during the configuration the 10µA current sink turns off. check to remove noise related false positive detections. With the part enabled and the current sink off, the disable level A successful configuration check initiates a soft-start interval is set by the resistor divider. The disable level is defined in 100µs after completion. Failing the configuration check, the Equation 3. controller will attempt a configuration check again 100µs after completing the first check cycle. The controller repeats the R +R V = 0.6V-----1--------------2-- (EQ. 3) configuration check cycle every 100µs until a valid DISABLE R 2 configuration is detected or the controller is powered down. The difference between the enable and disable levels provides Once successful, the configuration check is not implemented the user with configurable hysteresis to prevent premature again until VCC falls below the POR falling threshold. tripping. Re-enabling the controller after a successful configuration check will immediately initiate a soft-start interval. To enable the controller, the system enable must be high, and one or both of the channel enables must be high. The POR Soft-start Interval circuitry must be satisfied for both VCC and PVINx inputs. Once the controller is enabled and power block configuration is Once these conditions are met, the controller immediately successful, the digital soft-start function clamps the error initiates a power block configuration check. amplifier reference. The digital soft-start circuitry ramps the output voltage by stepping the reference up gradually over a ISL65426 EXTERNAL CONDITIONS fixed interval of 4ms. The controlled ramp of the output voltage reduces the in-rush current during startup. +VCC1 Power-good Signal VCC Each power-good pin (PG1, PG2) is an open-drain logic output that indicates when the converter output voltage is within regulation limits. The power-good pins pull low during +VCC2 shutdown and remain low when the controller is enabled. After SYSTEM ENABLE COMPARATOR R1 a successful converter channel soft-start, the power-good pin EN signal associated with that channel releases and the power- + R2 good pin voltage rises with an external pull-up resistor. The POR - power-good signal transitions low immediately upon the LOGIC 10µA 0.6V removal of individual channel or system enable. The power-good circuitry monitors both output voltage FB pins and compares them to the rising and falling limits shown in the “Electrical Specifications” table. If either channel’s feedback voltage exceeds the typical rising limit of 115% of the reference voltage, the power-good pin pulls low. The power-good pin FIGURE 37. SYSTEM ENABLE INPUT continues to pull low until the feedback voltage recovers down Power Block Configuration Check by a typical of 110% of the reference voltage. If either channel’s After VCC exceeds its POR rising threshold, the controller feedback voltage drops below a typical of 85% of the reference decodes ISET1 and ISET2 states into one of four valid power voltage, the power-good pin related to the offending channel(s) block configurations (see Table 1). These pins are not checked pulls low. The power-good pin continues to pull low until the again unless VCC falls below the POR falling threshold. The feedback voltage rises to within 90% of the reference voltage. valid configuration is saved for comparison with the LX slave The power-good pin then releases and signals the return of the connectivity result, which is determined during the output voltage within the power-good window. configuration check. Fault Monitoring and Protection Once the POR and enable circuitry is satisfied, the controller initiates a configuration check. The master power block of output The ISL65426 actively monitors output voltage and current to Channel 1 (Power Block 2) pulses high for 100ns. The detect fault conditions. Fault monitors trigger protective configuration check circuitry detects which power blocks share a measures to prevent damage to the controller and external common LX connection and compares this to the decoded valid load device. Individual power-good indicators provide options configuration. The master power block of output Channel 2 for linking to external system monitors. (Power Block 5) pulses, and again, the LX pins of the other non- Undervoltage Protection master blocks are monitored. The common LX connections are Separate hysteretic comparators monitor the feedback pin (FB) checked versus the decoded valid configuration. Each floating of each converter channel. The feedback voltage is compared FN6340 Rev 3.00 Page 17 of 22 March 25, 2008

ISL65426 to a set undervoltage (UV) threshold based on the output This hiccup mode continues indefinitely until both outputs soft- voltage selected. Once one of the comparators trip indicating a start successfully. valid UV condition, a 4-bit UV counter increments. If both Note: It is recommended to add a Schottky diode of adequate channel comparators detect an UV condition during the same rating from LX1 to PGND and from LX5 to PGND to avoid switching cycle, the 4-bit counter increments twice. Once the 4- severe negative ringing that can disturb the OC counter. bit counter overflows, the UV protection logic shuts down both regulators. Thermal Monitor The comparator is reset if the feedback voltage rises back up Thermal-overload protection limits total power dissipation in above the UV threshold plus a specified amount of hysteresis the ISL65426. An internal thermal sensor monitors die outlined in the “Electrical Specifications” table. If both converter temperature continuously. If controller junction temperature channels experience an UV condition and one rises back exceeds +150°C, the thermal monitor commands the POR within regulation, then the counter continues to progress circuitry to shutdown both channels and latch-off. The POR toward overflow. latch is reset by cycling VCC to the controller. Overvoltage Response Component Selection Guide If the output voltage exceeds the overvoltage (OV) level for the This design guide is intended to provide a high-level power-good signal, the controller will fight this condition by explanation of the steps necessary to create a power actively trying to regulate the output voltage back down to the converter. It is assumed that the reader is familiar with many of reference level. This method of fighting the rise in output the basic skills and techniques referenced in the following. In voltage is limited by the reverse current capability of the total addition to this guide, Intersil provides a complete reference number of power blocks associated with the output. The design that includes schematics, a bill of materials and approximate reverse current capability of each power block is example board layout. 0.5A. The power-good signal will drop indicating the output Output Filter Design voltage is out of specification. This signal will not transition high again until the output voltage has dropped below the falling The output inductor and the output capacitor bank together PGOOD OV threshold. form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The output filter also must provide Overcurrent Protection the transient energy until the regulator can respond. Due to its A pilot device is integrated into the upper device structure of inherent low bandwidth as compared to the switching each master power block. The pilot device samples current frequency, the output filter limits the system transient response. through the master power block upper device each cycle. This The output capacitors must supply or sink load current while channel current feedback is scaled based on the state of the the current in the output inductors increases or decreases to ISET1 and ISET2 pins. The channel current information is meet the demand. compared to an overcurrent (OC) limit based on the power block OUTPUT CAPACITOR SELECTION configuration. Each 1A power block tied to the master power block increases the OC limit by 2A. For example, if both masters The critical load parameters in choosing the output capacitors are have two slaves associated with each of them then the OC limit the maximum size of the load step (I), the load-current slew rate for each output is 6A for a 3A configuration. (di/dt), and the maximum allowable output voltage deviation under transient loading (VMAX). Capacitors are characterized If the sampled current exceeds the OC threshold, a 4-bit OC according to their capacitance, ESR (Equivalent Series up/down counter increments by one LSB. If the sampled current Resistance), and ESL (Equivalent Series Inductance). falls below the OC threshold before the counter overflows, the counter is reset. If both regulators experience an OC event At the beginning of the load transient, the output capacitors supply during the same cycle, the counter increments twice. Once the all of the transient current. The output voltage will initially deviate OC counter reaches 1111, both channels are shutdown. If both by an amount approximated by the voltage drop across the ESL. channels fall below the overcurrent limit during the same cycle, As the load current increases, the voltage drop across the ESR the OC counter is reset. increases linearly until the load current reaches its final value. Neglecting the contribution of inductor current and regulator Once in shutdown, the controller enters a delay interval, response, the output voltage initially deviates by an amount equivalent to the SS interval, allowing the die to cool. The OC shown in Equation 4. counter is reset entering the delay interval. The protection logic di initiates a normal SS internal once the delay interval ends. If V ESL----- +ESRI (EQ. 4) dt the outputs both successfully soft-start, the power-good signal goes high and normal operation continues. If OC conditions The filter capacitors selected must have sufficiently low ESL continue to exist during the SS interval, the OC counter must and ESR so that the total output voltage deviation V is less overflow before the controller shutdowns both outputs again. than the maximum allowable ripple. FN6340 Rev 3.00 Page 18 of 22 March 25, 2008

ISL65426 The recommended load capacitance can be estimated using It is recommended to use a 30% peak-to-peak ripple current Equation 5. value to calculate out the inductance required for the 1.8V application. Accordingly, the inductance estimated using C = 0.5Number of LX channels used150F---------------- OUT VOUT Equation 10 below would fall between the minimum inductance value calculated in Equation 7 and the maximum values (EQ. 5) determined from Equations 8 and 9. The internal compensation scheme assumes low-ESR output capacitors. It is recommended to only use specialty polymer or V –V V IN OUT OUT ceramic capacitors with ESRs of 10m or lower. Care also L@ ---------------------------------I--O-----U-----T------------------- (EQ. 10) needs to be taken to ensure that the dielectric of the capacitor V f ----------------M------A----X--- IN s 3 used will work reliably in the entire temperature range of the Input Capacitor Selection application. Input capacitors are responsible for sourcing the AC Design Example: component of the input current flowing into the switching power Consider an output voltage of 1.2V, with LX1, LX2, LX3 and devices. Their RMS current capacity must be sufficient to LX4 connected. The output capacitance required would be: handle the AC component of the current drawn by the 1.8V switching power devices, which is related to duty cycle. The C = 0.54150F------------= 450F (EQ. 6) OUT 1.2V maximum RMS current required by the regulator is closely approximated by Equation 11. A 330µF specialty polymer capacitor in parallel with three 47µF X7R ceramic capacitors would be the recommended choice of VOUT  2 1 VIN–VOUT VOUT2 output filter. IRMSMAX = ----V----I--N-------IOUTMAX +1----2------------L-----------f--s---------------V----I--N-------  (EQ. 11) OUTPUT INDUCTOR SELECTION The important parameters to consider when selecting an input Once the output capacitors are selected, the maximum capacitor are the voltage rating and the RMS current rating. allowable ripple voltage, VPPMAX, determines the lower limit For reliable operation, select capacitors with voltage ratings on the inductance. See Equation 7. above the maximum input voltage. The rated voltage rating V –V V should be at least 1.25 times greater than the maximum input IN OUT OUT LESR ----------------------------------------------------- (EQ. 7) f V V voltage while using aluminum electrolytic capacitors, and about s IN PP MAX 2 times the maximum input voltage to account for capacitance Since the output capacitors are supplying a decreasing portion derating in case of ceramic capacitors. The capacitor RMS of the load current while the regulator recovers from the current rating should be higher than the largest RMS current transient, the capacitor voltage becomes slightly depleted. The required by the circuit. output inductors must be capable of assuming the entire load The ISL65426 needs a minimum effective input capacitance of current before the output voltage decreases more than VMAX. 70µF with low ESR for stable operation. This places an upper limit on inductance. Layout Considerations Equation 8 gives the upper limit on output inductance for the cases when the trailing edge of the current transient causes Careful printed circuit board (PCB) layout is critical in high the greater output voltage deviation than the leading edge. frequency switching converter design. Current transitions from Equation 9 addresses the leading edge. Normally, the trailing one device to another at this frequency induce voltage spikes edge dictates the inductance selection because duty cycles across the interconnecting impedances and parasitic are usually less than 50%. Nevertheless, both inequalities elements. These spikes degrade efficiency, lead to device should be evaluated, and inductance should be governed overvoltage stress, radiate noise into sensitive nodes, and based on the lower of the two results. In each equation, L is the increase thermal stress on critical components. Careful output inductance and C is the total output capacitance. component placement and PCB layout minimizes the voltage spikes in the converter. 2CVO (EQ. 8) The following multi-layer printed circuitry board layout L------------------------- V –IESR I2 MAX strategies minimize the impact of board parasitics on converter performance and optimize the heat-dissipating capabilities of L---1---.--2---5--I----2-----C--- VMAX–IESR VIN–VO (EQ. 9) the printed circuit board. This section highlights some important practices which should not be overlooked during the The other concern when selecting an output inductor is the layout process. Figure 38 provides a top level view of the internally set current mode slope compensation. Designs critical components, layer utilization, and signal routing for should not allow inductor ripple currents below 0.125 times the reference. maximum output current to prevent regulation issues. FN6340 Rev 3.00 Page 19 of 22 March 25, 2008

ISL65426 Component Placement One additional solid layer is dedicated as a power plane and broken into smaller islands of common voltage. The power Determine the total implementation area and orient the critical plane should support the input power and output power nodes. switching components first. These include the controller, input Use copper filled polygons on the top and bottom circuit layers and output capacitors, and the output inductors. Symmetry is for the phase nodes. Use the remaining printed circuit board very important in determining how available space is filled and layers for small signal wiring and additional power or ground depends on the power block configuration selected. The islands as required. controller must be placed equidistant from each output stage with the LX or phase connection distance minimized. Signal Routing An output stage consists of the area reserved for the output If the output stage component placement guidelines are inductor, and input capacitors, and output capacitors for a followed, stray inductance in the switch current path is single channel. Place the inductor such that one pad is a minimized along with good routing techniques. Great attention minimal distance from the associated phase connection. Orient should be paid to routing the PHASE plane since high current the inductor such that the load device is a short distance from pulses are driven through them. Stray inductance in this high- the other pad. Placing the input capacitors a minimal distance current path induces large noise voltages that couple into from the PVIN pins prevents long distances from adding too sensitive circuitry. By keeping the PHASE plane small, the much trace inductance and a reduction in capacitor magnitude of the potential spikes is minimized. It is important performance. Locate the output capacitors between the to size traces from the LX pins to the PHASE plane as large inductor and the load device, while keeping them in close and short as possible to reduce their overall impedance and proximity. Care should be taken not to add inductance through inductance. long trace lengths that could cancel the usefulness of the low inductance components. Keeping the components in tight proximity will help reduce parasitic impedances once the components are routed together. Bypass capacitors, CBP, supply critical filtering and must be placed close to their respective pins. Stray trace parasitics will reduce their effectiveness, so keep the distance between the VCC bias supply pad and capacitor pad to a minimum. Plane Allocation PCB designers typically have a set number of planes available for a converter design. Dedicate one solid layer, (usually an internal layer underneath the component side of the board), for a ground plane and make all critical component ground connections with vias to this layer. VIN VIN KEY THICK TRACE ON CIRCUIT PLANE LAYER VCC PVIN ISLAND ON CIRCUIT PLANE LAYER CBP CIN ISLAND ON POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE LOUT PHASE VOUT ISL65426 LX COUT CHFOUT LOAD GND FB PGND FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN6340 Rev 3.00 Page 20 of 22 March 25, 2008

ISL65426 Sensitive signals should be routed on different layers or some Thermal Management distance away from the PHASE plane on the same layer. For maximum thermal performance in high current, high Crosstalk due to switching noise is reduced into these lines by switching frequency applications, connecting the thermal isolating the routing path away from the PHASE plane. Layout PGND pad of the ISL65426 to the ground plane with multiple the PHASE planes on one layer, usually the top or bottom vias is recommended. This heat spreading allows the IC to layer, and route the voltage feedback traces on another achieve its full thermal potential. If possible, place the remaining layer. controller in a direct path of any available airflow to improve thermal performance. © Copyright Intersil Americas LLC 2006-2008. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6340 Rev 3.00 Page 21 of 22 March 25, 2008

ISL65426 L50.5x10 50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 7/06 5.00 A 0.10M C A B 0.05M C B 4 0.25 0.50 A 43 50 (PCIN 0 .14 0IN)DEX AREA 42 1 PIN 1 INDEX AREA F E 00 R 9.20 8. 10.00 8.10 50x16= 0. 0 5 0. 26 17 A 0.15 (4X) 25 18 3.30 0 VIEW "A-A" 0.50x7=3.50 REF 0.1 ± 0.40±0.10 4.20 40 0. TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C C SIDE VIEW SEATING PLANE 0.08 C MAX. 1.00 9.80 8.10 C 0.2 REF 5 0.00 MIN. 0.05 MAX. (46 x 0.50) DETAIL "X" (50 x 0.25) NOTES: 1. CONTROLLING DIMENSIONS ARE IN MM. 2. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL ±0.05 (50 x 0.60) ANGULAR ±2× 3.30 3. DIMENSIONING AND TOLERANCE PER ASME Y 14.5M-1994. 4. DIMENSION LEAD WIDTH APPLIES TO THE PLATED TERMINAL 4.80 AND IS MEASURED BETWEEN 0.23MM AND 0.28MM FROM THE TERMINAL TIP. RECOMMENDED LAND PATTERN 5. TIEBAR SHOWN (if present) IS A NON-FUNCTIONAL FEATURE FN6340 Rev 3.00 Page 22 of 22 March 25, 2008