DATASHEET ISL6524 FN9015 VRM8.5 PWM and Triple Linear Power System Controller Rev 3.00 Apr 18, 2005 The ISL6524 provides the power control and protection for Features four output voltages in high-performance microprocessor • Provides 4 Regulated Voltages and computer applications. The IC integrates one PWM - Microprocessor Core, AGTL+ Bus, AGP Bus Power, controller and three linear controllers, as well as the and North/South Bridge Core monitoring and protection functions into a 28-pin SOIC package. The PWM controller regulates the microprocessor • Drives N-Channel MOSFETs core voltage with a synchronous-rectified buck converter. • Linear Regulator Drives Compatible with both MOSFET One linear controller supplies the computer system’s AGTL+ and Bipolar Series Pass Transistors 1.2V bus power. The other two linear controllers regulate • Simple Single-Loop Control Design power for the 1.5V AGP bus and the 1.8V power for the chip - Voltage-Mode PWM Control set core voltage and/or cache memory circuits. • Fast PWM Converter Transient Response The ISL6524 includes an Intel VRM8.5 compatible, TTL - High-Bandwidth Error Amplifier 5-input digital-to-analog converter (DAC) that adjusts the - Full 0% to 100% Duty Ratio microprocessor core-targeted PWM output voltage from 1.050V to 1.825V in 25mV steps. The precision reference and • Excellent Output Voltage Regulation voltage-mode control provide ±1% static regulation. The linear - Core PWM Output: ±1% Over Temperature regulators use external N-channel MOSFETs or bipolar NPN - All Other Outputs: ±3% Over Temperature pass transistors to provide fixed output voltages of 1.2V ±3% • VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core (VOUT2), 1.5V ±3% (VOUT3) and 1.8V ±3% (VOUT4). Output Voltage Selection The ISL6524 monitors all the output voltages. A delayed- - Wide Range - 1.050V to 1.825V rising VTT (VOUT2 output) Power Good signal is issued • Power-Good Output Voltage Monitors before the core PWM starts to ramp up. Another system - Separate delayed VTT Power Good Power Good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their under- • Overcurrent Fault Monitor voltage levels. Additional built-in overvoltage protection for - Switching Regulator Doesn’t Require Extra Current the core output uses the lower MOSFET to prevent output Sensing Element, Uses MOSFET’s rDS(ON) voltages above 115% of the DAC setting. The PWM • Small Converter Size controllers’ overcurrent function monitors the output current - Constant Frequency Operation by using the voltage drop across the upper MOSFET’s - 200kHz Internal Oscillator rDS(ON), eliminating the need for a current sensing resistor. • Pb-Free Available (RoHS Compliant) Applications Ordering Information • Motherboard Power Regulation for Computers TEMP. PKG. PART NUMBER RANGE (°C) PACKAGE DWG. # Pinout ISL6524 (SOIC) TOP VIEW ISL6524CB* 0 to 70 28 Ld SOIC M28.3 DRIVE2 1 28 VCC ISL6524CBZ* 0 to 70 28 Ld SOIC M28.3 FIX 2 27 UGATE (See Note) (Pb-free) VID3 3 26 PHASE ISL6524CBZA* 0 to 70 28 Ld SOIC M28.3 (See Note) (Pb-free) VID2 4 25 LGATE ISL6524EVAL1 Evaluation Board VID1 5 24 PGND VID0 6 23 OCSET *Add “-T” suffix for tape and reel. VID25 7 22 VSEN1 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin PGOOD 8 21 FB plate termination finish, which are RoHS compliant and compatible VTTPG 9 20 COMP with both SnPb and Pb-free soldering operations. Intersil Pb-free FAULT/RT 10 19 VSEN3 products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VSEN2 11 18 DRIVE3 SS24 12 17 GND SS13 13 16 VAUX VSEN4 14 15 DRIVE4 FN9015 Rev 3.00 Page 1 of 17 Apr 18, 2005

ApFN Block Diagram IS r 18, 29015 L6524 0R 0e 5v 3 VSEN3 VSEN1 OCSET VCC .0 0 VAUX 1.5V or 1.26V + - EA3 - DRIVE3 + POWER-ON x0.75 - UV3 RESET (POR) VAUX + x1.10 + 200A - + x0.75 + UV4 DRIVE4 - - EA4 + + 1.8V or 1.26V x0.90 - VSEN4 PGOOD - + FIX - x1.15 INHIBIT VCC OV DRIVE1 SOFT- START UGATE DRIVE2 AND FAULT OC + LOGIC - PHASE FAULT VSEN2 - GATE + + EA2 - + CONTROL VCC - EA1 PWM PWM VCC - UV2 COMP x0.90 + SYNCH LGATE + DRIVE PGND - 1.2V QSCELTK> OSCILLATOR 28A 28A DACOUT COTNTVLE DR/TAER GND Q D (DAC) CLR 4.5V 4.5V P a g VTTPG FAULT/RT SS13 SS24 FB COMP VID3VID2VID1 VID0VID25 e 2 o FIGURE 1. f 1 7

ISL6524 +5VIN Q3 Q1 LINEAR VOUT2 CONTROLLER VOUT1 PWM1 CONTROLLER Q2 ISL6524 +3.3VIN VOUT3 Q4 CONLITNREOALRLER CONLITNREOALRLER Q5 VOUT4 FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM +12VIN +5VIN LIN CIN VCC OCSET POWERGOOD Q3 DRIVE2 PGOOD VOUT2 UGATE Q1 1.2V FAULT/RT PHASE LOUT1 VOUT1 1.3V to 3.5V COUT2 FIX LGATE Q2 COUT1 VSEN2 PGND VSEN1 VTT POWERGOOD VTTPG ISL6524 FB VAUX +3.3VIN COMP Q4 DRIVE3 VOUT3 VSEN3 VID3 1.5V VID2 COUT3 VID1 VID0 DRIVE4 Q5 VID25 VOUT4 VSEN4 SS13 1.8V SS24 COUT4 CSS13 CSS24 GND FIGURE 3. TYPICAL APPLICATION FN9015 Rev 3.00 Page 3 of 17 Apr 18, 2005

ISL6524 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V Thermal Resistance (Typical, Note 1) JA (oC/W) PGOOD, RT/FAULT, DRIVE, PHASE, and SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 GATE Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . GND -0.3V to 7V Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Recommended Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply Current ICC UGATE, LGATE, DRIVE2, DRIVE3, and - 9 - mA DRIVE4 Open POWER-ON RESET Rising VCC Threshold - - 10.4 V Falling VCC Threshold 8.2 - - V Rising VAUX Threshold - 2.5 - V VAUX Threshold Hysteresis - 0.5 - V Rising VOCSET Threshold - 1.26 - V OSCILLATOR Free Running Frequency FOSC 185 200 215 kHz Total Variation 6k < RT to GND < 200k Note 2 -15 - +15 % Ramp Amplitude VOSC - 1.9 - VP-P DAC REFERENCE DAC (VID25-VID3) Input Low Voltage 0.8 V DAC (VID25-VID3) Input High Voltage 2.0 V DACOUT Voltage Accuracy -1.0 - +1.0 % LINEAR REGULATORS (VOUT2, VOUT3, AND VOUT4) Regulation Tolerance - 3 - % VSEN3 Regulation Voltage VREG3 FIX = 0V - 1.26 - V VSEN2 Regulation Voltage VREG2 - 1.2 - V VSEN3 Regulation Voltage VREG3 FIX = Open - 1.5 - V VSEN4 Regulation Voltage VREG4 FIX = Open - 1.8 - V VSEN3, 4 Undervoltage Level VSEN3, 4UV VSEN3, 4 Rising - 75 - % VSEN3, 4 Undervoltage Hysteresis VSEN3, 4 Falling 7 % Output Drive Current VAUX-VDRIVE2,3,4 > 0.6V 20 40 - mA SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Note 2 - 88 - dB FN9015 Rev 3.00 Page 4 of 17 Apr 18, 2005

ISL6524 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Gain-Bandwidth Product GBWP Note 2 - 15 - MHz Slew Rate SR COMP = 10pF, Note 2 - 6 - V/s PWM CONTROLLERS GATE DRIVERS UGATE Source IUGATE VCC = 12V, VUGATE = 6V - 1 - A UGATE Sink RUGATE VGATE-PHASE = 1V - 1.7 3.5  LGATE Source ILGATE VCC = 12V, VLGATE = 1V - 1 - A LGATE Sink RLGATE VLGATE = 1V - 1.4 3.0  PROTECTION FAULT Sourcing Current IOVP VFAULT/RT = 2.0V - 8.5 - mA OCSET Current Source IOCSET VOCSET = 4.5VDC 170 200 230 A Soft-Start Current ISS13,24 VSS13,24 = 2.0VDC - 28 - A POWER GOOD VSEN1 Upper Threshold VSEN1 Rising 108 - 110 % (VSEN1/DACOUT) VSEN1 Undervoltage VSEN1 Rising 92 - 94 % (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1/DACOUT) VSEN1 Falling - 2 - % PGOOD Voltage Low VPGOOD IPGOOD = -4mA - - 0.8 V VSEN2 Undervoltage VSEN2 Rising 1.08 V VSEN2 Hysteresis VSEN2 Falling - 48 - mV VTTPG Voltage Low VVTTPG IVTTPG = -4mA - - 0.8 V NOTE: 2. Guaranteed by design Typical Performance Curves 100 CUGATE = CLGATE = C C = 4800pF VIN = 5V 80 VCC = 12V 1000 RT PULLUP ) TO +12V E (k mA) 60 C = 3600pF C 100 STAN I (CC 40 C = 1500pF SI E R 10 RT PULLDOWN TO VSS 20 C = 660pF 0 10 100 1000 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) FIGURE 4. RT RESISTANCE vs FREQUENCY FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY FN9015 Rev 3.00 Page 5 of 17 Apr 18, 2005

ISL6524 Functional Pin Descriptions OCSET (Pin 23) VCC (Pin 28) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200mA current source Provide a 12V bias supply for the IC to this pin. This pin also (IOCSET), and the upper MOSFET’s on-resistance (rDS(ON)) provides the gate bias charge for all the MOSFETs set the converter overcurrent (OC) trip point according to the controlled by the IC. The voltage at this pin is monitored for following equation: Power-On Reset (POR) purposes. I R I = --O-----C----S----E----T--------------O----C-----S----E---T--- GND (Pin 17) PEAK r DSON Signal ground for the IC. All voltage levels are measured An overcurrent trip cycles the soft-start function. with respect to this pin. The voltage at OCSET pin is monitored for power-on reset PGND (Pin 24) (POR) purposes. This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source to this pin. PHASE (Pin 26) Connect the PHASE pin to the PWM converter’s upper VAUX (Pin 16) MOSFET source. This pin represents the gate drive return Connect this pin to the ATX 3.3V output. The voltage present current path and is used to monitor the voltage drop across at this pin is monitored for sequencing purposes. This pin the upper MOSFET for overcurrent protection. provides the necessary base bias for the NPN pass transistors, as well as the current sunk through the 5kW VID UGATE (Pin 27) pull-up resistors. Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper SS13 (Pin 13) MOSFET. Connect a capacitor from this pin to ground. This capacitor, along with an internal 28mA current source, sets the soft-start LGATE (Pin 25) interval of the synchronous switching converter (VOUT1) and Connect LGATE to the synchronous PWM converter’s lower the AGP regulator (VOUT3). A VTTPG high signal is also MOSFET gate. This pin provides the gate drive for the lower delayed by the time interval required by the charging of this MOSFET. capacitor from 0V to 1.25V (see Soft-Start details). COMP and FB (Pins 20, 21) SS24 (Pin 12) COMP and FB are the available external pins of the Connect a capacitor from this pin to ground. This capacitor, synchronous PWM regulator error amplifier. The FB pin is along with an internal 28mA current source, sets the the inverting input of the error amplifier. Similarly, the COMP soft-start interval of the VOUT2 regulator. Pulling this pin pin is the error amplifier output. These pins are used to below 0.8V induces a chip reset (POR) and shutdown. compensate the voltage-mode control feedback loop of the synchronous PWM converter. VTTPG (Pin 9) VTTPG is an open collector output used to indicate the VSEN1 (Pin 22) status of the VOUT2 regulator output voltage. This pin is This pin is connected to the synchronous PWM converters’ pulled low when the VOUT2 output is below the undervoltage output voltage. The PGOOD and OVP comparator circuits threshold or when the SS13 pin is below 1.25V. use this signal to report output voltage status. PGOOD (Pin 8) DRIVE2 (Pin 1) PGOOD is an open collector output used to indicate the Connect this pin to the gate/base of a N-type external pass status of the output voltages. This pin is pulled low when the transistor (MOSFET or bipolar). This pin provides the drive synchronous regulator output is not within ±10% of the for the 1.2V regulator’s pass transistor. DACOUT reference voltage or when any of the other outputs VSEN2 (Pin 11) is below its undervoltage threshold. Connect this pin to the output of the standard buck PWM VID3, VID2, VID1, VID0, VID25 (Pins 3-7) regulator. The voltage at this pin is regulated to a 1.2V level. VID3-25 are the TTL-compatible input pins to the 5-bit DAC. This pin is also monitored for undervoltage events. The logic states of these five pins program the internal FIX (Pin 2) voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage (VOUT1), as Grounding this pin bypasses the internal resistor dividers that well as the corresponding PGOOD and OVP thresholds. set the output voltage of the 1.5V and 1.8V linear regulators. Each VID pin is connected to the VAUX pin through a 5kW This way, the output voltage of the two regulators can be pull-up resistor. adjusted from 1.26V up to the input voltage (+3.3V or +5V; FN9015 Rev 3.00 Page 6 of 17 Apr 18, 2005

ISL6524 VOUT4 can only be set from 1.7V up) by way of an external controller drives 2 MOSFETs (Q1 and Q2) in a synchronous- resistor divider connected at the corresponding VSEN pin. The rectified buck converter configuration and regulates the core new output voltage set by the external resistor divider can be voltage to a level programmed by the 5-bit digital-to-analog determined using the following formula: converter (DAC). The first linear controller (EA2) is designed to V = 1.265V1+-R----O-----U----T--- provide the AGTL+ bus voltage (VOUT2) by driving a MOSFET OUT  RGND (Q3) pass element to regulate the output voltage to a level of 1.2V. The remaining two linear controllers (EA3 and EA4) where ROUT is the resistor connected from VSEN to the supply the 1.5V advanced graphics port (AGP) bus power output of the regulator, and RGND is the resistor connected (VOUT3) and the 1.8V chip set core power (VOUT4). from VSEN to ground. Left open, the FIX pin is pulled high, Initialization enabling fixed output voltage operation. The ISL6524 automatically initializes in ATX-based systems DRIVE3 (Pin 18) upon receipt of input power. The Power-On Reset (POR) Connect this pin to the gate/base of a N-type external pass function continually monitors the input supply voltages. The transistor (MOSFET or bipolar). This pin provides the drive POR monitors the bias voltage (+12VIN) at the VCC pin, the for the 1.5V regulator’s pass transistor. 5V input voltage (+5VIN) at the OCSET pin, and the 3.3V input voltage (+3.3VIN) at the VAUX pin. The normal level on VSEN3 (Pin 19) OCSET is equal to +5VIN less a fixed voltage drop (see Connect this pin to the output of the 1.5V linear regulator. overcurrent protection). The POR function initiates soft-start This pin is monitored for undervoltage events. operation after all supply voltages exceed their POR thresholds. DRIVE4 (Pin 15) Connect this pin to the base of an external bipolar transistor. Soft-Start This pin provides the drive for the 1.8V regulator’s pass The 1.8V supply designed to power the chip set (OUT4), transistor. cannot lag the ATX 3.3V by more than 2V, at any time. To meet this special requirement, the linear block controlling VSEN4 (Pin 14) this output operates independently of the chip’s power-on Connect this pin to the output of the linear 1.8V regulator. reset. Thus, DRIVE4 is driven to raise the OUT4 voltage This pin is monitored for undervoltage events. before the input supplies reach their POR levels. As seen in FAULT/RT (Pin 10) Figure 6, at time T0 the power is turned on and the input supplies ramp up. Immediately following, OUT4 is also This pin provides oscillator switching frequency adjustment. ramped up, lagging the ATX 3.3V by about 1.8V. At time T1, By placing a resistor (RT) from this pin to GND, the nominal the POR function initiates the SS24 soft-start sequence. 200kHz switching frequency is increased according to the Initially, the voltage on the SS24 pin rapidly increases to following equation: approximately 1V (this minimizes the soft-start interval). 6 510 Then, an internal 28mA current source charges an external Fs200kHz+-R----T------k---------- (RT to GND) capacitor (CSS24) on the SS24 pin to about 4.5V. As the SS24 voltage increases, the EA2 error amplifier drives Q3 to Conversely, connecting a resistor from this pin to VCC provide a smooth transition to the final set voltage. The reduces the switching frequency according to the following OUT4 reference (clamped to SS24) increasing past the equation: intermediary level, established based on the ATX 3.3V 7 Fs200kHz–R-4----------1k---0------- (RT to 12V) presence at the VAUX pin, brings the output in regulation T soon after T2. Nominally, the voltage at this pin is 1.26V. In the event of an As OUT2 increases past the 90% power-good level, the second overvoltage or overcurrent condition, this pin is internally soft-start (SS13) is released. Between T2 and T3, the SS13 pin pulled to VCC. voltage ramps from 0V to the valley of the oscillator’s triangle wave (at 1.25V). Contingent upon OUT2 remaining above Description 1.08V, the first PWM pulse on PHASE1 triggers the VTTPG pin Operation to go high. The oscillator’s triangular wave form is compared to the clamped error amplifier output voltage. As the SS13 pin The ISL6524 monitors and precisely controls 4 output voltage voltage increases, the pulse-width on the PHASE1 pin levels (Refer to Figures 1, 2, 3). It is designed for increases, bringing the OUT1 output within regulation limits. microprocessor computer applications with 3.3V, 5V, and 12V Similarly, the SS13 voltage clamps the reference voltage for bias input from an ATX power supply. The IC has one PWM OUT3, enabling a controlled output voltage ramp-up. At time and three linear controllers. The PWM controller is designed to T4, all output voltages are within power-good limits, situation regulate the microprocessor core voltage (VOUT1). The PWM reported by the PGOOD pin going high. FN9015 Rev 3.00 Page 7 of 17 Apr 18, 2005

ISL6524 VSEN3, or VSEN4) is ignored until the respective UP signal goes high. This allows VOUT3 and VOUT4 to increase ATX 12V without fault at start-up. Following an overcurrent event 10V (OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V VTTPG resets the overcurrent latch and generates a soft-started SS13 ramp-up of the outputs 1, 2, and 3. ATX 5V SS13UP UV3 SS24 PGOOD 0V OC LATCH INHIBIT1,2,3 3.0V ATX 3.3V OC1 S Q VOUT1 (1.65V) R COU>NTER SSDOWN 4V VOUT4 (1.8V) SS13 R 0.8V FAULT SS24 LATCH VOUT2 (1.2V) VOUT3 (1.5V) SS24UP S Q 4V POR R Q 0V OV FAULT R UV4 COUNTER T0 T1 T2 T3 T4T5 > TIME R FIGURE 6. SOFT-START INTERVAL UV2 S Q The T2 to T3 time interval is dependent upon the value of OC LATCH CSS13. The same capacitor is also responsible for the ramp- FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC up time of the OUT1 and OUT3 voltages. If selecting a different capacitor then recommended in the circuit application OUT1 Overvoltage Protection literature, consider the effects the different value will have on The overvoltage circuit provides protection during the initial the ramp-up time and inrush currents of the OUT1 and OUT3 application of power. For voltages on the VCC pin below the outputs. power-on reset level (and above ~4V), the output level is Fault Protection monitored for voltages above 1.3V. Should VSEN1 exceed All four outputs are monitored and protected against extreme this level, the lower MOSFET, Q2, is driven on. overload. The chip’s response to an output overload is Overcurrent Protection selective, depending on the faulting output. All outputs are protected against excessive overcurrents. An overvoltage on VOUT1 output (VSEN1) disables outputs The PWM controller uses the upper MOSFET’s on- 1, 2, and 3, and latches the IC off. An undervoltage on resistance, rDS(ON) to monitor the current for protection VOUT4 output latches the IC off. A single overcurrent event against a shorted output. All linear regulators monitor their on output 1, or an undervoltage event on output 2 or 3, respective VSEN pins for undervoltage to protect against increments the respective fault counters and triggers a excessive currents. shutdown of outputs 1, 2, and 3, followed by a soft-start re- Figure 8 illustrates the overcurrent protection with an overload start. After three consecutive fault events on either counter, on OUT1. The overload is applied at T0 and the current the chip is latched off. Removal of bias power resets both the fault latch and the counters. Both counters are also reset by increases through the inductor (LOUT1). At time T1, the OC1 a successful start-up of all the outputs. comparator trips when the voltage across Q1 (iD • rDS(ON)) exceeds the level programmed by ROCSET. This inhibits Figure 6 shows a simplified schematic of the fault logic. The outputs 1, 2, and 3, discharges the soft-start capacitor CSS24 overcurrent latches are set dependent upon the states of the with 28mA current sink, and increments the counter. Soft-start overcurrent (OC1), output 2 and 3 undervoltage (UV2, UV3) capacitor CSS13 is quickly discharged. CSS13 starts ramping and the soft-start signals (SS13, SS24). Window up at T2 and initiates a new soft-start cycle. With OUT2 still comparators monitor the SS pins and indicate when the overloaded, the inductor current increases to trip the respective CSS pins are fully charged to above 4.0V (UP overcurrent comparator. Again, this inhibits the outputs, but signals). An undervoltage on either linear output (VSEN2, the CSS24 soft-start voltage continues increasing to above FN9015 Rev 3.00 Page 8 of 17 Apr 18, 2005

ISL6524 4.0V before discharging. Soft-start capacitor CSS13 is, again, The OC trip point varies with MOSFET’s rDS(ON) quickly discharged. The counter increments to 2. The soft- temperature variations. To avoid overcurrent tripping in the start cycle repeats at T3 and trips the overcurrent comparator. normal operating load range, determine the ROCSET The SS24 pin voltage increases to above 4.0V at T4 and the resistor value from the equation above with: counter increments to 3. This sets the fault latch to disable the 1. The maximum rDS(ON) at the highest junction temperature converter. 2. The minimum IOCSET from the specification table RT FAULT 3. Determine IPEAK for IPEAK > IOUT(MAX) + (DI)/2, T/10V REPORTED where DI is the output inductor ripple current. L U FA 0V For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. COUNT COUNT COUNT = 1 = 2 = 3 4V OVERCURRENT TRIP: VIN = +5V 43 V >V SS2SS12V iDrDSODNS>IOSCESTETROCSET 0V OCSET ROCSET OVERLOAD ENT APPLIED IOCSET VSET+ iD R 200A R U VCC R C DRIVE UGATE + O VDS T UC 0A + D - N OC I PHASE T0T1 T2 T3 T4 TIME PWM GATE V = V –V PHASE IN DS FIGURE 8. OVERCURRENT OPERATION CONTROL V = V –V OCSET IN SET The three linear controllers monitor their respective VSEN FIGURE 9. OVERCURRENT DETECTION pins for undervoltage. Should excessive currents cause VSEN3 or VSEN4 to fall below the linear undervoltage OUT1 Voltage Program threshold, the respective UV signals set the OC latch or the FAULT latch, providing respective CSS capacitors are fully The output voltage of the PWM converter is programmed to charged. Blanking the UV signals during the CSS charge discrete levels between 1.050V and 1.825V. This output interval allows the linear outputs to build above the (OUT1) is designed to supply the core voltage of Intel’s undervoltage threshold during normal operation. Cycling the advanced microprocessors. The voltage identification (VID) bias input power off then on resets the counter and the fault pins program an internal voltage reference (DACOUT) with a latch. TTL-compatible 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. An external resistor (ROCSET) programs the overcurrent trip Table 1 specifies the DACOUT voltage for the different level for the PWM converter. As shown in Figure 9, the internal combinations of connections on the VID pins. The VID pins 200mA current sink (IOCSET) develops a voltage across can be left open for a logic 1 input, since they are internally ROCSET (VSET) that is referenced to VIN. The DRIVE signal pulled to the VAUX pin through 5kW resistors. Changing the enables the overcurrent comparator (OC). When the voltage VID inputs during operation is not recommended and could across the upper MOSFET (VDS(ON)) exceeds VSET, the toggle the PGOOD signal and exercise the overvoltage overcurrent comparator trips to set the overcurrent latch. Both protection. The output voltage program is Intel VRM8.5 VSET and VDS are referenced to VIN and a small capacitor compatible. across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I R OCSET OCSET I = ---------------------------------------------------- PEAK r DSON FN9015 Rev 3.00 Page 9 of 17 Apr 18, 2005

ISL6524 TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM up to their set values in a quick and controlled fashion, while meeting the system timing requirements. PIN NAME NOMINAL DACOUT Shutdown VID3 VID2 VID1 VID0 VID25 VOLTAGE The PWM output does not switch until the soft-start voltage 0 1 0 0 0 1.050 0 1 0 0 1 1.075 (VSS13) exceeds the oscillator’s valley voltage. Additionally, the reference on each linear’s amplifier is clamped to the soft- 0 0 1 1 0 1.100 start voltage. Holding the SS24 pin low (with an open drain or 0 0 1 1 1 1.125 open collector signal) turns off regulators 1, 2 and 3. 0 0 1 0 0 1.150 Regulator 4 (MCH) will simply drop its output to the 0 0 1 0 1 1.175 intermediate soft-start level. This output is not allowed to 0 0 0 1 0 1.200 violate the 2V maximum potential gap to the ATX 3.3V output. 0 0 0 1 1 1.225 Layout Considerations 0 0 0 0 0 1.250 MOSFETs switch very fast and efficiently. The speed with 0 0 0 0 1 1.275 which the current transitions from one device to another 1 1 1 1 0 1.300 causes voltage spikes across the interconnecting 1 1 1 1 1 1.325 impedances and parasitic circuit elements. The voltage 1 1 1 0 0 1.350 spikes can degrade efficiency, radiate noise into the circuit, 1 1 1 0 1 1.375 and lead to device overvoltage stress. Careful component 1 1 0 1 0 1.400 layout and printed circuit design minimizes the voltage 1 1 0 1 1 1.425 spikes in the converter. Consider, as an example, the turn-off 1 1 0 0 0 1.450 transition of the upper MOSFET. Prior to turn-off, the upper 1 1 0 0 1 1.475 MOSFET was carrying the full load current. During the turn- 1 0 1 1 0 1.500 off, current stops flowing in the upper MOSFET and is picked 1 0 1 1 1 1.525 up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike 1 0 1 0 0 1.550 during the switching interval. Careful component selection, 1 0 1 0 1 1.575 tight layout of the critical components, and short, wide circuit 1 0 0 1 0 1.600 traces minimize the magnitude of voltage spikes. 1 0 0 1 1 1.625 1 0 0 0 0 1.650 There are two sets of critical components in a DC-DC 1 0 0 0 1 1.675 converter using an ISL6524 controller. The switching power components are the most critical because they switch large 0 1 1 1 0 1.700 amounts of energy, and as such, they tend to generate 0 1 1 1 1 1.725 equally large amounts of noise. The critical small signal 0 1 1 0 0 1.750 components are those connected to sensitive nodes or 0 1 1 0 1 1.775 those supplying critical bypass current. 0 1 0 1 0 1.800 0 1 0 1 1 1.825 The power components and the controller IC should be placed first. Locate the input capacitors, especially the high- NOTE: 0 = connected to GND, 1 = open or connected to 3.3V through pull-up resistors frequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM Application Guidelines controller close to the MOSFETs. Soft-Start Interval The critical small signal components include the bypass Initially, the soft-start function clamps the error amplifier’s output capacitor for VCC and the soft-start capacitor, CSS. Locate of the PWM converter. This generates PHASE pulses of these components close to their connecting pins on the increasing width that charge the output capacitor(s). The control IC. Minimize any leakage current paths from any SS resulting output voltages start-up as shown in Figure 6. node, since the internal current source is only 28mA. The soft-start function controls the output voltage rate of rise A multi-layer printed circuit board is recommended. Figure to limit the current surge at start-up. The soft-start interval 10 shows the connections of the critical components in the and the surge current are programmed by the soft-start converter. Note that the capacitors CIN and COUT each capacitor, CSS. Programming a faster soft-start interval could represent numerous physical capacitors. Dedicate one increases the peak surge current. Using the recommended solid layer for a ground plane and make all critical 0.1mF soft start capacitors ensure all output voltages ramp component ground connections with vias to this layer. FN9015 Rev 3.00 Page 10 of 17 Apr 18, 2005

ISL6524 Dedicate another solid layer as a power plane and break this The modulator transfer function is the small-signal transfer plane into smaller islands of common voltage levels. The function of VOUT/VE/A. This function is dominated by a DC power plane should support the input power and output Gain, given by VIN/VOSC, and shaped by the output filter, with power nodes. Use copper filled polygons on the top and a double pole break frequency at FLC and a zero at FESR. bottom circuit layers for the PHASE node, but do not unnecessarily oversize this particular island. Since the VIN PHASE node is subject to very high dV/dt voltages, the stray OSC DRIVER ccaircpuaictrityo rw fioll rtmenedd tboe ctwouepelne tshwesitech isinlagn ndo aisned. Uthsee s tuhrero unding VOSC CPOWMMP LO VOUT remaining printed circuit layers for small signal wiring. The +- DRIVER PHASE wiring traces from the control IC to the MOSFET gate and CO source should be sized to carry 2A peak currents. ESR (PARASITIC) LIN VE/A ZFB +5VIN - ZIN CIN +12V + REFERENCE CVCC ERROR VCC GND COCSET AMP +3.3VIN OCSET ROCSET DETAILED COMPENSATION COMPONENTS Q3 DRIVE2 VOUT2 UGATE Q1 C2 ZFB VOUT LOUT VOUT1 ZIN AD COUT2 PHASE C1 R2 C3 R3 LO SS24 LGATE Q2 CCRO1UT1 LOAD COMP R1 CSS24,13 SS13 FB VOUT3 ISL6524 VOUT4 +- ISL6524 OAD COUT3 DRIVE3DRIVE4 COUT4 AD DACOUT L PGND O Q4 Q5 L FIGURE 11. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN +3.3VIN KEY Modulator Break Frequency Equations ISLAND ON POWER PLANE LAYER 1 1 ISLAND ON CIRCUIT PLANE LAYER F = ---------------------------------------- F = ----------------------------------------- VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE LC 2 LOCO ESR 2ESRCO The compensation network consists of the error amplifier FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS (internal to the ISL6524) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency PWM1 Controller Feedback Compensation (f0dB) and adequate phase margin. Phase margin is the The PWM controller uses voltage-mode control for output difference between the closed loop phase at f0dB and 180o. regulation. This section highlights the design consideration for a The equations below relate the compensation network’s poles, voltage-mode controller requiring external compensation. zeros and gain to the components (R1, R2, R3, C1, C2, and Figure 11 highlights the voltage-mode control loop for a C3) in Figure 11. Use these guidelines for locating the poles synchronous-rectified buck converter. The output voltage and zeros of the compensation network: (VOUT) is regulated to the Reference voltage level. The 1. Pick Gain (R2/R1) for desired converter bandwidth reference voltage level is the DAC output voltage (DACOUT) for the PWM. The error amplifier output (VE/A) is compared with 32.. PPllaaccee 12SNTDZ eZreor oB ealto Fwi ltFeilrt’esr ’Ds oDuobuleb leP oPloele (~75% FLC) the oscillator (OSC) triangular wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. 4. Place 1ST Pole at the ESR Zero The PWM wave is smoothed by the output filter (LO and CO). 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary FN9015 Rev 3.00 Page 11 of 17 Apr 18, 2005

ISL6524 Compensation Break Frequency Equations PWM Output Capacitors 1 1 Modern microprocessors produce transient load rates F = ----------------------------------- F = ------------------------------------------------------- Z1 2R2C1 P1 2R -C----1----------C-----2-- above 1A/ns. High frequency capacitors initially supply the 2 C1+C2 transient current and slow the load rate-of-change seen by 1 1 the bulk capacitors. The bulk filter capacitor values are F = ------------------------------------------------------- F = ----------------------------------- Z2 2R1+R3C3 P2 2R3C3 generally determined by the ESR (effective series resistance) and voltage rating requirements rather than Figure 12 shows an asymptotic plot of the DC-DC converter’s actual capacitance requirements. gain vs. frequency. The actual Modulator Gain has a high gain High frequency decoupling capacitors should be placed as peak dependent on the quality factor (Q) of the output filter, close to the power pins of the load as physically possible. Be which is not shown in Figure 12. Using the above guidelines careful not to add inductance in the circuit board wiring that should yield a Compensation Gain similar to the curve plotted. could cancel the usefulness of these low inductance The open loop error amplifier gain bounds the compensation components. Consult with the manufacturer of the load on gain. Check the compensation gain at FP2 with the capabilities specific decoupling requirements. of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 12 by adding the Modulator Gain (in Use only specialized low-ESR capacitors intended for dB) to the Compensation Gain (in dB). This is equivalent to switching-regulator applications for the bulk capacitors. The multiplying the modulator transfer function to the compensation bulk capacitor’s ESR determines the output ripple voltage and transfer function and plotting the gain. the initial voltage drop following a high slew-rate transient’s edge. An aluminum electrolytic capacitor’s ESR value is FZ1 FZ2 FP1 FP2 OPEN LOOP related to the case size with lower ESR available in larger ERROR AMP GAIN 100 case sizes. However, the equivalent series inductance (ESL) 80 20log----V----I---N------- of these capacitors increases with case size and can reduce VP–P the usefulness of the capacitor to high slew-rate transient 60 loading. Unfortunately, ESL is not a specified parameter. Work B) 40 COMPENSATION with your capacitor supplier and measure the capacitor’s N (d 20 GAIN impedance with frequency to select a suitable component. In AI most cases, multiple electrolytic capacitors of small case size G 0 perform better than a single large case capacitor. 20logR-----2--- R1 -20 Linear Output Capacitors MODULATOR CLOSED LOOP -40 GAIN FLC FESR GAIN The output capacitors for the linear regulators provide dynamic load current. Thus capacitors COUT2, COUT3, and -60 10 100 1K 10K 100K 1M 10M COUT4 should be selected for transient load regulation. FREQUENCY (Hz) PWM Output Inductor Selection FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The PWM converter requires an output inductor. The output The compensation gain uses external impedance networks inductor is selected to meet the output voltage ripple ZFB and ZIN to provide a stable, high bandwidth (BW) overall requirements and sets the converter’s response time to a loop. A stable control loop has a gain crossing with load transient. The inductor value determines the converter’s -20dB/decade slope and a phase margin greater than ripple current and the ripple voltage is a function of the ripple 45degrees. Include worst case component variations when current. The ripple voltage and current are approximated by determining phase margin. the following equations: V –V V Component Selection Guidelines I = -----I--N--------------O----U----T--------O----U----T--- VOUT = IESR F L V S IN Output Capacitor Selection Increasing the value of inductance reduces the ripple The output capacitors for each output have unique current and voltage. However, large inductance values requirements. In general the output capacitors should be increase the converter’s response time to a load transient. selected to meet the dynamic regulation requirements. Additionally, the PWM converter requires an output capacitor One of the parameters limiting the converter’s response to to filter the current ripple. The load transient for the a load transient is the time required to change the inductor microprocessor core requires high quality capacitors to current. Given a sufficiently fast control loop design, the supply the high slew rate (di/dt) current demands. ISL6524 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial FN9015 Rev 3.00 Page 12 of 17 Apr 18, 2005

ISL6524 current value to the post-transient current level. During this MOSFET Selection/Considerations interval the difference between the inductor current and the The ISL6524 requires 5 external transistors. Two N-channel transient current level must be supplied by the output MOSFETs are employed by the PWM converter. The GTL, capacitor(s). Minimizing the response time can minimize AGP, and memory linear controllers can each drive a the output capacitance required. MOSFET or a NPN bipolar as a pass transistor. All these The response time to a transient is different for the transistors should be selected based upon rDS(ON), current application of load and the removal of load. The following gain, saturation voltages, gate supply requirements, and equations give the approximate response time interval for thermal management considerations. application and removal of a transient load: PWM MOSFET Selection and Considerations L I L I In high-current PWM applications, the MOSFET power tRISE = V----O--------–----V-T---R----A----N---- tFALL = ----O----V--------T----R----A----N--- dissipation, package selection and heatsink are the dominant IN OUT OUT design factors. The power dissipation includes two main loss where: ITRAN is the transient load current step, tRISE is the components: conduction losses and switching losses. These response time to the application of load, and tFALL is the losses are distributed between the upper and lower MOSFET response time to the removal of load. Be sure to check both according to the duty factor. The conduction losses are the of these equations at the minimum and maximum output main component of power dissipation for the lower MOSFETs. levels for the worst case response time. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. Input Capacitor Selection The important parameters for the bulk input capacitor are the The equations presented assume linear voltage-current voltage rating and the RMS current rating. For reliable transitions and do not model power losses due to the lower operation, select bulk input capacitors with voltage and MOSFET’s body diode or the output capacitances associated current ratings above the maximum input voltage and largest with either MOSFET. The gate charge losses are dissipated RMS current required by the circuit. The capacitor voltage by the controller IC (ISL6524) and do not contribute to the rating should be at least 1.25 times greater than the maximum MOSFETs’ heat rise. Ensure that both MOSFETs are within input voltage. The maximum RMS current rating requirement their maximum junction temperature at high ambient for the input capacitors of a buck regulator is approximately temperature by calculating the temperature rise according to 1/2 of the DC output load current. Worst-case RMS current package thermal resistance specifications. A separate draw in a circuit employing the ISL6524 amounts to the heatsink may be necessary depending upon MOSFET power, largest RMS current draw of the switching regulator. package type, ambient temperature and air flow. Use a mix of input bypass capacitors to control the voltage 2 I r V I V t F overshoot across the MOSFETs. Use ceramic capacitance P = --O----------------D----S------O-----N----------------O-----U----T--+--O---------------I--N------------S----W---------------S-- UPPER V 2 for the high frequency decoupling and bulk capacitors to IN supply the RMS current. Small ceramic capacitors can be 2 I r V –V  placed very close to the upper MOSFET to suppress the P = --O----------------D----S------O-----N-------------------I--N--------------O----U----T----- LOWER V voltage induced in the parasitic circuit impedances. IN For a through-hole design, several electrolytic capacitors The rDS(ON) is different for the two equations above even if the same device is used for both. This is because the gate (Panasonic HFQ series or Nichicon PL series or Sanyo drive applied to the upper MOSFET is different than the MV-GX or equivalent) may be needed. For surface mount lower MOSFET. Figure 13 shows the gate drive where the designs, solid tantalum capacitors can be used, but caution upper MOSFET’s gate-to-source voltage is approximately must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the VCC less the input supply. For +5V main power and +12VDC for the bias, the approximate gate-to-source voltage of Q1 is surge current at power-up. The TPS series available from 7V. The lower gate drive voltage is 12V. A logic-level AVX, and the 593D series from Sprague are both surge MOSFET is a good choice for Q1 and a logic-level MOSFET current tested. can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. FN9015 Rev 3.00 Page 13 of 17 Apr 18, 2005

ISL6524 Linear Controllers Transistor Selection +5V OR LESS +12V The ISL6524 linear controllers are compatible with both NPN bipolar as well as N-channel MOSFET transistors. The main VCC criteria for selection of pass transistors for the linear regulators is package selection for efficient removal of heat. ISL6524 UGATE Q1 The power dissipated in a linear regulator is PHASE NOTE: P = I V –V  VGS VCC -5V LINEAR O IN OUT - LGATE Q2 CR1 Select a package and heatsink that maintains the junction + temperature below the maximum desired temperature with PGND NOTE: the maximum expected ambient temperature. VGS VCC GND When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given FIGURE 13. UPPER GATE DRIVE - DIRECT VCC DRIVE operating VCE is sufficiently large to provide the desired Rectifier CR1 is a clamp that catches the negative inductor output load current when the base is fed with the minimum swing during the dead time between the turn off of the lower driver output current. MOSFET and the turn on of the upper MOSFET. For best In order to ensure the strict timing/level requirement of results, the diode must be a surface-mount Schottky type to OUT4, an NPN transistor is recommended for use as a pass prevent the parasitic MOSFET body diode from conducting. It element on this output (Q5). A low gate threshold NMOS is acceptable to omit the diode and let the body diode of the could be used, but meeting the requirements would then lower MOSFET clamp the negative inductor swing, but one depend on the VCC bias being sufficiently high to allow must ensure the PHASE node negative voltage swing does control of the MOSFET. not exceed -3V to -5V peak. The diode's rated reverse breakdown voltage must be equal or greater to 1.5 times the maximum input voltage. FN9015 Rev 3.00 Page 14 of 17 Apr 18, 2005

ISL6524 +5V L1 1H + C1 +12V 680F +3.3V GND GND C2 C3 GND 1F C4 1F 1nF VCC 28 R2 R3 FIX 2 23 10k OCSET1 1.5k HUF761Q037 DRIVE2 8 PGOOD POWER GOOD 1 VOUT2 (VTT) VSEN2 UGATE1 Q1 11 27 HUF76139 +1.2V L2 VOUT1 (CORE) + FAULT/RT 26 (1.050V to 1.825V) C6 10 PHASE1 1000F 1.8H Q2 LGATE1 + 25 HUF76143 C7-9 3x1000F PGND R7 R10 24 4.99k 10k VSEN1 C11 22 R11 0.30F VTT VTTPG U1 21 FB1 9 POWER GOOD 3.32k ISL6524 C12 R12 270pF C13 R13 VAUX COMP1 12.1k 16 20 22nF 33 C14 + C15 R14 10F 2.2nF 43k R15 Q4 267k HUF76107 DRIVE3 18 VID25 VOUT3 (AGP) 7 VSEN3 VID0 19 6 +1.5V VID1 + 5 C17 560F 4 VID2 VID3 Q5 3 2SD1802 DRIVE4 15 SS24 12 VO+U1T.48 V(MCH) VSEN4 14 13 SS13 0C.118F + 17 C20 560F GND C21 0.1F FIGURE 14. TYPICAL APPLICATION CIRCUIT ISL6524 DC-DC Converter Application memory controller hub voltage (VOUT4) from +3.3V, +5VDC, Circuit and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Figure 14 shows an application circuit of a power supply for Application Note AN9925. Also see Intersil web page a microprocessor computer system. The power supply (www.intersil.com), for the latest information. provides the microprocessor core voltage (VOUT1), the GTL bus voltage (VOUT2), the AGP bus voltage (VOUT3), and the FN9015 Rev 3.00 Page 15 of 17 Apr 18, 2005

ISL6524 © Copyright Intersil Americas LLC 2001-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9015 Rev 3.00 Page 16 of 17 Apr 18, 2005

ISL6524 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - 1 2 3 L B 0.013 0.0200 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D A h x 45o D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 -C- e 0.05 BSC 1.27 BSC - µ H 0.394 0.419 10.00 10.65 - e A1 C h 0.01 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 28 28 7  0o 8o 0o 8o - NOTES: Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. FN9015 Rev 3.00 Page 17 of 17 Apr 18, 2005