DATASHEET ISL6353 FN6897 Multiphase PWM Regulator for VR12 DDR Memory Systems Rev 0.00 September 15, 2011 The ISL6353 is a three-phase PWM buck regulator controller for Features VR12 DDR memory applications. The multi-phase implementation results in better system performance, superior • VR12 Serial Communications Bus thermal management, lower component cost and smaller PCB • Precision Voltage Regulation area. - 5mV Steps with VID Fast/Slow Slew Rates The ISL6353 has two integrated power MOSFET drivers for • Supports Two Current Sensing Methods implementing a cost effective and space saving power - Lossless Inductor DCR Current Sensing management solution. - Precision Resistor Current Sensing The PWM modulator of the ISL6353 is based on Intersil’s Robust • Programmable 1, 2 or 3-Phase Operation Ripple Regulator™ (R3) technology. Compared with the • Adaptive Body Diode Conduction Time Reduction traditional multi-phase buck regulator, the R3 modulator • Superior Noise Immunity and Transient Response commands variable PWM switching frequency during load transients, achieving faster transient response. R3 also naturally • Pin Programmable Output Voltage and Power State Mode goes into pulse frequency modulation operation in light load • Output Current Monitor and Thermal Monitor conditions to achieve higher light load efficiency. • Differential Remote Voltage Sensing The ISL6353 is designed to be completely compliant with VR12 • High Efficiency Across Entire Load Range specifications. The ISL6353 has a serial VID (SVID) bus • Programmable Switching Frequency communicating with the CPU. The output can be programmed for • Resistor Programmable VBOOT, Power State Operation, 1-,2- or 3-phase interleaved operation. The output voltage and power state can also be controlled independent of the serial VID SVID Address Setting, IMAX bus. • Excellent Dynamic Current Balance Between Phases • OCP/WOC, OVP, OT Alert, PGOOD The ISL6353 has several other key features. It supports DCR current sensing with a single NTC thermistor for DCR • Small Footprint 40 Ld 5x5 TQFN Package temperature compensation or accurate resistor current • Pb-Free (RoHS Compliant) sensing. It also has remote voltage sense, adjustable switching Applications frequency, current monitor, OC/OV protection and power-good. Temperature monitor and thermal alert is available too. • DDR Memory 95 1.5V PS0 COMP 94 1.5V PS1 2ph CCM 200mV/DIV 93 %) 92 1.5V PS2 1ph DE VDDQ = 1.5V Y ( 91 50mV/DIV C 1.35VPS0 N 90 E CI PHASE1/2/3 FI 89 1.35V PS1 2ph CCM 5V/DIV EF 88 1.35VPS2 1ph DE 87 86 26A STEP LOAD 1V/DIV 85 0 10 20 30 40 50 60 70 80 20µs/DIV LOAD (A) FIGURE 1. FAST TRANSIENT RESPONSE FIGURE 2. ISL6353EVAL1Z EFFICIENCY vs LOAD FN6897 Rev 0.00 Page 1 of 30 September 15, 2011

ISL6353 Simplified Application Circuit Using Inductor DCR Current Sensing +5VDUAL VIN +5VDUAL D N N P VD VI _O DD VIN (5VSB/12V DUAL) R V ADDR V PROG2 BOOT1 PROG1 UG1 RNTC NTC PH1 °C SDA LG1 PH1 VO1 µP { ALERT# GND SCLK VW +12V COMP BOOT2 UG2 FB PH2 VDDQ ISL6353 PH2 VO2 LG2 VCCSENSE VSEN GND VSSSENSE RTN +5V +12V FB2 1 2 3 VCTRL BOOT H H H P P P VCC UGATE ISL6596 PHASE ISEN1 DRIVER GND ISEN2 PWM ISEN3 PWM3 LGATE PH3 VO3 VSET1 VSUMN VO1 ISUMN VSET2 VO2 PSI VO3 °C ISUMP D # IMON ND PA GOOD R_HOT VP G P V O 1 2 3 H H H P P P FN6897 Rev 0.00 Page 2 of 30 September 15, 2011

ISL6353 Block Diagram VR_ON PSI VREADY PROG POWER-ON RESET VDD SDA A/D T_MONITOR (POR) ALERT# IMON DIGITAL SCLK INTERFACE VSET1 ISEN1 DAC VSET2 D/A IBAL PHASE CURRENT ISEN2 BALANCE ADDR ISEN3 IMAX PROG1 VBOOT PROG TMAX DROOP PROG2 # OF PHASES FOR PS1 VIN SET (A/D) BOOT2 T_MONITOR NTC DRIVER UG2 TEMP MONITOR VR_HOT# PH2 VW DAC + DRIVER LG2 RTN ? + + GND FB2 E/A R3 MODULATOR PWM3 FB - BOOT1 COMP DRIVER UG1 DROOP PH1 VDDP ISUMP + CURRENT SENSE OC AND WOC DRIVER LG1 PROTECTION - ISUMN GND IMON PGOOD OV PROTECTION VSEN OVP FN6897 Rev 0.00 Page 3 of 30 September 15, 2011

ISL6353 Pin Configuration ISL6353 (40 LD TQFN) TOP VIEW DDR VP SET1 SET2 SI ROG2 OOT2 G2 H2 ND A O V V P P B U P G 40 39 38 37 36 35 34 33 32 31 SDA 1 30 LG2 ALERT# 2 29 VDDP SCLK 3 28 PWM3 VR_ON 4 27 LG1 PGOOD 5 26 GND GND (BOTTOM PAD) IMON 6 25 PH1 VR_HOT# 7 24 UG1 NTC 8 23 BOOT1 VW 9 22 PROG1 COMP 10 21 VIN 11 12 13 14 15 16 17 18 19 20 B 2 3 2 1 N N N P D F B N N N E T M M D F ISE ISE ISE VS R ISU ISU V Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 2, 3 SDA, ALERT#, SCLK Serial communication bus signals connected between the CPU and the voltage regulator. 4 VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the VR. 5 PGOOD Open-drain output to indicate the regulator is ready to supply regulated voltage. Use an appropriate external pull-up resistor. 6 IMON Output current monitor pin. IMON sources a current proportional to the regulator output current. A resistor connected from this pin to ground will set a voltage that is proportional to the load current. This voltage is sampled with an internal ADC to produce a digital IMON signal that can be read through the serial communications bus. 7 VR_HOT# Thermal overload output indicator. 8 NTC Thermistor input to the VR_HOT# circuit. 9 VW Window voltage set pin used to set the switching frequency. A resistor from this pin to COMP programs the switching frequency (18k gives approximately 300kHz). 10 COMP This pin is the output of the error amplifier. 11 FB This pin is the inverting input of the error amplifier. 12 FB2 This pin switches in an RC network from VOUT to FB in PS1 and PS2 modes to help improve transient performance and phase margin when dropping phases in low power states. There is a switch between the FB2 pin and the FB pin. The switch is off in the PS0 state and on in the PS1 and PS2 states. If this function is not needed, the pin can be left open. 13 ISEN3 Individual current sensing input for Phase 3. Leave this pin open when ISL6353 is configured in 2-phase mode. 14 ISEN2 Individual current sensing input for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2, and the controller will run in 1-phase mode. 15 ISEN1 Individual current sensing input for Phase 1. 16 VSEN Output voltage sense pin. Connect to the output voltage (typically VDDQ) at the desired remote voltage sensing location. FN6897 Rev 0.00 Page 4 of 30 September 15, 2011

ISL6353 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 17 RTN Output voltage sense return pin. Connect to the ground at desired remote sensing location. 18, 19 ISUMN and ISUMP Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP. 20 VDD 5V bias power. 21 VIN Input supply voltage, used for input supply feed-forward compensation. 22 PROG1 The program pin for the voltage regulator IMAX setting. Refer to Table 6. 23 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal switch connected from the VDDP pin to the BOOT1 pin. 24 UG1 Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side MOSFET. 25 PH1 Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1. 26 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the controller or to the exposed pad on the back of the IC using a low impedance path. 27 LG1 Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side MOSFET. 28 PWM3 PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other phases to operate. 29 VDDP Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an MLCC capacitor to the ground plane close to the IC. 30 LG2 Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side MOSFET. 31 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the controller or to the exposed pad on the back of the IC using a low impedance path. 32 PH2 Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2. 33 UG2 Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side MOSFET. 34 BOOT2 Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal switch connected from the VDDP pin to the BOOT2 pin. 35 PROG2 The program pin for the voltage regulator VBOOT voltage, droop enable/disable and the number of active phases for PS1 mode. 36 PSI This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to ground, the controller will refer only to the power state indicated by the serial communication bus register. If the pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high, the controller will enter the PS2 state. 37 VSET2 This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the VID setting indicated by the serial communication bus register. 38 VSET1 This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the VID setting indicated by the serial communication bus register. 39 OVP An inverter output, latched high for an overvoltage event. It is reset by POR. 40 ADDR This pin sets the address offset register, range from 0 to 13 (0h to Dh). - GND (Bottom Pad) Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground planes in PCB internal layers. FN6897 Rev 0.00 Page 5 of 30 September 15, 2011

ISL6353 Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) MARKING (°C) (Pb-free) DWG. # ISL6353CRTZ ISL6353 CRTZ 0 to +70 40 Ld 5x5 TQFN L40.5x5 ISL6353IRTZ ISL6353 IRTZ -40 to +85 40 Ld 5x5 TQFN L40.5x5 ISL6353EVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6353. For more information on MSL please see techbrief TB363. FN6897 Rev 0.00 Page 6 of 30 September 15, 2011

ISL6353 Table of Contents Simplified Application Circuit Using Inductor DCR Current Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multiphase R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage Regulation and Differential Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 VID Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VID OFFSET Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Current Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 CCM Switching Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Phase Count Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FB2 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Adaptive Body Diode Conduction Time Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 System Parameter Programming PROG1/2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SVID ADDRESS Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 External Control of VOUT and Power State VSET1/2, PSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Supported Serial VID Data And Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FN6897 Rev 0.00 Page 7 of 30 September 15, 2011

ISL6353 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Input Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V 40 Ld TQFN Package (Notes 4, 5) . . . . . . . 32 3 Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC) Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) http://www.intersil.com/pbfree/Pb-FreeReflow.asp UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT . . . . . . . . . . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT Recommended Operating Conditions LGATE Voltage (LGATE). . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD + 0.3V . . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD +0.3V) Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V Ambient Temperature ESD Rating ISL6353CRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . .2000V ISL6353IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V Junction Temperature Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . 750V ISL6353CRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +125°C Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA ISL6353IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C for ISL6353CRTZ and TA = -40°C to +85°C for ISL6353IRTZ, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS INPUT POWER SUPPLY +5V Supply Current IVDD VR_ON = 1V 4 4.6 mA VR_ON = 0V 1 µA Input Supply Current IVIN VR_ON = 0V 1 µA Power-On-Reset Threshold PORr VDD rising 4.35 4.5 V PORf VDD falling 4.00 4.15 V PORr VIN pin rising 4.00 4.35 V PORf VIN pin falling 2.8 3.50 V SYSTEM AND REFERENCES System Accuracy CRTZ No load; closed loop, active mode range -0.5 +0.5 % %Error (VCC_CORE) VID = 0.75V to 1.50V, VID = 0.5V to 0.7375V -8 8 mV VID = 0.3V to 0.4875V -15 15 mV IRTZ No load; closed loop, active mode range -0.8 0.8 % %Error (VCC_CORE) VID = 0.75V to 1.50V, VID = 0.5V to 0.7375V -10 10 mV VID = 0.3V to 0.4875V -18 18 mV Maximum Output Voltage + Offset VCC_CORE(max) VID = FFh 1.520+ V OFFSET = 7Fh 0.635 = 2.155 Minimum Output Voltage VCC_CORE(min) VID = 01h 0.25 V OFFSET = 00h FN6897 Rev 0.00 Page 8 of 30 September 15, 2011

ISL6353 Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C for ISL6353CRTZ and TA = -40°C to +85°C for ISL6353IRTZ, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS CHANNEL FREQUENCY Nominal Channel Frequency fSW(nom) RFSET = 18kΩ, 3-channel operation, VCOMP= 1V 280 300 320 kHz Adjustment Range 200 500 kHz AMPLIFIERS Current-Sense Amplifier Input Offset IFB = 0A -0.1 +0.1 mV Error Amp DC Gain Av0 119 dB Error Amp Gain-Bandwidth Product GBW CL= 20pF 17 MHz ISEN1/2/3 Input Bias Current 20 nA POWER GOOD AND PROTECTION MONITORS PGOOD Low Voltage VOL IPGOOD = 4mA 0.26 0.4 V PGOOD Leakage Current IOH PGOOD = 3.3V -1 1 µA ALERT# Pull-Down Resistance 7 13 Ω ALERT# Leakage Current 1 µA VR_HOT# Pull-Down Resistance 7 13 Ω VR_HOT# Leakage Current 1 µA GATE DRIVER UGATE Pull-Up Resistance RUGPU 200mA Source Current 1.0 1.5 Ω UGATE Source Current IUGSRC UGATE - PHASE = 2.5V 2.0 A UGATE Sink Resistance RUGPD 250mA Sink Current 1.0 1.5 Ω UGATE Sink Current IUGSNK UGATE - PHASE = 2.5V 2.0 A LGATE Pull-Up Resistance RLGPU 250mA Source Current 1.0 1.5 Ω LGATE Source Current ILGSRC LGATE - GND = 2.5V 2.0 A LGATE Sink Resistance RLGPD 250mA Sink Current 0.5 0.9 Ω LGATE Sink Current ILGSNK LGATE - GND = 2.5V 4.0 A UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load 23 ns LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load 28 ns PROTECTION FUNCTIONS Pre-Charge Overvoltage Threshold OVP VSEN rising above setpoint for >1ms 2.29 2.35 V Overvoltage Threshold OVH VSEN rising above setpoint for >1ms 145 175 200 mV OVP Pin Sink Current IOVP VOVP = VDD-1V 20 mA Overcurrent Threshold CRTZ 3/2/1-Phase Config, PS0 56.5 60 64.5 µA IRTZ 3/2/1-Phase Config, PS0 54.5 60 64.5 µA CRTZ 3-Phase Config, PS1 - Drop to 2-Phase 38.3 40 43.2 µA IRTZ 3-Phase Config, PS1 - Drop to 2-Phase 37 40 43.2 µA CRTZ 3-Phase Config, PS1/2 - Drop to 1-Phase 19 20 22.25 µA IRTZ 3-Phase Config, PS1/2 - Drop to 1-Phase 18.5 20 22.25 µA CRTZ 2-Phase Config, PS1/2 - Drop to 1-Phase 28 30 33 µA IRTZ 2-Phase Config, PS1/2 - Drop to 1-Phase 27 30 33 µA FN6897 Rev 0.00 Page 9 of 30 September 15, 2011

ISL6353 Electrical Specifications Operating Conditions: VDD = 5V, TA = 0°C to +70°C for ISL6353CRTZ and TA = -40°C to +85°C for ISL6353IRTZ, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS Way Overcurrent Threshold CRTZ 3/2/1-Phase Config, PS0 76.8 88 100 µA IRTZ 3/2/1-Phase Config, PS0 74 88 100 µA CRTZ 3-Phase Config, PS1 - Drop to 2-Phase 52 60 68 µA IRTZ 3-Phase Config, PS1 - Drop to 2-Phase 50 60 68 µA CRTZ 3-Phase Config, PS1/2 - Drop to 1-Phase 28 32 35.8 µA IRTZ 3-Phase Config, PS1/2 - Drop to 1-Phase 27 32 35.8 µA CRTZ 2-Phase Config, PS1/2 - Drop to 1-Phase 40 46 52 µA IRTZ 2-Phase Config, PS1/2 - Drop to 1-Phase 39.5 46 52 µA Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 20 mV PWM PWM3 Output Low VOL_MAX Sinking 5mA 1.0 V PWM3 Output High VOH_MIN Sourcing 5mA 3.5 V PWM3 Tri-State Leakage PWM3 = 2.5V 2 µA THERMAL MONITOR NTC Source Current CRTZ NTC = 1.3V 58 60 62 µA IRTZ NTC = 1.3V 56 60 62 µA VR_HOT# Trip Voltage Falling 0.895 0.91 V VR_HOT# Reset Voltage Rising 0.95 0.965 V ALERT# Trip Voltage Falling 0.915 0.93 V ALERT# Reset Voltage Rising 0.97 0.985 V CURRENT MONITOR IMON Output Current IIMON ISUM- pin current = 50µA 12.3 12.45 12.6 µA ISUM- pin current = 2µA 400 500 600 nA IccMAX Alert Trip Voltage VIMONMAX Rising 1.2 1.225 V IccMAX Alert Reset Voltage Falling 1.05 1.14 V INPUTS VR_ON Input Low VIL_MAX 0.3 V VR_ON Input High VIH_MIN 0.8 V VR_ON Leakage Current IVR_ON VR_ON = 0V -1 0 µA VR_ON = 1V, 300kΩTypical Pull-Down 3.3 µA VSET1/2 Input Low VSETIL_MAX 1.5 V VSET1/2 Input High VSETIH_MIN 3.1 V PSI Sink/Source Current PSI Voltage 12 16 20 µA PSI Pin State PS0, VDD=5V 0 0.51 V PS1, VDD=5V 1.06 3.91 V PS2, VDD=5V 4.47 5 V PSI High-Z Voltage 2.12 2.37 2.60 V SCLK, SDA SCLK, SDA Leakage VR_ON = 0V, SCLK & SDA = 0V & 1V -1 1 µA VR_ON = 1V, SCLK & SDA = 1V -5 1 µA VR_ON = 1V, SDA = 0V 20 µA VR_ON = 1V, SCLK = 0V 40 µA NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN6897 Rev 0.00 Page 10 of 30 September 15, 2011

ISL6353 Gate Driver Timing Diagram PWM tLGFUGR tFU tRU UGATE 1V LGATE 1V tRL tFL tUGFLGR Theory of Operation VW 3 Multiphase R Modulator V HYSTERETIC crm WINDOW VW MASTER CLOCK CIRCUIT COMP MASTER MCALSOTCEKR VcCrmOMP CLOCKSePqhuaesnec er CClloocckk12 MASTER Clock3 CLOCK gmVo Crm CLOCK1 SLAVE CIRCUIT 1 VW Clock1 SQ PWM1Phase1 L1 Vo PWM1 R IL1 Co CLOCK2 Vcrs1 gm PWM2 Crs1 CLOCK3 SLAVE CIRCUIT 2 VW Clock2 SQ PWM2Phase2 L2 PWM3 R IL2 VW Vcrs2 gm Crs2 V V V SLAVE CIRCUIT 3 crs2 crs3 crs1 VW Clock3 SQ PWM3Phase3 L3 R IL3 FIGURE 4. R3 MODULATOR OPERATION PRINCIPLES IN STEADY STATE Vcrs3 gm Crs3 FIGURE 3. R3 MODULATOR CIRCUIT FN6897 Rev 0.00 Page 11 of 30 September 15, 2011

ISL6353 voltage VCrs hits VW, the slave circuit turns off the PWM pulse, VW and the current source discharges Crs. Since the ISL6353 individual phase modulators use a large-amplitude and noise-free synthesized signal, Vcrs, to COMP determine the pulse width, phase jitter is lower than conventional Vcrm hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the ISL6353 has an Master error amplifier that allows the controller to maintain 0.5% output Clock voltage accuracy. Clock1 Figure 5 shows the principle of operation during a load step-up PWM1 response. The COMP voltage rises after the load step up, Clock2 generating master clock pulses more quickly, so PWM pulses turn on earlier, increasing the effective switching frequency. This PWM2 allows for higher control loop bandwidth than conventional fixed Clock3 frequency PWM controllers. The VW voltage rises as the COMP PWM3 voltage rises, making the PWM pulses wider as well. During load step-down response, COMP voltage falls. It takes the master VW clock circuit longer to generate the next clock signal, so the PWM pulse is held off until needed. The VW voltage falls as the COMP voltage falls, reducing the current PWM pulse width. This kind of behavior gives the ISL6353 excellent load transient response. Vcrs1 Vcrs3 The fact that all the phases share the same VW window voltage Vcrs2 also ensures excellent dynamic current balance among phases. FIGURE 5. R3 MODULATOR OPERATION DURING A LOAD Diode Emulation and Period Stretching STEP-UP RESPONSE The ISL6353 is a multiphase regulator controller implementing the Intel VR12™ protocol primarily intended for use in DDR memory regulator applications. It can be programmed for 1-, 2- or PHASE 3-phase operation. It uses Intersil’s patented R3 (Robust Ripple Regulator™) modulator. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while UGATE eliminating many of their respective shortcomings. Figure 3 conceptually shows the ISL6353 multiphase R3 modulator circuit, LGATE and Figure4 shows the principle of operation. A current source flows from the VW pin to the COMP pin, creating IL a voltage window set by the resistor between the two pins. This voltage window is called the VW window in the following discussion. FIGURE 6. DIODE EMULATION OPERATION Inside the IC, the modulator uses the master clock circuit to ISL6353 can operate in diode emulation (DE) mode to improve generate the clocks for the slave circuits. The modulator discharges light load efficiency. In DE mode, the low-side MOSFET conducts the ripple capacitor Crm with a current source equal to gmVo, where when the current is flowing from source to drain and does not gm is a gain factor. The Crm voltage Vcrm is a sawtooth waveform allow reverse current, thus emulating a diode. As Figure 6 shows, traversing between the VW and COMP voltages. It resets to VW when LGATE is on, the low-side MOSFET carries current, creating when it hits COMP, and generates a one-shot master clock signal. A negative voltage on the phase node due to the voltage drop across phase sequencer distributes the master clock signal to the slave the ON-resistance. The ISL6353 monitors the current by circuits. If the ISL6353 is in 3-phase mode, the master clock signal monitoring the phase node voltage. It turns off LGATE when the will be distributed to the three phases, and the Clock1~3 signals will phase node voltage reaches zero to prevent the inductor current be 120° out-of-phase. If the ISL6353 is in 2-phase mode, the from reversing direction and creating unnecessary power loss. master clock signal will be distributed to Phases 1 and 2, and the Clock1 and Clock2 signals will be 180° out-of-phase. If the ISL6353 If the load current is light enough, as Figure 6 shows, the inductor is in 1-phase mode, the master clock signal will be distributed to current will reach and stay at zero before the next phase node Phase 1 only and is the Clock1 signal. pulse, and the regulator is in discontinuous conduction mode (DCM). If the load current is heavy enough, the inductor current Each slave circuit has its own ripple capacitor Crs, whose voltage will never reach 0A, and the regulator is in CCM although the mimics the inductor ripple current. A gm amplifier converts the controller is in DE mode. inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source charges Crs. When Crs FN6897 Rev 0.00 Page 12 of 30 September 15, 2011

ISL6353 CCM/DCM BOUNDARY VDD VW V VR_ON crs 2.5mV/µs VBOOT 1.3ms iL DAC LIGHT DCM VW PGOOD Vcrs READY FOR SVID COMMAND FIGURE 8. SOFT-START WAVEFORMS iL Voltage Regulation and Differential Sensing DEEP DCM VW V After the start sequence, the ISL6353 regulates the output voltage crs to the value set by the SetVID commands through the SVID bus or to the value set by the status of the VSET1/2 pins. The ISL6353 will regulate the output voltage to VID + OFFSET (Register 33h). A differential amplifier allows remote voltage sensing for precise iL voltage regulation. VID Table FIGURE 7. PERIOD STRETCHING Figure 7 shows the principle of operation in diode emulation mode The ISL6353 will regulate the output voltage to VID+OFFSET (33h). at light load. The load gets incrementally lighter in the three cases Table 1 shows the output voltage setting based on the VID register from top to bottom. The PWM on-time is determined by the VW setting. window size and therefore it is the same, making the inductor TABLE 1. VID TABLE current triangle the same in the three cases. The ISL6353 clamps the ripple capacitor voltage Vcrs in DE mode to make it mimic the VO VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) inductor current. It takes the COMP voltage longer to hit Vcrs, naturally stretching the switching period. The inductor current 0 0 0 0 0 0 0 0 0 0 0.0000 triangles move further apart from each other such that the 0 0 0 0 0 0 0 1 0 1 0.2500 inductor current average value is equal to the load current. The 0 0 0 0 0 0 1 0 0 2 0.2550 reduced switching frequency helps increase light load efficiency. 0 0 0 0 0 0 1 1 0 3 0.2600 Start-up Timing 0 0 0 0 0 1 0 0 0 4 0.2650 With the controller's VDD voltage above the POR threshold, the 0 0 0 0 0 1 0 1 0 5 0.2700 start-up sequence begins about 1.3ms after VR_ON exceeds the logic high threshold. The ISL6353 uses digital soft-start to ramp 0 0 0 0 0 1 1 0 0 6 0.2750 up the DAC to the boot voltage, VBOOT. VBOOT is set by the PROG2 0 0 0 0 0 1 1 1 0 7 0.2800 pin resistor and the status of the VSET1/2 pins. The DAC slew 0 0 0 0 1 0 0 0 0 8 0.2850 rate during soft-start is about 2.5mV/µs. PGOOD is asserted high at the end of the start-up sequence indicating that the output 0 0 0 0 1 0 0 1 0 9 0.2900 voltage has moved to the VBOOT setting, the VR is operating 0 0 0 0 1 0 1 0 0 A 0.2950 properly and all phases are switching. Figure 8 shows the typical 0 0 0 0 1 0 1 1 0 B 0.3000 start-up timing. 0 0 0 0 1 1 0 0 0 C 0.3050 0 0 0 0 1 1 0 1 0 D 0.3100 0 0 0 0 1 1 1 0 0 E 0.3150 0 0 0 0 1 1 1 1 0 F 0.3200 0 0 0 1 0 0 0 0 1 0 0.3250 0 0 0 1 0 0 0 1 1 1 0.3300 0 0 0 1 0 0 1 0 1 2 0.3350 0 0 0 1 0 0 1 1 1 3 0.3400 0 0 0 1 0 1 0 0 1 4 0.3450 0 0 0 1 0 1 0 1 1 5 0.3500 FN6897 Rev 0.00 Page 13 of 30 September 15, 2011

ISL6353 TABLE 1. VID TABLE (Continued) TABLE 1. VID TABLE (Continued) VO VO VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) 0 0 0 1 0 1 1 0 1 6 0.3550 0 1 0 0 0 0 0 0 4 0 0.5650 0 0 0 1 0 1 1 1 1 7 0.3600 0 1 0 0 0 0 0 1 4 1 0.5700 0 0 0 1 1 0 0 0 1 8 0.3650 0 1 0 0 0 0 1 0 4 2 0.5750 0 0 0 1 1 0 0 1 1 9 0.3700 0 1 0 0 0 0 1 1 4 3 0.5800 0 0 0 1 1 0 1 0 1 A 0.3750 0 1 0 0 0 1 0 0 4 4 0.5850 0 0 0 1 1 0 1 1 1 B 0.3800 0 1 0 0 0 1 0 1 4 5 0.5900 0 0 0 1 1 1 0 0 1 C 0.3850 0 1 0 0 0 1 1 0 4 6 0.5950 0 0 0 1 1 1 0 1 1 D 0.3900 0 1 0 0 0 1 1 1 4 7 0.6000 0 0 0 1 1 1 1 0 1 E 0.3950 0 1 0 0 1 0 0 0 4 8 0.6050 0 0 0 1 1 1 1 1 1 F 0.4000 0 1 0 0 1 0 0 1 4 9 0.6100 0 0 1 0 0 0 0 0 2 0 0.4050 0 1 0 0 1 0 1 0 4 A 0.6150 0 0 1 0 0 0 0 1 2 1 0.4100 0 1 0 0 1 0 1 1 4 B 0.6200 0 0 1 0 0 0 1 0 2 2 0.4150 0 1 0 0 1 1 0 0 4 C 0.6250 0 0 1 0 0 0 1 1 2 3 0.4200 0 1 0 0 1 1 0 1 4 D 0.6300 0 0 1 0 0 1 0 0 2 4 0.4250 0 1 0 0 1 1 1 0 4 E 0.6350 0 0 1 0 0 1 0 1 2 5 0.4300 0 1 0 0 1 1 1 1 4 F 0.6400 0 0 1 0 0 1 1 0 2 6 0.4350 0 1 0 1 0 0 0 0 5 0 0.6450 0 0 1 0 0 1 1 1 2 7 0.4400 0 1 0 1 0 0 0 1 5 1 0.6500 0 0 1 0 1 0 0 0 2 8 0.4450 0 1 0 1 0 0 1 0 5 2 0.6550 0 0 1 0 1 0 0 1 2 9 0.4500 0 1 0 1 0 0 1 1 5 3 0.6600 0 0 1 0 1 0 1 0 2 A 0.4550 0 1 0 1 0 1 0 0 5 4 0.6650 0 0 1 0 1 0 1 1 2 B 0.4600 0 1 0 1 0 1 0 1 5 5 0.6700 0 0 1 0 1 1 0 0 2 C 0.4650 0 1 0 1 0 1 1 0 5 6 0.6750 0 0 1 0 1 1 0 1 2 D 0.4700 0 1 0 1 0 1 1 1 5 7 0.6800 0 0 1 0 1 1 1 0 2 E 0.4750 0 1 0 1 1 0 0 0 5 8 0.6850 0 0 1 0 1 1 1 1 2 F 0.4800 0 1 0 1 1 0 0 1 5 9 0.6900 0 0 1 1 0 0 0 0 3 0 0.4850 0 1 0 1 1 0 1 0 5 A 0.6950 0 0 1 1 0 0 0 1 3 1 0.4900 0 1 0 1 1 0 1 1 5 B 0.7000 0 0 1 1 0 0 1 0 3 2 0.4950 0 1 0 1 1 1 0 0 5 C 0.7050 0 0 1 1 0 0 1 1 3 3 0.5000 0 1 0 1 1 1 0 1 5 D 0.7100 0 0 1 1 0 1 0 0 3 4 0.5050 0 1 0 1 1 1 1 0 5 E 0.7150 0 0 1 1 0 1 0 1 3 5 0.5100 0 1 0 1 1 1 1 1 5 F 0.7200 0 0 1 1 0 1 1 0 3 6 0.5150 0 1 1 0 0 0 0 0 6 0 0.7250 0 0 1 1 0 1 1 1 3 7 0.5200 0 1 1 0 0 0 0 1 6 1 0.7300 0 0 1 1 1 0 0 0 3 8 0.5250 0 1 1 0 0 0 1 0 6 2 0.7350 0 0 1 1 1 0 0 1 3 9 0.5300 0 1 1 0 0 0 1 1 6 3 0.7400 0 0 1 1 1 0 1 0 3 A 0.5350 0 1 1 0 0 1 0 0 6 4 0.7450 0 0 1 1 1 0 1 1 3 B 0.5400 0 1 1 0 0 1 0 1 6 5 0.7500 0 0 1 1 1 1 0 0 3 C 0.5450 0 1 1 0 0 1 1 0 6 6 0.7550 0 0 1 1 1 1 0 1 3 D 0.5500 0 1 1 0 0 1 1 1 6 7 0.7600 0 0 1 1 1 1 1 0 3 E 0.5550 0 1 1 0 1 0 0 0 6 8 0.7650 0 0 1 1 1 1 1 1 3 F 0.5600 0 1 1 0 1 0 0 1 6 9 0.7700 FN6897 Rev 0.00 Page 14 of 30 September 15, 2011

ISL6353 TABLE 1. VID TABLE (Continued) TABLE 1. VID TABLE (Continued) VO VO VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) 0 1 1 0 1 0 1 0 6 A 0.7750 1 0 0 1 0 1 0 0 9 4 0.9850 0 1 1 0 1 0 1 1 6 B 0.7800 1 0 0 1 0 1 0 1 9 5 0.9900 0 1 1 0 1 1 0 0 6 C 0.7850 1 0 0 1 0 1 1 0 9 6 0.9950 0 1 1 0 1 1 0 1 6 D 0.7900 1 0 0 1 0 1 1 1 9 7 1.0000 0 1 1 0 1 1 1 0 6 E 0.7950 1 0 0 1 1 0 0 0 9 8 1.0050 0 1 1 0 1 1 1 1 6 F 0.8000 1 0 0 1 1 0 0 1 9 9 1.0100 0 1 1 1 0 0 0 0 7 0 0.8050 1 0 0 1 1 0 1 0 9 A 1.0150 0 1 1 1 0 0 0 1 7 1 0.8100 1 0 0 1 1 0 1 1 9 B 1.0200 0 1 1 1 0 0 1 0 7 2 0.8150 1 0 0 1 1 1 0 0 9 C 1.0250 0 1 1 1 0 0 1 1 7 3 0.8200 1 0 0 1 1 1 0 1 9 D 1.0300 0 1 1 1 0 1 0 0 7 4 0.8250 1 0 0 1 1 1 1 0 9 E 1.0350 0 1 1 1 0 1 0 1 7 5 0.8300 1 0 0 1 1 1 1 1 9 F 1.0400 0 1 1 1 0 1 1 0 7 6 0.8350 1 0 1 0 0 0 0 0 A 0 1.0450 0 1 1 1 0 1 1 1 7 7 0.8400 1 0 1 0 0 0 0 1 A 1 1.0500 0 1 1 1 1 0 0 0 7 8 0.8450 1 0 1 0 0 0 1 0 A 2 1.0550 0 1 1 1 1 0 0 1 7 9 0.8500 1 0 1 0 0 0 1 1 A 3 1.0600 0 1 1 1 1 0 1 0 7 A 0.8550 1 0 1 0 0 1 0 0 A 4 1.0650 0 1 1 1 1 0 1 1 7 B 0.8600 1 0 1 0 0 1 0 1 A 5 1.0700 0 1 1 1 1 1 0 0 7 C 0.8650 1 0 1 0 0 1 1 0 A 6 1.0750 0 1 1 1 1 1 0 1 7 D 0.8700 1 0 1 0 0 1 1 1 A 7 1.0800 0 1 1 1 1 1 1 0 7 E 0.8750 1 0 1 0 1 0 0 0 A 8 1.0850 0 1 1 1 1 1 1 1 7 F 0.8800 1 0 1 0 1 0 0 1 A 9 1.0900 1 0 0 0 0 0 0 0 8 0 0.8850 1 0 1 0 1 0 1 0 A A 1.0950 1 0 0 0 0 0 0 1 8 1 0.8900 1 0 1 0 1 0 1 1 A B 1.1000 1 0 0 0 0 0 1 0 8 2 0.8950 1 0 1 0 1 1 0 0 A C 1.1050 1 0 0 0 0 0 1 1 8 3 0.9000 1 0 1 0 1 1 0 1 A D 1.1100 1 0 0 0 0 1 0 0 8 4 0.9050 1 0 1 0 1 1 1 0 A E 1.1150 1 0 0 0 0 1 0 1 8 5 0.9100 1 0 1 0 1 1 1 1 A F 1.1200 1 0 0 0 0 1 1 0 8 6 0.9150 1 0 1 1 0 0 0 0 B 0 1.1250 1 0 0 0 0 1 1 1 8 7 0.9200 1 0 1 1 0 0 0 1 B 1 1.1300 1 0 0 0 1 0 0 0 8 8 0.9250 1 0 1 1 0 0 1 0 B 2 1.1350 1 0 0 0 1 0 0 1 8 9 0.9300 1 0 1 1 0 0 1 1 B 3 1.1400 1 0 0 0 1 0 1 0 8 A 0.9350 1 0 1 1 0 1 0 0 B 4 1.1450 1 0 0 0 1 0 1 1 8 B 0.9400 1 0 1 1 0 1 0 1 B 5 1.1500 1 0 0 0 1 1 0 0 8 C 0.9450 1 0 1 1 0 1 1 0 B 6 1.1550 1 0 0 0 1 1 0 1 8 D 0.9500 1 0 1 1 0 1 1 1 B 7 1.1600 1 0 0 0 1 1 1 0 8 E 0.9550 1 0 1 1 1 0 0 0 B 8 1.1650 1 0 0 0 1 1 1 1 8 F 0.9600 1 0 1 1 1 0 0 1 B 9 1.1700 1 0 0 1 0 0 0 0 9 0 0.9650 1 0 1 1 1 0 1 0 B A 1.1750 1 0 0 1 0 0 0 1 9 1 0.9700 1 0 1 1 1 0 1 1 B B 1.1800 1 0 0 1 0 0 1 0 9 2 0.9750 1 0 1 1 1 1 0 0 B C 1.1850 1 0 0 1 0 0 1 1 9 3 0.9800 1 0 1 1 1 1 0 1 B D 1.1900 FN6897 Rev 0.00 Page 15 of 30 September 15, 2011

ISL6353 TABLE 1. VID TABLE (Continued) TABLE 1. VID TABLE (Continued) VO VO VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex (V) 1 0 1 1 1 1 1 0 B E 1.1950 1 1 1 0 1 0 0 0 E 8 1.4050 1 0 1 1 1 1 1 1 B F 1.2000 1 1 1 0 1 0 0 1 E 9 1.4100 1 1 0 0 0 0 0 0 C 0 1.2050 1 1 1 0 1 0 1 0 E A 1.4150 1 1 0 0 0 0 0 1 C 1 1.2100 1 1 1 0 1 0 1 1 E B 1.4200 1 1 0 0 0 0 1 0 C 2 1.2150 1 1 1 0 1 1 0 0 E C 1.4250 1 1 0 0 0 0 1 1 C 3 1.2200 1 1 1 0 1 1 0 1 E D 1.4300 1 1 0 0 0 1 0 0 C 4 1.2250 1 1 1 0 1 1 1 0 E E 1.4350 1 1 0 0 0 1 0 1 C 5 1.2300 1 1 1 0 1 1 1 1 E F 1.4400 1 1 0 0 0 1 1 0 C 6 1.2350 1 1 1 1 0 0 0 0 F 0 1.4450 1 1 0 0 0 1 1 1 C 7 1.2400 1 1 1 1 0 0 0 1 F 1 1.4500 1 1 0 0 1 0 0 0 C 8 1.2450 1 1 1 1 0 0 1 0 F 2 1.4550 1 1 0 0 1 0 0 1 C 9 1.2500 1 1 1 1 0 0 1 1 F 3 1.4600 1 1 0 0 1 0 1 0 C A 1.2550 1 1 1 1 0 1 0 0 F 4 1.4650 1 1 0 0 1 0 1 1 C B 1.2600 1 1 1 1 0 1 0 1 F 5 1.4700 1 1 0 0 1 1 0 0 C C 1.2650 1 1 1 1 0 1 1 0 F 6 1.4750 1 1 0 0 1 1 0 1 C D 1.2700 1 1 1 1 0 1 1 1 F 7 1.4800 1 1 0 0 1 1 1 0 C E 1.2750 1 1 1 1 1 0 0 0 F 8 1.4850 1 1 0 0 1 1 1 1 C F 1.2800 1 1 1 1 1 0 0 1 F 9 1.4900 1 1 0 1 0 0 0 0 D 0 1.2850 1 1 1 1 1 0 1 0 F A 1.4950 1 1 0 1 0 0 0 1 D 1 1.2900 1 1 1 1 1 0 1 1 F B 1.5000 1 1 0 1 0 0 1 0 D 2 1.2950 1 1 1 1 1 1 0 0 F C 1.5050 1 1 0 1 0 0 1 1 D 3 1.3000 1 1 1 1 1 1 0 1 F D 1.5100 1 1 0 1 0 1 0 0 D 4 1.3050 1 1 1 1 1 1 1 0 F E 1.5150 1 1 0 1 0 1 0 1 D 5 1.3100 1 1 1 1 1 1 1 1 F F 1.5200 1 1 0 1 0 1 1 0 D 6 1.3150 VID OFFSET Table 1 1 0 1 0 1 1 1 D 7 1.3200 The ISL6353 will regulate the output voltage to VID+OFFSET (33h). 1 1 0 1 1 0 0 0 D 8 1.3250 Table 2 shows the output voltage setting based on the VID register 1 1 0 1 1 0 0 1 D 9 1.3300 setting. 1 1 0 1 1 0 1 0 D A 1.3350 TABLE 2. VID TABLE 1 1 0 1 1 0 1 1 D B 1.3400 VOFS 1 1 0 1 1 1 0 0 D C 1.3450 OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 Hex (V) 1 1 0 1 1 1 0 1 D D 1.3500 0 0 0 0 0 0 0 0 0 0 0.0000 1 1 0 1 1 1 1 0 D E 1.3550 0 0 0 0 0 0 0 1 0 1 0.005 1 1 0 1 1 1 1 1 D F 1.3600 0 0 0 0 0 0 1 0 0 2 0.010 1 1 1 0 0 0 0 0 E 0 1.3650 0 0 0 0 0 0 1 1 0 3 0.015 1 1 1 0 0 0 0 1 E 1 1.3700 0 0 0 0 0 1 0 0 0 4 0.020 1 1 1 0 0 0 1 0 E 2 1.3750 0 0 0 0 0 1 0 1 0 5 0.025 1 1 1 0 0 0 1 1 E 3 1.3800 0 0 0 0 0 1 1 0 0 6 0.030 1 1 1 0 0 1 0 0 E 4 1.3850 0 0 0 0 0 1 1 1 0 7 0.035 1 1 1 0 0 1 0 1 E 5 1.3900 0 0 0 0 1 0 0 0 0 8 0.040 1 1 1 0 0 1 1 0 E 6 1.3950 0 0 0 0 1 0 0 1 0 9 0.045 1 1 1 0 0 1 1 1 E 7 1.4000 0 0 0 0 1 0 1 0 0 A 0.050 FN6897 Rev 0.00 Page 16 of 30 September 15, 2011

ISL6353 TABLE 2. VID TABLE (Continued) TABLE 2. VID TABLE (Continued) VOFS VOFS OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 Hex (V) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 Hex (V) 0 0 0 0 1 0 1 1 0 B 0.055 0 0 1 1 0 1 0 1 3 5 0.265 0 0 0 0 1 1 0 0 0 C 0.060 0 0 1 1 0 1 1 0 3 6 0.270 0 0 0 0 1 1 0 1 0 D 0.065 0 0 1 1 0 1 1 1 3 7 0.275 0 0 0 0 1 1 1 0 0 E 0.070 0 0 1 1 1 0 0 0 3 8 0.280 0 0 0 0 1 1 1 1 0 F 0.075 0 0 1 1 1 0 0 1 3 9 0.285 0 0 0 1 0 0 0 0 1 0 0.080 0 0 1 1 1 0 1 0 3 A 0.290 0 0 0 1 0 0 0 1 1 1 0.085 0 0 1 1 1 0 1 1 3 B 0.295 0 0 0 1 0 0 1 0 1 2 0.090 0 0 1 1 1 1 0 0 3 C 0.300 0 0 0 1 0 0 1 1 1 3 0.095 0 0 1 1 1 1 0 1 3 D 0.305 0 0 0 1 0 1 0 0 1 4 0.100 0 0 1 1 1 1 1 0 3 E 0.310 0 0 0 1 0 1 0 1 1 5 0.105 0 0 1 1 1 1 1 1 3 F 0.315 0 0 0 1 0 1 1 0 1 6 0.110 0 1 0 0 0 0 0 0 4 0 0.320 0 0 0 1 0 1 1 1 1 7 0.115 0 1 0 0 0 0 0 1 4 1 0.325 0 0 0 1 1 0 0 0 1 8 0.120 0 1 0 0 0 0 1 0 4 2 0.330 0 0 0 1 1 0 0 1 1 9 0.125 0 1 0 0 0 0 1 1 4 3 0.335 0 0 0 1 1 0 1 0 1 A 0.130 0 1 0 0 0 1 0 0 4 4 0.340 0 0 0 1 1 0 1 1 1 B 0.135 0 1 0 0 0 1 0 1 4 5 0.345 0 0 0 1 1 1 0 0 1 C 0.140 0 1 0 0 0 1 1 0 4 6 0.350 0 0 0 1 1 1 0 1 1 D 0.145 0 1 0 0 0 1 1 1 4 7 0.355 0 0 0 1 1 1 1 0 1 E 0.150 0 1 0 0 1 0 0 0 4 8 0.360 0 0 0 1 1 1 1 1 1 F 0.155 0 1 0 0 1 0 0 1 4 9 0.365 0 0 1 0 0 0 0 0 2 0 0.160 0 1 0 0 1 0 1 0 4 A 0.370 0 0 1 0 0 0 0 1 2 1 0.165 0 1 0 0 1 0 1 1 4 B 0.375 0 0 1 0 0 0 1 0 2 2 0.170 0 1 0 0 1 1 0 0 4 C 0.380 0 0 1 0 0 0 1 1 2 3 0.175 0 1 0 0 1 1 0 1 4 D 0.385 0 0 1 0 0 1 0 0 2 4 0.180 0 1 0 0 1 1 1 0 4 E 0.390 0 0 1 0 0 1 0 1 2 5 0.185 0 1 0 0 1 1 1 1 4 F 0.395 0 0 1 0 0 1 1 0 2 6 0.190 0 1 0 1 0 0 0 0 5 0 0.400 0 0 1 0 0 1 1 1 2 7 0.195 0 1 0 1 0 0 0 1 5 1 0.405 0 0 1 0 1 0 0 0 2 8 0.200 0 1 0 1 0 0 1 0 5 2 0.410 0 0 1 0 1 0 0 1 2 9 0.205 0 1 0 1 0 0 1 1 5 3 0.415 0 0 1 0 1 0 1 0 2 A 0.210 0 1 0 1 0 1 0 0 5 4 0.420 0 0 1 0 1 0 1 1 2 B 0.215 0 1 0 1 0 1 0 1 5 5 0.425 0 0 1 0 1 1 0 0 2 C 0.220 0 1 0 1 0 1 1 0 5 6 0.430 0 0 1 0 1 1 0 1 2 D 0.225 0 1 0 1 0 1 1 1 5 7 0.435 0 0 1 0 1 1 1 0 2 E 0.230 0 1 0 1 1 0 0 0 5 8 0.440 0 0 1 0 1 1 1 1 2 F 0.235 0 1 0 1 1 0 0 1 5 9 0.445 0 0 1 1 0 0 0 0 3 0 0.240 0 1 0 1 1 0 1 0 5 A 0.450 0 0 1 1 0 0 0 1 3 1 0.245 0 1 0 1 1 0 1 1 5 B 0.455 0 0 1 1 0 0 1 0 3 2 0.250 0 1 0 1 1 1 0 0 5 C 0.460 0 0 1 1 0 0 1 1 3 3 0.255 0 1 0 1 1 1 0 1 5 D 0.465 0 0 1 1 0 1 0 0 3 4 0.260 0 1 0 1 1 1 1 0 5 E 0.470 FN6897 Rev 0.00 Page 17 of 30 September 15, 2011

ISL6353 TABLE 2. VID TABLE (Continued) VOFS OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 Hex (V) 0 1 0 1 1 1 1 1 5 F 0.475 VCCSENSE 0 1 1 0 0 0 0 0 6 0 0.480 FB VR LOCAL VO 0 1 1 0 0 0 0 1 6 1 0.485 “CATCH” RESISTOR 0 1 1 0 0 0 1 0 6 2 0.490 E/A 0 1 1 0 0 0 1 1 6 3 0.495 COMP  DAC VDAC 0 1 1 0 0 1 0 0 6 4 0.500 RTN 0 1 1 0 0 1 0 1 6 5 0.505 VSSSENSE INTERNAL TO IC X 1 VSS 0 1 1 0 0 1 1 0 6 6 0.510 0 1 1 0 0 1 1 1 6 7 0.515 “CATCH” RESISTOR 0 1 1 0 1 0 0 0 6 8 0.520 FIGURE 9. DIFFERENTIAL SENSING 0 1 1 0 1 0 0 1 6 9 0.525 Figure 9 shows the differential voltage sensing scheme. VCCSENSE 0 1 1 0 1 0 1 0 6 A 0.530 and VSSSENSE are the remote voltage sensing signals from the DDR 0 1 1 0 1 0 1 1 6 B 0.535 memory. A unity gain differential amplifier senses the VSSSENSE voltage and adds it to the DAC output. The error amplifier regulates 0 1 1 0 1 1 0 0 6 C 0.540 the inverting and the non-inverting input voltages to be equal as 0 1 1 0 1 1 0 1 6 D 0.545 shown in Equation 1: 0 1 1 0 1 1 1 0 6 E 0.550 VCCSENSE = VDAC+VSSSENSE (EQ. 1) 0 1 1 0 1 1 1 1 6 F 0.555 Rewriting Equation 1 gives Equation 2: 0 1 1 1 0 0 0 0 7 0 0.560 VCCSENSE–VSSSENSE = VDAC (EQ. 2) 0 1 1 1 0 0 0 1 7 1 0.565 The VCCSENSE and VSSSENSE signals are routed from the 0 1 1 1 0 0 1 0 7 2 0.570 memory socket. In most cases the remote sensing location will 0 1 1 1 0 0 1 1 7 3 0.575 be on the PCB right next to one of the DDR memory sockets. If a remote sensing location is used on a module that passes through 0 1 1 1 0 1 0 0 7 4 0.580 a socket then the feedback signals will be open circuit in the 0 1 1 1 0 1 0 1 7 5 0.585 absence of the module. As shown in Figure 9, a “catch” resistor 0 1 1 1 0 1 1 0 7 6 0.590 should be added in this case to feed the local VR output voltage back to the compensator, and another “catch” resistor should be 0 1 1 1 0 1 1 1 7 7 0.595 added to connect the local VR output ground to the RTN pin. 0 1 1 1 1 0 0 0 7 8 0.600 These resistors, typically 10~100, will provide voltage 0 1 1 1 1 0 0 1 7 9 0.605 feedback if the system is powered up without any memory cards installed. 0 1 1 1 1 0 1 0 7 A 0.610 0 1 1 1 1 0 1 1 7 B 0.615 Inductor DCR Current-Sensing Network 0 1 1 1 1 1 0 0 7 C 0.620 The ISL6353 can sense the inductor current through the intrinsic DC 0 1 1 1 1 1 0 1 7 D 0.625 Resistance (DCR) of the inductors or through precision resistors in 0 1 1 1 1 1 1 0 7 E 0.630 series with the inductors. With both current-sensing methods, the voltage across capacitor Cn represents the total inductor current 0 1 1 1 1 1 1 1 7 F 0.635 from all phases. An amplifier converts the Cn voltage, VCn, into an internal current source, Isense, with the gain set by resistor Ri shown in Equation 3. V I = ----C---n-- (EQ. 3) sense R i FN6897 Rev 0.00 Page 18 of 30 September 15, 2011

ISL6353 The sensed current is used for current monitoring and overcurrent protection. DCR (EQ. 7)  = ------------ L L Phase1 Phase2 Phase3 1  = ------------------------------------------------------ sns R Rsum R -----s--u----m--- -----n---t--c---n---e---t--------------N--------C (EQ. 8) Rsum R n R +-----s--u----m--- Rsum ISUM+ ntcnet N where N is the number of phases. L L L Rntcs Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, Rp CnVcn giving higher a reading of the inductor DC current. The NTC Rntc Rntc values decreases as its temperature increases. Proper selections DCR DCR DCR Ro Ri ISUM- of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represents the total inductor DC current over the temperature Ro range of interest. Ro There are many sets of parameters that can properly temperature- compensate the DCR change. Since the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the Io inductor DCR voltage. A higher ratio of Vcn to the inductor DCR voltage is recommended so the current monitor and OCP circuit has FIGURE 10. DCR CURRENT-SENSING NETWORK a higher signal level to work with. Figure 10 shows the inductor DCR current-sensing network for a A typical set of parameters that provide good temperature 3-phase regulator. Inductor current flows through the DCR and compensation are: Rsum = 3.65k, Rp=11k, Rntcs = 2.61k creates a voltage drop. Each inductor has two resistors Rsum and and Rntc = 10k(ERT-J1VR103J). The NTC network component Ro connected to the pads to accurately sense the inductor current values may need to be fine tuned on actual boards. To help fine by sensing the DCR voltage drop. The Rsum and Ro resistors are tune the network apply a full load condition to the regulator and connected in a summing network as shown, and feed the total record the IMON pin voltage reading immediately; then record the current information to the NTC network (consisting of Rntcs, Rntc IMON voltage reading again when the board has reached thermal and Rp) and capacitor Cn. Rntc is a negative temperature steady state. A good NTC network can limit the IMON voltage drift coefficient (NTC) thermistor, used to compensate for the increase to within 1% over the temperature range. If droop is used for the in inductor DCR as temperature increases. ISL6353 based regulator the output voltage can be used for this test rather than IMON. DDR memory regulators typically do not The inductor output pads are electrically shorted in the schematic, operate with droop enabled. The Intersil evaluation board layout but have some parasitic impedance in the actual board layout, and current-sensing network parameters can be referred to in which is why the signals cannot simply be shorted together for the order to help minimize engineering time. current-sense summing network. A resistor from 1~10 for Ro is recommended to create quality signals. Since the Ro value is much VCn(s) needs to represent real-time Io(s) for the controller to smaller than the rest of the current sensing circuit, the following achieve best OCP and IMON response. The transfer function analysis will ignore it for simplicity. Acs(s) has a pole sns and a zero L. L and sns should be matched so Acs(s) is unity gain at all frequencies. By forcing L The summed inductor current information is represented at equal to sns and solving for the solution, Equation 9 gives Cn capacitor Cn. Equations 4 through 8 describe the value. frequency-domain relationship between total inductor current L Io(s) and the Cn voltage VCn(s): Cn = ---------------------------R---------------------------------   Rntcnet-----s-N-u----m--- (EQ. 9) VCns = R-----n---t--c-R--n--n-e---tt--c-+-n----eR------t----s--N--u--------m------D-----NC----R---IosAcss (EQ. 4) R-----n---t--c---n---e---t---+-----R---------s---N--u--------m------DCR For example, given N=3, Rsum=3.65k, Rp=11k, R = ---R----n---t--c---s----+-----R----n---t--c------------R----p-- (EQ. 5) Rntcs=2.61k, Rntc=10k, DCR=0.29m and L=0.22µH, ntcnet Rntcs+Rntc+Rp Equation 9 gives Cn=0.79µF. 1+---s--- Cn is the capacitor used to match the inductor time constant. A s = ------------------L---- (EQ. 6) Sometimes it takes the parallel combination of two or more cs s capacitors to get the desired value. To verify the capacitor value 1+------------ sns is correct a repetitive load can be placed on the output voltage and the IMON voltage can be monitored. The capacitor in parallel with the IMON resistor needs to be removed for this test. The FN6897 Rev 0.00 Page 19 of 30 September 15, 2011

ISL6353 IMON voltage should be approximately a square wave with little and 20µA in PS2 mode. For a 2-phase design, the OCP threshold or no overshoot. In regulators without droop control the capacitor is 60µA in PS0 mode and 30µA in PS1 and PS2 mode. The value can be selected to err on the high side to overdamp the ISL6353 declares a OCP fault when Isense is above the threshold current sense input to the controller to avoid overshoots. for 120µs. Resistor Current-Sensing Network Referring to Equation 3 and Figure 10, resistor Ri sets the sensed Phase1 Phase2 Phase3 current Isense. In general, Isense can be set to 40µA at the maximum load current expected in the design. The OCP trip level will be 1.5 times the maximum load current with a threshold at L L L 60µA. The OCP ratio can be set to something other than 1.5 times the maximum load current by setting Isense=60µA/OCPratio DCR DCR DCR Rsum For inductor DCR sensing, Equation 13 gives the DC relationship of Vcn(s) and Io(s). Rsum   Rsen Rsen Rsen Rsum Vcn Cn ISUM+ VCn = R-----n---t--c-R--n--n-e--t-t--c-+-n----eR------t---s---N--u-------m-------D-----NC----R---Io (EQ. 13) Ro Ri ISUM- Substitution of Equation 13 into Equation 3 gives Equation 14: Ro Ro IIsense = R-1---------------R----n----t--c--n----eR---t-----------D-----NC----R---Io (EQ. 14) i R +-----s--u----m--- ntcnet N Io Therefore: R DCRI FIGURE 11. RESISTOR CURRENT-SENSING NETWORK Ri = --------------------n---t--c---n---e---t------R-----------------------o----------------- (EQ. 15) Figure 11 shows the precision resistor current-sensing network NR +-----s--u----m---I  ntcnet N  sense for a 3-phase solution. Each inductor has a series current-sensing resistor, Rsen. Rsum and Ro are connected to the Rsen pads to Substitution of Equation 5 and application of the full load accurately capture the inductor current information. The Rsum condition in Equation 15 gives Equation 16: and Ro resistors are connected to capacitor Cn. Rsum and Cn R +R R form a filter for noise attenuation. Equations 10 through 12 give ---R----n---t--c---s----+-----R----n---t--c----+-----R-------p--DCRIomax VCn(s) expressions: Ri = ----------------------n----t--c--s-------------n----t--c-------------p------------------------------------------------------------ (EQ. 16) VCns = R-----sN--e---n--IosARsens (EQ. 10) N---RR----nn---tt--cc---ss----++-----RR----nn---tt--cc----+-----R---R-p---p--+R-----s-N-u----m---Isensemax A s = ----------1------------ (EQ. 11) where Iomax is the full load current, and Isensemax is the Rsen 1+------s------ corresponding sensed current based on the desired OCP to Iomax  ratio. sns 1 For resistor sensing, Equation 17 gives the DC relationship of  = --------------------------- (EQ. 12) Rsen R-----s--u----m---C Vcn(s) and Io(s). N n V = R-----s--e----n-I (EQ. 17) Cn N o Transfer function ARsen(s) always has unity gain at DC. The current-sensing resistor Rsen value will not have a significant Substitution of Equation 17 into Equation 3 gives Equation 18: vnaertiwaotirokn. over temperature, so there is no need for the NTC Isense = R-1----R-----sN--e----n-Io (EQ. 18) i Recommended values are Rsum=1k and Cn=5600pF. Therefore: Overcurrent Protection R I R = ------s---e---n-----------o--- (EQ. 19) i NI The ISL6353 implements overcurrent protection (OCP) by sense comparing the average value of the measured current Isense with Application of the full load condition gives Equation 20: an internal current source reference. The OCP threshold is 60µA R I for 3-phase, 2-phase and 1-phase PS0 operation. In PS1/2 mode R = ------s---e---n-----------o---m-----a---x--- (EQ. 20) i NI the OCP threshold is scaled based on the number of active sensemax phases in PS1/2 mode divided by the number of active phases in PS0 mode. For example, if the regulator operates in 3-phase where Iomax is the full load current, and Isensemax is the corresponding sensed current. mode in PS0, 2-phase in PS1 mode and 1-phase in PS2 mode, the OCP threshold will be 60µA in PS0 mode, 40µA in PS1 mode FN6897 Rev 0.00 Page 20 of 30 September 15, 2011

ISL6353 Current Monitor time constant for RsCs should be used such that the ISEN voltages have minimal ripple and represent the DC current The ISL6353 provides a current monitor function. The IMON pin flowing through the inductors. Recommended values are outputs a high-speed analog current source that is 1/4 times the Rs=10k and Cs=0.22µF. Isense current. I = 1---I (EQ. 21) Rs should be routed to the inductor phase-node pad in order to IMON 4 sense help eliminate the effect of phase node parasitic PCB DCR. Equations 26 through 28 give the ISEN pin voltages: A resistor Rimon is connected to the IMON pin to convert the V = R +R I (EQ. 26) IMON pin current to a voltage. The voltage across Rimon is ISEN1 dcr1 pcb1 L1 expressed in Equation 22: V = 1---I R (EQ. 22) VISEN2 = Rdcr2+Rpcb2IL2 (EQ. 27) Rimon 4 sense imon V = R +R I (EQ. 28) Substitution of Equation 14 into Equation 22 gives Equation 23: ISEN3 dcr3 pcb3 L3 VRimon = 4---1-R----------------R----n----t--c--n----eR---t-----------D-----NC----R---IoRimon (EQ. 23) wanhde rRep Rcbd3cr a1r, eR pdacrr2a saintidc RPCdcBr 3D aCrRe binedtwuceteonr DthCeR i;n Rdpuccbto1r, Rouptcpbu2t i Rntcnet+-----s-N-u----m--- pad and the output voltage rail; and IL1, IL2 and IL3 are inductor average currents. Rewriting Equation 23 gives Equation 24: The ISL6353 will adjust the phase pulse-width relative to the V R NR +R  other phases to make VISEN1=VISEN2=VISEN3, thus to achieve Rimon = ----R----i-m-----o----n1-------------i------------------n----t--c---n---e---t------------s---u---m------ (EQ. 24) IL1=IL2=IL3, when Rdcr1=Rdcr2=Rdcr3 and 4---RntcnetDCRIo Rpcb1=Rpcb2=Rpcb3. Substitution of Equation 5 and application of the full load Using the same components for L1, L2 and L3 will provide a good condition in Equation 24 gives Equation 25: match of Rdcr1, Rdcr2 and Rdcr3. Board layout will determine Rpcb1, Rpcb2 and Rpcb3. Each phase should be as symmetric as VRimonRiN---RR----nn---tt--cc---ss----++-----RR----nn---tt--cc----+-----R---R-p---p--+Rsum (EQ. 25) peaocsshi binled uinc ttohre a PnCdB t hlaey oouuttp fuotr vtohlet apgoew leora dde, lsivuecrhy tphaatth between Rimon = -------------1----------------------------------------------------------------------------------------------------------- Rpcb1=Rpcb2=Rpcb3. ---R +R R -4----------n---t---c--s-------------n----t--c---------------p--DCRI V3p L3 Rdcr3 Rpcb3 R +R +R omax Phase3 ntcs ntc p Rs ISEN3 IL3 V3n where Iomax is the full load current. Cs Rs Api nca vpoaltcaigtoer. CTihmeo Rni mcaonn Cbiem poanr tailmleele cdo wnsittha nRti miso tnh eto u fsileter’rs t chheo IiMceO. N INTTEOR INCAL PhaseR2sV2p L2 Rdcr2 Rpcb2 Vo The time constant should be long enough such that switching Rs frequency ripple is removed. ISEN2 IL2 V2n Rs Cs Phase Current Balancing Rs L1 Rdcr1 V1p Rpcb1 L3 Rdcr3 Phase1 Rpcb3 Rs Phase3 ISEN1 IL1 V1n Rs Rs ISEN3 IL3 Cs Cs Rs L2 Rdcr2 INTERNAL Rpcb2 Vo Phase2 TO IC Rs FIGURE 13. DIFFERENTIAL-SENSING CURRENT BALANCING ISEN2 IL2 CIRCUIT Cs L1 Rdcr1 Rpcb1 Phase1 Sometimes, it is difficult to implement a symmetric layout. For Rs the circuit shown in Figure 12, an asymmetric layout causes ISEN1 IL1 Cs different Rpcb1, Rpcb2 and Rpcb3 resulting in phase current imbalance. Figure 13 shows a differential-sensing current balancing circuit recommended for the ISL6353. The current FIGURE 12. CURRENT BALANCING CIRCUIT sensing traces should be routed to the inductor pads so they only pick up the inductor DCR voltage. Each ISEN pin sees the average The ISL6353 monitors individual phase current by monitoring the voltage of three sources: its own phase inductor phase-node pad, ISEN1, ISEN2, and ISEN3 pin voltages. Figure12 shows the current balancing circuit recommended for the ISL6353. Each phase node voltage is averaged by a low-pass filter consisting of Rs and Cs, and presented to the corresponding ISEN pin. A long FN6897 Rev 0.00 Page 21 of 30 September 15, 2011

ISL6353 and the other two phases inductor output pads. Equations 29 through 31 give the ISEN pin voltages: R  = 1.29310–7F 2–0.1445F +52055 (EQ. 38) fset SW SW V = V +V +V (EQ. 29) ISEN1 1p 2n 3n Phase Count Configurations V = V +V +V (EQ. 30) The ISL6353 can be configured for 1, 2 or 3-phase operation. ISEN2 1n 2p 3n For 2-phase configuration, tie the PWM3 pin to VDD. Phase 1 and V = V +V +V (EQ. 31) Phase 2 PWM pulses are 180° out-of-phase. Leave the ISEN3 pin ISEN3 1n 2n 3p open for 2-phase configuration. The ISL6353 will make VISEN1 = VISEN2 = VISEN3 as in For 1-phase configuration, tie the PWM3 and ISEN2 pins to VDD. Equations32 and 33: In this configuration, only Phase 1 is active. The ISEN3, ISEN2, ISEN1, and FB2 pins are not used because there is no need for (EQ. 32) V1p+V2n+V3n = V1n+V2p+V3n current balancing or the FB2 function. Modes of Operation (EQ. 33) V +V +V = V +V +V 1n 2p 3n 1n 2n 3p TABLE 3. ISL6353 MODES OF OPERATION Rewriting Equation 32 gives Equation 34: CONFIGURATION PS# OPERATIONAL MODE V1p–V1n = V2p–V2n (EQ. 34) 3-phase Configuration PS0 3-phase CCM and rewriting Equation 33 gives Equation 35: PS1 2-phase CCM or 1-phase CCM (EQ. 35) V –V = V –V 2p 2n 3p 3n PS2 1-phase DE Combining Equations 34 and 35 gives Equation 36: PS3 1-phase DE V –V = V –V = V –V (EQ. 36) 2-phase Configuration PS0 2-phase CCM 1p 1n 2p 2n 3p 3n PS1 1-phase CCM Therefore: PS2 1-phase DE R I = R I = R I (EQ. 37) dcr1 L1 dcr2 L2 dcr3 L3 PS3 1-phase DE Current balancing (IL1=IL2=IL3) is achieved when 1-phase Configuration PS0 1-phase CCM Rdcr1=Rdcr2=Rdcr3. Rpcb1, Rpcb2 and Rpcb3 will not have any PS1 1-phase CCM effect. PS2 1-phase DE Since the slave ripple capacitor voltages mimic the inductor currents, the R3™ modulator can naturally achieve excellent current PS3 1-phase DE balancing during steady-state and dynamic operation. The inductor currents follow the load current dynamic change, with the output Table 3 shows the modes of operation for the various power states capacitors supplying the difference. The inductor currents can programmed using the SetPS command through the SVID bus or track the load current well at low rep rate, but cannot keep up by changing the state of the PSI pin. Table 3 is used in conjunction when the rep rate gets into the hundred-kHz range, where it is out with the status of the PROG2 pin. Refer to Table 7 for the PROG2 of the control loop bandwidth. The controller achieves excellent programming options. current balancing in all cases. Dynamic Operation CCM Switching Frequency The controller responds to VID changes by slewing to the new The resistor connected between the COMP pin and the VW pin voltage at a slew rate indicated in the SetVID command. There sets the VW windows size, therefore setting the steady state are three SetVID slew rates SetVID_fast, SetVID_slew and PWM switching frequency. When the ISL6353 is in continuous SetVID_decay. conduction mode (CCM), the switching frequency is not absolutely constant due to the nature of the R3 modulator. As The SetVID_fast command prompts the controller to enter CCM and to actively drive the output voltage to the new VID value at a explained in the “Multiphase R3 Modulator” on page11, the minimum 10mV/µs slew rate. effective switching frequency will increase during load step-up and will decrease during load step-down to achieve fast transient The SetVID_slow command prompts the controller to enter CCM response. On the other hand, the switching frequency is relatively and to actively drive the output voltage to the new VID value at a constant at steady state. Equation 38 gives an estimate of the minimum 2.5mV/µs slew rate. frequency-setting resistor Rfset value. 20k Rfset gives The SetVID_decay command prompts the controller to enter DE approximately 300kHz switching frequency. Lower resistance mode. The output voltage will decay down to the new VID value at yields higher switching frequency. a slew rate determined by the load. If the voltage decay rate is FN6897 Rev 0.00 Page 22 of 30 September 15, 2011

ISL6353 too fast, the controller will limit the voltage slew rate at the system. The VR_HOT# pin will be pulled back high if the voltage SetVID_slow slew rate. on the NTC pin goes above 0.95V. ALERT# will be asserted low at the end of SetVID_fast and If the voltage on the NTC pin goes below 0.93V the ALERT# pin SetVID_slow VID transitions. will be pulled low indicating a thermal alert. ALERT# is reset by checking the status register. ALERT# will be pulled low again if When the ISL6353 is in DE mode, it will actively drive the output the NTC pin voltage goes above 0.97V. voltage up when the VID changes to a higher value. DE operation will resume after reaching the new voltage level. If the load is All the above fault conditions can be reset by bringing VR_ON low light enough to warrant DCM, it will enter DCM after the inductor or by bringing VDD below the POR threshold. When VR_ON and current has crossed zero for four consecutive cycles. The ISL6353 VDD return to their high operating levels, a soft-start will occur. will remain in DE mode when the VID changes to a lower value. VR_HOT#/ALERT# BEHAVIOR The output voltage will decay to the new value and the load will determine the slew rate. VR Temperature Temp Zone 3% Hysteris Protection Functions 7 1111 1111 Bit 7 =1 1 10 0111 1111 The ISL6353 provides overcurrent, current-balance, overvoltage, Bit 6 =1 and over-temperature protection. 0011 1111 Bit 5 =1 OVERCURRENT PROTECTION 12 0001 1111 The ISL6353 determines overcurrent protection (OCP) by Temp Zone Register 2 8 comparing the average value of the measured current Isense with 0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111 an internal current source threshold. ISL6353 declares OCP when Status 1 3 Isense is above the threshold for 120µs. Register = “001” = “011” = “001” 5 13 15 GerReg GerReg The way-overcurrent protection threshold is significantly above SVID Status1 Status1 the standard overcurrent protection threshold. The way-overcurrent function is intended to provide a fast overcurrent ALERT# 4 6 14 16 detection and action mechanism in a short circuit output condition. Once the way-overcurrent condition is detected, the VR_HOT# 9 11 PWM outputs will immediately shut off and PGOOD will go low to FIGURE 14. VR_HOT#/ALERT# BEHAVIOR maximize protection. The controller drives a 60µA current source out of the NTC pin. CURRENT BALANCE FAULT The current source flows through the NTC resistor network on the The ISL6353 monitors the ISEN pin voltages to detect severe pin and creates a voltage that is monitored by the controller phase current imbalances. If any ISEN pin voltage is more than through an A/D converter (ADC) to generate the Tzone value. 20mV different than the average ISEN voltage for 1ms, the Table 4 shows the typical programming table for Tzone. The user controller will declare a fault and latch off. needs to scale the NTC a network resistance such that it generates the NTC pin voltage that corresponds to the left-most OVERVOLTAGE PROTECTION column. The ISL6353 will declare an OVP fault if the output voltage exceeds 175mV above the VID set value + positive offset. In the TABLE 4. TZONE TABLE event of an OVP condition, the OVP pin is pulled high. OVP is VNTC (V) TMAX (%) TZONE blanked during dynamic VID events to prevent false trigger. 0.86 >100 FFh During soft-start, the OVP threshold is set at 2.33V to avoid a false trigger due to turn on into a precharged output capacitor 0.88 100 FFh bank. 0.92 97 7Fh POWER GOOD INDICATOR 0.96 94 3Fh The ISL6353 takes the same actions for all of the above fault 1.00 91 1Fh protection functions: PGOOD is set low and the high-side and low- 1.04 88 0Fh side MOSFETs are turned off. Any residual inductor current will 1.08 85 07h decay through the MOSFET body diodes. These fault conditions can be reset by bringing VR_ON low or by bringing VDD below the 1.12 82 03h POR threshold. When VR_ON and VDD return to their high 1.16 79 01h operating levels, a soft-start will occur. 1.20 76 01h THERMAL MONITOR >1.20 <76 00h The ISL6353 has a thermal throttling feature. If the voltage on the NTC pin goes below the 0.91V threshold, the VR_HOT# pin is pulled low indicating the need for thermal throttling to the FN6897 Rev 0.00 Page 23 of 30 September 15, 2011

ISL6353 Figure 14 shows the how the NTC network should be designed to get FB2 Function correct VR_HOT#/ALERT# behavior when the system temperature CONTROLLER IN CONTROLLER IN rises and falls, manifested as the NTC pin voltage falling and rising. 3 OR 2-PHASE PS1 OR PS2 MODE C1 R2 MODE C1 R2 The series of events are: C2.1R3.1 C3 C2.1R3.1 C3 1. The temperature rises so the NTC pin voltage drops. Tzone value changes accordingly. VSEN R1 FB VSEN R1 FB 2. The temperature crosses the threshold where Tzone register C2.2R3.2 E/A COMP C2.2R3.2 E/A COMP FB2 FB2 Bit 6 changes from 0 to 1. Vref Vref 3. The controller changes Status_1 register bit 1 from 0 to 1. FIGURE 15. FB2 FUNCTION IN 2-PHASE MODE 4. The controller asserts ALERT#. Figure 15 shows the FB2 function. In order to improve transient response and stability when phases are disabled in PS1 or PS2 5. The CPU reads Status_1 register value to know that the alert mode, the ISL6353 FB2 function allows a second type 3 assertion is due to Tzone register bit 6 flipping. compensation network to be connected from the output voltage 6. The controller clears ALERT#. to the FB pin. 7. The temperature continues rising. In PS0 mode of operation the FB2 switch is open (off). In PS1 or 8. The temperature crosses the threshold where Tzone register PS2 mode of operation the FB2 switch closes (on). Bit 7 changes from 0 to 1. The FB2 function ensures excellent transient response in both 9. The controllers asserts VR_HOT# signal. The CPU throttles PS0 mode and PS1/2 mode. If the FB2 function is not needed back and the system temperature starts dropping eventually. C2.2 and R3.2 can be unpopulated and the FB2 pin can be left 10.The temperature crosses the threshold where Tzone register unconnected. bit 6 changes from 1 to 0. This threshold is 1 ADC step lower than the one when VR_HOT# gets asserted, to provide 3% Adaptive Body Diode Conduction Time hysteresis. Reduction 11.The controllers de-asserts VR_HOT# signal. In DCM, the controller turns off the low-side MOSFET when the 12.The temperature crosses the threshold where Tzone register inductor current approaches zero. During the on-time of the bit 5 changes from 1 to 0. This threshold is 1 ADC step lower low-side MOSFET, the phase voltage is negative and the amount than the one when ALERT# gets asserted during the is the MOSFET rDS(ON) voltage drop, which is proportional to the temperature rise to provide 3% hysteresis. inductor current. A phase comparator inside the controller 13.The controller changes Status_1 register bit 1 from 1 to 0. monitors the phase voltage during on-time of the low-side 14.The controller asserts ALERT#. MOSFET and compares it with a threshold to determine the zero-crossing point of the inductor current. If the inductor current 15.The CPU reads Status_1 register value to know that the alert has not reached zero when the low-side MOSFET turns off, it will assertion is due to Tzone register bit 5 flipping. flow through the low-side MOSFET body diode, causing the phase 16. The controller clears ALERT#. node to have a larger voltage drop until it decays to zero. If the Table 5 summarizes the fault protection functionality. inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it will flow through the TABLE 5. FAULT PROTECTION SUMMARY high-side MOSFET body diode, causing the phase node to have a FAULT DURATION spike until the current decays to zero. The controller continues BEFORE PROTECTION FAULT monitoring the phase voltage after turning off the low-side FAULT TYPE PROTECTION ACTION RESET MOSFET and adjusts the phase comparator threshold voltage Overcurrent 120µs PWM tri-state, VR_ON accordingly in iterative steps such that the low-side MOSFET body PGOOD latched low toggle or diode conducts for approximately 40ns to minimize the body Phase Current 1ms VDD toggle diode-related loss. Unbalance Way-Overcurrent Immediately System Parameter Programming PROG1/2 (1.5xOC) Pins Overvoltage PGOOD latched low. ISL6353 has two system parameter programming pins PROG1 +175mV Actively pulls the and PROG2. Some system parameters, such as maximum output output voltage to below VID value, current, boot voltage, number of phases for PS1 state, can be then tri-state. programmed by changing the resistors connected to these three pins. FN6897 Rev 0.00 Page 24 of 30 September 15, 2011

ISL6353 Table 6 shows the definition of PROG1. PROG1 defines the TABLE 7. DEFINITION OF PROG2 (Continued) maximum output current setting in the IMAX register of the RPROG2 WORKING MODE VBOOT ISL6353. (Ω) DROOP AT PS1 (V) TABLE 6. DEFINITION OF PROG1 3480 Disabled 2 phase CCM (3-phase 1.20 Configuration) RPROG1 IMAX 3-PHASE IMAX 2-PHASE IMAX 1-PHASE 1-Phase CCM (2-phase (Ω) MODE (A) MODE(A) MODE (A) configuration) 158 99 66 33 4120 Disabled 2 phase CCM (3-phase 1.35 475 90 60 30 Configuration) 1-Phase CCM (2-phase 787 84 56 28 configuration) 1100 81 54 27 4750 Disabled 2 phase CCM (3-phase 1.50 1430 75 50 25 Configuration) 1-Phase CCM (2-phase 1740 69 46 23 configuration) 2050 66 44 22 5360 Disabled 1 phase CCM 1.50 2370 60 40 20 6040 Disabled 1 phase CCM 1.35 2870 54 36 18 6650 Disabled 1 phase CCM 1.20 3480 51 34 17 7500 Disabled 1 phase CCM 0 4120 45 30 15 SVID ADDRESS Setting 4750 39 26 13 The SVID address of ISL6353 can be programmed by changing the resistor connected to the ADDR pin. Table 8 shows the SVID Table 7 shows the definition of PROG2. PROG2 defines the boot address definition. voltage, enable/disable droop and the working mode for PS1. TABLE 8. SVID ADDRESS DEFINITION TABLE 7. DEFINITION OF PROG2 RPROG2 WORKING MODE VBOOT RADDR (Ω) ADDRESS (Ω) DROOP AT PS1 (V) 158 0 158 Enabled 1-phase CCM 0 475 1 475 Enabled 1- phase CCM 1.20 787 2 787 Enabled 1-phase CCM 1.35 1100 3 1100 Enabled 1- phase CCM 1.50 1430 4 1430 Enabled 2-Phase CCM (3-Phase 1.50 Configuration) 1740 5 1-Phase CCM (2-phase configuration) 2050 6 1740 Enabled 2-Phase CCM (3-Phase 1.35 2370 7 Configuration) 2870 8 1-Phase CCM (2-phase configuration) 3480 9 2050 Enabled 2-Phase CCM (3-Phase 1.20 4120 A Configuration) 4750 B 1-Phase CCM (2-phase configuration) 5360 C 2370 Enabled 2-Phase CCM (3-Phase 0 6040 D Configuration) 1-Phase CCM (2-Phase External Control of VOUT and Power State configuration) VSET1/2, PSI 2870 Disabled 2-Phase CCM (3-Phase 0 Configuration) For additional design flexibility, the ISL6353 has 3 pins that can be 1-Phase CCM (2-Phase used to set the output voltage and power state of the regulator configuration) with external signals independent of the serial communication bus register settings. FN6897 Rev 0.00 Page 25 of 30 September 15, 2011

ISL6353 VSET1 and VSET2 can be used to set the output voltage of the Supported Serial VID Data And Configuration regulator. Table 9 shows the available options. If VSET1 and VSET2 Registers are connected to ground, the controller will refer only to the SVID register setting to program the output voltage. If any other logic The controller supports the following data and configuration combination is used on VSET1/2, the controller will ignore the registers. SVID register setting and program the output voltage based on TABLE 11. SUPPORTED DATA AND CONFIGURATION Table 8 for soft-start and steady state. REGISTERS TABLE 9. VSET1/2 PIN DEFINITION REGISTER DEFAULT INDEX NAME DESCRIPTION VALUE VBOOT from PROG2 OUTPUT 00h Vendor ID Uniquely identifies the VR 12h (V) VSET1 VSET2 VOLTAGE vendor. Assigned by Intel. 1.5 0 0 SVID Setting 01h Product ID Uniquely identifies the VR 35h product. Intersil assigns this 1.5 0 1 1.35V number. 1.5 1 0 1.6V 02h Product Uniquely identifies the revision 1.5 1 1 1.65V Revision of the VR control IC. Intersil assigns this data. 1.35 0 0 SVID Setting 05h Protocol ID Identifies which revision of SVID 01h 1.35 0 1 1.2V protocol the controller supports. 1.35 1 0 1.4V 06h Capability Identifies the SVID VR 81h capabilities and which of the 1.35 1 1 1.45V optional telemetry registers are 1.2 0 0 SVID Setting supported. 1.2 0 1 1.1V 10h Status_1 Data register read after ALERT# 00h signal; indicating if a VR rail has 1.2 1 0 1.25V settled, has reached VRHOT 1.2 1 1 1.3V condition or has reached ICC max. 0 0 0 SVID Setting 11h Status_2 Data register showing Status_2 00h 0 0 1 1.05V communication. 0 1 0 1.55V 12h Temperature Data register showing 00h Zone temperature zones that have 0 1 1 1.15V been entered. The PSI pin can be used to set the power state of the regulator as 15h IOUT Data register showing output 00h indicated on Table 10. If PSI is connected to ground the controller current information. The voltage will refer only to the SVID register contents to set the power state. If at the IMON pin is digitized and PSI is pulled high, the controller will enter the PS2 state. If PSI is stored in this register. connected to a high impedance, the controller will enter the PS1 1Ch Status_2_ This register contains a copy of 00h state. LastRead the Status_2 data that was last read with the GetReg (Status_2) TABLE 10. PSI PIN DEFINITION command. PSI ADDRESS 21h ICC max Data register containing the ICC Refer to 0 Internal SVID Power State max the platform supports; set Table 6 at start-up by resistor on PROG1 High-Z PS1 pin. The platform design engineer programs this value 1 PS2 during the design process. Binary format in amps, for example 100A= 64h. 24h SR-fast Slew Rate Normal. The fastest 0Ah slew rate the platform VR can sustain. Binary format in mV/µs. i.e. 0Ah = 10mV/µs. 25h SR-slow Is 4x slower than normal. Binary 02h format in mV/µs. i.e. 02h=2.5mV/µs FN6897 Rev 0.00 Page 26 of 30 September 15, 2011

ISL6353 TABLE 11. SUPPORTED DATA AND CONFIGURATION REGISTERS (Continued) REGISTER DEFAULT INDEX NAME DESCRIPTION VALUE 26h Vboot If programmed by the platform, Refer to the VR supports VBOOT voltage Table 6 during start-up ramp. The VR will ramp to VBOOT and hold at VBOOT until it receives a new SetVID command to move to a different voltage. 30h Vout max This register is programmed by FBh the master and sets the maximum VID the VR will support. If a higher VID code is received, the VR will respond with “not supported” acknowledge. 31h VID Setting Data register containing 00h currently programmed VID voltage. VID data format. 32h Power State Register containing the 00h programmed power state. 33h Voltage Offset Sets offset in VID steps added to 00h the VID setting for voltage margining. Bit 7 is a sign bit, 0=positive margin, 1=negative margin. Remaining 7 bits are # VID steps for the margin. 00h = no margin, 01h = +1 VID step 02h = +2 VID steps... 34h Multi VR Data register that configures VR1: 00h Config multiple VRs behavior on the VR2: 01h same SVID bus. Layout Guidelines ISL6353 PIN NUMBER SYMBOL LAYOUT GUIDELINES BOTTOM PAD GND Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect to ground planes in PCB internal layers. 1, 2, 3 SDA, Follow Intel recommendations. ALERT#, SCLK 4, 5, 6, 7, 22, VR_ON, No special consideration. 28, 36, 37, 38, PGOOD, 39 IMON, VR_HOT#, PROG1, PWM3, PSI, VSET1, VSET2, OVP 8 NTC The NTC thermistor needs to be placed close to the thermal source that is monitored to determine the desired VR_HOT# and thermal ALERT# toggling. Recommend placing it at the hottest spot of the ISL6353 based regulator. 9 VW Place the resistor and capacitor from VW to COMP in close proximity of the controller. FN6897 Rev 0.00 Page 27 of 30 September 15, 2011

ISL6353 Layout Guidelines (Continued) ISL6353 PIN NUMBER SYMBOL LAYOUT GUIDELINES 10, 11, 12 COMP, FB, Place the compensator components in general proximity of the controller FB2 13, 14, 15 ISEN3, Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place ISEN2, ISEN1 Cisen capacitors as close as possible to the controller and keep the following loops small: 1. Any ISEN pin to another ISEN pin 2. Any ISEN pin to GND The red traces in the following drawing show the loops that need to minimized. Phase1 L3 Risen Ro ISEN3 Cisen Vo Phase2 L2 Risen Ro ISEN2 Cisen Phase3 L1 Risen Ro ISEN1 Vsumn GND Cisen Cvsumn 16, 17 VSEN, RTN Place the VSEN/RTN filter in close proximity of the controller for good decoupling. Route these signals differentially from the remote sense location back to the controller. 18, 19 ISUMN, Place the current sensing circuit in general proximity of the controller. ISUMP Place capacitor Cn very close to the controller. Place the NTC thermistor next to the phase 1 inductor so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion. IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. If possible connect the traces to the inductor pad in only one place and isolate this connection from other planes of the same net that may be present on other layers. Also make the connections a symmetric as possible for all phases. Inductor Inductor Vias Current-Sensing Current-Sensing Traces Traces 20 VDD Place the decoupling capacitor a close as possible to this pin. 21 VIN Place the decoupling capacitor a close as possible to this pin. FN6897 Rev 0.00 Page 28 of 30 September 15, 2011

ISL6353 Layout Guidelines (Continued) ISL6353 PIN NUMBER SYMBOL LAYOUT GUIDELINES 23 BOOT1 Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. 24, 25 UG1, PH1 Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general copper. 26 GND Connect this pin to ground right next to the controller or to the exposed pad underneath the controller. 27 LG1 Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. 29 VDDP Place the decoupling capacitor a close as possible to this pin. 30 LG2 Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. 31 GND Connect this pin to ground right next to the controller or to the exposed pad underneath the controller. 32, 33 PH2, UG2 Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general copper. 34 BOOT2 Use fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace. 35 PROG2 Place resistor close to the controller. 40 ADDR Place resistor close to the controller. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 09/15/2011 FN6897.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL6353 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php © Copyright Intersil Americas LLC 2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6897 Rev 0.00 Page 29 of 30 September 15, 2011

ISL6353 Package Outline Drawing L40.5x5 40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 9/10 4X 3.60 5.00 A B 36X 0.40 6 6 PIN #1 INDEX AREA PIN 1 INDEX AREA 5.00 3.50 (4X) 0.15 40X 0.4± 0 .1 0.20 TOP VIEW BOTTOM VIEW b 0.10M C A B 4 PACKAGE OUTLINE 0.40 0.750 SEE DETAIL “X” // 0.10C C BASE PLANE 0.050 SEATING PLANE 0.08C SIDE VIEW 0 0 0 5 5. 3. (36X 0.40 0.2 REF (40X 0.20) 5 C (40X 0.60) 0.00 MIN 0.05 MAX TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. JEDEC reference drawing: MO-220WHHE-1 FN6897 Rev 0.00 Page 30 of 30 September 15, 2011