DATASHEET ISL6333, ISL6333A, ISL6333B, ISL6333C FN6520 Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Rev 3.00 Load Efficiency Enhancements for Intel VR11.1 Applications Oct 8, 2010 The ISL6333 three-phase PWM family of control ICs provide a Features precision voltage regulation system for advanced • Intel VR11.1 Compatible microprocessors. The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM - IMON Pin for Output Current Monitoring controller and driver configuration of previous multi-phase - Power State Indicator (PSI#) Pin for Phase Dropping product families. By reducing the number of external parts, this and Higher Efficiency During Light Load States integration is optimized for a cost and space saving power • CPURST_N Input to Eliminate Required Extensive management solution. External Circuit for proper PSI# Operation of Intel’s Eaglelake Chipset Platform (ISL6333B, ISL6333C Only) The ISL6333 controllers are designed to be compatible with Intel VR11.1 Applications. Features that make these controllers • Integrated Multi-Phase Power Conversion compatible include an IMON pin for output current monitoring, - 3-Phase or 2-Phase Operation with Internal Drivers and a Power State Indicator (PSI#) pin for phase dropping and • Precision Core Voltage Regulation higher efficiency during light load states. An 8-bit VID input is - Differential Remote Voltage Sensing used to select the desired output voltage from the VR11 DAC - ±0.5% System Accuracy Over-Temperature table. A circuit is provided for remote voltage sensing, - Adjustable Reference-Voltage Offset compensating for any potential difference between remote and local grounds. The output voltage can also be positively or • Optimal Transient Response negatively offset through the use of a single external resistor. - Active Pulse Positioning (APP) Modulation The ISL6333 controllers also include advanced control loop - Adaptive Phase Alignment (APA) features for optimal transient response to load application and • Fully Differential, Continuous DCR Current Sensing removal. One of these features is highly accurate, fully - Integrated Programmable Current Sense Resistors differential, continuous DCR current sensing for load line - Accurate Load Line Programming programming and channel current balance. Active Pulse - Precision Channel Current Balancing Positioning (APP) Modulation and Adaptive Phase Alignment (APA) are two other unique features, allowing for quicker initial • Gate Voltage Optimization Technology (ISL6333, response to high di/dt load transients. With this quicker initial ISL6333B Only) response to load transients, the number of output bulk • Power Saving Diode Emulation Mode (ISL6333, ISL6333B capacitors can be reduced, helping to reduce cost. Only) Integrated into the ISL6333 controllers are user-programmable • Optimized for use with Coupled Inductors current sense resistors, which require only a single external • Variable Gate Drive Bias: +5V to +12V resistor to set their values. No external current sense resistors are required. Another unique feature of the ISL6333 controllers • Microprocessor Voltage Identification Inputs is the addition of a dynamic VID compensation pin that allows - 8-bit VID Input for Selecting VR11 DAC Voltages optimizing compensation to be added for well-controlled - Dynamic VID Technology dynamic VID response. • Dynamic VID Compensation Protection features of these controller ICs include a set of • Overcurrent Protection and Channel Current Limit sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6333 controllers include • Multi-tiered Overvoltage Protection protection against an open circuit on the remote sensing inputs. • Digital Soft-Start Combined, these features provide advanced protection for the • Selectable Operation Frequency up to 1.0MHz Per Phase microprocessor and power system. • Pb-free (RoHS Compliant) FN6520 Rev 3.00 Page 1 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Note) MARKING (°C) (Pb-free) DWG. # ISL6333CRZ* ISL6333 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333IRZ* ISL6333 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333ACRZ* ISL6333A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333AIRZ* ISL6333A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333BCRZ* ISL6333B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333BIRZ* ISL6333B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333CCRZ* ISL6333C CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333CIRZ* ISL6333C IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL6333 (48 LD QFN) TOP VIEW N1+ N1- N2+ N2- N3+ N3- CC1 P1 ATE1 OT1 ATE1 ASE1 ISE ISE ISE ISE ISE ISE PV BY LG BO UG PH 48 47 46 45 44 43 42 41 40 39 38 37 RSET 1 36 VR_RDY OFS 2 35 EN FS 3 34 PUVCC SS 4 33 PHASE2 VCC 5 32 UGATE2 REF 6 31 BOOT2 GND (PIN 49) APA 7 30 LGATE2 COMP 8 29 PVCC2_3 DVC 9 28 LGATE3 FB 10 27 BOOT3 IDROOP 11 26 UGATE3 VDIFF 12 25 PHASE3 13 14 15 16 17 18 19 20 21 22 23 24 D N N # 7 6 5 4 3 2 1 0 N E O SI D D D D D D D D G S M P VI VI VI VI VI VI VI VI R V I FN6520 Rev 3.00 Page 2 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Pinouts (Continued) ISL6333A (48 LD QFN) TOP VIEW N1+ N1- N2+ N2- N3+ N3- CC1 CC2 ATE1 OT1 ATE1 ASE1 ISE ISE ISE ISE ISE ISE PV PV LG BO UG PH 48 47 46 45 44 43 42 41 40 39 38 37 RSET 1 36 VR_RDY OFS 2 35 EN FS 3 34 PUVCC SS 4 33 PHASE2 VCC 5 32 UGATE2 REF 6 31 BOOT2 GND (PIN 49) APA 7 30 LGATE2 COMP 8 29 PVCC3 DVC 9 28 LGATE3 FB 10 27 BOOT3 IDROOP 11 26 UGATE3 VDIFF 12 25 PHASE3 13 14 15 16 17 18 19 20 21 22 23 24 D N N # 7 6 5 4 3 2 1 0 N E O SI D D D D D D D D G S M P VI VI VI VI VI VI VI VI R V I ISL6333B (48 LD QFN) TOP VIEW N1+ N1- N2+ N2- N3+ N3- CC1 P1 ATE1 OT1 ATE1 ASE1 ISE ISE ISE ISE ISE ISE PV BY LG BO UG PH 48 47 46 45 44 43 42 41 40 39 38 37 RSET 1 36 VR_RDY OFS 2 35 EN FS 3 34 PUVCC SS 4 33 PHASE2 VCC 5 32 UGATE2 REF 6 31 BOOT2 GND (PIN 49) APA 7 30 LGATE2 COMP 8 29 PVCC2_3 DVC 9 28 LGATE3 FB 10 27 BOOT3 CPURST_N 11 26 UGATE3 VDIFF 12 25 PHASE3 13 14 15 16 17 18 19 20 21 22 23 24 D N N # 7 6 5 4 3 2 1 0 N E O SI D D D D D D D D G S M P VI VI VI VI VI VI VI VI R V I FN6520 Rev 3.00 Page 3 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Pinouts (Continued) ISL6333C (48 LD QFN) TOP VIEW N1+ N1- N2+ N2- N3+ N3- CC1 CC2 ATE1 OT1 ATE1 ASE1 ISE ISE ISE ISE ISE ISE PV PV LG BO UG PH 48 47 46 45 44 43 42 41 40 39 38 37 RSET 1 36 VR_RDY OFS 2 35 EN FS 3 34 PUVCC SS 4 33 PHASE2 VCC 5 32 UGATE2 REF 6 31 BOOT2 GND (PIN 49) APA 7 30 LGATE2 COMP 8 29 PVCC3 DVC 9 28 LGATE3 FB 10 27 BOOT3 CPURST_N 11 26 UGATE3 VDIFF 12 25 PHASE3 13 14 15 16 17 18 19 20 21 22 23 24 D N N # 7 6 5 4 3 2 1 0 N E O SI D D D D D D D D G S M P VI VI VI VI VI VI VI VI R V I Controller Descriptions and Comments DIODE GATE VOLTAGE OPTIMIZATION EMULATION TECHNOLOGY CONTROLLER MODE (DEM) (GVOT) DROOP PIN ENABLE/DISABLE DROOP CPURST_N PIN ISL6333 YES YES YES Enable/Disable NO ISL6333A NO NO YES Enable/Disable NO ISL6333B YES YES NO Always Enabled YES ISL6333C NO NO NO Always Enabled YES CONTROLLER COMMENTS ISL6333 When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing. When the PSI# pin is set low, the controller transitions to single phase operation and changes to diode emulation mode (DEM). The controller also utilizes it’s new Gate Voltage Optimization Technology (GVOT) to reduce Channel 1’s lower MOSFET gate drive voltage. This controller yields the highest low load efficiency. ISL6333A When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing. When the PSI# pin is set low, the controller transitions to single phase operation only. ISL6333B Same feature set as the ISL6333 controller with two additional changes. The CPURST_N pin is added to eliminate extensive external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed and the droop current now flows out of the FB pin. The droop feature is always active. This controller yields the highest low load efficiency. ISL6333C Same feature set as the ISL6333A controller with two additional changes. The CPURST_N pin is added to eliminate extensive external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed and the droop current now flows out of the FB pin. The droop feature is always active. FN6520 Rev 3.00 Page 4 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Integrated Driver Block Diagram LVCC UVCC BOOT UGATE PWM 20k GATE SHOOT- LOW POWER CONTROL THROUGH PHASE STATE LOGIC PROTECTION SOFT-START 10k AND FAULT LOGIC LGATE FN6520 Rev 3.00 Page 5 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333 VR_RDY SS EN OPEN SENSE LINE PREVENTION 0.85V VSEN VCC x1 RGND PVCC1 POWER-ON PVCC2_3 RESET VDIFF PUVCC UNDERVOLTAGE DETECTION LOGIC SOFT-START SS AND LDO FAULT LOGIC OVERVOLTAGE DETECTION LOGIC BYP1 LOW POWER STATE PSI# CIRCUITRY I_AVG OCP I_TRIP BOOT1 APA ADAPTIVE PHASE MOSFET UGATE1 ALLIGNMENT DRIVER CIRCUITRY PHASE1 LGATE1 CLOCK AND FS MODULATOR WAVEFORM GENERATOR VID7 BOOT2 VID6 MOSFET UGATE2 DRIVER VID5 APP AND APA PWM1 PHASE2 DYNAMIC VID4 VID MODULATOR LGATE2 VID3 D/A VID2 VID1 APP AND APA PWM2 VID0 MODULATOR BOOT3 1k MOSFET UGATE3 DRIVER PHASE3 DVC x2 APP AND APA PWM3 LGATE3 MODULATOR REF E/A FB I_AVG 1 CHANNEL N DETECT COMP CH3 ISEN3- OFS OFFSET +  CURRENT RISEN3 + + SENSE ISEN3+ IDROOP I_AVG CHANNEL IMON CURRENT CH2 ISEN2- BALANCE AND CURRENT RISEN2 CURRENT SENSE ISEN2+ LIMIT RSET OCP OCP CH1 ISEN1+ CURRENT RISEN1 VOCP SENSE ISEN1- RGND GND FN6520 Rev 3.00 Page 6 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333A VR_RDY SS EN OPEN SENSE LINE PREVENTION 0.85V VSEN VCC x1 RGND PVCC1 POWER-ON PVCC3 RESET VDIFF PUVCC UNDERVOLTAGE DETECTION LOGIC SOFT-START AND FAULT LOGIC OVERVOLTAGE DETECTION LOGIC PVCC2 LOW POWER STATE PSI# CIRCUITRY I_AVG OCP I_TRIP BOOT1 APA ADAPTIVE PHASE MOSFET UGATE1 ALLIGNMENT DRIVER CIRCUITRY PHASE1 LGATE1 CLOCK AND FS MODULATOR WAVEFORM GENERATOR VID7 BOOT2 VID6 MOSFET UGATE2 DRIVER VID5 APP AND APA PWM1 PHASE2 DYNAMIC VID4 VID MODULATOR LGATE2 VID3 D/A VID2 VID1 APP AND APA PWM2 VID0 MODULATOR BOOT3 1k MOSFET UGATE3 DRIVER PHASE3 DVC x2 APP AND APA PWM3 LGATE3 MODULATOR REF E/A FB I_AVG 1 CHANNEL N DETECT COMP CH3 ISEN3- OFS OFFSET +  CURRENT RISEN3 + + SENSE ISEN3+ IDROOP I_AVG CHANNEL IMON CURRENT CH2 ISEN2- BALANCE AND CURRENT RISEN2 CURRENT SENSE ISEN2+ LIMIT RSET OCP OCP CH1 ISEN1+ CURRENT RISEN1 VOCP SENSE ISEN1- RGND GND FN6520 Rev 3.00 Page 7 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333B VR_RDY SS EN OPEN SENSE LINE PREVENTION 0.85V VSEN VCC x1 RGND PVCC1 POWER-ON PVCC2_3 RESET VDIFF PUVCC UNDERVOLTAGE DETECTION LOGIC SOFT-START SS AND LDO FAULT LOGIC OVERVOLTAGE DETECTION BYP1 LOGIC LOW POWER PSI# STATE CIRCUITRY CPURST_N I_AVG OCP I_TRIP BOOT1 APA ADAPTIVE PHASE MOSFET UGATE1 ALLIGNMENT DRIVER CIRCUITRY PHASE1 LGATE1 CLOCK AND FS MODULATOR WAVEFORM GENERATOR VID7 BOOT2 VID6 MOSFET UGATE2 DRIVER VID5 APP AND APA PWM1 PHASE2 DYNAMIC VID4 VID MODULATOR LGATE2 VID3 D/A VID2 VID1 APP AND APA PWM2 VID0 MODULATOR BOOT3 1k MOSFET UGATE3 DRIVER PHASE3 DVC x2 APP AND APA PWM3 LGATE3 MODULATOR REF E/A FB I_AVG 1 CHANNEL N DETECT COMP I_AVG CH3 ISEN3- OFS OFFSET +  CURRENT RISEN3 + + SENSE ISEN3+ CHANNEL IMON CURRENT CH2 ISEN2- BALANCE AND CURRENT RISEN2 CURRENT SENSE ISEN2+ LIMIT RSET OCP OCP CH1 ISEN1+ CURRENT RISEN1 VOCP SENSE ISEN1- RGND GND FN6520 Rev 3.00 Page 8 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333C VR_RDY SS EN OPEN SENSE LINE PREVENTION 0.85V VSEN VCC x1 RGND PVCC1 POWER-ON PVCC3 RESET VDIFF PUVCC UNDERVOLTAGE DETECTION LOGIC SOFT-START AND FAULT LOGIC OVERVOLTAGE PVCC2 DETECTION LOGIC LOW POWER PSI# STATE CIRCUITRY CPURST_N I_AVG OCP I_TRIP BOOT1 APA ADAPTIVE PHASE MOSFET UGATE1 ALLIGNMENT DRIVER CIRCUITRY PHASE1 LGATE1 CLOCK AND FS MODULATOR WAVEFORM GENERATOR VID7 BOOT2 VID6 MOSFET UGATE2 DRIVER VID5 APP AND APA PWM1 PHASE2 DYNAMIC VID4 VID MODULATOR LGATE2 VID3 D/A VID2 VID1 APP AND APA PWM2 VID0 MODULATOR BOOT3 1k MOSFET UGATE3 DRIVER PHASE3 DVC x2 APP AND APA PWM3 LGATE3 MODULATOR REF E/A FB I_AVG 1 CHANNEL N DETECT COMP I_AVG CH3 ISEN3- OFS OFFSET +  CURRENT RISEN3 + + SENSE ISEN3+ CHANNEL IMON CURRENT CH2 ISEN2- BALANCE AND CURRENT RISEN2 CURRENT SENSE ISEN2+ LIMIT RSET OCP OCP CH1 ISEN1+ CURRENT RISEN1 VOCP SENSE ISEN1- RGND GND FN6520 Rev 3.00 Page 9 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B +5V VCC VDIFF RGND VSEN DVC RSET BYP1 FB +12V IDROOP PVCC1 PUVCC COMP BOOT1 APA UGATE1 1.8 +5V PHASE1 VCC LGATE1 OFS ISEN1- ISEN1+ FS REF +12V LOAD PVCC2_3 ISL6333/B RGND IMON BOOT2 SS UGATE2 1.8 PHASE2 VID7 LGATE2 VID6 VID5 ISEN2- VID4 ISEN2+ VID3 VID2 +12V VID1 VID0 CPURST_N BOOT3 PSI# UGATE3 1.8 VR_RDY PHASE3 EN LGATE3 ISEN3- GND ISEN3+ *NOTE: ISL6333 - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist. *NOTE: ISL6333B - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist. FN6520 Rev 3.00 Page 10 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B with NTC Thermal Compensation +5V VCC VDIFF RGND VSEN DVC RSET BYP1 FB +12V IDROOP PVCC1 PUVCC COMP BOOT1 PLACE IN CLOSE NTC PROXIMITY APA UGATE1 1.8 +5V PHASE1 VCC LGATE1 OFS ISEN1- ISEN1+ FS REF +12V LOAD PVCC2_3 ISL6333/B RGND IMON BOOT2 SS UGATE2 1.8 PHASE2 VID7 LGATE2 VID6 VID5 ISEN2- VID4 ISEN2+ VID3 VID2 +12V VID1 VID0 CPURST_N BOOT3 PSI# UGATE3 1.8 VR_RDY PHASE3 EN LGATE3 ISEN3- GND ISEN3+ *NOTE: ISL6333 - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist. *NOTE: ISL6333B - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist. FN6520 Rev 3.00 Page 11 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333A, ISL6333C +5V VCC VDIFF RGND VSEN DVC RSET FB PVCC1 +12V IDROOP PVCC2 PUVCC COMP BOOT1 APA UGATE1 1.8 +5V PHASE1 VCC LGATE1 OFS ISEN1- ISEN1+ FS REF +12V LOAD PVCC3 ISL6333A RGND IMON BOOT2 SS UGATE2 1.8 PHASE2 VID7 LGATE2 VID6 VID5 ISEN2- VID4 ISEN2+ VID3 VID2 +12V VID1 VID0 CPURST_N BOOT3 PSI# UGATE3 1.8 VR_RDY PHASE3 EN LGATE3 ISEN3- GND ISEN3+ *NOTE: ISL6333A - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist. *NOTE: ISL6333C - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist. FN6520 Rev 3.00 Page 12 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Absolute Maximum Ratings Thermal Information Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Thermal Resistance JA (°C/W) JC (°C/W) Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V QFN Package (Notes 1, 2). . . . . . . . . . 28 1.5 Absolute BOOT Voltage, VBOOT. . . . . . .GND - 0.3V to GND + 36V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C PHASE Voltage, VPHASE . . . . . . . . .GND - 8V (<400ns, 20µJ) to 30V Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C (<200ns, VBOOT - VGND < 36V) Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below UGATE Voltage, VUGATE. . . . . . . .VPHASE - 0.3V to VBOOT + 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V LGATE Voltage, VLGATE . . . . . . . . . . . GND - 0.3V to PVCC + 0.3V Recommended Operating Conditions GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5% Ambient Temperature ISL6333CRZ, ISL6333ACRZ, ISL6333BCRZ, ISL6333CCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6333IRZ, ISL6333AIRZ, ISL6333BIRZ, ISL6333CIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. MIN MAX PARAMETER TEST CONDITIONS (Note 4) TYP (Note 4) UNITS BIAS SUPPLIES Input Bias Supply Current IVCC; EN = high 13 16.7 19.5 mA Lower Gate Drive Bias Current - IPVCC1; EN = high 0.7 1.8 4 mA PVCC1 Pin Lower Gate Drive Bias Current - IPVCC2_3; EN = high 1.5 2.6 5 mA PVCC2_3 Pin (ISL6333, ISL6333B Only) Lower Gate Drive Bias Current - PVCC3 IPVCC3; EN = high 1.5 2.6 5 mA Pin (ISL6333A, ISL6333C Only) Upper Gate Drive Bias Current - IUVCC; EN = high 0.6 1 1.4 mA PUVCC Pin VCC POR (Power-On Reset) Threshold VCC rising 4.25 4.41 4.50 V VCC falling 3.75 3.85 4.00 V PVCC POR (Power-On Reset) PVCC1, PVCC2_3, PUVCC rising 4.30 4.42 4.55 V Threshold PVCC1, PVCC2_3, PUVCC falling 3.70 3.83 3.95 V BYP1 POR (Power-On Reset) BYP1 rising 4.20 4.40 4.55 V Threshold BYP1 falling 3.70 3.80 3.90 V PWM MODULATOR Oscillator Frequency Accuracy, FSW RT = 100k (± 0.1%) 225 250 275 kHz (ISL6333CRZ, ISL6333ACRZ, ISL6333BCRZ, ISL6333CCRZ) Oscillator Frequency Accuracy, FSW RT = 100k (± 0.1%) 215 250 280 kHz (ISL6333IRZ, ISL6333AIRZ, (Note 3) ISL6333BIRZ, ISL6333CIRZ) Adjustment Range of Switching (Note 3) 0.08 - 1.0 MHz Frequency FN6520 Rev 3.00 Page 13 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. (Continued) MIN MAX PARAMETER TEST CONDITIONS (Note 4) TYP (Note 4) UNITS Oscillator Ramp Amplitude, VP-P (Note 3) - 1.50 - V CONTROL THRESHOLDS EN Rising Threshold 0.84 0.86 0.88 V EN Hysteresis 96 104 120 mV REFERENCE AND DAC System Accuracy (1.000V to 1.600V) -0.5 - 0.5 % System Accuracy (0.600V to 1.000V) -1.0 - 1.0 % System Accuracy (0.400V to 0.600V) -2.0 - 2.0 % DAC Input Low Voltage - - 0.4 V DAC Input High Voltage 0.8 - - V PSI# INPUT PSI# Input Low Voltage Threshold - - 0.4 V PSI# Input High Voltage Threshold 0.8 - - V PIN-ADJUSTABLE OFFSET OFS Sink Current Accuracy ROFS = 32.4kfrom OFS to VCC -52.0 -50.3 -48.0 µA (NegativeOffset) OFS Source Current Accuracy ROFS = 6.04kfrom OFS to GND 47.0 48.7 51.0 µA (Positive Offset) ERROR AMPLIFIER DC Gain RL = 10k to ground, (Note 3) - 96 - dB Gain-Bandwidth Product CL = 100pF, RL = 10k to ground, - 40 - MHz (Note 3) Slew Rate CL = 100pF, Load = ±400µA, (Note 3) - 20 - V/µs Maximum Output Voltage Load = 1mA 4.00 4.196 - V Minimum Output Voltage Load = -1mA - 1.231 1.60 V SOFT-START RAMP Soft-Start Ramp Rate RS = 100k 1.15 1.274 1.37 mV/µs Adjustment Range of Soft-Start Ramp (Note 3) 0.156 - 6.25 mV/µs Rate CURRENT SENSING IDROOP Current Sense Offset RSET = 40.2kVISEN1+ = VISEN2+ = 0V -2.5 0 2.5 µA IDROOP Current Sense Gain RSET = 40.2kVISEN1 = VISEN2 = 24mV 77.5 81.2 85 µA OVERCURRENT PROTECTION Overcurrent Trip Level - Average Normal operation 88 100 110 µA Channel Dynamic VID change 120 140 160 µA Overcurrent Trip Level - Individual Normal operation 120 138 160 µA Channel Dynamic VID change 170 195 222 µA IMON Pin Clamped Overcurrent Level 1.1 1.127 1.15 V OVERVOLTAGE AND UNDERVOLTAGE PROTECTION Undervoltage Threshold VSEN falling 0.48*VDAC 0.503*VDAC 0.525*VDAC V Undervoltage Hysteresis VSEN rising 0.02*VDAC 0.084*VDAC 0.15*VDAC V FN6520 Rev 3.00 Page 14 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. (Continued) MIN MAX PARAMETER TEST CONDITIONS (Note 4) TYP (Note 4) UNITS Overvoltage Threshold During 1.260 1.280 1.300 V Soft-Start Overvoltage Threshold VR11, VSEN rising VDAC + 160mV VDAC + 175mV VDAC + 194mV V Overvoltage Hysteresis VSEN falling 90 108 120 mV SWITCHING TIME (Note 3) UGATE Rise Time tRUGATE; VPVCC = 12V, 3nF load, 10% to - 26 - ns 90% LGATE Rise Time tRLGATE; VPVCC = 12V, 3nF load, 10% to - 18 - ns 90% UGATE Fall Time tFUGATE; VPVCC = 12V, 3nF load, 90% to - 18 - ns 10% LGATE Fall Time tFLGATE; VPVCC = 12V, 3nF load, 90% to - 12 - ns 10% UGATE Turn-On Non-Overlap tPDHUGATE; VPVCC = 12V, 3nF load, - 10 - ns adaptive LGATE Turn-On Non-Overlap tPDHLGATE; VPVCC = 12V, 3nF load, - 10 - ns adaptive GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance VPVCC = 12V, 15mA source current - 2.0 -  Upper Drive Sink Resistance VPVCC = 12V, 15mA sink current - 1.35 -  Lower Drive Source Resistance VPVCC = 12V, 15mA source current - 1.35 -  Lower Drive Sink Resistance VPVCC = 12V, 15mA sink current - 0.90 -  OVER-TEMPERATURE SHUTDOWN (Note 3) Thermal Shutdown Setpoint - 160 - °C Thermal Recovery Setpoint - 100 - °C NOTES: 3. Limits established by characterization and are not production tested. 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Timing Diagram tPDHUGATE tRUGATE tFUGATE UGATE LGATE tFLGATE tRLGATE tPDHLGATE FN6520 Rev 3.00 Page 15 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Functional Pin Descriptions VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7 These are the inputs for the internal DAC that provide the VCC reference voltage for output regulation. These pins respond to VCC is the bias supply for the ICs small-signal circuitry. TTL logic thresholds. These pins are internally pulled high to Connect this pin to a +5V supply and decouple using a approximately 1.2V, by 40µA internal current sources. The quality 0.1µF ceramic capacitor. internal pull-up current decreases to 0 as the VID voltage PVCC1 (ISL6333, ISL6333B Only) approaches the internal pull-up voltage. All VID pins are compatible with external pull-up voltages not exceeding the This pin is the input to an internal LDO that regulates the IC’s bias voltage (VCC). voltage on the BYP1 pin and should be connected to a +12V supply. It is very important that this pin is decoupled using a VSEN and RGND quality 1.0µF ceramic capacitor. VSEN and RGND are inputs to the precision differential PVCC2_3 (ISL6333, ISL6333B Only) remote-sense amplifier and should be connected to the sense pins of the remote load. This pin is the power supply pin for Channels 2 and 3 lower MOSFET drivers, and should be connected to a +12V supply. VDIFF Decouple this pin with a quality 1.0µF ceramic capacitor. VDIFF is the output of the differential remote-sense amplifier. PVCC1, PVCC2, and PVCC3 (ISL6333A, ISL6333C The voltage on this pin is equal to the difference between Only) VSEN and RGND. These pins are the power supply pins for Channels 1, 2, and FB and COMP 3 lower MOSFET drivers, and should be connected to a These pins are the internal error amplifier inverting input and +12V supply. Decouple these pins with quality 1.0µF output respectively. The FB pin, COMP pin, and the VDIFF ceramic capacitors pins are tied together through external R-C networks to PUVCC compensate the regulator. This pin is the power supply pin for Channels 1, 2, and 3 DVC upper MOSFET drivers, and can be connected to any A series resistor and capacitor can be connected from the voltage from +5V to +12V depending on the desired DVC pin to the FB pin to compensate and smooth dynamic MOSFET gate-drive level. Decouple this pin with a quality VID transitions. 1.0µF ceramic capacitor. IDROOP (ISL6333, ISL6333A Only) BYP1 (ISL6333, ISL6333B Only) The IDROOP pin is the average channel-current sense This pin is the output of an internal LDO which powers output. Connecting this pin directly to FB allows the Channel 1 lower MOSFET driver. A quality 1.0µF ceramic converter to incorporate output voltage droop proportional to capacitor should be placed from this pin to ground. the output current. If voltage droop is not desired leave this GND pin unconnected. GND is the bias and reference ground for the IC. IMON EN The IMON pin is the average channel-current sense output. This pin is used as a load current indicator to monitor the This pin is a threshold-sensitive (approximately 0.86V) enable output load current. input for the controllers. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for APA operation. This is the Adaptive Phase Alignment set pin. A 100µA FS current flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase A resistor, RFS, tied from this pin to ground sets the channel Alignment circuitry can be set. switching frequency of the controller. Refer to Equation 46 for proper resistor calculation. REF The FS pin also determines whether the controllers operate The REF input pin is the positive input of the error amplifier. It is in the coupled inductor mode or the standard inductor mode internally connected to the DAC output through a 1k resistor. of operation. Tying the RFS resistor to ground will set the A capacitor is used between the REF pin and ground to smooth controllers to operate in standard inductor mode. Tying the the voltage transition during soft-start and Dynamic VID RFS resistor to VCC sets the controllers to operate in transitions. This pin can also be bypassed to RGND if desired. coupled inductor mode. FN6520 Rev 3.00 Page 16 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C RSET regulates BYP1 to 5.75V. Tying the RSS resistor to VCC, Connect this pin to VCC through a resistor to set the effective regulates BYP1 to 7.75V. value of the internal RISEN current sense resistors. It is VR_RDY recommended a 0.1µF ceramic capacitor be placed in VR_RDY indicates whether VDIFF is within specified parallel with this resistor for noise immunization. overvoltage and undervoltage limits after a fixed delay from OFS the end of soft-start. It is an open-drain logic output. If VDIFF exceeds these limits, an overcurrent event occurs, or if the The OFS pin provides a means to program a DC current for part is disabled, VR_RDY is pulled low. VR_RDY is always generating an offset voltage across the resistor between FB low prior to the end of soft-start. and VSEN. The offset current is generated via an external resistor and precision internal voltage references. The polarity PSI# of the offset is selected by connecting the resistor to GND or The PSI# pin is a digital logic input pin used to indicate VCC. For no offset, the OFS pin should be left unconnected. whether the controllers should be in a low power state of ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, and operation or not. When PSI# is HIGH the controllers will run in ISEN3+ it’s normal power state. When PSI# is LOW the controllers will change their operating state to improve light load efficiency. These pins are used for differentially sensing the The controllers resume normal operation when this pin is corresponding channel output currents. The sensed currents pulled HIGH again. are used for channel balancing, protection and load line regulation. CPURST_N (ISL6333B, ISL6333C Only) Connect ISEN1-, ISEN2-, and ISEN3- to the node between The CPURST_N pin is a digital logic input pin used in the RC sense elements surrounding the inductor of their conjunction with the PSI# pin to indicate whether the respective channel. Tie the ISEN+ pins to the VCORE side ISL6333B and ISL6333C should be in a lower power state of of their corresponding channel’s sense capacitor. operation or not. If CPURST_N is high, the operating state of the controllers can be changed to improve light load efficiency Tying ISEN3- to VCC programs the part for two-phase by setting PSI# low. If CPURST_N is low, the controllers operation. cannot be put into it’s light load operating state. Once UGATE1, UGATE2, and UGATE3 CPURST_N toggles high again, there is a 50ms delay before the controllers are allowed to enter a low power state. Connect these pins to their corresponding upper MOSFET gates through 1.8 resistors. These pins are used to control Operation the upper MOSFETs and are monitored for shoot-through Multi-phase Power Conversion prevention purposes. Microprocessor load current profiles have changed to the BOOT1, BOOT2, and BOOT3 point that using single-phase regulators is no longer a viable These pins provide the bias voltage for the corresponding solution. Designing a regulator that is cost-effective, thermally upper MOSFET drives. Connect these pins to appropriately sound, and efficient has become a challenge that only multi- chosen external bootstrap capacitors. Internal bootstrap phase converters can accomplish. The ISL6333 family of diodes connected to the PVCC pin provides the necessary controllers help simplify implementation by integrating vital bootstrap charge. functions and requiring minimal external components. The block diagrams provide a top level view of multi-phase power PHASE1, PHASE2, and PHASE3 conversion using the ISL6333 family of controllers. Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the Interleaving upper MOSFET drives. The switching of each channel in a multi-phase converter is timed to be symmetrically out-of-phase with each of the other LGATE1, LGATE2, and LGATE3 channels. In a 3-phase converter, each channel switches 1/3 These pins are used to control the lower MOSFETs. Connect cycle after the previous channel and 1/3 cycle before the these pins to the corresponding lower MOSFETs’ gates. following channel. As a result, the three-phase converter has a SS combined ripple frequency 3x greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of A resistor, RSS, placed from SS to ground or VCC, will set the combined inductor currents is reduced in proportion to the the soft-start ramp slope. Refer to Equations 20 and 21 for number of phases (Equations 1 and 2). Increased ripple proper resistor calculation. frequency and lower ripple amplitude mean that the designer On the ISL6333 and ISL6333B the SS pin also determines can use less per-channel inductance and lower total output what voltage level the internal LDO regulates the BYP1 pin capacitance for any performance specification. to when PSI# is low. Tying the RSS resistor to ground FN6520 Rev 3.00 Page 17 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C . capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. IL1 + IL2 + IL3, 7A/DIV The converter depicted in Figure 2 delivers 1.5V to a 36A load IL3, 7A/DIV from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down PWM3, 5V/DIV 12V to 1.5V at 36A. The single-phase converter has IL2, 7A/DIV 11.9ARMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current PWM2, 5V/DIV capacity as the equivalent three-phase converter. IL1, 7A/DIV INPUT-CAPACITOR CURRENT, 10A/DIV PWM1, 5V/DIV 1µs/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER CHANNEL 3 INPUT CURRENT Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load CHANNEL 2 current. The ripple component has three times the ripple INPUT CURRENT frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the CHANNEL 1 previous phase. The peak-to-peak current for each phase is INPUT CURRENT about 7A, and the DC components of the inductor currents combine to feed the load. 1µs/DIV FIGURE 2. CHANNEL INPUT CURRENTS AND To understand the reduction of ripple current amplitude in the INPUT-CAPACITOR RMS CURRENT FOR multi-phase circuit, examine the equation representing an 3-PHASE CONVERTER individual channel peak-to-peak inductor current. Active Pulse Positioning (APP) Modulated PWM V –V V IPP= -------I--N--------------O-----U----T---------------O----U-----T-- (EQ. 1) Operation Lf V S IN The controllers use a proprietary Active Pulse Positioning In Equation 1, VIN and VOUT are the input and output (APP) modulation scheme to control the internal PWM voltages respectively, L is the single-channel inductor value, signals that command each channel’s driver to turn their and fS is the switching frequency. upper and lower MOSFETs on and off. The time interval in The output capacitors conduct the ripple component of the which a PWM signal can occur is generated by an internal inductor current. In the case of multi-phase converters, the clock, whose cycle time is the inverse of the switching capacitor current is the sum of the ripple currents from each frequency set by the resistor connected to the FS pin. The of the individual channels. Compare Equation 1 to the advantage of Intersil’s proprietary Active Pulse Positioning expression for the peak-to-peak current after the summation (APP) modulator is that the PWM signal has the ability to of N symmetrically phase-shifted inductor currents in turn on at any point during this PWM time interval, and turn Equation 2. Peak-to-peak ripple current decreases by an off immediately after the PWM signal transitions high. This is amount proportional to the number of channels. Output important because it allows the controllers to quickly voltage ripple is a function of capacitance, capacitor respond to output voltage drops associated with current load equivalent series resistance (ESR), and inductor ripple spikes, while avoiding the ring back affects associated with current. Reducing the inductor ripple current allows the other modulation schemes. designer to use fewer or less costly output capacitors. The PWM output state is driven by the position of the error I = ---V----I--N-----–-----N----------V----O-----U----T-----------V----O----U-----T-- (EQ. 2) amplifier output signal, VCOMP minus the current correction CPP Lf V signal relative to the proprietary modulator ramp waveform as S IN illustrated in Figure 4. At the beginning of each PWM time Another benefit of interleaving is to reduce input ripple interval, this modified VCOMP signal is compared to the current. Input capacitance is determined in part by the internal modulator waveform. As long as the modified VCOMP maximum input ripple current. Multi-phase topologies can voltage is lower then the modulator waveform voltage, the improve overall system cost and size by lowering input ripple PWM signal is commanded low. The internal MOSFET driver current and allowing the designer to reduce the cost of input detects the low state of the PWM signal and turns off the FN6520 Rev 3.00 Page 18 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C upper MOSFET and turns on the lower synchronous Number of Active Channels MOSFET. When the modified VCOMP voltage crosses the The default number of active channels on the controllers is modulator ramp, the PWM output transitions high, turning off three for 3-phase operation. If 2-phase operation is desired, the synchronous MOSFET and turning on the upper the ISEN3- pin should be tied to the VCC pin. This will MOSFET. The PWM signal will remain high until the modified disable Channel 3, so only Channel 1 and 2 will fire. In VCOMP voltage crosses the modulator ramp again. When this 2-phase operation all of the Channel 3 pins should be left occurs the PWM signal will transition low again. unconnected including the PHASE3, LGATE3, UGATE3, BOOT3, and ISEN3+ pins. During each PWM time interval, the PWM signal can only transition high once. Once PWM transitions high it cannot PSI# (Low Power State) Operation transition high again until the beginning of the next PWM The controllers are designed to operate in both their normal time interval. This prevents the occurrence of double PWM power state for high efficiency at heavy loads, and a low pulses occurring during a single period. power state to increase the regulator’s light load efficiency. The power state of the regulator is controlled by the PSI# EXTERNAL CIRCUIT ISL6333 INTERNAL CIRCUIT pin, which is a digital logic input. When this pin is set HIGH the regulators will operate in their normal power state, with APA all active channels firing in continuous conduction mode (CCM). When the PSI# pin is set LOW the controllers 100µA - + change their operating state to the low power state to CAPA RAPA VAPA,TRIP APA increase light load efficiency. The different controllers have + - TO APA different low power operating states as described in Table 1 LOW CIRCUITRY PASS and the following sections. COMP FILTER TABLE 1. POWER STATE OPERATION DESCRIPTION ERROR AMPLIFIER PHASE CCM OR - + CONTROLLER PSI# COUNT DEM GVOT ISL6333, HIGH 3/2-phase CCM Yes FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION ISL6333B LOW 1-phase DEM Yes Adaptive Phase Alignment (APA) ISL6333A, HIGH 3/2-phase CCM No ISL6333C To further improve the transient response, the controllers LOW 1-phase CCM No also implement Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the It’s important to note that during soft-start and dynamic VID channels together at the same time during large current transitions the PSI# pin is ignored and the controllers are step, high di/dt transient events. As Figure 3 shows, the APA forced to run in their normal power state. The state of the circuitry works by monitoring the voltage on the APA pin and PSI# pin is considered again at the end of a successful comparing it to a filtered copy of the voltage on the COMP soft-start sequence or dynamic VID transition. pin. The voltage on the APA pin is a copy of the COMP pin voltage that has been negatively offset. If the APA pin ISL6333, ISL6333B LOW POWER STATE exceeds the filtered COMP pin voltage an APA event occurs On the ISL6333 and ISL6333B, when the PSI# pin is set and all of the channels are forced on. LOW, the controllers change their operating state in multiple ways. First, all active channels are turned off accept for The APA trip level is the amount of DC offset between the Channel 1. Channel 1 continues to operate but does so in COMP pin and the APA pin. This is the voltage excursion diode emulation mode (DEM). DEM only allows the upper and that the APA and COMP pin must have during a transient lower MOSFETs to turn on to allow positive current to flow event to activate the Adaptive Phase Alignment circuitry. through the output inductor. If the inductor current falls to 0A This APA trip level is set through a resistor, RAPA, that during a switching cycle, both the lower and upper MOSFETs connects from the APA pin to the COMP pin. A 100µA are turned off to allow no negative current to build up in the current flows across RAPA into the APA pin to set the APA inductor. This helps to decrease the conduction losses of the trip level as described in Equation 3. An APA trip level of MOSFETs and the inductor at very low load currents. 500mV is recommended for most applications. A 1000pF capacitor, CAPA, should also be placed across the RAPA When the ISL6333 and ISL6333B are operating in DEM, it’s resistor to help with noise immunity. important for the controllers to know whether the output inductors are standard inductors or coupled inductors. PWM V = R 10010–6 (EQ. 3) APATRIP APA operation is optimized for use with coupled inductors by minimizing switching losses and body-diode conduction FN6520 Rev 3.00 Page 19 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C losses. The FS pin determines whether the controllers In order to realize the thermal advantage, it is important that operate in the coupled inductor mode or the standard each channel in a multi-phase converter be controlled to inductor mode of operation. Tying the FS pin resistor, RFS, carry equal amounts of current at any load level. To achieve to ground will set the controllers to operate in standard this, the currents through each channel must be sensed inductor mode. Tying the RFS resistor to VCC sets the continuously every switching cycle. The sensed currents, controllers to operate in coupled inductor mode. ISEN, from each active channel are summed together and divided by the number of active channels. The resulting When PSI# is set LOW, the ISL6333 and ISL6333B also cycle average current, IAVG, provides a measure of the total utilize the new Gate Voltage Optimization Technology load-current demand on the converter during each switching (GVOT) to reduce Channel 1 lower MOSFET gate drive cycle. Channel current balance is achieved by comparing voltage. The controllers are designed to optimize the the sensed current of each channel to the cycle average Channel 1 lower MOSFET gate drive voltage to ensure high current, and making the proper adjustment to each channel efficiency in both normal and low power states. In the low pulse width based on the error. Intersil’s patented power state where the converter load current is low, current-balance method is illustrated in Figure 4, with error MOSFET driving loss is a higher percentage of the power correction for Channel 1 represented. In the figure, the cycle loss associated with the lower MOSFET. In low power state, average current, IAVG, is compared with the Channel 1 the lower gate drive voltage can therefore be reduced to sensed current, ISEN1, to create an error signal IER. decrease the driving losses of the lower MOSFETs and increase the system efficiency. More information about this + can be found in the “Gate Voltage Optimization Technology VCOMP + PWM1 TO GATE (GVOT) (ISL6333, ISL6333B Only)” on page27. - MODRUALMAPT OR - CLOOGNITCROL WAVEFORM When the PSI# pin is set HIGH, the controllers will FILTER f(s) immediately begin returning the regulator to it’s normal power state, by turning on all the active channels, placing IER IAVG them in CCM mode, and increasing the Channel 1 lower - N  ISEN3 gate drive voltage back to it’s original level. + ISEN2 ISL6333A, ISL6333C LOW POWER STATE ISEN1 On the ISL6333A and ISL6333C, when the PSI# pin is set LOW, the controllers change their operating state by turning NOTE: CHANNEL 3 IS OPTIONAL. off all active channels accept for Channel 1. This is the only FIGURE 4. CHANNEL-1 PWM FUNCTION AND change made to the regulator. Channel 1 continues to CURRENT-BALANCE ADJUSTMENT operate in CCM just as it does in the normal power state. The filtered error signal modifies the pulse width When the PSI# pin is set HIGH, the controllers immediately begin returning the regulator to it’s normal power state, by commanded by VCOMP to correct any unbalance and force turning on all the active channels. IER toward zero. The same method for error signal correction is applied to each active channel. CPURST_N Operation (ISL6333B, ISL6333C Only) The ISL6333B and ISL6333C both include a CPURST_N pin which can be utilized by microprocessors that have a CPURST_N output. The CPURST_N pin is a digital input used in conjunction with the PSI# pin to indicate whether the PWM controllers should be in a lower power state of operation or not. If CPURST_N is HIGH, the operating state of the SWITCHING PERIOD controllers is controlled by the PSI# pin. If CPURST_N is LOW, the controllers will only run in their normal power state IL and cannot be put into their light load power state. Once CPURST_N toggles HIGH again, there is a 50ms delay before the controllers recognize the state of the PSI# pin. Channel Current Balance ISEN One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer TIME avoids the complexity of driving parallel MOSFETs and the FIGURE 5. CONTINUOUS CURRENT SAMPLING expense of using expensive heat sinks and exotic magnetic materials. FN6520 Rev 3.00 Page 20 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Continuous Current Sensing The capacitor voltage VC, is then replicated across the In order to realize proper current-balance, the currents in effective internal sense resistance, RISEN. This develops a each channel are sensed continuously every switching current through RISEN which is proportional to the inductor cycle. During this time the current-sense amplifier uses the current. This current, ISEN, is continuously sensed and is ISEN inputs to reproduce a signal proportional to the then used by the controllers for load-line regulation, inductor current, IL. This sensed current, ISEN, is simply a channel-current balancing, and overcurrent detection and limiting. Equation 6 shows that the proportion between the scaled version of the inductor current. channel-current, IL, and the sensed current, ISEN, is driven The controllers support inductor DCR current sensing to by the value of the effective sense resistance, RISEN, and continuously sense each channel’s current for channel-current the DCR of the inductor. balance. The internal circuitry, shown in Figure 6 represents DCR one channel of the controller. This circuitry is repeated for each ISEN = ILR------------------ (EQ. 6) ISEN channel in the converter, but may not be active depending on how many channels are operating. The effective internal RISEN resistance is important to the current sensing process because it sets the gain of the load VIN I line regulation loop as well as the gain of the channel-current L balance loop and the overcurrent trip level. The effective UGATE L MOSFET DCR VOUT internal RISEN resistance is user programmable and is set INDUCTOR through use of the RSET pin. Placing a single resistor, RSET, DRIVER LGATE +VL(s) - COUT from the RSET pin to the VCC pin programs the effective internal RISEN resistance according to Equation 7. +VC(s) - 3 R = ----------R (EQ. 7) ISEN 400 SET R1 C1 The current sense circuitry operates in a very similar manner In ISL6333 INTERNAL CIRCUIT for negative current feedback, where inductor current is flowing from the output of the regulator to the PHASE node, SENSE opposite of flow pictured in Figure 6. However, the range of + proper operation with negative current sensing is limited to ISEN- +VC(s)- ~60% of full positive current OCP threshold. Care should be - RISEN ISEN+ taken to avoid operation with negative current feedback exceeding this threshold, as this may lead to momentary ISEN RSET loss of current balance between phases and disruption of VCC normal circuit operation. RSET Output Voltage Setting FIGURE 6. INDUCTOR DCR CURRENT SENSING The controllers use a digital to analog converter (DAC) to CONFIGURATION generate a reference voltage based on the logic signals at Inductor windings have a characteristic distributed the VID pins. The DAC decodes the logic signals into one of resistance or DCR (Direct Current Resistance). For the discrete voltages shown in Table 2. Each VID pin is simplicity, the inductor DCR is considered as a separate pulled up to an internal 1.2V voltage by a weak current lumped quantity, as shown in Figure 6. The channel current source (40µA), which decreases to 0A as the voltage at the IL, flowing through the inductor, passes through the DCR. VID pin varies from 0 to the internal 1.2V pull-up voltage. Equation 4 shows the S-domain equivalent voltage, VL, External pull-up resistors or active-high output stages can across the inductor. augment the pull-up current sources, up to a voltage of 5V. V s = I sL+DCR (EQ. 4) L L TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES A simple R-C network across the inductor (R1 and C) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC extracts the DCR voltage, as shown in Figure 6. The voltage 0 0 0 0 0 0 0 0 OFF across the sense capacitor, VC, can be shown to be 0 0 0 0 0 0 0 1 OFF proportional to the channel current IL, shown in Equation 5. --s--------L---+1 (EQ. 5) 0 0 0 0 0 0 1 0 1.60000 DCR  V s = -----------------------------------------DCRI 0 0 0 0 0 0 1 1 1.59375 C sR C +1 L 1 1 0 0 0 0 0 1 0 0 1.58750 If the R1-C1 network components are selected such that their 0 0 0 0 0 1 0 1 1.58125 time constant matches the inductor L/DCR time constant, then VC is equal to the voltage drop across the DCR. 0 0 0 0 0 1 1 0 1.57500 FN6520 Rev 3.00 Page 21 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC 0 0 0 0 0 1 1 1 1.56875 0 0 1 0 1 1 1 1 1.31875 0 0 0 0 1 0 0 0 1.56250 0 0 1 1 0 0 0 0 1.31250 0 0 0 0 1 0 0 1 1.55625 0 0 1 1 0 0 0 1 1.30625 0 0 0 0 1 0 1 0 1.55000 0 0 1 1 0 0 1 0 1.30000 0 0 0 0 1 0 1 1 1.54375 0 0 1 1 0 0 1 1 1.29375 0 0 0 0 1 1 0 0 1.53750 0 0 1 1 0 1 0 0 1.28750 0 0 0 0 1 1 0 1 1.53125 0 0 1 1 0 1 0 1 1.28125 0 0 0 0 1 1 1 0 1.52500 0 0 1 1 0 1 1 0 1.27500 0 0 0 0 1 1 1 1 1.51875 0 0 1 1 0 1 1 1 1.26875 0 0 0 1 0 0 0 0 1.51250 0 0 1 1 1 0 0 0 1.26250 0 0 0 1 0 0 0 1 1.50625 0 0 1 1 1 0 0 1 1.25625 0 0 0 1 0 0 1 0 1.50000 0 0 1 1 1 0 1 0 1.25000 0 0 0 1 0 0 1 1 1.49375 0 0 1 1 1 0 1 1 1.24375 0 0 0 1 0 1 0 0 1.48750 0 0 1 1 1 1 0 0 1.23750 0 0 0 1 0 1 0 1 1.48125 0 0 1 1 1 1 0 1 1.23125 0 0 0 1 0 1 1 0 1.47500 0 0 1 1 1 1 1 0 1.22500 0 0 0 1 0 1 1 1 1.46875 0 0 1 1 1 1 1 1 1.21875 0 0 0 1 1 0 0 0 1.46250 0 1 0 0 0 0 0 0 1.21250 0 0 0 1 1 0 0 1 1.45625 0 1 0 0 0 0 0 1 1.20625 0 0 0 1 1 0 1 0 1.45000 0 1 0 0 0 0 1 0 1.20000 0 0 0 1 1 0 1 1 1.44375 0 1 0 0 0 0 1 1 1.19375 0 0 0 1 1 1 0 0 1.43750 0 1 0 0 0 1 0 0 1.18750 0 0 0 1 1 1 0 1 1.43125 0 1 0 0 0 1 0 1 1.18125 0 0 0 1 1 1 1 0 1.42500 0 1 0 0 0 1 1 0 1.17500 0 0 0 1 1 1 1 1 1.41875 0 1 0 0 0 1 1 1 1.16875 0 0 1 0 0 0 0 0 1.41250 0 1 0 0 1 0 0 0 1.16250 0 0 1 0 0 0 0 1 1.40625 0 1 0 0 1 0 0 1 1.15625 0 0 1 0 0 0 1 0 1.40000 0 1 0 0 1 0 1 0 1.15000 0 0 1 0 0 0 1 1 1.39375 0 1 0 0 1 0 1 1 1.14375 0 0 1 0 0 1 0 0 1.38750 0 1 0 0 1 1 0 0 1.13750 0 0 1 0 0 1 0 1 1.38125 0 1 0 0 1 1 0 1 1.13125 0 0 1 0 0 1 1 0 1.37500 0 1 0 0 1 1 1 0 1.12500 0 0 1 0 0 1 1 1 1.36875 0 1 0 0 1 1 1 1 1.11875 0 0 1 0 1 0 0 0 1.36250 0 1 0 1 0 0 0 0 1.11250 0 0 1 0 1 0 0 1 1.35625 0 1 0 1 0 0 0 1 1.10625 0 0 1 0 1 0 1 0 1.35000 0 1 0 1 0 0 1 0 1.10000 0 0 1 0 1 0 1 1 1.34375 0 1 0 1 0 0 1 1 1.09375 0 0 1 0 1 1 0 0 1.33750 0 1 0 1 0 1 0 0 1.08750 0 0 1 0 1 1 0 1 1.33125 0 1 0 1 0 1 0 1 1.08125 0 0 1 0 1 1 1 0 1.32500 0 1 0 1 0 1 1 0 1.07500 FN6520 Rev 3.00 Page 22 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC 0 1 0 1 0 1 1 1 1.06875 0 1 1 1 1 1 1 1 0.81875 0 1 0 1 1 0 0 0 1.06250 1 0 0 0 0 0 0 0 0.81250 0 1 0 1 1 0 0 1 1.05625 1 0 0 0 0 0 0 1 0.80625 0 1 0 1 1 0 1 0 1.05000 1 0 0 0 0 0 1 0 0.80000 0 1 0 1 1 0 1 1 1.04375 1 0 0 0 0 0 1 1 0.79375 0 1 0 1 1 1 0 0 1.03750 1 0 0 0 0 1 0 0 0.78750 0 1 0 1 1 1 0 1 1.03125 1 0 0 0 0 1 0 1 0.78125 0 1 0 1 1 1 1 0 1.02500 1 0 0 0 0 1 1 0 0.77500 0 1 0 1 1 1 1 1 1.01875 1 0 0 0 0 1 1 1 0.76875 0 1 1 0 0 0 0 0 1.01250 1 0 0 0 1 0 0 0 0.76250 0 1 1 0 0 0 0 1 1.00625 1 0 0 0 1 0 0 1 0.75625 0 1 1 0 0 0 1 0 1.00000 1 0 0 0 1 0 1 0 0.75000 0 1 1 0 0 0 1 1 0.99375 1 0 0 0 1 0 1 1 0.74375 0 1 1 0 0 1 0 0 0.98750 1 0 0 0 1 1 0 0 0.73750 0 1 1 0 0 1 0 1 0.98125 1 0 0 0 1 1 0 1 0.73125 0 1 1 0 0 1 1 0 0.97500 1 0 0 0 1 1 1 0 0.72500 0 1 1 0 0 1 1 1 0.96875 1 0 0 0 1 1 1 1 0.71875 0 1 1 0 1 0 0 0 0.96250 1 0 0 1 0 0 0 0 0.71250 0 1 1 0 1 0 0 1 0.95625 1 0 0 1 0 0 0 1 0.70625 0 1 1 0 1 0 1 0 0.95000 1 0 0 1 0 0 1 0 0.70000 0 1 1 0 1 0 1 1 0.94375 1 0 0 1 0 0 1 1 0.69375 0 1 1 0 1 1 0 0 0.93750 1 0 0 1 0 1 0 0 0.68750 0 1 1 0 1 1 0 1 0.93125 1 0 0 1 0 1 0 1 0.68125 0 1 1 0 1 1 1 0 0.92500 1 0 0 1 0 1 1 0 0.67500 0 1 1 0 1 1 1 1 0.91875 1 0 0 1 0 1 1 1 0.66875 0 1 1 1 0 0 0 0 0.91250 1 0 0 1 1 0 0 0 0.66250 0 1 1 1 0 0 0 1 0.90625 1 0 0 1 1 0 0 1 0.65625 0 1 1 1 0 0 1 0 0.90000 1 0 0 1 1 0 1 0 0.65000 0 1 1 1 0 0 1 1 0.89375 1 0 0 1 1 0 1 1 0.64375 0 1 1 1 0 1 0 0 0.88750 1 0 0 1 1 1 0 0 0.63750 0 1 1 1 0 1 0 1 0.88125 1 0 0 1 1 1 0 1 0.63125 0 1 1 1 0 1 1 0 0.87500 1 0 0 1 1 1 1 0 0.62500 0 1 1 1 0 1 1 1 0.86875 1 0 0 1 1 1 1 1 0.61875 0 1 1 1 1 0 0 0 0.86250 1 0 1 0 0 0 0 0 0.61250 0 1 1 1 1 0 0 1 0.85625 1 0 1 0 0 0 0 1 0.60625 0 1 1 1 1 0 1 0 0.85000 1 0 1 0 0 0 1 0 0.60000 0 1 1 1 1 0 1 1 0.84375 1 0 1 0 0 0 1 1 0.59375 0 1 1 1 1 1 0 0 0.83750 1 0 1 0 0 1 0 0 0.58750 0 1 1 1 1 1 0 1 0.83125 1 0 1 0 0 1 0 1 0.58125 0 1 1 1 1 1 1 0 0.82500 1 0 1 0 0 1 1 0 0.57500 FN6520 Rev 3.00 Page 23 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) the output voltage can effectively be level shifted in a direction which works to achieve the load line regulation VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC required by these manufacturers. 1 0 1 0 0 1 1 1 0.56875 In other cases, the designer may determine that a more 1 0 1 0 1 0 0 0 0.56250 cost-effective solution can be achieved by adding droop. 1 0 1 0 1 0 0 1 0.55625 Droop can help to reduce the output voltage spike that 1 0 1 0 1 0 1 0 0.55000 results from fast load current demand changes. 1 0 1 0 1 0 1 1 0.54375 EXTERNAL CIRCUIT ISL6333 INTERNAL CIRCUIT 1 0 1 0 1 1 0 0 0.53750 COMP 1 0 1 0 1 1 0 1 0.53125 VID DAC 1 0 1 0 1 1 1 0 0.52500 CC 1 0 1 0 1 1 1 1 0.51875 REF 1k 1 0 1 1 0 0 0 0 0.51250 RC 1 0 1 1 0 0 0 1 0.50625 CREF + ERROR 1 0 1 1 0 0 1 0 0.50000 FB AMPLIFIER - VCOMP 1 1 1 1 1 1 1 0 OFF IOFS 1 1 1 1 1 1 1 1 OFF IDROOP IAVG + Voltage Regulation RFB (VDROOP + VOFS) - The integrating compensation network shown in Figure 7, VDIFF insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, VOUT+ VSEN remote-sense and error amplifiers. Intersil specifies the + guaranteed tolerance of the controllers to include the VOUT- RGND - combined tolerances of each of these elements. DIFFERENTIAL REMOTE-SENSE The output of the error amplifier, VCOMP, is compared to the AMPLIFIER modulator waveform to generate the PWM signals. The FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE PWM signals control the timing of the Internal MOSFET REGULATION WITH OFFSET ADJUSTMENT drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the The magnitude of the spike is dictated by the ESR and ESL output voltage to be equal to Equation 8. The internal and of the output capacitors selected. By positioning the no-load external circuitry that controls voltage regulation is illustrated voltage level near the upper specification limit, a larger in Figure 7. negative spike can be sustained without crossing the lower V = V –V –V (EQ. 8) limit. By adding a well controlled output impedance, the OUT REF OFS DROOP output voltage under load can effectively be level shifted The controllers incorporate an internal differential down so that a larger positive spike can be sustained without remote-sense amplifier in the feedback path. The amplifier crossing the upper specification limit. removes the voltage error encountered when measuring the As shown in Figure 7, a current proportional to the average output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output current of all active channels, IAVG, flows from the IDROOP pin voltage. Connect the microprocessor sense pins to the through a load line regulation resistor RFB. The resulting non-inverting input, VSEN, and inverting input, RGND, of the voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state remote-sense amplifier. The remote sense output, VDIFF, is value defined as Equation 9: connected to the inverting input of the error amplifier through an external resistor. VDROOP = IAVG RFB (EQ. 9) The regulated output voltage is reduced by the droop voltage Load Line (Droop) Regulation VDROOP. The output voltage as a function of load current is Some microprocessor manufacturers require a precisely derived by combining Equations 6, 7, 8, and 9. controlled output resistance. This dependence of output vreogltualgaeti oonn. lBoya da dcduirnregn at iws eolfl tceonn tterormlleedd o“durtpouotp i”m opr e“ldoaandc lein, e” VOUT = VREF–VOFS–I--O---N--U----T-- R-D----S-C---E--R--T--4----03---0--- RFB (EQ. 10) FN6520 Rev 3.00 Page 24 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C In Equation 10, VREF is the reference voltage, VOFS is the VDIFF programmed offset voltage, IOUT is the total output current of the converter, RISEN is the internal sense resistor connected - ISL6333 INTERNAL CIRCUIT to the ISEN+ pin, RFB is the feedback resistor, N is the active VOFS RFB number of channels, and DCR is the Inductor DCR value. + VREF E/A Therefore the equivalent loadline impedance, i.e. droop FB impedance, is equal to Equation 11: IOFS RFB DCR 400 RLL = -----N-------R-------------------3------ (EQ. 11) SET Output-Voltage Offset Programming VCC The controllers allow the designer to accurately adjust the offset voltage by connecting a resistor, ROFS, from the OFS ROFS -1.6V pin to VCC or GND. When ROFS is connected between OFS + + and VCC, the voltage across it is regulated to 1.6V. This 0.3V OFS - causes a proportional current (IOFS) to flow into the OFS pin and out of the FB pin, providing a negative offset. If ROFS is GND VCC connected to ground, the voltage across it is regulated to FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE 0.3V, and IOFS flows into the FB pin and out of the OFS pin, PROGRAMMING providing a positive offset. The offset current flowing through Dynamic VID the resistor between VSEN and FB will generate the desired Modern microprocessors need to make changes to their core offset voltage which is equal to the product (IOFS x RFB). voltage as part of normal operation. They direct the controllers These functions are shown in Figures 8 and 9. to do this by making changes to the VID inputs. The VDIFF controllers are required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner, + ISL6333 INTERNAL CIRCUIT VOFS RFB supervising a safe output voltage transition without - VREF discontinuity or disruption. E/A FB The controllers check for VID changes by comparing the internal DAC code to the VID pin inputs on the positive edge IOFS of an internal 5.55MHz clock. If a new code is established on the VID inputs and it remains stable for 3 consecutive readings (360ns to 540ns), the controllers recognize the new code and begins incrementing/decrementing the DAC in 6.25mV steps at a stepping frequency of 1.85MHz. This controlled slew rate of 6.25mV/540ns (11.6mV/µs) continues - until the VID input and DAC are equal. Thus, the total time 1.6V + + required for a VID change, tDVID, is dependent only on the size OFS - 0.3V of the VID change (VVID). ROFS The time required for a ISL6333-based converter to make a GND VCC 1.6V to 0.5V reference voltage change is about 95µs, as GND FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE calculated using Equation 14. PROGRAMMING V t = 54010–9-----------V---I--D----- (EQ. 14) DVID 0.00625 Once the desired output offset voltage has been determined, use Equations 12 and 13 to set ROFS: VID “Off” DAC Codes The Intel VR11 VID tables include “Off” DAC codes, which For Negative Offset (connect ROFS to VCC): indicate to the controllers to disable all regulation. Recognition 1.6R R = -------------------F----B--- (EQ. 12) of these codes is slightly different in that they must be stable for OFS V OFFSET 4 consecutive readings of a 5.55MHz clock (540ns to 720ns) to be recognized. Once an “Off” code is recognized the For Positive Offset (connect ROFS to GND): controllers latch off, and must be reset by toggling the EN pin. 0.3R FB R = -------------------------- (EQ. 13) OFS V OFFSET FN6520 Rev 3.00 Page 25 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Compensating Dynamic VID Transitions Driver Operation During a VID transition, the resulting change in voltage on the FB Adaptive Zero Shoot-Through Deadtime Control pin and the COMP pin causes an AC current to flow through the The integrated drivers incorporate an adaptive deadtime control error amplifier compensation components from the FB to the technique to minimize deadtime and to prevent the upper and COMP pin. This current then flows through the feedback resistor, lower MOSFETs from conducting simultaneously. This results in RFB, and can cause the output voltage to overshoot or high efficiency from the reduced freewheeling time of the lower undershoot at the end of the VID transition. In order to ensure the MOSFET body-diode conduction. This is accomplished by smooth transition of the output voltage during a VID change, a ensuring either rising gate turns on its MOSFET with minimum VID-on-the-fly compensation network is required. This network is and sufficient delay after the other has turned off. composed of a resistor and capacitor in series, RDVC and CDVC, between the DVC and the FB pin. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches 1.75V. At this time the UGATE is This VID-on-the-fly compensation network works by sourcing released to rise. Once the PHASE is high, the advanced adaptive AC current into the FB node to offset the effects of the AC shoot-through circuitry monitors the PHASE and UGATE voltages current flowing from the FB to the COMP pin during a VID during a PWM falling edge and the subsequent UGATE turn-off. If transition. To create this compensation current the controllers either the UGATE falls to less than 1.75V above the PHASE or set the voltage on the DVC pin to be 2x the voltage on the REF the PHASE falls to less than +0.8V, the LGATE is released to turn pin. Since the error amplifier forces the voltage on the FB pin on. and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin Internal Bootstrap Device voltage. The RC compensation components, RDVC and CDVC, All three integrated drivers feature an internal bootstrap can then be selected to create the desired amount of schottky diode. Simply adding an external capacitor across the compensation current. BOOT and PHASE pins completes the bootstrap circuit. The RFB IDVC = IC bootstrap function is also designed to prevent the bootstrap VDIFF capacitor from overcharging due to the large negative swing at IC the PHASE node. This reduces voltage stress on the boot to IDVC phase pins. CC RC The bootstrap capacitor should have a maximum voltage rating CDVC RDVC DVC FB COMP that’s at least 30% above PVCC and its capacitance value can be chosen from Equation 18: Q GATE x2 - C -------------------------------------- REF BOOT_CAP VBOOT_CAP (EQ. 18) + CREF AMERPLRIOFIRER QGATE= Q-----G-----1V-------P-----V----C-----C---NQ1 GS1 VDAC ISL6333 INTERNAL CIRCUIT where QG1 is the amount of gate charge per upper MOSFET FIGURE 10. DYNAMIC VID COMPENSATION NETWORK at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable The amount of compensation current required is dependant on droop in the rail of the upper gate drive. the modulator gain of the system, K1, and the error amplifier R-C 1.6 components, RC and CC, that are in series between the FB and 1.4 COMP pins. Use Equations 15, 16, and 17 to calculate the RC component values, RDVC and CDVC, for the VID-on-the-fly 1.2 cvoolmtapgeen fsoar ttiohne npeotwweorr ktr.a Fino;r V thPe-Ps eis e tqhuea otisocnilsla: tVoIrN r aism thpe a imnppulittu de (µF)P 1.0 A (1.5V); and RC and CC are the error amplifier R-C components _C 0.8 T between the FB and COMP pins. O O K1 = -V-----I-N---- A = -----K-----1------- (EQ. 15) CB 0.6 QGATE = 100nC V K1–1 PP 0.4 50nC RDVC = ARC (EQ. 16) 0.2 20nC C 0.0 C = -----C--- (EQ. 17) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DVC A VBOOT_CAP (V) FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE FN6520 Rev 3.00 Page 26 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C . 12.0 +40°C THERMAL EXTERNAL CIRCUIT ISL6333, ISL6333B INTERNAL CIRCUIT 11.8 PVCC1 +12V SET BY STATE V) 11.6 GVOT OF PSI# AND E ( 1.0µF REG. SS PINS G A 11.4 T L O 1 V 11.2 C BYP1 LVC 11.0 1, 1.0µF LVCC1 YP 10.8 B 10.6 PVCC2_3 LVCC2, LVCC3 +12V 10.4 0 20 40 60 80 100 120 1.0µF AVERAGE LOAD CURRENT (mA) FIGURE 13. BYP1, LVCC1 VOLTAGE WHEN PSI# IS HIGH UVCC1, UVCC2, PUVCC UVCC3 +5V TO +12V 1.0µF LVCC = LOWER GATE DRIVE UVCC = UPPER GATE DRIVE 8.5 +40°C THERMAL FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND 8.0 GAVE VOLTAGE OPTIMIZATION (GVOT) RSS TIED TO VCC Gate Voltage Optimization Technology (GVOT) E (V) 7.5 G (ISL6333, ISL6333B Only) A LT 7.0 O The ISL6333 and ISL6333B are designed to optimize the V 1 Channel 1 lower MOSFET gate drive voltage to ensure high C 6.5 C efficiency in both normal and low power states. In the normal LV power state when the converter load current is high, the YP1, 6.0 RSS TIED TO GND conduction losses of the lower MOSFETs play a large role in B the overall system efficiency. In normal power state, the lower 5.5 gate drive voltage should be higher to decrease the conduction losses of the lower MOSFETs and increase the system 5.0 efficiency. In the low power state, where the converter load 0 20 40 60 80 100 120 current is significantly smaller, MOSFET driving loss becomes AVERAGE LOAD CURRENT (mA) a much higher percentage of power loss associated with the FIGURE 14. BYP1, LVCC1 VOLTAGE WHEN PSI# IS LOW lower MOSFET. In low power state, the lower gate drive As Figures 13 and 14 illustrate, the internal regulator has been voltage can therefore be reduced to decrease the driving designed so that its output voltage, BYP1, is dependent upon losses of the lower MOSFETs and increase the system the average load current. In the normal power state, when PSI# efficiency. is high, the ISL6333 and ISL6333B regulate BYP1 to around This gate drive voltage optimization is accomplished by an 11.2V at a 50mA average load current. In the low power state, internal linear regulator that regulates the Channel 1 lower when PSI# is low, BYP1 is regulated down to one of two gate drive voltage, LVCC1, to certain levels depending on the voltages depending on the state of the SS pin. If the SS pin is state of the PSI# and SS pins. The input and output of this tied to ground through the RSS resistor, BYP1 is regulated down internal regulator is the PVCC1 pin and BYP1 pin, respectively. to 5.75V at a 50mA average load current. If the SS pin is tied to The regulator input, PVCC1, should be connected to a +12V VCC through the RSS resistor, BYP1 is regulated down to 7.75V source and decoupled with a quality 1.0µF ceramic capacitor. at a 50mA average load current. The regulator output, BYP1, is internally connected to the It is possible to disable the internal GVOT regulator by shorting lower gate drive of the Channel 1 MOSFET driver, LVCC1. The the PVCC1 pin to the BYP1 pin. This essentially bypasses the BYP1 pin should also be decoupled using a quality 1.0µF internal regulator setting the Channel 1 lower gate drive voltage, ceramic capacitor. LVCC1, to the voltage input on the PVCC1 pin. FN6520 Rev 3.00 Page 27 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Upper MOSFET Gate Drive Voltage Versatility 3. The driver bias voltage applied at the PVCC1, PVCC2_3, PVCC2, PVCC3, PUVCC, and BYP1 pins must reach the The controllers provide the user flexibility in choosing the internal power-on reset (POR) rising threshold. Hysteresis upper MOSFET gate drive voltage for efficiency optimization. between the rising and falling thresholds assure that once The controllers tie all the upper gate drive rails together to the enabled, the controllers will not inadvertently turn off unless PUVCC pin. Simply applying a voltage from +5V up to +12V on the bias voltages drops substantially (see “Electrical PUVCC sets all of the upper gate drive rail voltages Specifications” on page 13). simultaneously. Once all of these conditions are met the controllers will begin Initialization the soft-start sequence and will ramp the output voltage up as described in “Soft-Start” on page28. Prior to initialization, proper conditions must exist on the EN, VCC, PVCC1, PVCC2_3, PUVCC, BYP1 and VID pins. When Soft-Start the conditions are met, the controllers begin soft-start. Once the The soft-start function allows the converter to bring up the output voltage is within the proper window of operation, the output voltage in a controlled fashion, resulting in a linear controllers assert VR_RDY. ramp-up. The soft-start sequence is composed of four periods, as shown in Figure 16. Once the controllers are released from ISL6333 INTERNAL CIRCUIT shutdown and soft-start begins (as described in “Enable and VCC Disable” on page28), there will be a fixed delay period, td1, of PVCC1 typically 1.10ms. After this delay period, the controllers will begin the first soft-start ramp, increasing the output voltage PVCC2_3 until it reaches the 1.1V VBOOT voltage. PUVCC BYP1 POR ENABLE CIRCUIT COMPARATOR VOUT, 500mV/DIV EN + - td1 td2 td3 td4 td5 0.86V SOFT-START EN AND FAULT LOGIC VR_RDY FIGURE 15. POWER SEQUENCING USING THRESHOLD-SENSITIVE ENABLE (EN) 500µs/DIV FUNCTION FIGURE 16. SOFT-START WAVEFORMS Enable and Disable The controllers will then regulate the output voltage at 1.1V for While in shutdown mode, the LGATE and UGATE signals are another fixed delay period, td3, of typically 93µs. At the end of held low to assure the MOSFETs remain off. The following the td3 period, the controllers will read the VID signals. It is input conditions must be met before the controllers are recommended that the VID codes be set no later then 50µs released from shutdown mode to begin the soft-start startup into period td3. If the VID code is valid, the controllers will sequence: initiate the second soft-start ramp, regulating the output voltage 1. The bias voltage applied at VCC must reach the internal up to the VID voltage ± any offset or droop voltage. power-on reset (POR) rising threshold. Once this threshold The soft-start time is the sum of the 4 periods as shown in is reached, proper operation of all aspects of the controllers Equation 19. are guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the controllers will not t = t +t +t +t (EQ. 19) SS d1 d2 d3 d4 inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 13). 2. The voltage on EN must be above 0.86V. The enable During td2 and td4, the controllers digitally control the DAC voltage change at 6.25mV per step. The time for each step is comparator holds the controllers in shutdown until the voltage at EN rises above 0.86V. The enable comparator determined by the frequency of the soft-start oscillator, which is has 104mV of hysteresis to prevent bounce. defined by the resistor RSS on the SS pin. The soft-start ramp FN6520 Rev 3.00 Page 28 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C times, td2 and td4, can be calculated based on Equations 20 within the proper levels, and whether any fault conditions exist. and 21: This pin should be tied through a resistor to a voltage source td2 = 1.1RSS810–3s (EQ. 20) that’s equal to or less then VCC. t = V –1.1 R 810–3s (EQ. 21) d4 VID SS IAVG + OCL+ I1 For example, when VID is set to 1.5V and the RSS is set at OCP - 140µA 100k, the first soft-start ramp time td2 will be 880µs and the 100µA - REPEAT FOR second soft-start ramp time td4 will be 320µs. EACH CHANNEL After the DAC voltage reaches the final VID setting, VR_RDY DAC IMON will be set to high with the fixed delay td5. The typical value for + OCP td5 is 93µs. +175mV - VOCP OUTPUT PRECHARGED ABOVE DAC LEVEL SOFT-START, FAULT AND CONTROL LOGIC 1.280V OUTPUT PRECHARGED BELOW DAC LEVEL - OVP GND> VOUT (0.5V/DIV) + VR_RDY VDIFF - GND> EN (5V/DIV) UV 0.50xDAC + t1 t2 t3 ISL6333 INTERNAL CIRCUITRY FIGURE 17. SOFT-START WAVEFORMS FOR ISL6333-BASED MULTI-PHASE CONVERTER FIGURE 18. POWER GOOD AND PROTECTION CIRCUITRY Pre-Biased Soft-Start VR_RDY indicates whether VDIFF is within specified overvoltage The controllers also have the ability to start up into a and undervoltage limits after a fixed delay from the end of soft- pre-charged output, without causing any unnecessary start. VR_RDY transitions low when an undervoltage, disturbance. The FB pin is monitored during soft-start, and overvoltage, or overcurrent condition is detected or when the should it be higher than the equivalent internal ramping controllers are disabled by a reset from EN, POR, or one of the reference voltage, the output drives hold both MOSFETs off. no-CPU VID codes. In the event of an overvoltage or overcurrent Once the internal ramping reference exceeds the FB pin condition, or a no-CPU VID code, the controllers latch off and potential, the output drives are enabled, allowing the output to VR_RDY will not return high until EN is toggled and a successful ramp from the pre-charged level to the final level dictated by the soft-start is completed. In the case of an undervoltage event, DAC setting. Should the output be pre-charged to a level VR_RDY will return high when the output voltage rises above the exceeding the DAC setting, the output drives are enabled at the undervoltage hysteresis level. VR_RDY is always low prior to the end of the soft-start period, leading to an abrupt correction in the end of soft-start. output voltage down to the DAC-set level. Overvoltage Protection Fault Monitoring and Protection The controllers constantly monitor the difference between the The controllers actively monitor the output voltage and current to VSEN and RGND voltages to detect if an overvoltage event detect fault conditions. Fault monitors trigger protective measures occurs. During soft-start, while the DAC is ramping up, the to prevent damage to a microprocessor load. One common overvoltage trip level is the higher of a fixed voltage 1.280V or VR_RDY indicator is provided for linking to external system DAC + 175mV. Upon successful soft-start, the overvoltage trip monitors. The schematic in Figure 18 outlines the interaction level is only DAC + 175mV. When the output voltage rises above between the fault monitors and the VR_RDY signal. the OVP trip level actions are taken by the controllers to protect the microprocessor load. VR_RDY Signal At the inception of an overvoltage event, LGATE1, LGATE2, The VR_RDY pin is an open-drain logic output that signals and LGATE3 are commanded high and the VR_RDY signal is whether or not the controllers are regulating the output voltage driven low. This turns on the all of the lower MOSFETs and FN6520 Rev 3.00 Page 29 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C pulls the output voltage below a level that might cause damage Overcurrent Protection to the load. The LGATE outputs remain high until VDIFF falls The controllers take advantage of the proportionality between 110mV below the OVP threshold that tripped the overvoltage the load current and the average current, IAVG, to detect an protection circuitry. The controllers will continue to protect the overcurrent condition. Two different methods of detecting load in this fashion as long as the overvoltage condition recurs. overcurrent events are available on the controllers. The first Once an overvoltage condition ends the controllers latch off, method continually compares the average sense current with a and must be reset by toggling EN, or through POR, before a constant 100µA OCP reference current, as shown in Figure18. soft-start can be reinitiated. Once the average sense current exceeds the OCP reference There is an OVP condition that exists that will not latch off the current, a comparator triggers the converter to begin controllers. During a soft-start sequence, if the VDIFF voltage is overcurrent protection procedures. above the OVP threshold an overvoltage event will occur, but will For this first method the overcurrent trip threshold is dictated by be released once VDIFF falls 110mV below the OVP threshold. If the DCR of the inductors, the number of active channels, and VDIFF then rises above the OVP trip threshold a second time, the the RSET pin resistor, RSET. To calculate the overcurrent trip controllers will be latched off and cannot be restarted until the level, IOCP, using this method use Equation22, where N is the controllers are reset. number of active channels, DCR is the individual inductor’s Pre-POR Overvoltage Protection DCR, and RSET is the RSET pin resistor value. –6 Prior to the controller and driver bias pins exceeding their POR I = 1----0---0--------1---0--------------R-----S----E----T-------N---------3-- (EQ. 22) levels, the controllers are designed to protect the load from any OCP DCR400 overvoltage events that may occur. This is accomplished by During VID-on-the-fly transitions the overcurrent trip level for means of an internal 10k resistor tied from PHASE to LGATE, this method is boosted to prevent false overcurrent trip events which turns on the lower MOSFET to control the output voltage that can occur. Starting from the beginning of a dynamic VID until the overvoltage event ceases or the input power supply transition, the overcurrent trip level is boosted to 140µA. The cuts off. For complete protection, the low side MOSFET should OCP level will stay at this boosted level until 50µs after the end have a gate threshold well below the maximum voltage rating of of the dynamic VID transition, at which point it will return to the the load/microprocessor. typical 100µA trip level. In the event that during normal operation the controller or The second method for detecting overcurrent events driver bias voltages fall back below their POR threshold, the continuously compares the voltage on the IMON pin, VIMON, to pre-POR overvoltage protection circuitry reactivates to protect the overcurrent protection voltage, VOCP, as shown in Figure from any more pre-POR overvoltage events. 18. The average channel sense current flows out the IMON pin Undervoltage Detection and through RIMON, creating the IMON pin voltage which is proportional to the output current. When the IMON pin voltage The undervoltage threshold is set at DAC*0.50V of the VID code. When the output voltage (VDIFF) is below the exceeds the VOCP voltage threshold, the overcurrent protection circuitry activates. Since the IMON pin voltage is undervoltage threshold, VR_RDY gets pulled low. No other proportional to the output current, the overcurrent trip level, action is taken by the controllers. VR_RDY will return high if the output voltage rises above DAC*0.60V. IOCP, can be set by selecting the proper value for RIMON, as shown in Equation 23. Open Sense Line Prevention 3V R N I = -------------O----C----P-------------S----E----T----------- (EQ. 23) In the case that either of the remote sense lines, VSEN or OCP DCRRIOUT400 GND, become open, the controllers are designed to prevent Once the output current exceeds the overcurrent trip level, the regulator from regulating. This is accomplished by means VIMON will exceed VOCP and a comparator will trigger the of a small 5µA pull-up current on VSEN, and a pull-down converter to begin overcurrent protection procedures. current on RGND. If the sense lines are opened at any time, the voltage difference between VSEN and RGND will increase At the beginning of an overcurrent shutdown, the controllers until an overvoltage event occurs, at which point overvoltage turn off both upper and lower MOSFETs and lowers VR_RDY. protection activates and the controllers stop regulating. The The controllers will then attempt to soft-start after a delay of controllers will be latched off and cannot be restarted until they are typically 8xTD1. If the overcurrent fault remains, the trip-retry reset. cycles will continue until either the controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. FN6520 Rev 3.00 Page 30 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25A and 30A. All surface-mount designs will tend toward the lower OUTPUT CURRENT, 50A/DIV end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, 0A inductors and heat-dissipating surfaces. MOSFETS OUTPUT VOLTAGE, 500mV/DIV The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. 0V FIGURE 19. OVERCURRENT BEHAVIOR IN HICCUP MODE LOWER MOSFET POWER CALCULATION Individual Channel Overcurrent Limiting The calculation for power loss in the lower MOSFET is simple, The controllers have the ability to limit the current in each since virtually all of the loss in the lower MOSFET is due to individual channel without shutting down the entire regulator. current conducted through the channel resistance (rDS(ON)). In This is accomplished by continuously comparing the sensed Equation 24, IM is the maximum continuous output current, IP- currents of each channel with a constant 140µA OCL reference P is the peak-to-peak inductor current (see Equation 1), and d current, as shown in Figure 18. If a channel’s individual sensed is the duty cycle (VOUT/VIN). cchuarrnennet le ixsc iememdse dthiaiste OlyC foLr climedit ,l othwe, aUnGdA tTheE LsGigAnTalE o sf itghnaat l is PLOW1 = rDSON I-N-M----21–d+I--L------P------P----1--2--2-----1----–-----d----- (EQ. 24) forced high. This turns off the upper MOSFET(s), turns on the lower MOSFET(s), and stops the rise of current in that An additional term can be added to the lower-MOSFET loss channel, forcing the current in the channel to decrease. That equation to account for additional loss accrued during the dead channel’s UGATE signal will not be able to return high until the time when inductor current is flowing through the lower-MOSFET sensed channel current falls back below the 140µA reference. body diode. This term is dependent on the diode forward voltage During VID-on-the-fly transitions the OCL trip level is boosted at IM, VD(ON), the switching frequency, fS, and the length of dead to prevent false overcurrent limiting events that can occur. times, td1 and td2, at the beginning and the end of the lower- Starting from the beginning of a dynamic VID transition, the MOSFET conduction interval respectively. ostvaeyr caut rtrheins tb toriops lteevde ll eisv eblo uonsttiel 5d0 tµo s1 a9f6teµrA t.h Teh een Od CofL t hleev el will PLOW2 = VDONfS I--NM----+I--P---2----P--- td1 +I--NM----–I--P---2----P--- td2 dynamic VID transition, at which point it will return to the typical (EQ. 25) 140µA trip level. The total maximum power dissipated in each lower MOSFET is MOSFETs General Design Guide approximated by the summation of PLOW(1) and PLOW(2). This design guide is intended to provide a high-level explanation UPPER MOSFET POWER CALCULATION of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic In addition to rDS(ON) losses, a large portion of the upper-MOSFET losses are due to currents conducted across skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on include schematics, bills of materials, and example board switching frequency, the power calculation is more complex. layouts for all common microprocessor applications. Upper MOSFET losses can be divided into separate Power Stages components involving the upper-MOSFET switching times, the The first step in designing a multi-phase converter is to lower-MOSFET body-diode reverse-recovery charge, Qrr, and determine the number of phases. This determination depends the upper MOSFET rDS(ON) conduction loss. heavily on the cost analysis, which in turn depends on system When the upper MOSFET turns off, the lower MOSFET does constraints that differ from one design to the next. Principally, not conduct any portion of the inductor current until the voltage the designer will be concerned with whether components can at the phase node falls below ground. Once the lower be mounted on both sides of the circuit board, whether MOSFET begins conducting, the current in the upper MOSFET through-hole components are permitted, the total board space falls to zero as the current in the lower MOSFET ramps up to available for power-supply circuitry, and the maximum amount FN6520 Rev 3.00 Page 31 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C assume the full inductor current. In Equation 26, the required and their corresponding average driver current can be estimated time for this commutation is t1 and the approximated with Equations 30 and 31, respectively. associated power loss is PUP(1). P = P +P +I VCC (EQ. 30) Qg_TOT Qg_Q1 Qg_Q2 Q I I t  P V --M----+--P-------P----1-- f (EQ. 26) UP1 IN N 2  2 S 3 P = ---Q PVCCF N N At turn-on, the upper MOSFET begins to conduct and this Qg_Q1 2 G1 SW Q1 PHASE transition occurs over a time t2. In Equation 27, the approximate power loss is PUP(2). P = Q PVCCF N N Qg_Q2 G2 SW Q2 PHASE I I  t  P V --M----–--P-------P----2--f (EQ. 27) (EQ. 31) UP2 IN N 2  2 S I = 3---Q N +Q N N F +I DR 2 G1 Q1 G2 Q2 PHASE SW Q A third component involves the lower MOSFET reverse-recovery charge, Qrr. Since the inductor current has In Equations 30 and 31, PQg_Q1 is the total upper gate drive fully commutated to the upper MOSFET before the power loss and PQg_Q2 is the total lower gate drive power loss; lower-MOSFET body diode can recover all of Qrr, it is the gate charge (QG1 and QG2) is defined at the particular gate conducted through the upper MOSFET across VIN. The power to source drive voltage PVCC in the corresponding MOSFET dissipated as a result is PUP(3) shown in Equation 28. data sheet; IQ is the driver total quiescent current with no load at P = V Q f (EQ. 28) both drive outputs; NQ1 and NQ2 are the number of upper and UP3 IN rr S lower MOSFETs per phase, respectively; NPHASE is the number Finally, the resistive part of the upper MOSFET is given in of active phases. The IQ*VCC product is the quiescent power of the controller without capacitive load and is typically 75mW at Equation 29 as PUP(4).. 300kHz. 2 2 I  I PUP4rDSONd -N-M---- +--P1----2---P-- (EQ. 29) PVCC BOOT D The total power dissipated by the upper MOSFET at full load CGD can now be approximated as the summation of the results from RHI1 UGATE G Equations 26, 27, 28 and 29. Since the power equations CDS depend on MOSFET parameters, choosing the correct RLO1 RG1 RGI1 MOSFETs can be an iterative process involving repetitive CGS Q1 solutions to the loss equations for different MOSFETs and S different switching frequencies. PHASE Package Power Dissipation FIGURE 20. TYPICAL UPPER-GATE DRIVE TURN-ON PATH When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controllers. Since there are a total of three PVCC drivers in the controller package, the total power dissipated by D all three drivers must be less than the maximum allowable power dissipation for the QFN package. CGD Calculating the power dissipation in the drivers for a desired RHI2 LGATE G CDS application is critical to ensure safe operation. Exceeding the RLO2 RG2 RGI2 maximum allowable power dissipation level will push the IC CGS Q2 beyond the maximum recommended operating junction S temperature of +125°C. The maximum allowable IC power dissipation for the 7x7 QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page37 for FIGURE 21. TYPICAL LOWER-GATE DRIVE TURN-ON PATH thermal transfer improvement suggestions. When designing the controllers into an application, it is The total gate drive power losses are dissipated among the recommended that the following calculation is used to ensure safe resistive components along the transition path and in the operation at the desired frequency for the selected MOSFETs. bootstrap diode. The portion of the total power dissipated in the The total gate drive power losses, PQg_TOT, due to the gate controller itself is the power dissipated in the upper drive path charge of MOSFETs and the integrated driver’s internal circuitry resistance, PDR_UP, the lower drive path resistance, PDR_UP, and in the boot strap diode, PBOOT. The rest of the power will be FN6520 Rev 3.00 Page 32 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of the MOSFETs. I L Figures 20 and 21 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the UGATE L DCR VOUT MOSFET controller itself, PDR, can be roughly estimated as calculated in INDUCTOR Equation 32: DRIVER LGATE COUT +VL(s) - P = P +P +P +I VCC DR DR_UP DR_LOW BOOT Q +VC(s) - P P = -----Q----g----_--Q-----1- R1 C1 BOOT 3 In ISL6333 INTERNAL  RHI1 RLO1  PQg_Q1 CIRCUIT P = --------------------------------------+------------------------------------------------------------- DR_UP RHI1+REXT1 RLO1+REXT1 3 (EQ. 32) SENSE PDR_LOW = R-----H----I--2--R---+--H--R--I--2-E----X----T---2--+R-----L---O-----2R----+-L---O-R----2-E----X----T---2--P-----Q----g-2---_---Q----2- +- +VC(s)- ISEN- RISEN ISEN+ R R REXT1 = RG1+-N----G-----I-1-- REXT2 = RG2+-N----G-----I-2-- ISEN RSET Q1 Q2 VCC RSET Inductor DCR Current Sensing Component Selection FIGURE 22. DCR SENSING CONFIGURATION The controllers sense each individual channel’s inductor current Use Equation 34 to calculate the value of RSET. In by detecting the voltage across the output inductor DCR of that Equation 34, DCR is the DCR of the output inductor at room channel (As described in the “Continuous Current Sensing” on temperature, IOCP is the desired overcurrent trip level, and N is page21). As Figure 22 illustrates, an R-C network is required to the number of phases. It is recommended that the desired accurately sense the inductor DCR voltage and convert this overcurrent trip level, IOCP, be chosen so that it’s 30% larger information into a current, which is proportional to the total output then the maximum load current expected. current. The time constant of this R-C network must match the time constant of the inductor L/DCR. R = --------D-----C-----R----------I--O-----C----P---4----0---0--- (EQ. 34) SET –6 N 3 10010 Follow the steps below to choose the component values for this RC network. Due to errors in the inductance or DCR it may be necessary to adjust the value of R1 to match the time constants correctly. 1. Choose an arbitrary value for C1. The recommended value The effects of time constant mismatch can be seen in the form is 0.1µF. of droop overshoot or undershoot during the initial load 2. Plug the inductor L and DCR component values, and the transient spike, as shown in Figure 23. Follow the steps below value for C1 chosen in step 1, into Equation 33 to calculate to ensure the R-C and inductor L/DCR time constants are the value for R1. matched accurately. R = ------------L------------- (EQ. 33) 1 DCRC1 1. Capture a transient event with the oscilloscope set to about Once the R-C network components have been chosen, the L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1m, set the oscilloscope to 500µs/div. effective internal RISEN resistance must then be set. The RISEN resistance sets the gain of the load line regulation loop as well as 2. Record V1 and V2 as shown in Figure 23. the gain of the channel-current balance loop and the overcurrent 3. Select new values, R1(NEW), for the time constant resistor trip level. The effective internal RISEN resistance is set through a based on the original value, R1(OLD), using Equation 35. single resistor on the RSET pin, RSET. V R = R --------1-- (EQ. 35) 1NEW 1OLD V 2 4. Replace R1 with the new value and check to see that the error is corrected. Repeat the procedure if necessary. FN6520 Rev 3.00 Page 33 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C . Use Equation 39 to set RAPA to get the desired APA trip level. An APA trip level of 500mV is recommended for most applications. V2 RAPA = V---1--A-0---P0----A------T1---R0----–I--P-6---- = -1---0-5--0-0----0----m-1---0-V---–---6-- = 5k (EQ. 39) V1 Compensation VOUT The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load- ITRAN Line Regulation, there are two distinct methods for achieving these goals. I COMPENSATION WITH LOAD-LINE REGULATION The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the FIGURE 23. TIME CONSTANT MISMATCH BEHAVIOR output filter L-C resonant frequency split with the introduction Loadline Regulation Resistor of current information into the control loop. The final location of these poles is determined by the system function, the gain of If load line regulation is desired on the ISL6333 and the current signal, and the value of the compensation ISL6333A, the IDROOP pin should be connected to the FB pin in order for the internal average sense current to flow out components, RC and CC. See Figure 24. across the loadline regulation resistor, labeled RFB in Figure Since the system poles and zero are affected by the values of 7. The ISL6333B and ISL6333C always have the load line the components that are meant to compensate them, the regulation enabled. The RFB resistor value sets the desired solution to the system equation becomes fairly complicated. loadline required for the application. The desired loadline, Fortunately, there is a simple approximation that comes very RLL, can be calculated by Equation 36 where VDROOP is the close to an optimal solution. Treating the system as though it desired droop voltage at the full load current IFL. were a voltage-mode regulator, by compensating the L-C poles V R = -----D----R----O-----O----P--- (EQ. 36) and the ESR zero of the voltage mode approximation, yields a LL I FL solution that is always stable with very close to ideal transient Based on the desired loadline, the loadline regulation resistor, performance. RFB, can be calculated from Equation 37. C2 (OPTIONAL) R = -R----L---L--------N---------R----S----E----T------3------ (EQ. 37) FB DCR 400 RC CC COMP In Equation 37, RLL is the loadline resistance; N is the number of active channels; DCR is the DCR of the individual output inductors; and RSET is the RSET pin resistor. FB ISL6333 If no loadline regulation is required on the ISL6333 and IDROOP ISL6333A, the IDROOP pin should be left unconnected. To RFB choose the value for RFB in this situation, please refer to VDIFF “Compensation Without Load-line Regulation” on page35. IMON Pin Resistor FIGURE 24. COMPENSATION CONFIGURATION FOR A copy of the average sense current flows out of the IMON pin, LOAD-LINE REGULATED ISL6333 CIRCUIT and a resistor, RIMON, placed from this pin to ground can be used to set the overcurrent protection trip level. Based on the Select a target bandwidth for the compensated system, f0. The desired overcurrent trip threshold, IOCP, the IMON pin resistor, target bandwidth must be large enough to assure adequate RIMON, can be calculated from Equation38. transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation RSETN 3.381 RIMON = D-----C-----R---------I----------------4---0----0----- (EQ. 38) components depend on the relationships of f0 to the L-C pole OCP frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the APA Pin Component Selection compensation components. A 100µA current flows into the APA pin and across RAPA to set the APA trip level. A 1000pF capacitor, CAPA, should also be In Equation 40, L is the per-channel filter inductance divided by placed across the RAPA resistor to help with noise immunity. the number of active channels; C is the sum total of all output FN6520 Rev 3.00 Page 34 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C capacitors; ESR is the equivalent series resistance of the bulk C2 output filter capacitance; and VP-P is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page13. RC CC COMP Once selected, the compensation values in Equation 40 assure a stable converter with reasonable transient FB performance. In most cases, transient performance can be C1 improved by making adjustments to RC. Slowly increase the ISL6333 value of RC while observing the transient performance on an R1 RFB oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from VSEN Equation 40 unless some performance issue is noted. The optional capacitor C2, is sometimes needed to bypass FIGURE 25. COMPENSATION CIRCUIT WITHOUT LOAD-LINE noise away from the PWM comparator (see Figure 24). Keep a REGULATION position available for C2, and be prepared to install a The first step is to choose the desired bandwidth, f0, of the high-frequency capacitor of between 22pF and 150pF in case compensated system. Choose a frequency high enough to any leading edge jitter problem is noted. assure adequate transient performance but not higher than 1/3 1 of the switching frequency. The type-III compensator has an Case 1: 2--------------------L--------C---->f0 extra high-frequency pole, fHF. This pole can be used for 2f V  LC added noise rejection or to assure adequate attenuation at the 0 P-P RC = RFB-------------------------V--------------------------------- error-amplifier high-order pole and zero frequencies. A good IN general rule is to choose fHF=10f0, but it can be higher if V CC = 2----------------V-----------I--N-----R----------------f---- desired. Choosing fHF to be lower than 10f0 can cause P-P FB 0 problems with too much phase shift below the system bandwidth. Case 2: 2---------------1-----L--------C----f0<2----------------C--1-------E----S-----R--- R1 = RFB-----L-------C-C-----–---E--C--S-----R--E----S-----R--- 2 2 RC = RFBV-----P----P----------2----------V----I--N-------f-0----------L--------C---- (EQ. 40) C1 = -----L--------C----R-–---F--C--B-------E----S-----R--- CC = ---2--------------2--------f--0---2--------V-V---P-I--N---P--------R-----F---B------------L--------C---- C2 = ---2--------------2-------f--0--------f-H-----F------V-----I--N-L--------C-----------R-----F---B--------V-----P------P-- (EQ. 41) 2 Case 3: f0>2----------------C--1-------E----S-----R--- RC = -V----P----PV-----I--N----2------2------------f--0--f--H---f-F-H----F-------L-L-------C-C---–----1-R-----F----B--- 2f V L 0 P-P RC = RFB ----------V----I--N---------E----S-----R------------ C = ---------------V-----I-N-----------2----------------f--H----F------------L--------C----–----1------------------- C 22f f  LCR V V ESR C 0 HF FB P-P IN C = ------------------------------------------------------------------ C 2VP-PRFBf0 L In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in COMPENSATION WITHOUT LOAD-LINE REGULATION Equation 41, RFB is selected arbitrarily. The remaining compensation components are then selected. The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant In Equation 41, L is the per-channel filter inductance divided by frequency and a zero at the ESR frequency. A typeIII the number of active channels; C is the sum total of all output controller, as shown in Figure 25, provides the necessary capacitors; ESR is the equivalent-series resistance of the bulk compensation. output-filter capacitance; and VP-P is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page13. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating FN6520 Rev 3.00 Page 35 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C voltage at the phase nodes. The output filter also must provide inductors must be capable of assuming the entire load current the transient energy until the regulator can respond. Because it before the output voltage decreases more than VMAX. This has a low bandwidth compared to the switching frequency, the places an upper limit on inductance. output filter limits the system transient response. The output Equation 44 gives the upper limit on L for the cases when the capacitors must supply or sink load current while the current in trailing edge of the current transient causes a greater output- the output inductors increases or decreases to meet the voltage deviation than the leading edge. Equation 45 demand. addresses the leading edge. Normally, the trailing edge In high-speed converters, the output capacitor bank is usually dictates the selection of L because duty cycles are usually less the most costly (and often the largest) part of the circuit. Output than 50%. Nevertheless, both inequalities should be filter design begins with minimizing the cost of this part of the evaluated, and L should be selected based on the lower of the circuit. The critical load parameters in choosing the output two results. In each equation, L is the per-channel inductance, capacitors are the maximum size of the load step, I, the load- C is the total output capacitance, and N is the number of active current slew rate, di/dt, and the maximum allowable output- channels. voltage deviation under transient loading, VMAX. Capacitors 2NCVO (EQ. 44) are characterized according to their capacitance, ESR, and ESL L-----------------I----2------------ VMAX–IESR (equivalent series inductance). At the beginning of the load transient, the output capacitors L1----.--2---5--------N---------C--- V –IESR V –V  (EQ. 45) I2 MAX  IN O supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop Switching Frequency across the ESL. As the load current increases, the voltage There are a number of variables to consider when choosing drop across the ESR increases linearly until the load current the switching frequency, as there are considerable effects on reaches its final value. The capacitors selected must have the upper MOSFET loss calculation. These effects are outlined sufficiently low ESL and ESR so that the total output-voltage in the “MOSFETs General Design Guide” on page31 and they deviation is less than the allowable maximum. Neglecting the establish the upper limit for the switching frequency. The lower contribution of inductor current and regulator response, the limit is established by the requirement for fast transient output voltage initially deviates by an amount as shown in response and small output-voltage ripple. Choose the lowest Equation 42. switching frequency that allows the regulator to meet the VESL-d----i+ESRI (EQ. 42) transient-response requirements. dt Switching frequency is determined by the selection of the The filter capacitor must have sufficiently low ESL and ESR so frequency-setting resistor, RT. Figure 26 and Equation 46 are that V < VMAX. provided to assist in selecting the correct value for RT. Most capacitor solutions rely on a mixture of high frequency 500 capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high- frequency performance. Minimizing the ESL of the high- frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with k) 100 less output voltage deviation. R (T The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page17 and Equation 2), a voltage develops across the bulk capacitor ESR 10 equal to IC(P-P)(ESR). Thus, once the output capacitors are 50k 100k 1M 2M SWITCHING FREQUENCY (Hz) selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance. FIGURE 26. RT vs SWITCHING FREQUENCY V –NV V L ESR -------I--N------------------------O----U-----T---------------O----U----T--- (EQ. 43) R = 1010.61–1.035logfS (EQ. 46) f V V T S IN P-PMAX Input Capacitor Selection Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the The input capacitors are responsible for sourcing the AC capacitor voltage becomes slightly depleted. The output component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient FN6520 Rev 3.00 Page 36 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C enough to handle the AC component of the current drawn by 0.6 the upper MOSFETs which is related to duty cycle and the number of active phases. ) O /IS For a three-phase design, use Figure 27 to determine the M R input-capacitor RMS current requirement set by the duty cycle, T (I N 0.4 maximum sustained output current (IO), and the ratio of the RE peak-to-peak inductor current (IL,(P-P)) to IO. UR C 0.3 IL(P-P) = 0 IL(P-P) = 0.5 IO OR ) O IL(P-P) = 0.25 IO IL(P-P) = 0.75 IO CIT NT (IIRMS/0.2 UT-CAPA 0.2 IILL((PP--PP)) == 00.5 IO RE NP IL(P-P) = 0.75 IO R I U C 0 R 0 0.2 0.4 0.6 0.8 1.0 O T DUTY CYCLE (VIN/VO) CI FIGURE 29. NORMALIZED INPUT-CAPACITOR RMS A 0.1 P CURRENT FOR SINGLE-PHASE CONVERTER A C T- Low capacitance, high-frequency ceramic capacitors are U P needed in addition to the input bulk capacitors to suppress N I leading and falling edge voltage spikes. The spikes result from 0 the high current slew rate produced by the upper MOSFET turn 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) on and off. Select low ESL ceramic capacitors and place one as FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS close as possible to each upper MOSFET drain to minimize CURRENT FOR 3-PHASE CONVERTER board parasitics and maximize suppression. Select a bulk capacitor with a ripple current rating which will Layout Considerations minimize the total number of input capacitors required to support MOSFETs switch very fast and efficiently. The speed with the RMS current calculated. The voltage rating of the capacitors which the current transitions from one device to another should also be at least 1.25x greater than the maximum input causes voltage spikes across the interconnecting impedances 0.3 and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to ) O device overvoltage stress. Careful component selection, IS/ M layout, and placement minimizes these voltage spikes. R T (I Consider, as an example, the turnoff transition of the upper N 0.2 E PWM MOSFET. Prior to turnoff, the upper MOSFET was R R carrying channel current. During the turnoff, current stops U R C flowing in the upper MOSFET and is picked up by the lower TO MOSFET. Any inductance in the switched current path ACI 0.1 generates a large voltage spike during the switching interval. P CA IL(P-P) = 0 Careful component selection, tight layout of the critical UT- IL(P-P) = 0.5 IO components, and short, wide circuit traces minimize the NP IL(P-P) = 0.75 IO magnitude of voltage spikes. I 0 There are two sets of critical components in a DC/DC converter 0 0.2 0.4 0.6 0.8 1.0 using the ISL6333 family of controllers. The power DUTY CYCLE (VIN/VO) components are the most critical because they switch large FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current voltage. Figures 28 and 29 provide the same input RMS current and signal coupling. information for two-phase and single-phase designs respectively. Use the same approach for selecting the bulk capacitor type and number. FN6520 Rev 3.00 Page 37 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C RFB R2 C2 KEY CDVC RDVC +5V VCC HEAVY TRACE ON CIRCUIT PLANE LAYER ISLAND ON POWER PLANE LAYER DVC VDIFF VSEN RGND RSET ISLAND ON CIRCUIT PLANE LAYER IDROOP RSET VIA CONNECTION TO GROUND PLANE FB C1 BYP1 (CF1) LOCATE CLOSE TO IC C3 +12V (MINIMIZE CONNECTION PATH) R1 PVCC1 (CF2) COMP CBIN1 RAPA CBOOT1 LOCATE NEAR SWITCHING TRANSISTORS; BOOT1 (MINIMIZE CONNECTION PATH) APA UGATE1 +5V RUGATE PHASE1 VCC (CF1) R1 C1 ROFS LGATE1 OFS ISEN1- ISEN1+ FS +12V RT REF PVCC2_3 CREF ISL6333 (CF3) CBIN2 CBOOT2 BOOT2 SS UGATE2 RSS RUGATE PHASE2 VID7 R1 C1 (CHFOUT) CBOUT VID6 LGATE2 VID5 VID4 ISEN2- LOAD VID3 ISEN2+ VID2 +12V VID1 VID0 PUVCC (CF4) CBIN3 PSI# CBOOT3 (MLIONCIMAITZEE NCEOANRN ELCOTAIDO;N VR_RDY BOOT3 PATH) UGATE3 EN RUGATE PHASE3 IMON R1 C1 RIMON LGATE3 GND ISEN3- ISEN3+ FIGURE 30. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN6520 Rev 3.00 Page 38 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C The power components should be placed first, which includes Routing UGATE, LGATE, and PHASE Traces the MOSFETs, input and output capacitors, and the inductors. It Great attention should be paid to routing the UGATE, LGATE, is important to have a symmetrical layout for each power train, and PHASE traces since they drive the power train MOSFETs preferably with the controller located equidistant from each. using short, high current pulses. It is important to size them as Symmetrical layout allows heat to be dissipated equally across large and as short as possible to reduce their overall all power trains. Equidistant placement of the controller to the impedance and inductance. They should be sized to carry at power trains it controls through the integrated drivers helps least one ampere of current (0.02” to 0.05”). Going between keep the gate drive traces equally short, resulting in equal trace layers with vias should also be avoided, but if so, use two vias impedances and similar drive capability of all sets of MOSFETs. for interconnection when possible. When placing the MOSFETs, try to keep the source of the Extra care should be given to the LGATE traces in particular upper FETs and the drain of the lower FETs as close as since keeping their impedance and inductance low helps to thermally possible. Input bulk capacitors should be placed significantly reduce the possibility of shoot-through. It is also close to the drain of the upper FETs and the source of the lower important to route each channels UGATE and PHASE traces FETs. Locate the output inductors and output capacitors in as close proximity as possible to reduce their inductances. between the MOSFETs and the load. The high-frequency input Current Sense Component Placement and Trace and output decoupling capacitors (ceramic) should be placed Routing as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as One of the most critical aspects of the controller regulator vias to GND next or on the capacitor solder pad. layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components The critical small components include the bypass capacitors must be placed as close to their respective ISEN+ and for VCC and PVCC, and many of the components ISEN- pins on the controller as possible. surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC The sense traces that connect the R-C sense components to bypass capacitors as close to the controller as possible. It is each side of the output inductors should be routed on the especially important to locate the components associated bottom of the board, away from the noisy switching with the feedback circuit close to their respective controller components located on the top of the board. These traces pins, since they belong to a high-impedance circuit loop, should be routed side by side, and they should be very thin sensitive to EMI pick-up. traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces A multi-layer printed circuit board is recommended. Figure 30 should pick up as little noise as possible. shows the connections of the critical components for the converter. Note that capacitors Cxx(IN) and Cxx(OUT) could Thermal Management each represent numerous physical capacitors. Dedicate one For maximum thermal performance in high current, high solid layer, usually the one underneath the component side of switching frequency applications, connecting the thermal the board, for a ground plane and make all critical component GND pad of the controllers to the ground plane with multiple ground connections with vias to this layer. vias is recommended. This heat spreading allows the part to Dedicate another solid layer as a power plane and break this achieve its full thermal potential. It is also recommended plane into smaller islands of common voltage levels. Keep the that the controllers be placed in a direct path of airflow if metal runs from the PHASE terminal to output inductors short. possible to help thermally manage the part. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. © Copyright Intersil Americas LLC 2008-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6520 Rev 3.00 Page 39 of 40 Oct 8, 2010

ISL6333, ISL6333A, ISL6333B, ISL6333C Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 4/10 4X 5.5 7.00 A B 44X 0.50 6 37 48 PIN #1 INDEX AREA 6 PIN 1 36 1 INDEX AREA 0 0 4. 30 ± 0 . 15 7. 25 12 (4X) 0.15 24 13 0.10M C A B TOP VIEW 48X 0 . 40± 0 . 1 4 0.23 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" 0.10C C 0 . 90 ± 0 . 1 BASE PLANE ( 6 . 80 TYP ) SEATING PLANE 0.08 C ( 4 . 30 ) SIDE VIEW ( 44X 0 . 5 ) C 0 . 2 REF 5 ( 48X 0 . 23 ) ( 48X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. FN6520 Rev 3.00 Page 40 of 40 Oct 8, 2010