DATASHEET ISL6323 Hybrid SVI/PVI FN9278 Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Rev 5.00 Uniplane Processors May 17, 2011 The ISL6323 dual PWM controller delivers high efficiency Features and tight regulation from two synchronous buck DC/DC • Processor Core Voltage Via Integrated MultiPhase converters. The ISL6323 supports hybrid power control of Power Conversion AMD processors which operate from either a 6-bit parallel VID interface (PVI) or a serial VID interface (SVI). The dual • Configuration Flexibility output ISL6323 features a multiphase controller to support - 2-Phase Operation with Internal Drivers uniplane VDD core voltage and a single phase controller to - 3- or 4-Phase Operation with External PWM Drivers power the Northbridge (VDDNB) in SVI mode. Only the • Serial VID Interface Inputs multiphase controller is active in PVI mode to support - Two Wire, Clock and Data, Bus uniplane VDD only processors. - Conforms to AMD SVI Specifications A precision uniplane core voltage regulation system is • Parallel VID Interface Inputs provided by a 2- to 4-phase PWM voltage regulator (VR) - 6-bit VID input controller. The integration of two power MOSFET drivers, - 0.775V to 1.55V in 25mV Steps adding flexibility in layout, reduce the number of external - 0.375V to 0.7625V in 12.5mV Steps components in the multiphase section. A single phase PWM controller with integrated driver provides a second precision • Precision Core Voltage Regulation voltage regulation system for the North Bridge portion of the - Differential Remote Voltage Sensing processor. This monolithic, dual controller with integrated - ±0.5% System Accuracy Over-Temperature driver solution provides a cost and space saving power - Adjustable Reference-Voltage Offset management solution. • Optimal Processor Core Voltage Transient Response For applications which benefit from load line programming to - Adaptive Phase Alignment (APA) reduce bulk output capacitors, the ISL6323 features output - Active Pulse Positioning Modulation voltage droop. The multiphase portion also includes advanced • Fully Differential, Continuous DCR Current Sensing control loop features for optimal transient response to load - Accurate Load Line Programming application and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for - Precision Channel Current Balancing load line programming and channel current balance. Dual • Variable Gate Drive Bias: 5V to 12V edge modulation is another unique feature, allowing for • Overcurrent Protection quicker initial response to high di/dt load transients. • Multi-tiered Overvoltage Protection Ordering Information • Selectable Switching Frequency up to 1MHz PART NUMBER PART TEMP. PACKAGE PKG. • Simultaneous Digital Soft-Start of Both Outputs (Note) MARKING (°C) (Pb-free) DWG. # • Processor NorthBridge Voltage Via Single Phase ISL6323CRZ* ISL6323 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 Power Conversion ISL6323IRZ* ISL6323 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 • Precision Voltage Regulation *Add “-T” suffix for tape and reel. Please refer to TB347 for details on - Differential Remote Voltage Sensing reel specifications. - ±0.5% System Accuracy Over-Temperature NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach • Serial VID Interface Inputs materials, and 100% matte tin plate plus anneal (e3 termination - Two Wire, Clock and Data, Bus finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL - Conforms to AMD SVI Specifications classified at Pb-free peak reflow temperatures that meet or exceed • Overcurrent Protection the Pb-free requirements of IPC/JEDEC J STD-020. • Continuous DCR Current Sensing • Variable Gate Drive Bias: 5V to 12V • Simultaneous Digital Soft-Start of Both Outputs • Selectable Switching Frequency up to 1MHz • Pb-Free (RoHS Compliant) FN9278 Rev 5.00 Page 1 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Pinout ISL6323 (48 LD QFN) TOP VIEW D MP_NB N_NB- N4+ N4- N3+ N3- CC_NB ATE_NB OT_NB ATE_NB ASE_NB DPWRG CO ISE ISE ISE ISE ISE PV LG BO UG PH VD 48 47 46 45 44 43 42 41 40 39 38 37 FB_NB 1 36 PWM4 ISEN_NB+ 2 35 PWM3 RGND_NB 3 34 PWROK VID0/VFIXEN 4 33 PHASE1 VID1/SEL 5 32 UGATE1 VID2/SVD 6 31 BOOT1 49 GND VID3/SVC 7 30 LGATE1 VID4 8 29 PVCC1_2 VID5 9 28 LGATE2 VCC 10 27 BOOT2 FS 11 26 UGATE2 RGND 12 25 PHASE2 13 14 15 16 17 18 19 20 21 22 23 24 VSEN OFS DVC RSET FB COMP APA ISEN1+ ISEN1- ISEN2+ ISEN2- EN FN9278 Rev 5.00 Page 2 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Functional Pin Description PIN NUMBER SYMBOL DESCRIPTION 1, 48 FB_NB and These pins are the internal error amplifier inverting input and output respectively of the COMP_NB NB VR controller. FB_NB, VDIFF_NB, and COMP_NB are tied together through external R-C networks to compensate the regulator. 2, 47 ISEN_NB+, These pins are used for differentially sensing the North Bridge output current. The ISEN_NB1- sensed current is used for protection and load line regulation if droop is enabled. Connect ISEN_NB- to the node between the RC sense element surrounding the inductor. Tie the ISEN_NB+ pin to the VNB side of the sense capacitor. 3 RGND_NB This pin is an input to the NB VR controller precision differential remote-sense amplifier and should be connected to the sense pin of the North Bridge, VDDNBFBL. 4 VID0/VFIXEN If VID1 is LO prior to enable [SVI Mode], the pin functions as the VFIXEN selection input from the AMD processor for determining SVI mode versus VFIX mode of operation. If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has an internal 30µA pull-down current applied to it at all times. 5 VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6323. If the pin is LO prior to enable, the ISL6323 is in SVI mode and the dual purpose pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode related functions. If the pin held HI prior to enable, the ISL6323 is in PVI mode and dual purpose pins use their VIDx related functions to decode the correct DAC code. 6 VID2/SVD If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional signal to and from the master device on AMD processor. If VID1 is HI prior to enable [PVI Mode], this pin is used to decode the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down current in SVI mode. 7 VID3/SVC If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the AMD processor. If VID1 is HI prior to enable [PVI Mode], the ISL6323 is in PVI mode and this pin is used to decode the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down current in SVI mode. 8, 9 VID4, VID5 These pins are active only when the ISL6323 is in PVI mode. When VID1 is HI prior to enable, the ISL6323 decodes the programmed DAC voltage required by the AMD processor. These pins have an internal 30µA pull-down current applied to them at all times. 10 VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor. 11 FS A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of both controllers. Refer to Equation 1 for proper resistor calculation. 10.61–1.035logf  R = 10 s (EQ. 1) T With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from FS to VCC, Droop is disabled. 12, 13 RGND, VSEN VSEN and RGND are inputs to the core voltage regulator (VR) controller precision differential remote-sense amplifier and should be connected to the sense pins of the remote processor core(s), VDDFB[H,L]. 14 OFS The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VSEN The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unconnected. 15 DVC The DVC pin is a buffered version of the reference to the error amplifier. A series resistor and capacitor between the DVC pin and FB pin smooth the voltage transition during VID-on-the-fly operations. FN9278 Rev 5.00 Page 3 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Functional Pin Description (Continued) PIN NUMBER SYMBOL DESCRIPTION 16 RSET Connect this pin to the VCC pin through a resistor (RSET) to set the effective value of the internal RISEN current sense resistors. The values of the RSET resistor should be no less than 20k and no more than 80k. A 0.1µF capacitor should be placed in parallel to the RSET resistor. 17, 18 FB, COMP These pins are the internal error amplifier inverting input and output respectively of the core VR controller. FB, VSEN and COMP are tied together through external R-C networks to compensate the regulator. 19 APA Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A 100µA current flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set. 20, 21, 22, 23, ISEN1+, ISEN1-, These pins are used for differentially sensing the corresponding channel output currents. 43, 44, 45, 46 ISEN2+, ISEN2-, The sensed currents are used for channel balancing, protection, and core load line ISEN3-, ISEN3+, regulation. ISEN4-, ISEN4+ Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the VCORE side of their corresponding channel’s sense capacitor. 24 EN This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for operation. When the EN pin is pulled high, the ISL6323 will be placed in either SVI or PVI mode. The mode is determined by the latched value of VID1 on the rising edge of the EN signal. A third function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the center tap connected to this pin from the drive bias supply prevents enabling the controller before insufficient bias is provided to external driver. The resistors should be selected such that when the POR-trip point of the external driver is reached, the voltage at this pin meets the above mentioned threshold level. 25, 33 PHASE2 and PHASE1 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives. 26, 32 UGATE2 and UGATE1 Connect these pins to the corresponding upper MOSFET gates. These pins are used to control the upper MOSFETs and are monitored for shoot-through prevention purposes. Maximum individual channel duty cycle is limited to 93.3%. 27, 31 BOOT2 and BOOT1 These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC1_2 pin provide the necessary bootstrap charge. 28, 30 LGATE2 and LGATE1 These pins are used to control the lower MOSFETs. Connect these pins to the corresponding lower MOSFETs’ gates. 29 PVCC1_2 The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor. 34 PWROK System wide Power-Good signal. If this pin is low, the two SVI bits are decoded to determine the “metal VID”. When the pin is high, the SVI is actively running its protocol. 35, 36 PWM3 and PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver IC if 3- or 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable them and configure the core VR controller for 2-phase or 3-phase operation. 37 VDDPWRGD During normal operation this pin indicates whether both output voltages are within specified overvoltage and undervoltage limits. If either output voltage exceeds these limits or a reset event occurs (such as an overcurrent event), the pin is pulled low. This pin is always low prior to the end of soft-start. 38 PHASE_NB Connect this pin to the source of the corresponding upper MOSFET. This pin is the return path for the upper MOSFET drive. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. FN9278 Rev 5.00 Page 4 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Functional Pin Description (Continued) PIN NUMBER SYMBOL DESCRIPTION 39 UGATE_NB Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM- controlled gate drive for the upper MOSFET and is monitored for shoot-through prevention purposes. 40 BOOT_NB This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to appropriately chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC_NB pin provides the necessary bootstrap charge. 41 LGATE_NB Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM- controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. 42 PVCC_NB The power supply pin for the internal MOSFET driver for the Northbridge controller. Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor. 49 GND GND is the bias and reference ground for the IC. The GND connection for the ISL6323 is through the thermal pad on the bottom of the package. Integrated Driver Block Diagram PVCC BOOT UGATE PWM 20k SOFT-START GATE SHOOT- AND CONTROL THROUGH PHASE PROTECTION FAULT LOGIC LOGIC 10k LGATE FN9278 Rev 5.00 Page 5 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Controller Block Diagram RGND_NB FB_NB COMP_NB NB_REF  BOOT_NB E/A NB_CS UGATE_NB MOSFET ISEN_NB+ UV OV DRIVER CURRENT LOGIC LOGIC PHASE_NB SENSE RAMP ISEN_NB- LGATE_NB VDDPWRGD EN_12V PVCC_NB APA APA NB FAULT ENABLE EN LOGIC LOGIC COMP VCC POWER-ON OFS OFFSET RESET PVCC1_2 SOFT-START FB AND E/A FAULT LOGIC DVC 2X BOOT1  RGND DROOP CONTROL UGATE1 MOSFET LOAD APPLY DRIVER PWROK TRANSIENT PHASE1 ENHANCEMENT VID0/VFIXEN SVI LGATE1 VID1/SEL SLAVE VID2/SVD BUS CLOCK AND AND TRIANGLE WAVE FS VID3/SVC PVI GENERATOR DAC VID4 VID5 PWM1  NB_REF BOOT2 OV PWM2 LOGIC  MOSFET UGATE2 VSEN DRIVER PHASE2 UV LOGIC PWM3 LGATE2  NB_CS RESISTOR OC RSET MATCHING PH3/PH4 PWM4 POR  ISEN1+ CH1 I_TRIP I_AVG EN_12V CURRENT SENSE ISEN1- CHANNEL ISEN3- DETECT ISEN4- ISEN2+ CH2 CURRENT ISEN2- SENSE CHANNEL I_AVG 1 CURRENT N BALANCE ISEN3+ CH3 SPIGWNMA3L PWM3 CURRENT LOGIC SENSE ISEN3- ISEN3-  ISEN4+ CH4 CURRENT PWM4 SENSE SIGNAL PWM4 ISEN4- LOGIC ISEN4- GND FN9278 Rev 5.00 Page 6 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Typical Application - SVI Mode +12V +12V FB VSEN COMP ISEN3+ BOOT1 BOOT1 ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 LGATE1 LGATE1 PWM1 APA PGND ISEN1- DVC ISEN1+ +5V ISL6614 +12V +12V VDD PVCC1_2 +12V VCC VCC BOOT2 PVCC BOOT2 OFS UGATE2 UGATE2 GND FS PHASE2 PHASE2 CPU LOAD PWM2 LGATE2 LGATE2 RSET VFIXEN ISEN2- SEL SVD ISEN2+ SVC RGND NC VID4 NC VID5 PWROK VDDPWRGD ISEN4+ GND ISEN4- PWM4 +12V ISL6323 +12V PVCC_NB EN OFF ON BOOT_NB UGATE_NB PHASE_NB VDDNB LGATE_NB NB LOAD COMP_NB ISEN_NB- ISEN_NB+ FB_NB RGND_NB FN9278 Rev 5.00 Page 7 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Typical Application - PVI Mode +12V +12V FB VSEN COMP ISEN3+ BOOT1 BOOT1 ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 LGATE1 APA LGATE1 PGND PWM1 ISEN1- DVC ISEN1+ +5V ISL6614 +12V +12V VDD PVCC1_2 +12V VCC VCC BOOT2 PVCC BOOT2 OFS UGATE2 UGATE2 GND PHASE2 FS PHASE2 CPU LOAD PWM2 LGATE2 LGATE2 RSET VID0 ISEN2- VID1/SEL VID2 ISEN2+ VID3 RGND VID4 VID5 NC PWROK VDDPWRGD ISEN4+ GND ISEN4- PWM4 ISL6323 +12V +12V PVCC_NB NORTH BRIDGE REGULATOR EN DISABLED IN PVI MODE OFF ON BOOT_NB UGATE_NB PHASE_NB VDDNB LGATE_NB NB LOAD COMP_NB ISEN_NB- ISEN_NB+ FB_NB RGND_NB FN9278 Rev 5.00 Page 8 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Thermal Resistance JA (°C/W) JC (°C/W) Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V QFN Package (Notes 1, 2). . . . . . . . . . 27 2 Absolute Boot Voltage (VBOOT). . . . . . . .GND - 0.3V to GND + 36V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C Phase Voltage (VPHASE). . . . . . .GND - 0.3V to 24V (PVCC = 12V) Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C GND - 8V (<400ns, 20µJ) to 31V (<200ns, VBOOT-PHASE = 5V) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below Upper Gate Voltage (VUGATE). . . .VPHASE - 0.3V to VBOOT + 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V Lower Gate Voltage (VLGATE). . . . . . . GND - 0.3V to PVCC + 0.3V Recommended Operating Conditions GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5% Ambient Temperature ISL6323CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6323IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. MIN MAX PARAMETER TEST CONDITIONS (Note 3) TYP (Note 3) UNITS BIAS SUPPLIES Input Bias Supply Current IVCC; EN = high 15 22 30 mA Gate Drive Bias Current - PVCC1_2 Pin IPVCC1_2; EN = high 1 1.8 3 mA Gate Drive Bias Current - PVCC_NB Pin IPVCC_NB; EN = high 0.3 0.9 2 mA VCC POR (Power-On Reset) Threshold VCC Rising 4.20 4.40 4.55 V VCC Falling 3.70 3.90 4.10 V PVCC POR (Power-On Reset) Threshold PVCC Rising 4.20 4.40 4.55 V PVCC Falling 3.70 3.90 4.10 V PWM MODULATOR Oscillator Frequency Accuracy, fSW RT = 100k (±0.1%) to Ground, TA = +25°C 225 250 275 kHz (Droop Enabled) RT = 100k (±0.1%) to VCC, TA = +25°C 240 270 300 kHz (Droop Disabled) Typical Adjustment Range of Switching Frequency (Note 4) 0.08 1.0 MHz Oscillator Ramp Amplitude, VP-P (Note 4) 1.50 V CONTROL THRESHOLDS EN Rising Threshold 0.80 0.88 0.92 V EN Hysteresis 70 130 190 mV PWROK Input HIGH Threshold 1.1 V PWROK Input LOW Threshold 0.95 V VDDPWRGD Sink Current Open drain, V_VDDPWRGD = 400mV 4 mA PWM Channel Disable Threshold VISEN3-, VISEN4- 4.4 V PIN_ADJUSTABLE OFFSET OFS Source Current Accuracy (Positive Offset) ROFS = 10k(±0.1%)from OFS to GND 27.5 31 34.5 µA OFS Sink Current Accuracy (Negative Offset) ROFS = 30k(±0.1%)from OFS to VCC 50.5 53.5 56.5 µA FN9278 Rev 5.00 Page 9 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued) MIN MAX PARAMETER TEST CONDITIONS (Note 3) TYP (Note 3) UNITS REFERENCE AND DAC System Accuracy (VDAC > 1.000V) -0.6 0.6 % System Accuracy (0.600V < VDAC < 1.000V) -1.0 1.0 % System Accuracy (VDAC < 0.600V) -2.0 2.0 % DVC Voltage Gain VDAC = 1V 2.0 V APA Current Tolerance VAPA = 1V 90 100 108 µA ERROR AMPLIFIER DC Gain RL = 10k to ground, (Note 4) 96 dB Gain-Bandwidth Product (Note 4) CL = 100pF, RL = 10k to ground, (Note 4) 20 MHz Slew Rate (Note 4) CL = 100pF, Load = ±400µA, (Note 4) 8 V/µs Maximum Output Voltage Load = 1mA 3.80 4.20 V Minimum Output Voltage Load = -1mA 1.3 1.6 V SOFT-START RAMP Soft-Start Ramp Rate 2.2 3.0 4.0 mV/µs PWM OUTPUTS PWM Output Voltage LOW Threshold ILOAD = ±500µA 0.5 V PWM Output Voltage HIGH Threshold ILOAD = ±500A 4.5 V CURRENT SENSING - CORE CONTROLLER Current Sense Resistance, RISEN (Internal) TA = +25°C 2400  (Note4) Average Sensed and Droop Current Tolerance ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 77µA 68 77 87 µA CURRENT SENSING - NB CONTROLLER Current Sense Resistance, RISEN_NB (Internal) TA = +25°C 2400  (Note 4) Sensed Current Tolerance ISEN_NB = 80µA 80 µA OVERCURRENT PROTECTION Overcurrent Trip Level - Average Channel Normal Operation 83 100 111 µA Dynamic VID Change (Note 4) 130 µA Overcurrent Trip Level - Individual Channel Normal Operation 142 µA Dynamic VID Change (Note 4) 190 µA POWER GOOD Overvoltage Threshold VSEN Rising (Core and North Bridge) VDAC VDAC + VDAC + V +225mV 250mV 275mV Undervoltage Threshold VSEN Falling (Core) VDAC - VDAC - VDAC - mV 325mV 300mV 275mV VSEN Falling (North Bridge) VDAC - VDAC - VDAC - mV 310mV 275mV 245mV Power Good Hysteresis 50 mV OVERVOLTAGE PROTECTION OVP Trip Level 1.73 1.80 1.84 V OVP Lower Gate Release Threshold 350 400 mV FN9278 Rev 5.00 Page 10 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued) MIN MAX PARAMETER TEST CONDITIONS (Note 3) TYP (Note 3) UNITS SWITCHING TIME (Note 4) [See “Timing Diagram” on page11] UGATE Rise Time tRUGATE; VPVCC = 12V, 3nF Load, 10% to 90% 26 ns LGATE Rise Time tRLGATE; VPVCC = 12V, 3nF Load, 10% to 90% 18 ns UGATE Fall Time tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10% 18 ns LGATE Fall Time tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10% 12 ns UGATE Turn-On Non-overlap tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive 10 ns LGATE Turn-On Non-overlap tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive 10 ns GATE DRIVE RESISTANCE (Note 4) Upper Drive Source Resistance VPVCC = 12V, 15mA Source Current 2.0  Upper Drive Sink Resistance VPVCC = 12V, 15mA Sink Current 1.65  Lower Drive Source Resistance VPVCC = 12V, 15mA Source Current 1.25  Lower Drive Sink Resistance VPVCC = 12V, 15mA Sink Current 0.80  MODE SELECTION VID1/SEL Input Low EN taken from HI to LO, VDDIO = 1.5V 0.45 V VID1/SEL Input High EN taken from LO to HI, VDDIO = 1.5V 1.00 V PVI INTERFACE VIDx Pull-down VDDIO = 1.5V 30 45 µA VIDx Input Low VDDIO = 1.5V 0.45 V VIDx Input High VDDIO = 1.5V 1.00 V SVI INTERFACE SVC, SVD Input LOW (VIL) 0.4 V SVC, SVD Input HIGH (VIH) 1.10 V Schmitt Trigger Input Hysteresis 0.14 0.35 0.55 V SVD Low Level Output Voltage 3mA Sink Current 0.285 V Maximum SVC, SVD Leakage (Note 4) ±5 µA NOTES: 3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 4. Limits should be considered typical and are not production tested. Timing Diagram tPDHUGATE tRUGATE tFUGATE UGATE LGATE tFLGATE tRLGATE tPDHLGATE FN9278 Rev 5.00 Page 11 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Operation proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series The ISL6323 utilizes a multiphase architecture to provide a low resistance (ESR), and inductor ripple current. Reducing the cost, space saving power conversion solution for the processor inductor ripple current allows the designer to use fewer or less core voltage. The controller also implements a simple single costly output capacitors. phase architecture to provide the Northbridge voltage on the V –NV V same chip. I = -------I--N--------------------O-----U----T-----------O----U-----T-- (EQ. 3) CP-P Lf V S IN Multiphase Power Conversion Another benefit of interleaving is to reduce input ripple current. Microprocessor load current profiles have changed to the point Input capacitance is determined in part by the maximum input that the advantages of multiphase power conversion are ripple current. Multiphase topologies can improve overall impossible to ignore. The technical challenges associated with system cost and size by lowering input ripple current and producing a single-phase converter that is both cost-effective allowing the designer to reduce the cost of input capacitance. and thermally viable have forced a change to the cost-saving The example in Figure 2 illustrates input currents from a 3- approach of multiphase. The ISL6323 controller helps simplify phase converter combining to reduce the total input ripple implementation by integrating vital functions and requiring current. minimal external components. The “Controller Block Diagram” The converter depicted in Figure 2 delivers 1.5V to a 36A load on page6 provides a top level view of the multiphase power from a 12V input. The RMS input capacitor current is 5.9A. conversion using the ISL6323 controller. Compare this to a single-phase converter also stepping down Interleaving 12V to 1.5V at 36A. The single-phase converter has 11.9ARMS The switching of each channel in a multiphase converter is timed input capacitor current. The single-phase converter must use an to be symmetrically out-of-phase with each of the other channels. input capacitor bank with twice the RMS current capacity as the equivalent 3-phase converter. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a Figures 25, 26 and 27 in the section entitled “Input Capacitor result, the 3-phase converter has a combined ripple frequency 3x Selection” on page32 can be used to determine the input greater than the ripple frequency of any one phase. In addition, capacitor RMS current based on load current, duty cycle, and the peak-to-peak amplitude of the combined inductor currents is the number of channels. They are provided as aids in reduced in proportion to the number of phases (Equations 2 and determining the optimal input capacitor solution. 3). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. IL1 + IL2 + IL3, 7A/DIV Figure 1 illustrates the multiplicative effect on output ripple frequency. The 3-channel currents (IL1, IL2, and IL3) combine IL3, 7A/DIV to form the AC ripple current and the DC load current. The PWM3, 5V/DIV ripple component has 3x the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 IL2, 7A/DIV of a cycle after the PWM pulse of the previous phase. The peak- PWM2, 5V/DIV to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load. IL1, 7A/DIV To understand the reduction of ripple current amplitude in the PWM1, 5V/DIV multiphase circuit, examine the equation representing an 1µs/DIV individual channel peak-to-peak inductor current. FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS V –V V IP–P= -------I--N--------------O-----U----T-----------O----U-----T-- (EQ. 2) FOR 3-PHASE CONVERTER Lf V S IN In Equation 2, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency. The output capacitors conduct the ripple component of the inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 2 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 3. Peak-to-peak ripple current decreases by an amount FN9278 Rev 5.00 Page 12 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI To further improve the transient response, ISL6323 also INPUT-CAPACITOR CURRENT, 10A/DIV implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all phases together under transient events with large step current. With both APP and APA control, ISL6323 can achieve excellent transient performance and reduce CHANNEL 3 the demand on the output capacitors. INPUT CURRENT 10A/DIV Adaptive Phase Alignment (APA) To further improve the transient response, the ISL6323 also CHANNEL 2 implements Intersil’s proprietary Adaptive Phase Alignment INPUT CURRENT 10A/DIV (APA) technique, which turns on all of the channels together at the same time during large current step transient events. As CHANNEL 1 Figure 3 shows, the APA circuitry works by monitoring the INPUT CURRENT voltage on the APA pin and comparing it to a filtered copy of 10A/DIV the voltage on the COMP pin. The voltage on the APA pin is a 1s/DIV copy of the COMP pin voltage that has been negatively offset. FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT CAPACITOR RMS CURRENT FOR 3-PHASE If the APA pin exceeds the filtered COMP pin voltage an APA CONVERTER event occurs and all of the channels are forced on. Active Pulse Positioning Modulated PWM Operation The ISL6323 uses a proprietary Active Pulse Positioning (APP) EXTERNAL CIRCUIT ISL6323 INTERNAL CIRCUIT modulation scheme to control the internal PWM signals that command each channel’s driver to turn their upper and lower APA MOSFETs on and off. The time interval in which a PWM signal - + can occur is generated by an internal clock, whose cycle time is CAPA RAPA VAPA,TRIP 100µA APA the inverse of the switching frequency set by the resistor between - + TO APA the FS pin and ground. The advantage of Intersil’s proprietary LOW PASS CIRCUITRY Active Pulse Positioning (APP) modulator is that the PWM signal COMP FILTER has the ability to turn on at any point during this PWM time ERROR interval, and turn off immediately after the PWM signal has AMPLIFIER transitioned high. This is important because it allows the controller - + to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION other modulation schemes. The APA trip level is the amount of DC offset between the The PWM output state is driven by the position of the error COMP pin and the APA pin. This is the voltage excursion that amplifier output signal, VCOMP, minus the current correction the APA and COMP pins must have during a transient event to signal relative to the proprietary modulator ramp waveform as activate the Adaptive Phase Alignment circuitry. This APA trip illustrated in Figure 3. At the beginning of each PWM time level is set through a resistor, RAPA, that connects from the interval, this modified VCOMP signal is compared to the internal APA pin to the COMP pin. A 100µA current flows across RAPA modulator waveform. As long as the modified VCOMP voltage is into the APA pin to set the APA trip level as described in lower then the modulator waveform voltage, the PWM signal is Equation 4. An APA trip level of 500mV is recommended for commanded low. The internal MOSFET driver detects the low most applications. A 0.1µF capacitor, CAPA, should also be state of the PWM signal and turns off the upper MOSFET and placed across the RAPA resistor to help with noise immunity. turns on the lower synchronous MOSFET. When the modified VCOMP voltage crosses the modulator ramp, the PWM output VAPATRIP = RAPA10010–6 (EQ. 4) transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high PWM Operation until the modified VCOMP voltage crosses the modulator ramp The timing of each core channel is set by the number of active again. When this occurs the PWM signal will transition low channels. Channel detection on the ISEN3- and ISEN4- pins again. selects 2-channel to 4-channel operation for the ISL6323. The switching cycle is defined as the time between PWM pulse During each PWM time interval the PWM signal can only termination signals of each channel. The cycle time of the transition high once. Once PWM transitions high it can not pulse signal is the inverse of the switching frequency set by the transition high again until the beginning of the next PWM time resistor between the FS pin and ground. The PWM signals interval. This prevents the occurrence of double PWM pulses occurring during a single period. FN9278 Rev 5.00 Page 13 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI command the MOSFET driver to turn on/off the channel across the sense capacitor, VC, can be shown to be MOSFETs. proportional to the channel current ILn, shown in Equation 6. For 4-channel operation, the channel firing order is 4-3-2-1: --s--------L---+1 (EQ. 6) PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2 V s = -----------------D-----C----R------------------------------KDCRI C L output follows another 1/4 of a cycle after PWM3, and PWM1  R1R2  n s------------------------C+1 delays another 1/4 of a cycle after PWM2. For 3-channel  R1+R2  operation, the channel firing order is 3-2-1. Where: Connecting ISEN4- to VCC selects 3-channel operation and the R pulse times are spaced in 1/3 cycle increments. If ISEN3- is K = ------------2--------- (EQ. 7) R +R connected to VCC, 2-channel operation is selected and the 2 1 PWM2 pulse happens 1/2 of a cycle after PWM1 pulse. Continuous Current Sampling VIN ILn UGATE(n) In order to realize proper current-balance, the currents in each L channel are sampled continuously every switching cycle. MOSFET DCR VOUT During this time, the current-sense amplifier uses the ISEN DRIVER LGATE(n) INDUCTOR COUT inputs to reproduce a signal proportional to the inductor +VL(s) - current, IL. This sensed current, ISEN, is simply a scaled +VC(s) - version of the inductor current. R1 C R2 ISL6323 INTERNAL CIRCUIT In PWM SWITCHING PERIOD SAMPLE IL + ISENn- +VC(s)- - RISEN ISENn+ VCC ISEN ISEN TO ACTIVE { RSET CORE CHANNELS TO NORTH BRIDGE RSET TIME CSET FIGURE 4. CONTINUOUS CURRENT SAMPLING FIGURE 5. INDUCTOR DCR CURRENT SENSING The ISL6323 supports Inductor DCR current sensing to CONFIGURATION If the R-C network components are selected such that the RC continuously sample each channel’s current for channel-current time constant matches the inductor L/DCR time constant (see balance. The internal circuitry, shown in Figure 5 represents Channel N of an N-Channel converter. This circuitry is repeated Equation 8), then VC is equal to the voltage drop across the DCR multiplied by the ratio of the resistor divider, K. If a for each channel in the converter, but may not be active resistor divider is not being used, the value for K is 1. depending on how many channels are operating. Inductor windings have a characteristic distributed resistance ------L------- = -R-----1-------R-----2---C (EQ. 8) DCR R +R or DCR (Direct Current Resistance). For simplicity, the inductor 1 2 DCR is considered as a separate lumped quantity, as shown in The capacitor voltage VC, is then replicated across the effective Figure 5. The channel current ILn, flowing through the inductor, internal sense resistor, RISEN. This develops a current through passes through the DCR. Equation 5 shows the S-domain RISEN which is proportional to the inductor current. This current, equivalent voltage, VL, across the inductor. ISEN, is continuously sensed and is then used by the controller for V s = I sL+DCR (EQ. 5) load-line regulation, channel-current balancing, and overcurrent L L n detection and limiting. Equation 9 shows that the proportion A simple R-C network across the inductor (R1, R2 and C) between the channel current, IL, and the sensed current, ISEN, is extracts the DCR voltage, as shown in Figure 6. The voltage driven by the value of the effective sense resistance, RISEN, and the DCR of the inductor. FN9278 Rev 5.00 Page 14 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI . the figure, the cycle average current, IAVG, is compared with DCR ISEN = ILR------------------ (EQ. 9) the Channel 1 sample, I1, to create an error signal IER. ISEN The effective internal RISEN resistance is important to the The filtered error signal modifies the pulse width commanded current sensing process because it sets the gain of the load by VCOMP to correct any unbalance and force IER toward zero. line regulation loop when droop is enabled as well as the gain The same method for error signal correction is applied to each of the channel-current balance loop and the overcurrent trip active channel. level. The effective internal RISEN resistance is user VID Interface programmable and is set through use of the RSET pin. Placing a single resistor, RSET, from the RSET pin to the VCC pin The ISL6323 supports hybrid power control of AMD processors programs the effective internal RISEN resistance according to which operate from either a 6-bit parallel VID interface (PVI) or Equation 10. a serial VID interface (SVI). The VID1/SEL pin is used to 3 command the ISL6323 into either the PVI mode or the SVI RISEN = 4----0---0---RSET (EQ. 10) mode. Whenever the EN pin is held LOW, both the multiphase Core and single-phase North Bridge Regulators are disabled The North Bridge regulator samples the load current in the and the ISL6323 is continuously sampling voltage on the same manner as the Core regulator does. The RSET resistor VID1/SEL pin. When the EN pin is toggled HIGH, the status of will program all the effective internal RISEN resistors to the the VID1/SEL pin will latch the ISL6323 into either PVI or SVI same value. mode. This latching occurs on the rising edge of the EN signal.If the VID1/SEL pin is held LOW during the latch, the Channel-Current Balance ISL6323 will be placed into SVI mode. If the VID1/SEL pin is One important benefit of multiphase operation is the thermal held HIGH during the latch, the ISL6323 will be placed into PVI advantage gained by distributing the dissipated heat over mode. For the ISL6323 to properly enter into either mode, the multiple devices and greater area. By doing this the designer level on the VID1/SEL pin must be stable no less that 1µs prior avoids the complexity of driving parallel MOSFETs and the to the EN signal transitioning from low to high. expense of using expensive heat sinks and exotic magnetic materials. 6-Bit Parallel VID Interface (PVI) With the ISL6323 in PVI mode, the single-phase North Bridge + VCOMP + PWM1 TO GATE regulator is disabled. Only the multiphase controller is active in - MODRUALMAPT OR - COLNOTGRICOL PVI mode to support uniplane VDD only processors. Table 1 WAVEFORM shows the 6-bit parallel VID codes and the corresponding FILTER f(s) reference voltage. IER I4 TABLE 1. 6-BIT PARALLEL VID CODES IAVG - N  I3 VID5 VID4 VID3 VID2 VID1 VID0 VREF + I2 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 I1 0 0 0 0 1 0 1.5000 NOTE: Channel 3 and 4 are optional. 0 0 0 0 1 1 1.4750 FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT- 0 0 0 1 0 0 1.4500 BALANCE ADJUSTMENT 0 0 0 1 0 1 1.4250 In order to realize the thermal advantage, it is important that 0 0 0 1 1 0 1.4000 each channel in a multiphase converter be controlled to carry 0 0 0 1 1 1 1.3750 about the same amount of current at any load level. To achieve 0 0 1 0 0 0 1.3500 this, the currents through each channel must be sampled every 0 0 1 0 0 1 1.3250 switching cycle. The sampled currents, In, from each active channel are summed together and divided by the number of 0 0 1 0 1 0 1.3000 active channels. The resulting cycle average current, IAVG, 0 0 1 0 1 1 1.2750 provides a measure of the total load current demand on the 0 0 1 1 0 0 1.2500 converter during each switching cycle. Channel-current 0 0 1 1 0 1 1.2250 balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper 0 0 1 1 1 0 1.2000 adjustment to each channel pulse width based on the error. 0 0 1 1 1 1 1.1750 Intersil’s patented current balance method is illustrated in 0 1 0 0 0 0 1.1500 Figure 6, with error correction for Channel 1 represented. In 0 1 0 0 0 1 1.1250 FN9278 Rev 5.00 Page 15 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI TABLE 1. 6-BIT PARALLEL VID CODES (Continued) TABLE 1. 6-BIT PARALLEL VID CODES (Continued) VID5 VID4 VID3 VID2 VID1 VID0 VREF VID5 VID4 VID3 VID2 VID1 VID0 VREF 0 1 0 0 1 0 1.1000 1 0 1 1 1 0 0.5875 0 1 0 0 1 1 1.0750 1 0 1 1 1 1 0.5750 0 1 0 1 0 0 1.0500 1 1 0 0 0 0 0.5625 0 1 0 1 0 1 1.0250 1 1 0 0 0 1 0.5500 0 1 0 1 1 0 1.0000 1 1 0 0 1 0 0.5375 0 1 0 1 1 1 0.9750 1 1 0 0 1 1 0.5250 0 1 1 0 0 0 0.9500 1 1 0 1 0 0 0.5125 0 1 1 0 0 1 0.9250 1 1 0 1 0 1 0.5000 0 1 1 0 1 0 0.9000 1 1 0 1 1 0 0.4875 0 1 1 0 1 1 0.8750 1 1 0 1 1 1 0.4750 0 1 1 1 0 0 0.8500 1 1 1 0 0 0 0.4625 0 1 1 1 0 1 0.8250 1 1 1 0 0 1 0.4500 0 1 1 1 1 0 0.8000 1 1 1 0 1 0 0.4375 0 1 1 1 1 1 0.7750 1 1 1 0 1 1 0.4250 1 0 0 0 0 0 0.7625 1 1 1 1 0 0 0.4125 1 0 0 0 0 1 0.7500 1 1 1 1 0 1 0.4000 1 0 0 0 1 0 0.7375 1 1 1 1 1 0 0.3875 1 0 0 0 1 1 0.7250 1 1 1 1 1 1 0.3750 1 0 0 1 0 0 0.7125 Serial VID Interface (SVI) 1 0 0 1 0 1 0.7000 The on-board Serial VID interface (SVI) circuitry allows the 1 0 0 1 1 0 0.6875 processor to directly drive the core voltage and Northbridge 1 0 0 1 1 1 0.6750 voltage reference level within the ISL6323. The SVC and SVD 1 0 1 0 0 0 0.6625 states are decoded with direction from the PWROK and VFIXEN 1 0 1 0 0 1 0.6500 inputs as described in the following sections. The ISL6323 uses a digital to analog converter (DAC) to generate a reference voltage 1 0 1 0 1 0 0.6375 based on the decoded SVI value. See Figure7 for a simple SVI 1 0 1 0 1 1 0.6250 interface timing diagram. 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 2 3 4 5 6 7 8 9 10 11 12 VCC SVC SVD ENABLE PWROK METAL_VID V_SVI METAL_VID V_SVI VDD AND VDDNB VDDPWRGD VFIXEN FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP FN9278 Rev 5.00 Page 16 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI PRE-PWROK METAL VID target value and this results in a controlled ramp of the power planes. Once soft-start has ended and both output planes are Typical motherboard start-up occurs with the VFIXEN input within regulation limits, the VDDPWRGD pin transitions high. If low. The controller decodes the SVC and SVD inputs to the EN input falls below the enable falling threshold, then the determine the Pre-PWROK metal VID setting. Once the POR controller ramps both VDD and VDDNB down to near zero. circuitry is satisfied, the ISL6323 begins decoding the inputs per Table 2. Once the EN input exceeds the rising enable TABLE 3. VFIXEN VID CODES threshold, the ISL6323 saves the Pre-PWROK metal VID value SVC SVD OUTPUT VOLTAGE (V) in an on-board holding register and passes this target to the 0 0 1.4 internal DAC circuitry. 0 1 1.2 TABLE 2. PRE-PWROK METAL VID CODES 1 0 1.0 SVC SVD OUTPUT VOLTAGE (V) 1 1 0.8 0 0 1.1 0 1 1.0 SVI MODE 1 0 0.9 Once the controller has successfully soft-started and 1 1 0.8 VDDPWRGD transitions high, the Northbridge SVI interface can assert PWROK to signal the ISL6323 to prepare for SVI commands. The controller actively monitors the SVI interface The Pre-PWROK metal VID code is decoded and latched on for set VID commands to move the plane voltages to start-up the rising edge of the enable signal. Once enabled, the VID values. Details of the SVI Bus protocol are provided in the ISL6323 passes the Pre-PWROK metal VID code on to internal AMD Design Guide for Voltage Regulator Controllers DAC circuitry. The internal DAC circuitry begins to ramp both Accepting Serial VID Codes specification. the VDD and VDDNB planes to the decoded Pre-PWROK metal VID output level. The digital soft-start circuitry actually Once the set VID command is received, the ISL6323 decodes stair steps the internal reference to the target gradually over a the information to determine which plane and the VID target fix interval. The controlled ramp of both output voltage planes required. See Table 4. The internal DAC circuitry steps the reduces in-rush current during the soft-start interval. At the end required output plane voltage to the new VID level. During this of the soft-start interval, the VDDPWRGD output transitions time one or both of the planes could be targeted. In the event high indicating both output planes are within regulation limits. the core voltage plane, VDD, is commanded to power off by If the EN input falls below the enable falling threshold, the serial VID commands, the VDDPWRGD signal remains ISL6323 ramps the internal reference voltage down to near asserted. The Northbridge voltage plane must remain active zero. The VDDPWRGD de-asserts with the loss of enable. The during this time. VDD and VDDNB planes will linearly decrease to near zero. If the PWROK input is de-asserted, then the controller steps VFIX MODE both VDD and VDDNB planes back to the stored Pre-PWROK metal VID level in the holding register from initial soft-start. No In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed attempt is made to read the SVC and SVD inputs during this external to the controller through jumpers to either GND or time. If PWROK is reasserted, then the on-board SVI interface VDDIO. These inputs are not expected to change, but the waits for a set VID command. ISL6323 is designed to support the potential change of state of these inputs. If VFIXEN is high, the IC decodes the SVC and If VDDPWRGD deasserts during normal operation, both SVD states per Table 3. voltage planes are powered down in a controlled fashion. The internal DAC circuitry stair steps both outputs down to near Once enabled, the ISL6323 begins to soft-start both VDD and zero. VDDNB planes to the programmed VFIX level. The internal soft-start circuitry slowly stair steps the reference up to the TABLE 4. SERIAL VID CODES SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) 000_0000b 1.5500 010_0000b 1.1500 100_0000b 0.7500 110_0000b 0.3500* 000_0001b 1.5375 010_0001b 1.1375 100_0001b 0.7375 110_0001b 0.3375* 000_0010b 1.5250 010_0010b 1.1250 100_0010b 0.7250 110_0010b 0.3250* 000_0011b 1.5125 010_0011b 1.1125 100_0011b 0.7125 110_0011b 0.3125* 000_0100b 1.5000 010_0100b 1.1000 100_0100b 0.7000 110_0100b 0.3000* 000_0101b 1.4875 010_0101b 1.0875 100_0101b 0.6875 110_0101b 0.2875* FN9278 Rev 5.00 Page 17 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI TABLE 4. SERIAL VID CODES (Continued) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) 000_0110b 1.4750 010_0110b 1.0750 100_0110b 0.6750 110_0110b 0.2750* 000_0111b 1.4625 010_0111b 1.0625 100_0111b 0.6625 110_0111b 0.2625* 000_1000b 1.4500 010_1000b 1.0500 100_1000b 0.6500 110_1000b 0.2500* 000_1001b 1.4375 010_1001b 1.0375 100_1001b 0.6375 110_1001b 0.2375* 000_1010b 1.4250 010_1010b 1.0250 100_1010b 0.6250 110_1010b 0.2250* 000_1011b 1.4125 010_1011b 1.0125 100_1011b 0.6125 110_1011b 0.2125* 000_1100b 1.4000 010_1100b 1.0000 100_1100b 0.6000 110_1100b 0.2000* 000_1101b 1.3875 010_1101b 0.9875 100_1101b 0.5875 110_1101b 0.1875* 000_1110b 1.3750 010_1110b 0.9750 100_1110b 0.5750 110_1110b 0.1750* 000_1111b 1.3625 010_1111b 0.9625 100_1111b 0.5625 110_1111b 0.1625* 001_0000b 1.3500 011_0000b 0.9500 101_0000b 0.5500 111_0000b 0.1500* 001_0001b 1.3375 011_0001b 0.9375 101_0001b 0.5375 111_0001b 0.1375* 001_0010b 1.3250 011_0010b 0.9250 101_0010b 0.5250 111_0010b 0.1250* 001_0011b 1.3125 011_0011b 0.9125 101_0011b 0.5125 111_0011b 0.1125* 001_0100b 1.3000 011_0100b 0.9000 101_0100b 0.5000 111_0100b 0.1000* 001_0101b 1.2875 011_0101b 0.8875 101_0101b 0.4875* 111_0101b 0.0875* 001_0110b 1.2750 011_0110b 0.8750 101_0110b 0.4750* 111_0110b 0.0750* 001_0111b 1.2625 011_0111b 0.8625 101_0111b 0.4625* 111_0111b 0.0625* 001_1000b 1.2500 011_1000b 0.8500 101_1000b 0.4500* 111_1000b 0.0500* 001_1001b 1.2375 011_1001b 0.8375 101_1001b 0.4375* 111_1001b 0.0375* 001_1010b 1.2250 011_1010b 0.8250 101_1010b 0.4250* 111_1010b 0.0250* 001_1011b 1.2125 011_1011b 0.8125 101_1011b 0.4125* 111_1011b 0.0125* 001_1100b 1.2000 011_1100b 0.8000 101_1100b 0.4000* 111_1100b OFF 001_1101b 1.1875 011_1101b 0.7875 101_1101b 0.3875* 111_1101b OFF 001_1110b 1.1750 011_1110b 0.7750 101_1110b 0.3750* 111_1110b OFF 001_1111b 1.1625 011_1111b 0.7625 101_1111b 0.3625* 111_1111b OFF NOTE: * Indicates a VID not required for AMD Family 10h processors. Voltage Regulation The ISL6323 incorporates differential remote-sense amplification in the feedback path. The differential sensing The integrating compensation network shown in Figure 8 removes the voltage error encountered when measuring the insures that the steady-state error in the output voltage is output voltage relative to the controller ground reference point limited only to the error in the reference voltage and offset resulting in a more accurate means of sensing output voltage. errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6323 to include the combined tolerances of each of these elements. The output of the error amplifier, VCOMP, is used by the modulator to generate the PWM signals. The PWM signals control the timing of the Internal MOSFET drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 11. The internal and external circuitry that controls voltage regulation is illustrated in Figure 8. V = V –V –V (EQ. 11) OUT REF OFS DROOP FN9278 Rev 5.00 Page 18 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI . EXTERNAL CIRCUIT ISL6323 INTERNAL CIRCUIT V = V –V –I--O-----U----T--DCR4----0---0----------1--------K R  FS OUT REF OFS  N  3 RSET FB (EQ. 13) TO RFS DROOP OSCILLATOR Where, VREF is the reference voltage, VOFS is the CONTROL programmed offset voltage, IOUT is the total output current of COMP the converter, K is the DC gain of the RC filter across the inductor (K is defined in Equation 7), N is the number of active CC channels, and DCR is the Inductor DCR value. IAVG Output-Voltage Offset Programming RC The ISL6323 allows the designer to accurately adjust the offset IOFS FB voltage by connecting a resistor, ROFS, from the OFS pin to - VCOMP VCC or GND. When ROFS is connected between OFS and + VCC, the voltage across it is regulated to 1.6V. This causes a ERROR AMPLIFIER proportional current (IOFS) to flow into the FB pin and out of the + RFB (VDROOP + VOFS) OFS pin. If ROFS is connected to ground, the voltage across it - is regulated to 0.3V, and IOFS flows into the OFS pin and out of the FB pin. The offset current flowing through the resistor  + VID between VDIFF and FB will generate the desired offset voltage VSEN DAC + + which is equal to the product (IOFSxRFB). These functions VOUT are shown in Figures 9 and10. - RGND Once the desired output offset voltage has been determined, FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE use Equations 14 and 15 to set ROFS: REGULATION WITH OFFSET ADJUSTMENT For Positive Offset (connect ROFS to GND): Load-Line (Droop) Regulation 0.3R By adding a well controlled output impedance, the output ROFS = V--------------------F----B-- (EQ. 14) OFFSET voltage can effectively be level shifted in a direction which works to achieve a cost-effective solution can help to reduce For Negative Offset (connect ROFS to VCC): the output-voltage spike that results from fast load-current 1.6R FB demand changes. ROFS = V-------------------------- (EQ. 15) OFFSET The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load VDIFF voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower - limit. By adding a well controlled output impedance, the output VOFS RFB + VREF + voltage under load can effectively be level shifted down so that E/A a larger positive spike can be sustained without crossing the - FB upper specification limit. IOFS As shown in Figure 8, with the FS resistor tied to ground, the + average current of all active channels, IAVG, flows from FB - through a load-line regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state VCC - value defined as in Equation 12: - ROFS + 1.6V VDROOP = IAVG RFB (EQ. 12) + + 0.3V OFS - ISL6323 The regulated output voltage is reduced by the droop voltage VDROOP. The output voltage as a function of load current is GND VCC shown in Equation 13. FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE PROGRAMMING FN9278 Rev 5.00 Page 19 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI VOUT RFB IDVC = IC VSEN + IDVC IC VOFS RFB - VREF + E/A CC RC - CDVC RDVC FB DVC FB COMP IOFS + 2x - - + ERROR AMPLIFIER - VDAC+RGND ISL6323 INTERNAL CIRCUIT - + 1.6V FIGURE 11. DYNAMIC VID COMPENSATION NETWORK + + 0.3V This VID-on-the-fly compensation network works by sourcing OFS - ROFS ISL6323 AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID GND VCC GND transition. To create this compensation current the ISL6323 sets the voltage on the DVC pin to be 2x the voltage on the FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE REF pin. Since the error amplifier forces the voltage on the FB PROGRAMMING pin and the REF pin to be equal, the resulting voltage across Dynamic VID the series RC between DVC and FB is equal to the REF pin The AMD processor does not step the output voltage voltage. The RC compensation components, RDVC and CDVC, commands up or down to the target voltage, but instead can then be selected to create the desired amount of passes only the target voltage to the ISL6323 through either compensation current. the PVI or SVI interface. The ISL6323 manages the resulting The amount of compensation current required is dependant on VID-on-the-Fly transition in a controlled manner, supervising a the modulator gain of the system, K1, and the error amplifier safe output voltage transition without discontinuity or RC components, RC and CC, that are in series between the FB disruption. The ISL6323 begins slewing the DAC at 3.25mV/µs and COMP pins. Use Equations 16, 17, and 18 to calculate the until the DAC and target voltage are equal. Thus, the total time RC component values, RDVC and CDVC, for the VID-on-the-fly required for a dynamic VID transition is dependent only on the compensation network. For these equations: VIN is the input size of the DAC change. voltage for the power train; VP-P is the oscillator ramp To further improve dynamic VID performance, ISL6323 also amplitude (1.5V); and RC and CC are the error amplifier RC implements a proprietary DAC smoothing feature. The external components between the FB and COMP pins. series RC components connected between DVC and FB limit VIN K1 (EQ. 16) K1 = ---------------- A = ----------------- any stair-stepping of the output voltage during a VID-on-the-Fly V K1–1 P–P transition. R = AR (EQ. 17) RCOMP C Compensating Dynamic VID Transitions C During a VID transition, the resulting change in voltage on the C = -----C--- (EQ. 18) RCOMP A FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the Advanced Adaptive Zero Shoot-Through Deadtime FB to the COMP pin. This current then flows through the Control (Patent Pending) feedback resistor, RFB, and can cause the output voltage to The integrated drivers incorporate a unique adaptive deadtime overshoot or undershoot at the end of the VID transition. In control technique to minimize deadtime, resulting in high order to ensure the smooth transition of the output voltage efficiency from the reduced freewheeling time of the lower during a VID change, a VID-on-the-fly compensation network MOSFET body-diode conduction, and to prevent the upper and is required. This network is composed of a resistor and lower MOSFETs from conducting simultaneously. This is capacitor in series, RDVC and CDVC, between the DVC and accomplished by ensuring either rising gate turns on its MOSFET the FB pin. with minimum and sufficient delay after the other has turned off. During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor current). At this time the UGATE is released to rise. An auto-zero FN9278 Rev 5.00 Page 20 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI comparator is used to correct the rDS(ON) drop in the phase initialization cycle. Hysteresis between the rising and falling voltage preventing false detection of the -0.3V phase level during thresholds assure the ISL6323 will not advertently turn off rDS(ON) conduction period. In the case of zero current, the unless the bias voltage drops substantially (see “Electrical UGATE is released after 35ns delay of the LGATE dropping below Specifications” on page9). 0.5V. When LGATE first begins to transition low, this quick The bias voltage applied to the PVCC1_2 and PVCC_NB pins transition can disturb the PHASE node and cause a false trip, so power the internal MOSFET drivers of each output channel. In there is 20ns of blanking time once LGATE falls until PHASE is order for the ISL6323 to begin operation, both PVCC inputs monitored. must exceed their POR rising threshold to guarantee proper Once the PHASE is high, the advanced adaptive operation of the internal drivers. Hysteresis between the rising shoot-through circuitry monitors the PHASE and UGATE and falling thresholds assure that once enabled, the ISL6323 voltages during a PWM falling edge and the subsequent will not inadvertently turn off unless the PVCC bias voltage UGATE turn-off. If either the UGATE falls to less than 1.75V drops substantially (see “Electrical Specifications” on page9). above the PHASE or the PHASE falls to less than +0.8V, the Depending on the number of active CORE channels LGATE is released to turn-on. determined by the Phase Detect block, the external driver POR checking is supported by the Enable Comparator. Initialization Enable Comparator Prior to initialization, proper conditions must exist on the EN, The ISL6323 features a dual function enable input (EN) for VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When enabling the controller and power sequencing between the the conditions are met, the controller begins soft-start. Once the controller and external drivers or another voltage rail. The output voltage is within the proper window of operation, the enable comparator holds the ISL6323 in shutdown until the controller asserts VDDPWRGD. voltage at EN rises above 0.86V. The enable comparator has ISL6323 INTERNAL CIRCUIT EXTERNAL CIRCUIT about 110mV of hysteresis to prevent bounce. It is important that the driver ICs reach their rising POR level before the VCC ISL6323 becomes enabled. The schematic in Figure 12 demonstrates sequencing the ISL6323 with the ISL66xx family PVCC1_2 of Intersil MOSFET drivers, which require 12V bias. PVCC_NB When selecting the value of the resistor divider the driver +12V maximum rising POR threshold should be used for calculating POR the proper resistor values. This will prevent improper CIRCUIT ENABLE 10.7k sequencing events from creating false trips during soft-start. COMPARATOR If the controller is configured for 2-phase CORE operation, EN + then the resistor divider can be used for sequencing the - controller with another voltage rail. The resistor divider to EN 1.00k should be selected using a similar approach as the previous driver discussion. VEN_THR The EN pin is also used to force the ISL6323 into either PVI or ISEN3- SVI mode. The mode is set upon the rising edge of the EN CHANNEL SOFT-START DETECT signal. When the voltage on the EN pin rises above 0.86V, the AND ISEN4- mode will be set depending upon the status of the VID1/SEL FAULT LOGIC pin. Phase Detection FIGURE 12. POWER SEQUENCING USING THRESHOLD- SENSITIVE ENABLE (EN) FUNCTION The ISEN3- and ISEN4- pins are monitored prior to soft-start to determine the number of active CORE channel phases. Power-On Reset If ISEN4- is tied to VCC, the controller will configure the The ISL6323 requires VCC, PVCC1_2, and PVCC_NB inputs channel firing order and timing for 3-phase operation. If ISEN3- to exceed their rising POR thresholds before the ISL6323 has and ISEN4- are tied to VCC, the controller will set the channel sufficient bias to guarantee proper operation. firing order and timing for 2-phase operation (see “PWM Operation” on page13 for details). If Channel 4 and/or The bias voltage applied to VCC must reach the internal Channel 3 are disabled, then the corresponding PWMn and power-on reset (POR) rising threshold. Once this threshold is ISENn+ pins may be left unconnected. reached, the ISL6323 has enough bias to begin checking the driver POR inputs, EN, and channel detect portions of the FN9278 Rev 5.00 Page 21 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Soft-Start Output Voltage Targets pin is monitored during soft-start, and should it be higher than Once the POR and Phase Detect blocks and enable the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. comparator are satisfied, the controller will begin the soft-start sequence and will ramp the CORE and NB output voltages up Once the internal ramping reference exceeds the FB pin to the SVI interface designated target level if the controller is potential, the output drives are enabled, allowing the output to set SVI mode. If set to PVI mode, the North Bridge regulator is ramp from the pre-charged level to the final level dictated by the disabled and the core is soft started to the level designated by DAC setting. Should the output be pre-charged to a level the parallel VID code. exceeding the DAC setting, the output drives are enabled at the SVI MODE end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level. Prior to soft-starting both CORE and NB outputs, the ISL6323 must check the state of the SVI interface inputs to determine Both CORE and NB output support start up into a pre-charged the correct target voltages for both outputs. When the output. controller is enabled, the state of the VFIXEN, SVD and SVC inputs are checked and the target output voltages set for both OUTPUT PRECHARGED CORE and NB outputs are set by the DAC (see “Serial VID ABOVE DAC LEVEL Interface (SVI)” on page16). These targets will only change if the EN signal is pulled low or after a POR reset of VCC. OUTPUT PRECHARGED BELOW DAC LEVEL Soft-Start The soft-start sequence is composed of three periods, as VCORE shown in Figure 13. At the beginning of soft-start, the DAC 400mV/DIV immediately obtains the output voltage targets for both outputs by decoding the state of the SVI or PVI inputs. A 100µs fixed delay time, TDA, proceeds the output voltage rise. After this EN delay period the ISL6323 will begin ramping both CORE and 5V/DIV NB output voltages to the programmed DAC level at a fixed rate of 3.25mV/µs. The amount of time required to ramp the 100µs/DIV output voltage to the final DAC voltage is referred to as TDB, FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323-BASED and can be calculated as shown in Equation 19. MULTIPHASE CONVERTER V DAC TDB = ------------------------------ (EQ. 19) –3 3.2510 After the DAC voltage reaches the final VID setting, VDDPWRGD will be set to high. . 400VmNVB/DIV VCORE 400mV/DIV TDA TDB EN 5V/DIV VDDPWRGD 5V/DIV 100µs/DIV FIGURE 13. SOFT-START WAVEFORMS Pre-Biased Soft-Start The ISL6323 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB FN9278 Rev 5.00 Page 22 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Overvoltage Protection The ISL6323 constantly monitors the sensed output voltage on - 142µA the VSEN pin to detect if an overvoltage event occurs. When the OCL output voltage rises above the OVP trip level and exceeds the + I1 VDDPWRGD OV limit actions are taken by the ISL6323 to 100µA - REPEAT FOR EACH protect the microprocessor load. CORE CHANNEL OCP At the inception of an overvoltage event, both on-board lower INB + - 100µA gate pins are commanded low as are the active PWM outputs OCP to the external drivers, the VDDPWRGD signal is driven low, + IAVG and the ISL6323 latches off normal PWM action. This turns on NB ONLY CORE ONLY the all of the lower MOSFETs and pulls the output voltage below a level that might cause damage to the load. The lower SOFT-START, FAULT AND CONTROL LOGIC MOSFETs remain driven ON until VDIFF falls below 400mV. The ISL6323 will continue to protect the load in this fashion as DUPLICATED FOR long as the overvoltage condition recurs. Once an overvoltage + NB AND CORE 1.8V OVP condition ends the ISL6323 latches off, and must be reset by - toggling POR, before a soft-start can be re-initiated. Pre-POR Overvoltage Protection + DAC + 250mV OV Prior to PVCC and VCC exceeding their POR levels, the - ISL6323 is designed to protect either load from any overvoltage events that may occur. This is accomplished by VSEN - means of an internal 10k resistor tied from PHASE to LGATE, UV which turns on the lower MOSFET to control the output voltage + VDDPWRGD DAC - 300mV until the overvoltage event ceases or the input power supply ISL6323 INTERNAL CIRCUITRY cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating FIGURE 15. POWER-GOOD AND PROTECTION CIRCUITRY of the load/microprocessor. Fault Monitoring and Protection In the event that during normal operation the PVCC or VCC The ISL6323 actively monitors both CORE and NB output voltage falls back below the POR threshold, the pre-POR voltages and currents to detect fault conditions. Fault monitors overvoltage protection circuitry reactivates to protect from any trigger protective measures to prevent damage to either load. more pre-POR overvoltage events. One common power good indicator is provided for linking to Undervoltage Detection external system monitors. The schematic in Figure 15 outlines the interaction between the fault monitors and the power good The undervoltage threshold is set at VDAC - 300mV typical. signal. When the output voltage (VSEN-RGND) is below the undervoltage threshold, VDDPWRGD gets pulled low. No other Power-Good Signal action is taken by the controller. VDDPWRGD will return high if The power-good pin (VDDPWRGD) is an open-drain logic the output voltage rises above VDAC - 250mV typical. output that signals whether or not the ISL6323 is regulating Open Sense Line Protection both NB and CORE output voltages within the proper levels, and whether any fault conditions exist. This pin should be tied In the case that either of the remote sense lines, VSEN or to a +5V source through a resistor. GND, become open, the ISL6323 is designed to detect this and shut down the controller. This event is detected by During shutdown and soft-start, VDDPWRGD pulls low and monitoring small currents that are fed out the VSEN and releases high after a successful soft-start and both output RGND pins. In the event of an open sense line fault, the voltages are operating between the undervoltage and controller will continue to remain off until the fault goes away, at overvoltage limits. VDDPWRGD transitions low when an which point the controller will re-initiate a soft-start sequence. undervoltage, overvoltage, or overcurrent condition is detected on either output or when the controller is disabled by a POR Overcurrent Protection reset or EN. In the event of an overvoltage or overcurrent The ISL6323 takes advantage of the proportionality between condition, the controller latches off and VDDPWRGD will not the load current and the average current, IAVG, to detect an return high. Pending a POR reset of the ISL6323 and overcurrent condition. See “Continuous Current Sampling” on successful soft-start, the VDDPWRGD will return high. page14 and “Channel-Current Balance” on page15 for more detail on how the average current is measured. Once the average current exceeds 100µA, a comparator triggers the FN9278 Rev 5.00 Page 23 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI converter to begin overcurrent protection procedures. The Note that the energy delivered during trip-retry cycling is much Core regulator and the North Bridge regulator have the same less than during full-load operation, so there is no thermal type of overcurrent protection. hazard. The overcurrent trip threshold is dictated by the DCR of the inductors, the number of active channels, the DC gain of the inductor RC filter and the RSET resistor. The overcurrent trip OUTPUT CURRENT, 50A/DIV threshold is shown in Equation 20. I = 100A-----N---------1-------3------R –V-----I--N-----–----N---------V-----O----U----T--V-----O----U----T--- OCP DCR K 400 SET 2Lf V S IN (EQ. 20) 0A Where: R OUTPUT VOLTAGE, K = ------------2--------- See “Continuous Current Sampling” on 500mV/DIV R1+R2 page14. fS = Switching Frequency 0V 3ms/DIV Equation 20 is valid for both the Core regulator and the North FIGURE 16. OVERCURRENT BEHAVIOR IN HICCUP MODE Bridge regulator. This equation includes the DC load current as NORTH BRIDGE REGULATOR OVERCURRENT well as the total ripple current contributed by all the phases. The overcurrent shutdown sequence for the North Bridge For the North Bridge regulator, N is 1. regulator is identical to the Core regulator with the exception that During soft-start, the overcurrent trip point is boosted by a it is a single phase regulator and will only disable the MOSFET factor of 1.4. Instead of comparing the average measured drivers for the North Bridge. Once 7 retry attempts have been current to 100µA, the average current is compared to 140µA. executed unsuccessfully, the controller will disable UGATE and Immediately after soft-start is over, the comparison level LGATE signals for both Core and North Bridge and will latch off changes to 100µA. This is done to allow for start-up into an requiring a POR of VCC to reset the ISL6323. active load while still supplying output capacitor in-rush Note that the energy delivered during trip-retry cycling is much current. less than during full-load operation, so there is no thermal CORE REGULATOR OVERCURRENT hazard. At the beginning of overcurrent shutdown, the controller sets all Individual Channel Overcurrent Limiting of the UGATE and LGATE signals low, puts PWM3 and PWM4 The ISL6323 has the ability to limit the current in each (if active) in a high-impedance state, and forces VDDPWRGD individual channel of the Core regulator without shutting down low. This turns off all of the upper and lower MOSFETs. The the entire regulator. This is accomplished by continuously system remains in this state for fixed period of 12ms. If the comparing the sensed currents of each channel with a controller is still enabled at the end of this wait period, it will constant 140µA OCL reference current. If a channel’s attempt a soft-start, as shown in Figure 16. If the fault remains, individual sensed current exceeds this OCL limit, the UGATE the trip-retry cycles will continue until either the fault is cleared or signal of that channel is immediately forced low, and the for a total of seven attempts. If the fault is not cleared on the final LGATE signal is forced high. This turns off the upper attempt, the controller disables UGATE and LGATE signals for MOSFET(s), turns on the lower MOSFET(s), and stops the rise both Core and North Bridge and latches off requiring a POR of of current in that channel, forcing the current in the channel to VCC to reset the ISL6323. decrease. That channel’s UGATE signal will not be able to It is important to note that during soft start, the overcurrent trip return high until the sensed channel current falls back below point is increased by a factor of 1.4. If the fault draws enough the 140µA reference. current to trip overcurrent during normal run mode, it may not draw enough current during the soft-start ramp period to trip Exclusive Operation in Parallel Mode overcurrent while the output is ramping up. If a fault of this type The ISL6323 was designed such that the processor would be is affecting the output, then the regulator will complete soft- the determining factor of whether the ISL6323 operated in PVI start and the trip-retry counter will be reset to zero. Once the mode or in SVI mode. If, however, the ISL6323 is to be used in regulator has completed soft-start, the overcurrent trip point will a system that will be used exclusively in parallel mode and the return to it’s nominal setting and an overcurrent shutdown will North Bridge regulator will not be populated at all, there are be initiated. This will result in a continuous hiccup mode. some pin connections that must be made in order for the ISL6323 to function properly. The ISEN_NB+ (pin 2) and ISEN_NB- (pin 47) pins as well as the RGND_NB pin (pin 3) FN9278 Rev 5.00 Page 24 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI must be tied to ground. A small trace from the pin to the ground the length of dead times, td1 and td2, at the beginning and the pad under the part is all that is required. The PVCC_NB pin end of the lower-MOSFET conduction interval respectively. (pin 42) should be tied to either +5V or to +12V with a small dtheec oNuoprltihn gB rciadpgaec rietogru tloa tgorro munady. bAel l leoftth uenr cpoinnsn eacstseodc.iated with PLOW2 = VDONfS I--NM----+I--P---2----P--- td1 +I--NM----–I--P---2----P--- td2 (EQ. 22) General Design Guide The total maximum power dissipated in each lower MOSFET is This design guide is intended to provide a high-level explanation approximated by the summation of PLOW,1 and PLOW,2. of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills UPPER MOSFET POWER CALCULATION and techniques referenced in the following. In addition to this In addition to rDS(ON) losses, a large portion of the upper guide, Intersil provides complete reference designs that include MOSFET losses are due to currents conducted across the schematics, bills of materials, and example board layouts for all input voltage (VIN) during switching. Since a substantially common microprocessor applications. higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Power Stages Upper MOSFET losses can be divided into separate The first step in designing a multiphase converter is to components involving the upper-MOSFET switching times, the determine the number of phases. This determination depends lower-MOSFET body-diode reverse recovery charge, Qrr, and heavily on the cost analysis which in turn depends on system the upper MOSFET rDS(ON) conduction loss. constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can When the upper MOSFET turns off, the lower MOSFET does be mounted on both sides of the circuit board, whether not conduct any portion of the inductor current until the voltage through-hole components are permitted, the total board space at the phase node falls below ground. Once the lower available for power-supply circuitry, and the maximum amount MOSFET begins conducting, the current in the upper MOSFET of load current. Generally speaking, the most economical falls to zero as the current in the lower MOSFET ramps up to solutions are those in which each phase handles between 25A assume the full inductor current. In Equation 23, the required and 30A. All surface-mount designs will tend toward the lower time for this commutation is t1 and the approximated end of this current range. If through-hole MOSFETs and associated power loss is PUP(1). inductors can be used, higher per-phase currents are possible. I I t  P V --M----+--P-------P----1-- f (EQ. 23) In cases where board space is the limiting constraint, current UP1 IN N 2  2 S can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, At turn-on, the upper MOSFET begins to conduct and this inductors and heat dissipating surfaces. transition occurs over a time t2. In Equation 24, the approximate power loss is PUP(2). MOSFETS The choice of MOSFETs depends on the current each MOSFET P V I--M----–I--P-------P--t--2--f (EQ. 24) will be required to conduct, the switching frequency, the UP2 IN N 2  2 S capability of the MOSFETs to dissipate heat, and the availability A third component involves the lower MOSFET and nature of heat sinking and air flow. reverse-recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the LOWER MOSFET POWER CALCULATION lower-MOSFET body diode can recover all of Qrr, it is The calculation for power loss in the lower MOSFET is simple, conducted through the upper MOSFET across VIN. The power since virtually all of the loss in the lower MOSFET is due to dissipated as a result is PUP(3) as shown in Equation25. current conducted through the channel resistance (rDS(ON)). In Equation 21, IM is the maximum continuous output current, IP- PUP3 = VINQrrfS (EQ. 25) P is the peak-to-peak inductor current (see Equation 2), and d Finally, the resistive part of the upper MOSFET is given in is the duty cycle (VOUT/VIN). Equation 26 as PUP(4). PLOW1 = rDSON I-N-M----21–d+-I-L------P------P------12---2-------1-----–----d----- (EQ. 21) PUP4rDSON I-N-M----2d+I--P1----2---P-- 2 (EQ. 26) An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead The total power dissipated by the upper MOSFET at full load time when inductor current is flowing through the lower- can now be approximated as the summation of the results from MOSFET body diode. This term is dependent on the diode Equations 23, 24, 25 and 26. Since the power equations forward voltage at IM, VD(ON), the switching frequency, fS, and depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive FN9278 Rev 5.00 Page 25 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI solutions to the loss equations for different MOSFETs and drivers must be less than the maximum allowable power different switching frequencies. dissipation for the QFN package. Internal Bootstrap Device Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the All three integrated drivers feature an internal bootstrap maximum allowable power dissipation level will push the IC Schottky diode. Simply adding an external capacitor across the beyond the maximum recommended operating junction BOOT and PHASE pins completes the bootstrap circuit. The temperature of +125°C. The maximum allowable IC power bootstrap function is also designed to prevent the bootstrap dissipation for the 7x7 QFN package is approximately 3.5W at capacitor from overcharging due to the large negative swing at room temperature. See “Layout Considerations” on page33 for the PHASE node. This reduces voltage stress on the boot to thermal transfer improvement suggestions. phase pins. When designing the ISL6323 into an application, it is The bootstrap capacitor must have a maximum voltage rating recommended that the following calculations is used to ensure above PVCC + 4V and its capacitance value can be chosen safe operation at the desired frequency for the selected from Equation 27: MOSFETs. The total gate drive power losses, PQg_TOT, due to Q C ---------------G----A----T---E------------ the gate charge of MOSFETs and the integrated driver’s BOOT_CAP V BOOT_CAP (EQ. 27) internal circuitry and their corresponding average driver current can be estimated with Equations 28 and 29, respectively. Q PVCC Q = -----G-----1--------------------------N P = P +P +I VCC (EQ. 28) GATE V Q1 Qg_TOT Qg_Q1 Qg_Q2 Q GS1 3 where QG1 is the amount of gate charge per upper MOSFET PQg_Q1 = 2---QG1PVCCfSWNQ1NPHASE at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable PQg_Q2 = QG2PVCCfSWNQ2NPHASE droop in the rail of the upper gate drive. (EQ. 29) 1.6 I = 3---Q N +Q N N f +I DR 2 G1 Q1 G2 Q2 PHASE SW Q 1.4 Where, PQg_Q1 is the total upper gate drive power loss and 1.2 PQg_Q2 is the total lower gate drive power loss; the gate charge µF) 1.0 (QG1 and QG2) is defined at the particular gate to source drive (AP voltage PVCC in the corresponding MOSFET data sheet; IQ is _C 0.8 the driver total quiescent current with no load at both drive T OO outputs; NQ1 and NQ2 are the number of upper and lower B 0.6 C QGATE = 100nC MOSFETs per phase, respectively; NPHASE is the number of 0.4 active phases. The IQ*VCC product is the quiescent power of the controller without load on the drives. 50nC 0.2 20nC PVCC BOOT 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 D VBOOT_CAP (V) CGD FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE RHI1 UGATE G VOLTAGE CDS Gate Drive Voltage Versatility RLO1 RG1 RGI1 The ISL6323 provides the user flexibility in choosing the gate CGS Q1 drive voltage for efficiency optimization. The controller ties the S upper and lower drive rails together. Simply applying a voltage PHASE from 5V up to 12V on PVCC sets both gate drive rail voltages FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH simultaneously. Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power dissipated by all three FN9278 Rev 5.00 Page 26 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI For all three cases, use the expected VID voltage that would PVCC be used at TDC for Core and North Bridge for the VCORE and D VNB variables, respectively. CGD CASE 1 RHI2 LGATE G CDS ICore RLO2 RG2 RGI2 INBMAXDCRNB------------N---M-----A----X--DCRCore (EQ. 31) CGS Q2 In Case 1, the DC voltage across the North Bridge inductor at S full load is less than the DC voltage across a single phase of the Core regulator while at full load. Here, the DC voltage across the Core inductors must be scaled down to match the FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH DC voltage across the North Bridge inductor, which will be impressed across the ISEN_NB pins without any gain. So, the The total gate drive power losses are dissipated among the resistive components along the transition path and in the R2 resistor for the North Bridge inductor RC filter is left unpopulated and K = 1. bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path 1. Choose a capacitor value for the North Bridge RC filter. A resistance (PDR_UP) the lower drive path resistance (PDR_UP) 0.1µF capacitor is a recommended starting point. and in the boot strap diode (PBOOT). The rest of the power will 2. Calculate the value for resistor R1 using Equation 32: be dissipated by the external gate resistors (RG1 and RG2) and L NB (EQ. 32) tFhieg uinretesr n1a8l agnadte 1 r9e ssihsotowr st h(eR GtyIp1i caanld u RppGeI2r )a onfd t hloew MerO gSaFteE Ts. R1NB = D-----C-----R-----N----B--------C----N-----B-- drives turn-on transition path. The total power dissipation in the 3. Calculate the value for the RSET resistor using Equation33: controller itself, PDR, can be roughly estimated as Equation 30: R = 4----0---0---D-----C-----R-----N----B--------K---I +-V----I--N------–----V----N----B----V-----N----B-- PDR = PDR_UP+PDR_LOW +PBOOT+IQVCC SET 3 100A  OCPNB 2LNBfS VIN Where:K = 1 (EQ. 33) P Qg_Q1 P = --------------------- BOOT 3 (Derived from Equation 20).  RHI1 RLO1  PQg_Q1 4. Using Equation 34 (also derived from Equation 20), PDR_UP = R-----H----I--1-----+----R-----E----X----T---1--+R-----L---O-----1----+-----R-----E----X----T---1------------3----------- calculate the value of K for the Core regulator. 3 N 100A K = ----------R ----------------------------------------------------------------------------------------------------------------------------------------- PDR_LOW = R-----H----I--2--R---+--H--R--I--2-E----X----T---2--+R-----L---O-----2R----+-L---O-R----2-E----X----T---2--P-----Q----g-2---_---Q----2- 400 SET DCRCORE IOCPCORE+V----2-I--N-----–L----CN----O----R-V----E-C----O---f-R-S---E---V-----C-V---O-I--N-R-----E-- (EQ. 34) R R R = R +-----G-----I-1-- R = R +-----G-----I-2-- EXT1 G1 NQ1 EXT2 G2 NQ2 5. Choose a capacitor value for the Core RC filters. A 0.1µF (EQ. 30) capacitor is a recommended starting point. Inductor DCR Current Sensing Component 6. Calculate the values for R1 and R2 for Core. Equations35 and 36 will allow for their computation. Selection and R Value Calculation SET R 2 With the single RSET resistor setting the value of the effective K = ----------------------C----o---r--e--------------- (EQ. 35) R +R internal sense resistors for both the North Bridge and Core 1 2 Core Core regulators, it is important to set the RSET value and the R R inductor RC filter gain, K, properly. See “Continuous Current LCore 1Core 2Core (EQ. 36) -------------------------- = ----------------------------------------------C Sampling” on page14 and “Channel-Current Balance” on DCRCore R1 +R2 Core Core Core page15 for more details on the application of the RSET resistor and the RC filter gain. CASE 2 I There are 3 separate cases to consider when calculating these I DCR --C-----o---r--e---M-----A----X--DCR (EQ. 37) component values. If the system under design will never utilize NBMAX NB N Core the North Bridge regulator and the ISL6323 will always be in In Case 2, the DC voltage across the North Bridge inductor at parallel mode, then follow the instructions for Case 3 and only full load is greater than the DC voltage across a single phase calculate values for Core regulator components. of the Core regulator while at full load. Here, the DC voltage across the North Bridge inductor must be scaled down to match the DC voltage across the Core inductors, which will be FN9278 Rev 5.00 Page 27 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI impressed across the ISEN pins without any gain. So, the R2 CASE 3 resistor for the Core inductor RC filters is left unpopulated and I Core K = 1. I DCR = ---------------M-----A----X--DCR (EQ. 43) NBMAX NB N Core 1. Choose a capacitor value for the Core RC filter. A 0.1µF In Case 3, the DC voltage across the North Bridge inductor at capacitor is a recommended starting point. full load is equal to the DC voltage across a single phase of the 2. Calculate the value for resistor R1: Core regulator while at full load. Here, the full scale DC LCore (EQ. 38) inductor voltages for both North Bridge and Core will be R = ------------------------------------------------ 1Core DCRCoreCCore impressed across the ISEN pins without any gain. So, the R2 resistors for the Core and North Bridge inductor RC filters are 3. Calculate the value for the RSET resistor using Equation 39: left unpopulated and K = 1 for both regulators. 400 DCRCOREK  VIN–NVCORE VCORE RSET = ----3------------N---------1----0---0--------A---------IOCPCORE+----2--------L----C----O----R-----E--------f--S------------V----I--N-------- For this Case, it is recommended that the overcurrent trip point for the North Bridge regulator be equal to the overcurrent trip Where:K = 1 (EQ. 39) point for the Core regulator divided by the number of core phases. (Derived from Equation 20). 4. Using Equation 40 (also derived from Equation 20), 1. Choose a capacitor value for the North Bridge RC filter. A calculate the value of K for the North bridge regulator. 0.1µF capacitor is a recommended starting point. K = ----3------R ----------1---------------------------------------1----0---0--------A------------------------------- 2. Calculate the value for the North Bridge resistor R1: 400 SET DCR V –V V NB IOCPNB+2-----I--N-L----N----B-----N---f-B-S-----V---N-I--N-B-- R1NB = D-----C-----R----L-N---N-B---B-----C----N-----B-- (EQ. 44) (EQ. 40) 3. Choose a capacitor value for the Core RC filter. A 0.1µF 5. Choose a capacitor value for the North Bridge RC filter. A capacitor is a recommended starting point. 0.1µF capacitor is a recommended starting point. 4. Calculate the value for the Core resistor R1: 6. Calculate the values for R1 and R2 for North Bridge. L Equations 41 and 42 will allow for their computation. R = --------------------C----o----r--e------------------ (EQ. 45) 1Core DCRCoreCCore R 2 NB (EQ. 41) K = R-----------------+-----R--------------- 5. Calculate the value for the RSET resistor using Equation 46: 1 2 NB NB R R L 1 2 ---------N-----B------- = ---------N----B----------------N----B----C (EQ. 42) DCR R +R NB NB 1 2 NB NB 400 DCRCOREK  VIN–NVCORE VCORE R = -------------------------------------------------I +----------------------------------------------------------------- SET 3 N100A  OCPCORE 2LCOREfS VIN  Where:K = 1 (EQ. 46) 6. Calculate the OCP trip point for the North Bridge regulator represent the variable “K” in all equations. It is also very using equation 47. If the OCP trip point is higher than important that the RSET resistor be tied between the RSET pin desired, then the component values must be recalculated and the VCC pin of the ISL6323. utilizing Case 1. If the OCP trip point is lower than desired, then the component values must be recalculated utilizing Case 2. I = 100A----------1---------------3------R +-V----I--N-----–-----V----N----B----V-----N----B-- OCPNB DCRNB 400 SET 2LNBfS VIN (EQ. 47) NOTE: The values of RSET must be greater than 20k and less than 80k. For all of the 3 previous cases, if the calculated value of RSET is less than 20k, then either the OCP trip point needs to be increased or the inductor must be changed to an inductor with higher DCR. If the RSET resistor is greater than 80k, then a value of RSET that is less than 80k must be chosen and a resistor divider across both North Bridge and Core inductors must be set up with proper gain. This gain will FN9278 Rev 5.00 Page 28 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Inductor DCR Current Sensing Component Fine 4. Replace R1 and R2 with the new values and check to see Tuning that the error is corrected. Repeat the procedure if VIN IL necessary. n UGATE(n) L MOSFET DCR VOUT DRIVER LGATE(n) INDUCTOR COUT V2 +VL(s) - V1 +VC(s) - VOUT R1 C R2 ISL6323 INTERNAL CIRCUIT ITRAN In I SAMPLE FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR + ISENn- +VC(s)- Loadline Regulation Resistor - RISEN ISENn+ The loadline regulation resistor, labeled RFB in Figure 8, sets VCC the desired loadline required for the application. Equation 50 ISEN TO ACTIVE { can be used to calculate RFB. RSET CORE CHANNELS V DROOP TO NORTH BRIDGE RSET RFB = ---------------I---------------------------M-----A----X------------------- (EQ. 50) 400 OUTMAX DCR ---------------------------------------------------K CSET 3 N RSET FIGURE 20. DCR SENSING CONFIGURATION Where K is defined in Equation 7. Due to errors in the inductance and/or DCR it may be If no loadline regulation is required, FS resistor should be tied necessary to adjust the value of R1 and R2 to match the time constants correctly. The effects of time constant mismatch can between the FS pin and VCC. To choose the value for RFB in this situation, please refer to “Compensation Without Loadline be seen in the form of droop overshoot or undershoot during Regulation” on page30. the initial load transient spike, as shown in Figure 21. Follow the steps below to ensure the RC and inductor L/DCR time Compensation With Loadline Regulation constants are matched accurately. The load-line regulated converter behaves in a similar manner 1. If the regulator is not utilizing droop, modify the circuit by to a peak current mode controller because the two poles at the placing the frequency set resistor between FS and Ground output filter L-C resonant frequency split with the introduction for the duration of this procedure. of current information into the control loop. The final location of 2. Capture a transient event with the oscilloscope set to about these poles is determined by the system function, the gain of L/DCR/2 (sec/div). For example, with L = 1µH and DCR = the current signal, and the value of the compensation 1m, set the oscilloscope to 500µs/div. components, RC and CC. 3. Record V1 and V2 as shown in Figure 21. Select new values, R1(NEW) and R2(NEW) for the time constant resistors based on the original values, R1(OLD) and R2(OLD) using Equations 48 and 49. V R = R --------1-- (EQ. 48) 1NEW 1OLD V 2 R = R ----V----1-- (EQ. 49) 2NEW 2OLD V 2 FN9278 Rev 5.00 Page 29 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI C2 (OPTIONAL) ---------------1----------------->f 0 Case 1: 2 LC 2f V  LC RC CC COMP RC = RFB----------------0--0-.--6---6------p--V-p---I--N------------------ 0.66V IN C = ------------------------------------------------------ FB C 2VP-PRFBf0 ISL6323 1 1 RFB Case 2: 2--------------------L--------C----f0<2----------------C---------E----S-----R--- VSEN V 22 f2LC P-P 0 R = R ------------------------------------------------------------------ (EQ. 51) C FB 0.66 V IN FIGURE 22. COMPENSATION CONFIGURATION FOR 0.66VIN C = --------------------------------------------------------------------------------------- LOAD-LINE REGULATED ISL6323 CIRCUIT C 22 f 2V R  LC 0 P-P FB Since the system poles and zero are affected by the values of the components that are meant to compensate them, the Case 3: f0>2----------------C--1-------E----S-----R--- solution to the system equation becomes fairly complicated. 2f V L Fortunately, there is a simple approximation that comes very R = R -------------------0------------p---p----------- C FB 0.66V ESR close to an optimal solution. Treating the system as though it IN were a voltage-mode regulator, by compensating the L-C poles 0.66V ESR C IN C = ------------------------------------------------------------------ and the ESR zero of the voltage mode approximation, yields a C 2V R f  L P-P FB 0 solution that is always stable with very close to ideal transient performance. Compensation Without Loadline Regulation The non load-line regulated converter is accurately modeled as Select a target bandwidth for the compensated system, f0. The a voltage-mode regulator with two poles at the L-C resonant target bandwidth must be large enough to assure adequate frequency and a zero at the ESR frequency. A type-III transient performance, but smaller than 1/3 of the per-channel controller, as shown in Figure 23, provides the necessary switching frequency. The values of the compensation compensation. components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the C2 following three, there is a separate set of equations for the compensation components. RC CC COMP In Equation 51, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output FB capacitors; ESR is the equivalent series resistance of the bulk C1 output filter capacitance; and VP-P is the peak-to-peak ISL6323 sawtooth signal amplitude as described in the “Electrical R1 RFB Specifications” table on page9. Once selected, the compensation values in Equation 51 VSEN assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE value of RC while observing the transient performance on an REGULATION oscilloscope until no further improvement is noted. Normally, The first step is to choose the desired bandwidth, f0, of the CC will not need adjustment. Keep the value of CC from compensated system. Choose a frequency high enough to Equation 51 unless some performance issue is noted. assure adequate transient performance but not higher than 1/3 of The optional capacitor C2, is sometimes needed to bypass the switching frequency. The type-III compensator has an extra noise away from the PWM comparator (see Figure 22). Keep a high-frequency pole, fHF. This pole can be used for added noise position available for C2, and be prepared to install a high rejection or to assure adequate attenuation at the error amplifier frequency capacitor of between 22pF and 150pF in case any high-order pole and zero frequencies. A good general rule is to leading edge jitter problem is noted. choose fHF=10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth as shown in Equation 52. FN9278 Rev 5.00 Page 30 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI . the transient energy until the regulator can respond. Because it CESR R = R -------------------------------------------- has a low bandwidth compared to the switching frequency, the 1 FB LC–CESR output filter limits the system transient response. The output capacitors must supply or sink load current while the current in LC–CESR C1 = -----------------R--------------------------- the output inductors increases or decreases to meet the FB demand. 0.75VIN In high-speed converters, the output capacitor bank is usually C = ----------------------------------------------------------------------------------------------------- 2 22f f  LCR V the most costly (and often the largest) part of the circuit. Output 0 HF FB P-P (EQ. 52) filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output 2 R = -V----P-------P----------2------------------f--0-------f--H----F--------L--------C---------R----F----B--- capacitors are the maximum size of the load step, I, the load- C 0.75VIN2fHF LC–1 current slew rate, di/dt, and the maximum allowable output- voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL 0.75V 2f  LC–1 IN HF C = ----------------------------------------------------------------------------------------------------- (equivalent series inductance). C 22f f  LCR V 0 HF FB P-P In the solutions to the compensation equations, there is a At the beginning of the load transient, the output capacitors single degree of freedom. For the solutions presented in supply all of the transient current. The output voltage will Equation 53, RFB is selected arbitrarily. The remaining initially deviate by an amount approximated by the voltage drop compensation components are then selected according to across the ESL. As the load current increases, the voltage Equation 53. drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have In Equation 53, L is the per-channel filter inductance divided by sufficiently low ESL and ESR so that the total output voltage the number of active channels; C is the sum total of all output deviation is less than the allowable maximum. Neglecting the capacitors; ESR is the equivalent-series resistance of the bulk contribution of inductor current and regulator response, the output-filter capacitance; and VP-P is the peak-to-peak output voltage initially deviates by an amount as shown in sawtooth signal amplitude as described in “Electrical Equation 54: Specifications” on page9. Output Filter Design VESL-d----i+ESRI (EQ. 54) dt 1 Case 1: -------------------------------->f0 2 LC The filter capacitor must have sufficiently low ESL and ESR so 2f V  LC that V < VMAX. 0 P-P R = R ---------------------------------------------------------- C FB 0.66VIN Most capacitor solutions rely on a mixture of high frequency 0.66V capacitors with relatively low capacitance in combination with IN C = ------------------------------------------------------ C 2V R f bulk capacitors having high capacitance but limited high- P-P FB 0 frequency performance. Minimizing the ESL of the high- 1 1 frequency capacitors allows them to support the output voltage --------------------------------f <------------------------------------- Case 2: 2 LC 0 2CESR as the current increases. Minimizing the ESR of the bulk 2 2 capacitors allows them to supply the increased current with V 2  f LC R = R -----P------P-----------------------------------0--------------------- (EQ. 53) less output voltage deviation. C FB 0.66 V IN The ESR of the bulk capacitors also creates the majority of the 0.66V IN CC = ---2--------------2--------f-----2--------V-----------------R--------------------L--------C---- output-voltage ripple. As the bulk capacitors sink and source 0 P-P FB the inductor AC ripple current (see “Interleaving” on page12 and Equation 3), a voltage develops across the bulk capacitor ESR equal to IC(P-P)(ESR). Thus, once the output capacitors Case 3: f0>2----------------C--1-------E----S-----R--- are selected, the maximum allowable ripple voltage, VP- P(MAX), determines the lower limit on the inductance. 2f V L 0 P-P RC = RFB -0---.--6----6---------V----I--N--------E----S-----R---- L ESR ---V-----I-N------–----N----------V----O----U-----T-----------V----O----U----T--- (EQ. 55) 0.66VINESR C fSVINVP-P(MAX) C = ------------------------------------------------------------------ C 2V R f  L P-P FB 0 Since the capacitors are supplying a decreasing portion of the The output inductors and the output capacitor bank together to load current while the regulator recovers from the transient, the form a low-pass filter responsible for smoothing the pulsating capacitor voltage becomes slightly depleted. The output voltage at the phase nodes. The output filter also must provide FN9278 Rev 5.00 Page 31 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI inductors must be capable of assuming the entire load current Their RMS current capacity must be sufficient to handle the AC before the output voltage decreases more than VMAX. This component of the current drawn by the upper MOSFETs which is places an upper limit on inductance. related to duty cycle and the number of active phases. 0.3 Equation 56 gives the upper limit on L for the cases when the IL(P-P) = 0 IL(P-P) = 0.5 IO trailing edge of the current transient causes a greater output- ) O IL(P-P) = 0.25 IO IL(P-P) = 0.75 IO voltage deviation than the leading edge. Equation 57 IS/ M addresses the leading edge. Normally, the trailing edge R dictates the selection of L because duty cycles are usually less NT (I 0.2 E than 50%. Nevertheless, both inequalities should be R R evaluated, and L should be selected based on the lower of the CU two results. In each equation, L is the per-channel inductance, OR T C is the total output capacitance, and N is the number of active CI A 0.1 channels. P A C L2--------N---------C---------V----O--- V –IESR (EQ. 56) UT- I2 MAX NP I 0 L1----.--2---5--------N---------C--- V –IESR V –V  (EQ. 57) 0 0.2 0.4 0.6 0.8 1.0 I2 MAX  IN O DUTY CYCLE (VO/VIN) FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT Switching Frequency vs DUTY CYCLE FOR 4-PHASE CONVERTER There are a number of variables to consider when choosing For a 4-phase design, use Figure 25 to determine the input- the switching frequency, as there are considerable effects on capacitor RMS current requirement set by the duty cycle, the upper MOSFET loss calculation. These effects are outlined maximum sustained output current (IO), and the ratio of the in “MOSFETs” on page25, and they establish the upper limit peak-to-peak inductor current (IL(P-P)) to IO. Select a bulk for the switching frequency. The lower limit is established by capacitor with a ripple current rating which will minimize the the requirement for fast transient response and small output- total number of input capacitors required to support the RMS voltage ripple as outlined in “Output Filter Design” on page31. current calculated. Choose the lowest switching frequency that allows the The voltage rating of the capacitors should also be at least regulator to meet the transient-response requirements. 1.25x greater than the maximum input voltage. Figures 26 and Switching frequency is determined by the selection of the 27 provide the same input RMS current information for frequency-setting resistor, RT. Figure 24 and Equation 58 are 3-phase and 2-phase designs respectively. Use the same provided to assist in selecting the correct value for RT. approach for selecting the bulk capacitor type and number. 10.61–1.035logfS (EQ. 58) Low capacitance, high-frequency ceramic capacitors are R = 10 T needed in addition to the input bulk capacitors to suppress 1k leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression. ) (kT 100 R 10 60k 100k 1M 2M SWITCHING FREQUENCY (Hz) FIGURE 24. RT vs SWITCHING FREQUENCY Input Capacitor Selection The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. FN9278 Rev 5.00 Page 32 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI critical because they switch large amounts of energy. Next are 0.3 IL(P-P) = 0 IL(P-P) = 0.5 IO small signal components that connect to sensitive nodes or ) O IL(P-P) = 0.25 IO IL(P-P)= 0.75 IO supply critical bypassing current and signal coupling. IS/ M The power components should be placed first, which include the R T (I MOSFETs, input and output capacitors, and the inductors. It is N 0.2 E important to have a symmetrical layout for each power train, R R preferably with the controller located equidistant from each. U C R Symmetrical layout allows heat to be dissipated equally across O T all power trains. Equidistant placement of the controller to the CI A 0.1 CORE and NB power trains it controls through the integrated P A drivers helps keep the gate drive traces equally short, resulting C UT- in equal trace impedances and similar drive capability of all sets P N of MOSFETs. I 0 When placing the MOSFETs try to keep the source of the upper 0 0.2 0.4 0.6 0.8 1.0 FETs and the drain of the lower FETs as close as thermally DUTY CYCLE (VIN/VO) FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS possible. Input high-frequency capacitors, CHF, should be placed CURRENT FOR 3-PHASE CONVERTER close to the drain of the upper FETs and the source of the lower FETs. Input bulk capacitors, CBULK, case size typically limits 0.3 following the same rule as the high-frequency input capacitors. Place the input bulk capacitors as close to the drain of the upper I) S/O FETs as possible and minimize the distance to the source of the M lower FETs. R T (I N 0.2 Locate the output inductors and output capacitors between the E R MOSFETs and the load. The high-frequency output decoupling R U C capacitors (ceramic) should be placed as close as practicable to R O the decoupling target, making use of the shortest connection T CI paths to any internal planes, such as vias to GND next or on the A 0.1 P capacitor solder pad. CA IL(P-P) = 0 UT- IL(P-P) = 0.5 IO The critical small components include the bypass capacitors INP IL(P-P) = 0.75 IO (CFILTER) for VCC and PVCC, and many of the components surrounding the controller including the feedback network and 0 0 0.2 0.4 0.6 0.8 1.0 current sense components. Locate the VCC/PVCC bypass DUTY CYCLE (VIN/VO) capacitors as close to the ISL6323 as possible. It is especially FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS important to locate the components associated with the feedback CURRENT FOR 2-PHASE CONVERTER circuit close to their respective controller pins, since they belong to Layout Considerations a high-impedance circuit loop, sensitive to EMI pick-up. MOSFETs switch very fast and efficiently. The speed with which A multi-layer printed circuit board is recommended. Figure 27 the current transitions from one device to another causes voltage shows the connections of the critical components for the spikes across the interconnecting impedances and parasitic converter. Note that capacitors CIN and COUT could each circuit elements. These voltage spikes can degrade efficiency, represent numerous physical capacitors. Dedicate one solid layer, radiate noise into the circuit and lead to device overvoltage stress. usually the one underneath the component side of the board, for a Careful component selection, layout, and placement minimizes ground plane and make all critical component ground connections these voltage spikes. Consider, as an example, the turnoff with vias to this layer. Dedicate another solid layer as a power transition of the upper PWM MOSFET. Prior to turnoff, the upper plane and break this plane into smaller islands of common voltage MOSFET was carrying channel current. During the turn-off, levels. Keep the metal runs from the PHASE terminal to output current stops flowing in the upper MOSFET and is picked up by inductors short. The power plane should support the input power the lower MOSFET. Any inductance in the switched current path and output power nodes. Use copper filled polygons on the top generates a large voltage spike during the switching interval. and bottom circuit layers for the phase nodes. Use the remaining Careful component selection, tight layout of the critical printed circuit layers for small signal wiring. components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using a ISL6323 controller. The power components are the most FN9278 Rev 5.00 Page 33 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI RFB C2 +12V +12V CC RC FB VSEN CIN R3_2 CBOOT CISOEMNP3+ BOOT1 CBOOT C3 R3_1CIN BOOT1 ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 RAPA CAPA R1_1 C1 LGATE1 APA LGATE1 PGND PWM1 R1_2 ISEN1- DVC ISEN1+ ISL6614 +12V +12V V_CORE +5V PVCC1_2 +12V VCC CFILTER VCC CFCILBTEOROT CIN CIN BOOT2 PVCC OFS BOOT2 CBULK CHF CBOOT CFILTER ROFS UGATE2 UGATE2 GND PHASE2 FS PHASE2 CPU RFS LOAD PWM2 R2_1 C2 C4 R4_1 LGATE2 RSET LGATE2 RSET R2_2 R4_2 VFIXEN ISEN2- SEL SVD ISEN2+ SVC RGND NC VID4 NC VID5 PWROK VDDPWRGD ISEN4+ GND ISEN4- PWM4 +12V ISL6323 +12V KEY HEAVY TRACE ON CIRCUIT PLANE LAYER PVCC_NB REN1 EN CFILTER CIN ISLAND ON POWER PLANE LAYER OFF CBOOT_NB ISLAND ON CIRCUIT PLANE LAYER ON REN2 BOOT_NB VIA CONNECTION TO GROUND PLANE UGATE_NB PHASE_NB V_NB R1_NB C1_NB CBULK CHF RED COMPONENTS: LGATE_NB R2_NB LOCATE CLOSE TO IC TO MINIMIZE CONNECTION PATH ISEN_NB- NB LOAD ISEN_NB+ BLUE COMPONENTS: COMP_NB LOCATE NEAR LOAD FB_NB RGND_NB (MINIMIZE CONNECTION PATH) RC_NB CC_NB GREEN COMPONENTS: NB LOCATE CLOSE TO SWITCHING TRANSISTORS C2_ RFB_NB (MINIMIZE CONNECTION PATH) FIGURE 28. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN9278 Rev 5.00 Page 34 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Routing UGATE, LGATE, and PHASE Traces Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” to 0.05”). Going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances. Current Sense Component Placement and Trace Routing One of the most critical aspects of the ISL6323 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the ISL6323 as possible. The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible. Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6323 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part. © Copyright Intersil Americas LLC 2007-2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9278 Rev 5.00 Page 35 of 36 May 17, 2011

ISL6323 Hybrid SVI/PVI Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4X 5.5 7.00 A B 44X 0.50 6 37 48 PIN #1 INDEX AREA 6 PIN 1 36 1 INDEX AREA 0 0 4. 30 ± 0 . 15 7. 25 12 (4X) 0.15 24 13 0.10M C A B TOP VIEW 48X 0 . 40± 0 . 1 4 0.23 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" 0.10C C 0 . 90 ± 0 . 1 BASE PLANE ( 6 . 80 TYP ) SEATING PLANE 0.08 C ( 4 . 30 ) SIDE VIEW ( 44X 0 . 5 ) C 0 . 2 REF 5 ( 48X 0 . 23 ) ( 48X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN9278 Rev 5.00 Page 36 of 36 May 17, 2011