DATASHEET ISL62771 FN8321 Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0 Rev 4.00 November 18, 2015 The ISL62771 is fully compliant with AMD Fusion SVI 2.0 and Features provides a complete solution for microprocessor and graphics processor core power. The ISL62771 controller supports two • Supports AMD SVI 2.0 serial data bus interface Voltage Regulators (VRs) with three integrated gate drivers. The - Serial VID clock frequency range 100kHz to 25MHz Core VR supports 2-, or 1-phase configurations while the • Dual output controller with integrated drivers Northbridge VR supports 1-phase operation. The two VRs share a • Precision voltage regulation serial control bus to communicate with the AMD CPU and achieve - 0.5% system accuracy over-temperature lower cost and smaller board area compared with two-chip solutions. - 0.5V to 1.55V in 6.25mV steps - Enhanced load line accuracy The PWM modulator is based on Intersil’s Robust Ripple Regulator R3™ Technology. Compared to traditional modulators, • Supports multiple current sensing methods the R3 modulator can automatically change switching frequency - Lossless inductor DCR current sensing for faster transient settling time during load transients and - Precision resistor current sensing improved light-load efficiency. • Programmable 1- or 2-phase for the core output The ISL62771 has several other key features. Both outputs • Adaptive body diode conduction time reduction support DCR current sensing with single NTC thermistor for DCR temperature compensation or accurate resistor current • Superior noise immunity and transient response sensing. Both outputs utilize remote voltage sense, adjustable • Output current and voltage telemetry switching frequency, OC protection and power-good. • Differential remote voltage sensing Applications • High efficiency across entire load range • AMD fusion CPU/GPU and APU core power • Programmable VID offset and droop on both outputs • Notebook computers • Programmable switching frequency for both outputs Related Literature • Excellent dynamic current balance between phases • Protection: OCP/WOC, OVP, PGOOD and thermal monitor •TB497, “Disabling the North Bridge Regulator on the ISL62771” • Small footprint 40 Ld 5x5 TQFN package - Pb-free (RoHS compliant) Core Performance 100 1.12 90 1.10 80 %) 70 VIN = 8V 1.08 ENCY ( 5600 VIN = 19V VIN = 12V (A)UT 11..0046 VIN = 8V FICI 40 VO 1.02 VIN = 12V F 30 E 20 1.00 VIN = 19V 10 VOUT CORE = 1.1V 0.98 VOUT CORE = 1.1V 0 0.96 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 IOUT (A) IOUT (A) FIGURE 1. EFFICIENCY vs LOAD FIGURE 2. VOUT vs LOAD FN8321 Rev 4.00 Page 1 of 35 November 18, 2015

ISL62771 Table of Contents Simplified Application Circuit for Mid-Power CPUs . . . . . . .4 CCM Switching Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . 20 Simplified Application Circuit for Low Power CPUs [1+1 Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Con-figuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Simplified Application Circuit for Low Power CPUs [1+1 VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Con-figuration]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 SVI Data Communication Protocol. . . . . . . . . . . . . . . . . . . . . 21 SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Dynamic Load Line Slope Trim. . . . . . . . . . . . . . . . . . . . . . . . 23 Dynamic Offset Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .11 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Undervoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Recommended Operating Conditions . . . . . . . . . . . . . . . . .11 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Thermal Monitor [NTC, NTC_NB]. . . . . . . . . . . . . . . . . . . . . . . 25 Fault Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .13 Interface Pin Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Key Component Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . 26 Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . .15 Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . 28 Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage Regulation and Load Line Implementation . . . . . . .16 Current Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Thermal Monitor Component Selection. . . . . . . . . . . . . . . . . 30 Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PCB Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Adaptive Body Diode Conduction Time Reduction . . . . . . . .19 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . .19 About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 FN8321 Rev 4.00 Page 2 of 35 November 18, 2015

ISL62771 Simplified Application Circuit for Mid-Power CPUs D E P D L D V B D A V N E VIN BOOT_NB UGATE_NB Ri VNB ISUMN_NB VNB PHASE_NB NTC Cn LGATE_NB NB_PH VNB ISUMP_NB NB_PH IMON_NB COMP_NB NTC_NB FB_NB VSEN_NB VR_HOT_L THERMAL INDICATOR VNB_SENSE PWROK ISL62771 SVT IMON µP SVD SVC NTC VDDIO COMP BOOT2 VIN FB UGATE2 PHASE2 VSEN VCORE_SENSE RTN LGATE2 PH2 VO2 VCORE PH1 ISEN1 BOOT1 VIN PH2 ISEN2 UGATE1 Ri PHASE1 VO1 ISUMN B N VO2 Cn NTC AD D_ D LGATE1 PH1 VO1 P O O D O O ISUMP N G G G P P 1 2 H H P P FIGURE 3. TYPICAL APPLICATION CIRCUIT USING DCR SENSING FN8321 Rev 4.00 Page 3 of 35 November 18, 2015

ISL62771 Simplified Application Circuit for Low Power CPUs [1+1 Configuration] D E P D L D V B D A V EN BOOT_NB VIN UGATE_NB Ri VNB NBN ISUMN_NB PHASE_NB Cn NTC LGATE_NB NBP NBN NBP ISUMP_NB IMON_NB COMP_NB NTC_NB FB_NB VSEN_NB VR_HOT THERMAL INDICATOR VNB_SENSE NTC PWROK SVT ISL62771 IMON µP SVD SVC *RESISTOR REQUIRED OR ISEN1 VDDIO WILL PULL HIGH IF LEFT OPEN AND DISABLE CHANNEL 1. BOOT2 OPEN 10k* ISEN1 UGATE2 OPEN +5V ISEN2 PHASE2 OPEN LGATE2 OPEN COMP BOOT1 VIN FB UGATE1 VSEN VCORE PHASE1 VCORE_SENSE RTN LGATE1 CoreP CoreN Ri CoreN ISUMN B N D _ Cn NTC A D D P O O D O O CoreP ISUMP N G G G P P FIGURE 4. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING FN8321 Rev 4.00 Page 4 of 35 November 18, 2015

ISL62771 Simplified Application Circuit for Low Power CPUs [1+1 Configuration] D E P D L D V B D A V EN BOOT_NB VIN UGATE_NB Ri VNB ISUMN_NB VNB PHASE_NB Cn NTC LGATE_NB NB_PH VNB NB_PH ISUMP_NB IMON_NB COMP_NB NTC_NB FB_NB VSEN_NB VR_HOT THERMAL INDICATOR VNB_SENSE NTC PWROK SVT IMON µP SVD SVC VDDIO ISL62771 *RESISTOR REQUIRED OR ISEN1 WILL PULL HIGH IF LEFT OPEN AND 10k* BOOT2 OPEN DISABLE CHANNEL 1. ISEN1 UGATE2 OPEN +5V ISEN2 PHASE2 OPEN LGATE2 OPEN COMP BOOT1 VIN FB UGATE1 VSEN VCORE PHASE1 VCORE_SENSE RTN LGATE1 PH VO Ri VO ISUMN B Cn NTC AD D_N D P O O D O O PH ISUMP N G G G P P FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING FN8321 Rev 4.00 Page 5 of 35 November 18, 2015

ISL62771 Block Diagram VSEN_NB BOOT_NB COMP_NB DRIVER UGATE_NB + +  PHASE_NB RTN + E/A _ FB_NB VR2 IDROOP_NB MODULATOR DRIVER LGATE_NB ISUMP_NB + CURRENT VDD _ SENSE ISUMN_NB PGOOD_NB OC FAULT OV FAULT NB_V VOLTAGE NTC_NB A/D TEMP T_MONITOR NTC MONITOR VR_HOT_L CORE_I IMON OFFSET CURRENT FREQ NB_I A/D IMON_NB SLEWRATE CONFIG IDROOP_NB ENABLE A/D IDROOP PWROK DAC2 DIGITAL D/A DAC1 SVC VDDP INTERFACE CORE_I SVD BOOT2 NB_I SVT TELEMETRY CORE_V DRIVER UGATE2 NB_V VDDIO PHASE2 COMP VSEN + RTN +  + VR1 DRIVER LGATE2 MODULATOR E/A _ FB BOOT1 IDROOP VOLTAGE DRIVER UGATE1 ISUMP + A/D CURRENT PHASE1 _ SENSE ISUMN CORE_V DRIVER LGATE1 ISEN2 CURRENT BALANCING ISEN1 OC FAULT PGOOD IBAL FAULT OV FAULT GND FIGURE 6. BLOCK DIAGRAM FN8321 Rev 4.00 Page 6 of 35 November 18, 2015

ISL62771 Pin Configuration ISL62771 (40 LD TQFN) TOP VIEW ISUMP_NB ISUMN_NB VSEN_NB FB_NB COMP_NB PGOOD_NB LGATE_NB PHASE_NB UGATE_NB BOOT_NB 40 39 38 37 36 35 34 33 32 31 NTC_NB 1 30 BOOT2 IMON_NB 2 29 UGATE2 SVC 3 28 PHASE2 VR_HOT_L 4 27 LGATE2 SVD 5 26 VDDP GND (BOTTOM PAD) VDDIO 6 25 VDD SVT 7 24 LGATE1 ENABLE 8 23 PHASE1 PWROK 9 22 UGATE1 IMON 10 21 BOOT1 11 12 13 14 15 16 17 18 19 20 C 2 1 P N N N B P D T N N M M E T F M O N ISE ISE ISU ISU VS R CO PGO Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 NTC_NB Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature. 2 IMON_NB Northbridge output current monitor. A current proportional to the Northbridge VR output current is sourced from this pin. 3 SVC Serial VID clock input from the CPU processor master device. 4 VR_HOT_L Thermal indicator signal to AMD CPU. Thermal overload open-drain output indicator active LOW. 5 SVD Serial VID data bidirectional signal from the CPU processor master device to the VR. 6 VDDIO VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller IC for this processor I/O signal level. 7 SVT Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly complete signal provided on from this pin. 8 ENABLE Enable input. A high level logic on this pin enables both VRs. 9 PWROK System power-good input. When this pin is high, the SVI 2 interface is active and the I2C protocol is running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must be low prior to the ISL62771 PGOOD output going high per the AMD SVI 2.0 Controller Guidelines. 10 IMON Core output current monitor. A current proportional to the Core VR output current is sourced from this pin. 11 NTC Thermistor input to VR_HOT_L circuit to monitor Core VR temperature. 12 ISEN2 Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller disables Channel 2 and the Core VR runs in single-phase mode. FN8321 Rev 4.00 Page 7 of 35 November 18, 2015

ISL62771 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 13 ISEN1 Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is shut down. 14 ISUMP Noninverting input of the transconductance amplifier for current monitor and load line of Core output. 15 ISUMN Inverting input of the transconductance amplifier for current monitor and load line of Core output. 16 VSEN Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die. 17 RTN Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the microprocessor die. 18 FB Output voltage feedback to the inverting input of the Core controller error amplifier. 19 COMP Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage. 20 PGOOD Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull-up externally to VDD or 3.3V through a resistor. 21 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged, through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1 pin drops below VDDP minus the voltage dropped across the internal boot diode. 22 UGATE1 Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate of the Phase 1 high-side MOSFET(s). 23 PHASE1 Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of Phase1. 24 LGATE1 Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate of the Phase 1 low-side MOSFET(s). 25 VDD 5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high quality, X7R dielectric MLCC capacitor is recommended. 26 VDDP Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended. 27 LGATE2 Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate of the Phase2 low-side MOSFET(s). 28 PHASE2 Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of Phase 2. 29 UGATE2 Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate of the Phase 2 high-side MOSFET(s). 30 BOOT2 Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops below VDDP minus the voltage dropped across the internal boot diode. 31 BOOT_NB Boot connection of the Northbridge VR. Connect an MLCC capacitor across the BOOT1_NB and the PHASE_NB pins. The boot capacitor is charged, through an internal boot diode connected from the VDDP pin to the BOOT_NB pin, each time the PHASE_NB pin drops below VDDP minus the voltage dropped across the internal boot diode. 32 UGATE_NB High-side MOSFET gate driver of the Northbridge VR. Connect the UGATE_NB pin to the gate of the high-side MOSFET(s) of the Northbridge VR. 33 PHASE_NB Phase connection of the Northbridge VR. Current return path for the high-side MOSFET gate driver of the floating internal driver. Connect the PHASE_NB pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of the Northbridge VR. 34 LGATE_NB Low-side MOSFET gate driver of the Northbridge VR. Connect the LGATE_NB pin to the gate of the low-side MOSFET(s) of the Northbridge VR. 35 PGOOD_NB Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage. Pull-up externally to VDDP or 3.3V through a resistor. FN8321 Rev 4.00 Page 8 of 35 November 18, 2015

ISL62771 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 36 COMP_NB Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset voltage and is used to set the switching frequency for the Core VR and Northbridge VR. 37 FB_NB Output voltage feedback to the inverting input of the Northbridge controller error amplifier. 38 VSEN_NB Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor die. 39 ISUMN_NB Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR. 40 ISUMP_NB Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR. GND (Bottom Pad) Signal common of the IC. All signals are referenced to the GND pin. Ordering Information PART NUMBER PART TEMP. PACKAGE PKG. (Notes1, 2, 3) MARKING RANGE (°C) (RoHS Compliant) DWG. # ISL62771HRTZ 62771 HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5 ISL62771IRTZ 62771 IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62771. For more information on MSL please see tech brief TB363. FN8321 Rev 4.00 Page 9 of 35 November 18, 2015

ISL62771 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V 40 Ld TQFN Package (Notes4, 5) . . . . . . . 33 3 Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . .-0.3V to +7V (DC) Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C UGATE Voltage (UGATE) . . . . . . . . . .PHASE - 0.3V (DC) to BOOTPHASE - 5V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 . . . . . . . . . . . . . . . . . (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V Recommended Operating Conditions All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V) Open-Drain Outputs, PGOOD, PGOOD_NB, VR_HOT_L. . . . . . -0.3V to +7V Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V Ambient Temperature HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C Junction Temperature HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +125°C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +100°C. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note6) TYP (Note6) UNIT INPUT POWER SUPPLY +5V Supply Current IVDD ENABLE = 1V 8 11 mA ENABLE = 0V 1 µA POWER-ON-RESET THRESHOLDS VDD POR Threshold VDD_PORr VDD rising 4.35 4.50 V VDD_PORf VDD falling 4.00 4.15 V SYSTEM AND REFERENCES System Accuracy HRTZ No load; closed loop, active mode range, -0.5 +0.5 % %Error (VOUT) VID= 0.75V to 1.55V, VID = 0.25V to 0.74375V -10 +10 mV IRTZ No load; closed loop, active mode range, -0.8 +0.8 % %Error (VOUT) VID= 0.75V to 1.55V VID = 0.25V to 0.74375V -12 +12 mV Maximum Output Voltage VOUT(max) VID = [00000000] 1.55 V Minimum Output Voltage VOUT(min) VID = [11111111] 0.0 V CHANNEL FREQUENCY Nominal Channel Frequency fSW(nom) 280 300 320 kHz AMPLIFIERS Current-Sense Amplifier Input Offset HRTZ IFB = 0A -0.15 +0.15 mV IRTZ IFB = 0A -0.20 +0.20 mV Error Amp DC Gain Av0 119 dB Error Amp Gain-Bandwidth Product GBW CL = 20pF 17 MHz ISEN Input Bias Current 20 nA FN8321 Rev 4.00 Page 10 of 35 November 18, 2015

ISL62771 Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note6) TYP (Note6) UNIT POWER-GOOD (PGOOD, PGOOD_NB) AND PROTECTION MONITORS PGOOD Low Voltage VOL IPGOOD = 4mA 0.4 V PGOOD Leakage Current IOH PGOOD = 3.3V -1 1 µA PWROK High Threshold 750 mV VR_HOT_L Pull-Down 11 Ω PWROK Leakage Current 1 µA VR_HOT_L Leakage Current 1 µA GATE DRIVER UGATE Pull-Up Resistance RUGPU 200mA source current 1.0 1.5 Ω UGATE Source Current IUGSRC UGATE - PHASE = 2.5V 2.0 A UGATE Sink Resistance RUGPD 250mA sink current 1.0 1.5 Ω UGATE Sink Current IUGSNK UGATE - PHASE = 2.5V 2.0 A LGATE Pull-Up Resistance RLGPU 250mA source current 1.0 1.5 Ω LGATE Source Current ILGSRC LGATE - VSSP = 2.5V 2.0 A LGATE Sink Resistance RLGPD 250mA sink current 0.5 0.9 Ω LGATE Sink Current ILGSNK LGATE - VSSP = 2.5V 4.0 A UGATE to LGATE Dead Time tUGFLGR UGATE falling to LGATE rising, no load 23 ns LGATE to UGATE Dead Time tLGFUGR LGATE falling to UGATE rising, no load 28 ns PROTECTION Overvoltage Threshold OVH VSEN rising above setpoint for >1µs 275 325 375 mV Undervoltage Threshold OVH VSEN falls below setpoint for >1µs 275 325 375 mV Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 9 mV Way Overcurrent Trip Threshold IMONxWOC All states, IDROOP = 60µA, RIMON = 135kΩ 15 µA [IMONx Current Based Detection] Overcurrent Trip Threshold VIMONx_OCP All states, IDROOP = 45µA, 1.485 1.510 1.535 V [IMONx Voltage Based Detection] IIMONx = 11.25µA, RIMON = 135kΩ LOGIC THRESHOLDS ENABLE Input Low VIL 1 V ENABLE Input High VIH HRTZ 1.6 V VIH IRTZ 1.65 V ENABLE Leakage Current IENABLE ENABLE = 0V -1 0 1 µA ENABLE = 1V 18 35 µA SVT Impedance 50 Ω SVC, SVD Input Low VIL % of VDDIO 30 % SVC, SVD Input High VIH % of VDDIO 70 % SVC, SVD Leakage ENABLE = 0V, SVC, SVD = 0V and 1V -1 1 µA ENABLE = 1V, SVC, SVD = 1V -5 1 µA ENABLE = 1V, SVC, SVD = 0V -35 -20 -5 µA THERMAL MONITOR NTC Source Current NTC = 0.6V 27 30 33 µA NTC Thermal Warning Voltage 600 640 680 mV NTC Thermal Warning Voltage 20 mV Hysteresis NTC Thermal Shutdown Voltage 530 580 630 mV FN8321 Rev 4.00 Page 11 of 35 November 18, 2015

ISL62771 Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note6) TYP (Note6) UNIT SLEW RATE VID-on-the-Fly Slew Rate 8 10 12 mV/µs Soft-Start Slew Rate 10 mV/µs NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Gate Driver Timing Diagram PWM tLGFUGR tFU tRU UGATE 1V LGATE 1V tRL tFL tUGFLGR FIGURE 7. GATE DRIVER TIMING DIAGRAM FN8321 Rev 4.00 Page 12 of 35 November 18, 2015

ISL62771 Theory of Operation VW Multiphase R3™ Modulator VCRM HYSTERETIC WINDOW The ISL62771 is a multiphase regulator implementing two voltage regulators, CORE VR and Northbridge (NB) VR, on one chip COMP controlled by AMD’s SVI2 protocol. The CORE VR can be programmed for 1- or 2-phase operation. The Northbridge VR only MASTER CLOCK supports 1-phase operation. Both regulators use the Intersil patented R3™ (Robust Ripple Regulator) modulator. The R3™ CLOCK1 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. PWM1 Figure8 conceptually shows the multiphase R3™ modulator circuit and Figure9 shows the operation principles. CLOCK2 PWM2 VW MASTER CLOCK CIRCUIT MASTER MASTER COMP CLOCK PHASE CLOCK1 CLOCK3 CLOCK VCRM SEQUENCER CLOCK2 CLOCK3 PWM3 GMVO CRM VW SLAVE CIRCUIT 1 VW CLOCK1 S Q PWM1 PHASE1 L1 VO R IL1 CO VCRS2 VCRS3 VCRS1 VCRS1 GM FIGURE 9. R3™ MODULATOR OPERATION PRINCIPLES IN CRS1 STEADY STATE SLAVE CIRCUIT 2 VW CLOCK2 RS Q PWM2 PHASE2 L2 Emaicmhi cssla tvhee c iinrcduuictt hoar sri pitps loew cnu rrriepnptl.e A c agpma acimtopr lCifries,r wcohnovseer tvso ltthaeg e IL2 inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the VCRS2 GM clock signal and the current source charges Crs. When Crs CRS2 voltage VCrs hits VW, the slave circuit turns off the PWM pulse SLAVE CIRCUIT 3 and the current source discharges Crs. VW CLOCK3 S Q PWM3 PHASE3 L3 Since the controller works with Vcrs, which are large amplitude R and noise-free synthesized signals, it achieves lower phase jitter IL3 than conventional hysteretic mode and fixed PWM mode VCRS3 GM controllers. Unlike conventional hysteretic mode converters, the CRS3 error amplifier allows the ISL62771 to maintain a 0.5% output voltage accuracy. FIGURE 8. R3™ MODULATOR CIRCUIT Figure10 shows the operation principles during load insertion response. The COMP voltage rises during load insertion, Inside the IC, the modulator uses the master clock circuit to generating the master clock signal more quickly, so the PWM generate the clocks for the slave circuits. The modulator pulses turn on earlier, increasing the effective switching discharges the ripple capacitor Crm with a current source equal frequency. This allows for higher control loop bandwidth than to gmVo, where gm is a gain factor. Crm voltage VCRM is a conventional fixed frequency PWM controllers. The VW voltage sawtooth waveform traversing between the VW and COMP rises as the COMP voltage rises, making the PWM pulses wider. voltages. It resets to VW when it hits COMP and generates a During load release response, the COMP voltage falls. It takes one-shot master clock signal. A phase sequencer distributes the the master clock circuit longer to generate the next master clock master clock signal to the slave circuits. In this example, the signal so the PWM pulse is held off until needed. The VW voltage CORE VR is in 3-phase mode, the master clock signal is falls as the COMP voltage falls, reducing the current PWM pulse distributed to the three phases and the Clock 1~3 signals will be width. This kind of behavior gives the ISL62771 excellent 120° out-of-phase. If the Core VR is in 2-phase mode, the master response speed. clock signal is distributed to Phases 1 and 2 and the Clock1 and Clock2 signals will be 180° out-of-phase. If the Core VR is in The fact that all the phases share the same VW window voltage, 1-phase mode, the master clock signal will be distributed to also ensures excellent dynamic current balance among phases. Phase 1 only and be the Clock1 signal. FN8321 Rev 4.00 Page 13 of 35 November 18, 2015

ISL62771 Figure12 shows the operation principle in diode emulation mode VW at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size and therefore is the same, making the inductor COMP current triangle the same in the three cases. The ISL62771 clamps VCRM the ripple capacitor voltage VCRS in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit VCRS, naturally stretching the switching period. The inductor current MASTER triangles move farther apart such that the inductor current CLOCK average value is equal to the load current. The reduced switching CLOCK1 frequency helps increase light-load efficiency. PWM1 CCM/DCM CLOCK2 BOUNDARY VW PWM2 V CRS CLOCK3 PWM3 IL VW LIGHT DCM VW V CRS VCRS1 VCRS3 IL VCRS2 DEEP DCM FIGURE 10. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD VW V INSERTION RESPONSE CRS Diode Emulation and Period Stretching The ISL62771 can operate in Diode Emulation (DE) mode to IL improve light-load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source-to-drain and FIGURE 12. PERIOD STRETCHING does not allow reverse current, thus emulating a diode. Figure11 shows that when LGATE is on, the low-side MOSFET carries current, Channel Configuration creating negative voltage on the phase node due to the voltage drop across the ON-resistance. The ISL62771 monitors the current Individual PWM channels of the Core VR can be disabled by by monitoring the phase node voltage. It turns off LGATE when the connecting the ISENx pin of the channel not required to +5V. For phase node voltage reaches zero to prevent the inductor current example, placing the controller in a 1+1 configuration as shown from reversing the direction and creating unnecessary power loss. in Figure3 on page3 requires ISEN2 of the Core VR to be tied to +5V. This disables Channel 2 of the Core VR. ISEN1 must be tied through a 10kΩ resistor to GND to prevent this pin from pulling high and disabling the channel. Connecting ISEN1 to +5V will disable the Core VR output. PHASE Power-On Reset UGATE Before the controller has sufficient bias to guarantee proper operation, the ISL62771 requires a +5V input supply tied to VDD LGATE and VDDP to exceed the VDD rising Power-On Reset (POR) threshold. Once this threshold is reached or exceeded, the ISL62771 has enough bias to check the state of the SVI inputs IL once ENABLE is taken high. Hysteresis between the rising and the falling thresholds assure the ISL62771 does not inadvertently turn off unless the bias voltage drops substantially FIGURE 11. DIODE EMULATION (see “Electrical Specifications” on page10). Note that VIN must If the load current is light enough (see Figure11), the inductor be present for the controller to drive the output voltage. current reaches and stays at zero before the next phase node pulse and the regulator is in Discontinuous Conduction Mode (DCM). If the load current is heavy enough, the inductor current will never reach 0A and the regulator is in CCM, although the controller is in DE mode. FN8321 Rev 4.00 Page 14 of 35 November 18, 2015

ISL62771 1 2 3 4 5 6 7 8 VDD SVC SVD VOTF SVT Telemetry Telemetry ENABLE PWROK METAL_VID VCORE/ VCORE_NB V_SVI PGOOD & PGO OD_NB Interval 1 to 2: ISL62771 waits to POR. Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code. Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level. Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation. Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL62771 is prepared for SVI commands. Interval 6 to 7: SVC and SVD data lines communicate change in VID code. Interval 7 to 8: ISL62771 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes. Post 8: Telemetry is clocked out of the ISL62771. FIGURE 13. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP Start-Up Timing Voltage Regulation and Load Line Implementation With the controller's VDD POR threshold exceeded and VIN voltage present, the start-up sequence begins when ENABLE exceeds the After the soft-start sequence, the ISL62771 regulates the output logic high threshold. Figure14 shows the typical start-up timing of voltages to the pre-PWROK metal VID programmed, see Table5 Core and Northbridge VRs. The ISL62771 uses a digital soft-start on page19. The ISL62771 controls the no load output voltage to to ramp up the DAC to the voltage programmed by the Metal VID. an accuracy of ±0.5% over the range of 0.75V to 1.55V. A PGOOD is asserted high at the end of the ramp-up. Similar results differential amplifier allows voltage sensing for precise voltage occur if ENABLE is tied to VDD, with the soft-start sequence regulation at the microprocessor die. starting 8ms after VDD crosses the POR threshold. RDROOP VDD + - VCCSENSE VDROOP SLEW RATE FB ENABLE VR LOCAL VO MetalVID IDROOP CATCH RESISTOR VID COMMAND VOLTAGE 8ms + SVC E/A DAC COMP - DAC SVD SVID[7:0] VDAC + PGOOD RTN + VSSSENSE PWROK INTERNAL TO IC X 1 VSS - CATCH RESISTOR VIN FIGURE 14. TYPICAL SOFT-START WAVEFORMS FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION FN8321 Rev 4.00 Page 15 of 35 November 18, 2015

ISL62771 As the load current increases from zero, the output voltage to the RTN pin. These resistors, typically 10Ω~100Ω, provide voltage droops from the VID programmed value by an amount feedback if the system is powered up without a processor installed. proportional to the load current, to achieve the load line. Phase Current Balancing The ISL62771 can sense the inductor current through the intrinsic DC Resistance (DCR) of the inductors, as shown in Figures3 and 5, or through resistors in series with the inductors aresp srheosewnnt sin t hFeig tuorteal4 i.n Idnu bcotothr cmurertehnotd. sA,n c aapmapcliitfoier rC cno vnovletartgse C n INTTEOR INCAL L2 Rdcr2 Rpcb2 VO PHASE2 voltage into an internal current source with the gain set by Risen resistor Ri, see Equation1. This ISUM current is used for load line ISEN2 IL2 iomveprlceumrreenntta ptiroonte, cctuirorne.nt monitoring on the IMON pins and Cisen L1 Rdcr1 Rpcb1 PHASE1 Isum = V---R--C----n-- (EQ. 1) ISEN1 Risen IL1 i Cisen Figure15 shows the load line implementation. The ISL62771 drives a current source (Idroop) out of the FB pin, as described by FIGURE 16. CURRENT BALANCING CIRCUIT Equation2. The ISL62771 monitors individual phase average current by Idroop = 54---xIsum = 54---xV---R--C---i-n-- (EQ. 2) mrecoonmitomrienngd tehde cISuErrNe1n ta bnadl aISnEcNin2g vcoirlctaugite fso. rF DigCuRre s1e6n ssihnogw. Esa tchhe phase node voltage is averaged by a low-pass filter consisting of When using inductor DCR current sensing, a single NTC element Risen and Cisen and is presented to the corresponding ISEN pin. is used to compensate the positive temperature coefficient of the Risen should be routed to the inductor phase-node pad in order to copper winding, thus sustaining the load line accuracy with eliminate the effect of phase node parasitic PCB DCR. reduced cost. Equations6 and 7 give the ISEN pin voltages: Idroop flows through resistor Rdroop and creates a voltage drop as V = R +R I shown in Equation3. ISEN1 dcr1 pcb1 L1 (EQ. 6) Vdroop = RdroopIdroop (EQ. 3) VISEN2 = Rdcr2+Rpcb2IL2 (EQ. 7) Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can change the load line slope. Where Rdcr1 and Rdcr2 are inductor DCR; Rpcb1 and Rpcb2 are Since Isum sets the overcurrent protection level, it is parasitic PCB DCR between the inductor output side pad and the recommended to first scale Isum based on OCP requirement, output voltage rail; and IL1 and IL2 are inductor average currents. then select an appropriate Rdroop value to obtain the desired load line slope. The ISL62771 adjusts the phase pulse-width relative to the other phases to make VISEN1=VISEN2, thus to achieve IL1=IL2, when Differential Sensing Rdcr1=Rdcr2and Rpcb1=Rpcb2. Figure15 also shows the differential voltage sensing scheme. Using the same components for L1 and L2 provides a good VCCSENSE and VSSSENSE are the remote voltage sensing signals match of Rdcr1 and Rdcr2. Board layout determines Rpcb1 and from the processor die. A unity gain differential amplifier senses Rpcb2. It is recommended to have a symmetrical layout for the the VSSSENSE voltage and adds it to the DAC output. The error power delivery path between each inductor and the output amplifier regulates the inverting and noninverting input voltages to voltage rail, such that Rpcb1=Rpcb2. be equal as shown in Equation4: VCCSENSE+Vdroop = VDAC+VSSSENSE (EQ. 4) PHASE2 V2p L2 Rdcr2 Rpcb2 Vo Risen ISEN2 IL2 V2n Rewriting Equation4 and substituting Equation3 gives Risen Equation5. The exact equation required for load line Cisen Risen implementation. INTTEOR INCAL PHASE1 V1p L1 Rdcr1 Rpcb1 VCCSENSE–VSSSENSE = VDAC–RdroopIdroop (EQ. 5) ISEN1 Risen IL1 V1n Risen The VCCSENSE and VSSSENSE signals come from the processor die. Cisen Risen The feedback is an open circuit in the absence of the processor. As Figure15 shows, it is recommended to add a “catch” resistor to FIGURE 17. DIFFERENTIAL-SENSING CURRENT BALANCING feed the VR local output voltage back to the compensator and to CIRCUIT add another “catch” resistor to connect the VR local output ground FN8321 Rev 4.00 Page 16 of 35 November 18, 2015

ISL62771 Sometimes it is difficult to implement symmetrical layout. For the circuit shown in Figure16, asymmetric layout causes REP RATE = 10kHz different Rpcb1 and Rpcb2 values, thus creating a current imbalance. Figure17 shows a differential sensing current balancing circuit recommended for ISL62771. The current sensing traces should be routed to the inductor pads so they only pick up the inductor DCR voltage. Each ISEN pin sees the average voltage of two sources: its own, phase inductor phase-node pad and the other phase inductor output side pad. Equations8 and 9 give the ISEN pin voltages: VISEN1 = V1p+V2n (EQ. 8) VISEN2 = V1n+V2p (EQ. 9) REP RATE = 25kHz The ISL62771 will make VISEN1 = VISEN2 as shown in Equation10: V1p+V2n = V1n+V2p (EQ. 10) Rewriting Equation10 gives Equation11: V1p–V1n = V2p–V2n (EQ. 11) Therefore: R I = R I dcr1 L1 dcr2 L2 (EQ. 12) REP RATE = 50kHz Current balancing (IL1=IL2) is achieved when Rdcr1=Rdcr2. Rpcb1and Rpcb2 do not have any effect. Since the slave ripple capacitor voltages mimic the inductor currents, the R3™ modulator can naturally achieve excellent current balancing during steady state and dynamic operations. Figure18 shows the current balancing performance of the evaluation board with load transient of 12A/51A at different rep rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current well at a low REP RATE = 100kHz repetition rate, but cannot keep up when the repetition rate gets into the hundred-kHz range, where it is out of the control loop bandwidth. The controller achieves excellent current balancing in all cases installed. REP RATE = 200kHz FIGURE 18. CURRENT BALANCING DURING DYNAMIC OPERATION. CH1: IL1, CH2: ILOAD, CH3: IL2, CH4: IL3 FN8321 Rev 4.00 Page 17 of 35 November 18, 2015

ISL62771 Modes of Operation VID transitions, the output voltage decays to the lower VID value at the slew rate determined by the load. TABLE 1. CORE VR MODES OF OPERATION PSL0_L IMON OCP The R3™ modulator intrinsically has voltage feed-forward. The AND THRESHOLD output voltage is insensitive to a fast slew rate input voltage CONFIG. ISEN2 PSI1_L MODE (V) change. 2-phase Core To Power 11 2-phase CCM 1.5 Adaptive Body Diode Conduction Time VR Config. Stage 01 1-phase DE Reduction 00 1-phase DE In DCM, the controller turns off the low-side MOSFET when the 1-phase Core Tied to 5V 11 1-phase CCM 1.5 inductor current approaches zero. During on-time of the low-side VR Config. 01 1-phase DE MOSFET, phase voltage is negative and the amount is the 00 1-phase DE MOSFET rDS(ON) voltage drop, which is proportional to the inductor current. A phase comparator inside the controller The Core VR can be configured for 2- or 1-phase operation. monitors the phase voltage during on-time of the low-side Table1 shows Core VR configurations and operational modes, MOSFET and compares it with a threshold to determine the zero programmed by the ISEN2 pin status and the PSL0_L and crossing point of the inductor current. If the inductor current has PSL1_L commands via the SVI 2 interface, see Table8 on not reached zero when the low-side MOSFET turns off, it will flow page22. through the low-side MOSFET body diode, causing the phase For a 1-phase configuration, tie the ISEN2 pin to 5V. In this node to have a larger voltage drop until it decays to zero. If the configuration, only Phase 1 is active. inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it will flow through the For 2-phase configurations, the Core VR operates in 2-phase CCM high-side MOSFET body diode, causing the phase node to have a with PSI0_L and PSI_L both high. If PSI0_L is taken low via the spike until it decays to zero. The controller continues monitoring SVI 2 interface, the Core VR sheds Phase 2 and the Core VR the phase voltage after turning off the low-side MOSFET. To enters 1-phase DE mode. When both PSI0_L and PSI1_L are minimize the body diode-related loss, the controller also adjusts taken low, the Core VR continues to operate in the 1-phase DE the phase comparator threshold voltage accordingly in iterative mode. steps such that the low-side MOSFET body diode conducts for In a 1-phase configuration, the Core VR operates in 1-phase CCM approximately 40ns. and enters 1-phase DE when PSI0_L is taken low and continues Resistor Configuration Options to operate in this mode when both PSI0_l and PSI1_L are taken low. The ISL62771 uses the COMP and COMP_NB pins to configure The Core VR can be disabled completely by connecting ISEN1 to some functionality within the IC. Resistors from these pins to GND +5V. are read during the first portion of the soft-start sequence. The following sections outline how to select the resistor values for each ISL62771 Northbridge VR operates in 1-phase CCM. of these pins to correctly program the output voltage offset of each Table2 shows the Northbridge VR operational modes, which are output and switching frequency used for both VRs. programmed by the PSI0_L and PSI1_L bits of the SVI 2 command. VR Offset Programming TABLE 2. NORTHBRIDGE VR MODES OF OPERATION A positive or negative offset is programmed for the Core VR using a resistor to ground from the COMP pin and the Northbridge in a PSL0_L and IMON OCP CONFIG. PSI1_L MODE THRESHOLD similar manner from the COMP_NB pin. Table3 provides the resistor value to select the desired output voltage offset. The 1% 1-phase NB VR 11 1-phase CCM 1.5V tolerance resistor value shown in the table must be used to Configuration 01 1-phase DE program the corresponding Core or NB output voltage offset. The 00 1-phase DE MIN and MAX tolerance values provide margin to insure the 1% tolerance resistor will be read correctly. The Northbridge VR operates in 1-phase CCM and enters 1-phase DE when PSI0_L goes low and remains in this mode of operation when both PSI0_L and PSI1_L are low. The Core and Northbridge VRs have an overcurrent threshold of 1.5V on IMON and IMON_NB respectively and this level does not vary based on channel configuration. See “Overcurrent” on page23 for more details. Dynamic Operation Core VR and Northbridge VR behave the same during dynamic operation. The controller responds to VID-on-the-fly changes by slewing to the new voltage at a fixed slew rate. During negative FN8321 Rev 4.00 Page 18 of 35 November 18, 2015

ISL62771 TABLE 3. COMP AND COMP_NB OUTPUT VOLTAGE OFFSET AMD Serial VID Interface 2.0 SELECTION The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the RESISTOR VALUE [kΩ] AMD processor to directly control the Core and Northbridge COMP COMP_NB voltage reference levels within the ISL62771. Once the PWROK MIN 1% TOLERANCE MAX VCORE OFFSET OFFSET signal goes high, the IC begins monitoring the SVC and SVD pins TOLERANCE VALUE TOLERANCE [mV] [mV] for instructions. The ISL62771 uses a Digital-to-Analog Converter 5.54 5.62 5.70 -43.75 18.75 (DAC) to generate a reference voltage based on the decoded SVI value. See Figure13 for a simple SVI interface timing diagram. 7.76 7.87 7.98 -37.5 31.25 11.33 11.5 11.67 -31.25 43.76 Pre-PWROK Metal VID 16.65 16.9 17.15 -25 50 Typical motherboard start-up begins with the controller decoding the SVC and SVD inputs to determine the pre-PWROK Metal VID 19.3 19.6 19.89 -18.75 37.5 setting (see Table5). Once the ENABLE input exceeds the rising 24.53 24.9 25.27 -12.5 25 threshold, the ISL62771 decodes and locks the decoded value into an on-board hold register. 33.49 34.0 34.51 -6.25 12.5 TABLE 5. PRE-PWROK METAL VID CODES 40.58 41.2 41.81 6.25 0 OUTPUT VOLTAGE 51.52 52.3 53.08 18.75 18.75 SVC SVD (V) 72.10 73.2 74.29 31.25 31.25 0 0 1.1 93.87 95.3 96.72 43.76 43.76 0 1 1.0 119.19 121 112.81 50 50 1 0 0.9 151.69 154 156.31 37.5 37.5 1 1 0.8 179.27 182 184.73 25 25 The internal DAC circuitry begins to ramp Core and Northbridge 206.85 210 213.15 12.5 12.5 VRs to the decoded pre-PWROK Metal VID output level. The OPEN 0 0 digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of 10mV/µs. The controlled ramp CCM Switching Frequency of all output voltage planes reduces inrush current during the The Core and Northbridge VR switching frequency is set by the soft-start interval. At the end of the soft-start interval, the PGOOD programming resistor on COMP_NB. When the ISL62771 is in and PGOOD_NB outputs transition high, indicating both output Continuous Conduction Mode (CCM), the switching frequency is planes are within regulation limits. not absolutely constant due to the nature of the R3™ modulator. If the ENABLE input falls below the enable falling threshold, the As explained in the “Multiphase R3™ Modulator” on page13, the ISL62771 tri-states both outputs. PGOOD and PGOOD_NB are effective switching frequency increases during load insertion and pulled low with the loss of ENABLE. The Core and Northbridge VR decreases during load release to achieve fast response. Thus, the output voltages decay, based on output capacitance and load switching frequency is relatively constant at steady state. leakage resistance. If bias to VDD falls below the POR level, the Variation is expected when the power stage condition, such as ISL62771 responds in the manner previously described. Once input voltage, output voltage, load, etc. changes. The variation is VDD and ENABLE rise above their respective rising thresholds, usually less than 10% and does not have any significant effect on the internal DAC circuitry reacquires a pre-PWROK metal VID output voltage ripple magnitude. Table4 defines the switching code and the controller soft-starts. frequency based on the resistor value used to program the COMP_NB pin. Use the previous table related to COMP_NB to SVI Interface Active determine the correct resistor value in these ranges to program Once the Core and Northbridge VRs have successfully the desired output offset and switching frequency configuration. soft-started and PGOOD and PGOOD_NB signals transition high, TABLE 4. SWITCHING FREQUENCY SELECTION PWROK can be asserted externally to the ISL62771. Once PWROK is asserted to the IC, SVI instructions can begin as the FREQUENCY COMP_NB RANGE controller actively monitors the SVI interface. Details of the SVI [kHz] [kΩ] Bus protocol are provided in the “AMD Serial VID Interface 2.0 300 57.6 to OPEN (SVI2) Specification”. See AMD publication #48022. 400 5.62 to 41.2 Once a VID change command is received, the ISL62771 decodes the information to determine which VR is affected and the VID The controller monitors SVI commands to determine when to target is determined by the byte combinations in Table6. The enter power-saving mode, implement dynamic VID changes and internal DAC circuitry steps the output voltage of the VR shut down individual outputs. commanded to the new VID level. During this time, one or more of the VR outputs could be targeted. In the event either VR is FN8321 Rev 4.00 Page 19 of 35 November 18, 2015

ISL62771 commanded to power-off by serial VID commands, the PGOOD new VID target at the fixed slew rate of 10mV/µs. Once the DAC signal remains asserted. ramps to the new VID code, a VID-on-the-Fly Complete (VOTFC) request is sent on the SVI lines. If the PWROK input is deasserted, then the controller steps both the Core and the Northbridge VRs back to the stored pre-PWROK When the VID codes are lower than the current VID level, the metal VID level in the holding register from initial soft-start. No ISL62771 checks the state of power state bits in the SVI attempt is made to read the SVC and SVD inputs during this time. command. If power state bits are not active, the controller begins If PWROK is reasserted, then the ISL62771 SVI interface waits stepping the regulator output to the new VID target. If the power for instructions. state bits are active, the controller allows the output voltage to decay and slowly steps the DAC down with the natural decay of If ENABLE goes low during normal operation, all external the output. This allows the controller to quickly recover and move MOSFETs are tri-stated and both PGOOD and PGOOD_NB are to a high VID code if commanded. The controller issues a VOTFC pulled low. This event clears the pre-PWROK metal VID code and request on the SVI lines once the SVI command is decoded and forces the controller to check SVC and SVD upon restart, storing prior to reaching the final output voltage. the pre-PWROK metal VID code found on restart. VOTFC requests do not take priority over telemetry per the AMD A POR event on VCC during normal operation shuts down both SVI 2 specification. regulators and both PGOOD outputs are pulled low. The pre-PWROK metal VID code is not retained. Loss of VIN during SVI Data Communication Protocol operation will typically cause the controller to enter a fault The SVI WIRE protocol is based on the I2C bus concept. Three condition on one or both outputs. The controller will shut down wires [serial clock (SVC) and serial data (SVD) and telemetry both Core and Northbridge VRs and latch off. The pre-PWROK (SVT)], carry information between the AMD processor (master) metal VID code is not retained during the process of cycling and VR controller (slave) on the bus. The master initiates and ENABLE to reset the fault latch and restart the controller. terminates SVI transactions and drives the clock, SVC, during a VID-on-the-Fly Transition transaction. The AMD processor is always the master and the voltage regulators are the slaves. The slave receives the SVI Once PWROK is high, the ISL62771 detects this flag and begins transactions and acts accordingly. Mobile SVI WIRE protocol monitoring the SVC and SVD pins for SVI instructions. The timing is based on high-speed mode I2C. See AMD publication microprocessor follows the protocol outlined in the following #48022 for additional details. sections to send instructions for VID-on-the-fly transitions. The ISL62771 decodes the instruction and acknowledges the new VID code. For VID codes higher than the current VID level, the ISL62771 begins stepping the commanded VR outputs to the TABLE 6. SERIAL VID CODES SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) 0000_0000 1.55000 0010_0000 1.35000 0100_0000 1.15000 0110_0000 0.95000 0000_0001 1.54375 0010_0001 1.34375 0100_0001 1.14375 0110_0001 0.94375 0000_0010 1.53750 0010_0010 1.33750 0100_0010 1.13750 0110_0010 0.93750 0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125 0000_0100 1.52500 0010_0100 1.32500 0100_0100 1.12500 0110_0100 0.92500 0000_0101 1.51875 0010_0101 1.31875 0100_0101 1.11875 0110_0101 0.91875 0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250 0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625 0000_1000 1.50000 0010_1000 1.30000 0100_1000 1.10000 0110_1000 0.90000 0000_1001 1.49375 0010_1001 1.29375 0100_1001 1.09375 0110_1001 0.89375 0000_1010 1.48750 0010_1010 1.28750 0100_1010 1.08750 0110_1010 0.88750 0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125 0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500 0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875 0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250 0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625 0001_0000 1.45000 0011_0000 1.25000 0101_0000 1.05000 0111_0000 0.85000 0001_0001 1.44375 0011_0001 1.24375 0101_0001 1.04375 0111_0001 0.84375 0001_0010 1.43750 0011_0010 1.23750 0101_0010 1.03750 0111_0010 0.83750 0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125 FN8321 Rev 4.00 Page 20 of 35 November 18, 2015

ISL62771 TABLE 6. SERIAL VID CODES (Continued) SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) SVID[7:0] VOLTAGE (V) 0001_0100 1.42500 0011_0100 1.22500 0101_0100 1.02500 0111_0100 0.82500 0001_0101 1.41875 0011_0101 1.21875 0101_0101 1.01875 0111_0101 0.81875 0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250 0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625 0001_1000 1.40000 0011_1000 1.20000 0101_1000 1.00000 0111_1000 0.80000 0001_1001 1.39375 0011_1001 1.19375 0101_1001 0.99375 0111_1001 0.79375 0001_1010 1.38750 0011_1010 1.18750 0101_1010 0.98750 0111_1010 0.78750 0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125 0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500 0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875 0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250 0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625 1000_0000 0.75000 1010_0000 0.55000* 1100_0000 0.35000* 1110_0000 0.15000* 1000_0001 0.74375 1010_0001 0.54375* 1100_0001 0.34375* 1110_0001 0.14375* 1000_0010 0.73750 1010_0010 0.53750* 1100_0010 0.33750* 1110_0010 0.13750* 1000_0011 0.73125 1010_0011 0.53125* 1100_0011 0.33125* 1110_0011 0.13125* 1000_0100 0.72500 1010_0100 0.52500* 1100_0100 0.32500* 1110_0100 0.12500* 1000_0101 0.71875 1010_0101 0.51875* 1100_0101 0.31875* 1110_0101 0.11875* 1000_0110 0.71250 1010_0110 0.51250* 1100_0110 0.31250* 1110_0110 0.11250* 1000_0111 0.70625 1010_0111 0.50625* 1100_0111 0.30625* 1110_0111 0.10625* 1000_1000 0.70000 1010_1000 0.50000* 1100_1000 0.30000* 1110_1000 0.10000* 1000_1001 0.69375 1010_1001 0.49375* 1100_1001 0.29375* 1110_1001 0.09375* 1000_1010 0.68750 1010_1010 0.48750* 1100_1010 0.28750* 1110_1010 0.08750* 1000_1011 0.68125 1010_1011 0.48125* 1100_1011 0.28125* 1110_1011 0.08125* 1000_1100 0.67500 1010_1100 0.47500* 1100_1100 0.27500* 1110_1100 0.07500* 1000_1101 0.66875 1010_1101 0.46875* 1100_1101 0.26875* 1110_1101 0.06875* 1000_1110 0.66250 1010_1110 0.46250* 1100_1110 0.26250* 1110_1110 0.06250* 1000_1111 0.65625 1010_1111 0.45625* 1100_1111 0.25625* 1110_1111 0.05625* 1001_0000 0.65000 1011_0000 0.45000* 1101_0000 0.25000* 1111_0000 0.05000* 1001_0001 0.64375 1011_0001 0.44375* 1101_0001 0.24375* 1111_0001 0.04375* 1001_0010 0.63750 1011_0010 0.43750* 1101_0010 0.23750* 1111_0010 0.03750* 1001_0011 0.63125 1011_0011 0.43125* 1101_0011 0.23125* 1111_0011 0.03125* 1001_0100 0.62500 1011_0100 0.42500* 1101_0100 0.22500* 1111_0100 0.02500* 1001_0101 0.61875 1011_0101 0.41875* 1101_0101 0.21875* 1111_0101 0.01875* 1001_0110 0.61250 1011_0110 0.41250* 1101_0110 0.21250* 1111_0110 0.01250* 1001_0111 0.60625 1011_0111 0.40625* 1101_0111* 0.20625* 1111_0111 0.00625* 1001_1000 0.60000* 1011_1000 0.40000* 1101_1000 0.20000* 1111_1000 OFF* 1001_1001 0.59375* 1011_1001 0.39375* 1101_1001 0.19375* 1111_1001 OFF* 1001_1010 0.58750* 1011_1010 0.38750* 1101_1010 0.18750* 1111_1010 OFF* 1001_1011 0.58125* 1011_1011 0.38125* 1101_1011 0.18125* 1111_1011 OFF* 1001_1100 0.57500* 1011_1100 0.37500* 1101_1100 0.17500* 1111_1100 OFF* 1001_1101 0.56875* 1011_1101 0.36875* 1101_1101 0.16875* 1111_1101 OFF* 1001_1110 0.56250* 1011_1110 0.36250* 1101_1110 0.16250* 1111_1110 OFF* 1001_1111 0.55625* 1011_1111 0.35625* 1101_1111 0.15625* 1111_1111 OFF* NOTE: *Indicates a VID not required for AMD Family 10h processors. Loosened AMD requirements at these levels. FN8321 Rev 4.00 Page 21 of 35 November 18, 2015

ISL62771 L VID L SI0_ VID bits [7:1] bit [0]SI1_ P P SVC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SVD RT ACK ACK ACK A T S FIGURE 19. SVD PACKET STRUCTURE SVI Bus Protocol For the 1-Phase Northbridge VR, when PSI0_L is asserted, Channel 1 enters diode emulation mode to boost efficiency. The AMD processor bus protocol is compliant with SMBus send When PSI0_L and PSI1_L are asserted low, the Northbridge VR byte protocol for VID transactions. The AMD SVD packet structure continues to operate in this fashion. is shown in Figure19. The description of what each bit of the three bytes that make up the SVI command are shown in Table7. It is possible for the processor to assert or deassert PSI0_L and During a transaction, the processor sends the start sequence PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L followed by each of the three bytes, which end with an optional is deasserted while PSI1_L is still asserted, the ISL62771 will acknowledge bit. The ISL62771 does not drive the SVD line return the selected VR back full channel CCM operation. during the ACK bit. Finally, the processor sends the stop sequence. After the ISL62771 has detected the stop, it can then TABLE 8. PSI0_L, PSI1_L AND TFN DEFINITION proceed with the commanded action from the transaction. FUNCTION BIT DESCRIPTION TABLE 7. SVD DATA PACKET PSI0_L 10 Power State Indicate level 0. When this signal is asserted (active Low) the processor is in a low BITS DESCRIPTION enough power state for the VR controller to take 1:5 Always 11000b action to boost efficiency by dropping phases and/or entering 1-Phase DE. 6 Core domain selector bit, if set then the following data byte PSI1_L 20 Power State Indicate level 1. When this signal is contains VID, power state, telemetry control, load line trim and asserted (active Low) the processor is in a low offset trim apply to the Core VR. enough power state for the VR controller to take 7 Northbridge domain selector bit, if set then the following data action to boost efficiency by dropping phases and byte contains VID, power state, telemetry control, load line trim entering 1-Phase DE. and offset trim apply to the Northbridge VR. TFN 21 Telemetry Functionality. This is an active high signal 8 Always 0b that allows the processor to control the telemetry functionality of the VR. 9 Acknowledge bit Dynamic Load Line Slope Trim 10 PSI0_L The ISL62771 supports the SVI2 ability for the processor to 11:17 VID Code bits [7:1] manipulate the load line slope of the Core and Northbridge VRs 18 Acknowledge bit independently using the serial VID interface. The slope manipulation applies to the initial load line slope. A load line 19 VID Code bit [0] slope trim will typically coincide with a VOTF change. See Table9 20 PSI1_L for more information about the load line slope trim feature of the ISL62771. 21 TFN (Telemetry Functionality) TABLE 9. LOAD LINE SLOPE TRIM DEFINITION 22:24 Load line slope trim LOAD LINE 25:26 Offset trim [1:0] SLOPE TRIM [2:0] DESCRIPTION 27 Acknowledge bit 000 Disable LL 001 -40% mΩ Change Power States 010 -20% mΩ Change SVI2 defines two power state indicator levels, see Table8. As 011 No Change processor current consumption is reduced, the power state indicator level changes to improve VR efficiency under low power 100 +20% mΩ Change conditions. 101 +40% mΩ Change For the Core VR operating in 2-phase mode, when PSI0_L is 110 +60% mΩ Change asserted, Channel 2 is tri-stated and Channel 1 enters diode 111 +80% mΩ Change emulation mode to boost efficiency. When PSI0_L and PSI1_L are asserted low, the Core VR continues to operate in this mode. FN8321 Rev 4.00 Page 22 of 35 November 18, 2015

ISL62771 Dynamic Offset Trim Protection Features The ISL62771 supports the SVI2 ability for the processor to Core VR and Northbridge VR both provide overcurrent, manipulate the output voltage offset of the Core and Northbridge current-balance, undervoltage and overvoltage fault protections. VRs. This offset is in addition to any output voltage offset set via The controller also provides over-temperature protection. The the COMP resistor reader. The dynamic offset trim can disable following discussion is based on Core VR and also applies to the the COMP resistor programmed offset of either output when Northbridge VR. “Disable All Offset” is selected. Overcurrent TABLE 10. OFFSET TRIM DEFINITION The IMON voltage provides a means of determining the load OFFSET TRIM current at any moment in time. The Overcurrent Protection (OCP) [1:0] DESCRIPTION circuitry monitors the IMON voltage to determine when a fault 00 Disable All Offset occurs. Based on the previous description in the“Voltage 01 -25mV Change Regulation and Load Line Implementation” on page15, the current, which flows out of the IMON pin, is proportional to the 10 0mV Change ISUM current. The ISUM current is created from the sensed voltage 11 +25mV Change across Cn, which is a measure of the load current based upon the sensing element selected. The IMON current is generated Telemetry internally and is 1/4 of the ISUM current. The EDC or IDDspike current value for the AMD CPU load is used to set the maximum The ISL62771 can provide voltage and current information current level for droop and the IMON voltage of 1.2V, which through the telemetry system outlined by the AMD SVI2 indicates 100% loading for telemetry. The ISUM current level at specification. The telemetry data is transmitted through the SVC maximum load, or IDDspike is 36µA and this translates to an IMON and SVT lines of the SVI 2 interface. current level of 9µA. The IMON resistor is 133kΩ and the 9µA flowing through the IMON resistor results in a 1.2V level at Current telemetry is based on a voltage generated across a maximum loading of the VR. 133kΩ resistor placed from the IMON pin to GND. The current flowing out of the IMON pin is proportional to the load current in The overcurrent threshold is 1.5V on the IMON pin. Based on a the VR. The Isum current defined in the “Voltage Regulation and 1.2V IMON voltage equating to 100% loading, the additional 0.3V Load Line Implementation” on page15 provides the base provided above this level equates to a 25% increase in load current conversion from the load current to the internal amplifier created before an OCP fault is detected. The EDC or IDDspike current is Isum current. The Isum current is then divided down by a factor of used to set the 1.2V on IMON for full load current. So the OCP level 4 to create the IMON current, which flows out of the IMON pin. is 1.25x the EDC or IDDspike current level. This additional margin The Isum current will measure 35µA when the load current is at above the EDC or IDDspike current allows the AMD CPU to enter full load based on a droop current designed for 45µA at the same and exit the IDDspike performance mode without issue unless the load current. The difference between the Isum current and the load current is out of line with the IDDspike expectation, thus the droop current is provided in Equation2. The IMON current will need for overcurrent protection. measure 11.25µA at full load current for the VR and the IMON When the voltage on the IMON pin meets the overcurrent voltage will be 1.2V. The load percentage, which is reported by threshold of 1.5V, this triggers an OCP event. Within 2µs of the IC is based on this voltage. When the load is 25% of the full detecting an OCP event, the controller asserts VR_HOT_L low to load, the voltage on the IMON pin will be 25% of 1.2V or 0.3V. communicate to the AMD CPU to throttle back. A fault timer The SVI interface allows the selection of no telemetry, voltage begins counting while IMON is at or above the 1.5V threshold. The only, or voltage and current telemetry on either or both of the VR fault timer lasts 7.5µs to 11µs and then flags an OCP fault. The outputs. The TFN bit along with the Core and Northbridge domain controller then tri-states the active channels and goes into selector bits are used by the processor to change the shutdown. PGOOD is taken low and a fault flag from this VR is sent functionality of telemetry, see Table11 for more information. to the other VR and it is shutdown within 10µs. If the IMON voltage drops below the 1.5V threshold prior to the fault timer count TABLE 11. TFN TRUTH TABLE finishing, the fault timer is cleared and VR_HOT_L is taken high. TFN, CORE, NB The ISL62771 also features a way-overcurrent [WOC] feature, BITS [21,6,7] DESCRIPTION which immediately takes the controller into shutdown. This 1,0,1 Telemetry is in voltage and current mode. Therefore, protection is also referred to as fast overcurrent protection for voltage and current are sent for VDD and VDDNB short-circuit protection. If the IMON current reaches 15µA, WOC is domains by the controller. triggered. Active channels are tri-stated and the controller is placed in shutdown and PGOOD is pulled low. There is no fault 1,0,0 Telemetry is in voltage mode only. Only the voltage of VDD and VDDNB domains is sent by the controller. timer on the WOC fault, the controller takes immediate action. The other controller output is also shutdown within 10µs. 1,1,0 Telemetry is disabled. 1,1,1 Reserved FN8321 Rev 4.00 Page 23 of 35 November 18, 2015

ISL62771 Current Balance The controller monitors the ISENx pin voltages to determine current-balance protection. If the ISENx pin voltage difference is INTERNAL TO greater than 9mV for 1ms, the controller will declare a fault and ISL62771 latch off. +V VR_HOT_L Undervoltage 30µA R If the VSEN voltage falls below the output voltage VID value plus NTC any programmed offsets by -325mV, the controller declares an MONITOR undervoltage fault. The controller deasserts PGOOD and Rp + tri-states the power MOSFETs. VNTC RNTC - Overvoltage If the VSEN voltage exceeds the output voltage VID value plus any Rs W64A0RmNVING S58H0UmTVDOWN programmed offsets by +325mV, the controller declares an overvoltage fault. The controller deasserts PGOOD and turns on the low-side power MOSFETs. The low-side power MOSFETs remain on FIGURE 20. CIRCUITRY ASSOCIATED WITH THE THERMAL MONITOR until the output voltage is pulled down below the VID set value. Once FEATURE OF THE ISL62771 the output voltage is below this level, the lower gate is tri-stated. If the output voltage rises above the overvoltage threshold again, the As the board temperature rises, the NTC thermistor resistance protection process is repeated. when all power MOSFETs are turned decreases and the voltage at the NTC pin drops. When the off. This behavior provides the maximum amount of protection voltage on the NTC pin drops below the over-temperature trip against shorted high-side power MOSFETs while preventing output threshold, then VR_HOT is pulled low. The VR_HOT signal is used ringing below ground. to change the CPU operation and decrease power consumption. With the reduction in power consumption by the CPU, the board Thermal Monitor [NTC, NTC_NB] temperature decreases and the NTC thermistor voltage rises. Once the over-temperature threshold is tripped and VR_HOT is The ISL62771 features two thermal monitors, which use an taken low, the over-temperature threshold changes to the reset external resistor network that includes an NTC thermistor to level. The addition of hysteresis to the over-temperature monitor motherboard temperature and alert the AMD CPU of a threshold prevents nuisance trips. Once both pin voltages exceed thermal issue. Figure20 shows the basic thermal monitor circuit the over-temperature reset threshold, the pull-down on VR_HOT on the Core VR NTC pin. The Northbridge VR features the same is released. The signal changes state and the CPU resumes thermal monitor. The controller drives a 30µA current out of the normal operation. The over-temperature threshold returns to the NTC pin and monitors the voltage at the pin. The current flowing trip level. out of the NTC pin creates a voltage that is compared to a warning threshold of 640mV. When the voltage at the NTC pin Table12 summarizes the fault protections. falls to this warning threshold or below, the controller asserts VR_HOT_L to alert the AMD CPU to throttle back load current to TABLE 12. FAULT PROTECTION SUMMARY stabilize the motherboard temperature. A thermal fault counter FAULT DURATION begins counting toward a minimum shutdown time of 100µs. BEFORE PROTECTION FAULT The thermal fault counter is an up/down counter, so if the FAULT TYPE PROTECTION ACTION RESET voltage at the NTC pin rises above the warning threshold, it will Overcurrent 7.5µs to 11.5µs PWM tri-state, count down and extend the time for a thermal fault to occur. The PGOOD latched Phase Current 1ms warning threshold does have 20mV of hysteresis. low Unbalance If the voltage at the NTC pin continues to fall down to the Way-Overcurrent Immediately shutdown threshold of 580mV or below, the controller goes into (1.5xOC) shutdown and triggers a thermal fault. The PGOOD pin is pulled Undervoltage PGOOD latched low and tri-states the power MOSFETs. A fault on either side will -325mV low. shutdown both VRs. PWM tri-state. ENABLE toggle or Overvoltage PGOOD latched VDD toggle +325mV low. Actively pulls the output voltage to below VID value, then tri-state. NTC Thermal 100µs min PGOOD latched low. PWM tri-state. FN8321 Rev 4.00 Page 24 of 35 November 18, 2015

ISL62771 Fault Recovery the total current information to the NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative All of the previously described fault conditions can be reset by temperature coefficient (NTC) thermistor, used to temperature bringing ENABLE low or by bringing VDD below the POR compensate the inductor DCR change. threshold. When ENABLE and VDD return to their high operating levels, the controller resets the faults and soft-start occurs. The inductor output side pads are electrically shorted in the schematic but have some parasitic impedance in actual board Interface Pin Protection layout, which is why one cannot simply short them together for the The SVC and SVD pins feature protection diodes, which must be current-sensing summing network. It is recommended to use considered when removing power to VDD and VDDIO, but leaving 1Ω~10ΩRo to create quality signals. Since Ro value is much smaller it applied to these pins. Figure21 shows the basic protection on than the rest of the current sensing circuit, the following analysis the pins. If SVC and/or SVD are powered but VDD is not, leakage ignores it. current will flow from these pins to VDD. The summed inductor current information is presented to the capacitor Cn. Equations13 through 17 describe the frequency domain relationship between inductor total current Io(s) and Cn INTERNAL TO voltage VCn(s): ISL62771    Rntcnet DCR VDD VCns = R-----n---t--c---n----e---t---+-----R---------s--N-----u------m------------N--------IosAcss (EQ. 13) R +R R SVC, SVD Rntcnet = ---R-----n---t--c---s----+-----R----n----t--c----+----R-------p-- (EQ. 14) ntcs ntc p s 1+-------  A s = ------------------L----- (EQ. 15) cs s GND 1+-------------  sns  = D-----C-----R--- (EQ. 16) L L FIGURE 21. PROTECTION DEVICES ON THE SVC AND SVD PINS  = ---------------------------1----------------------------- (EQ. 17) sns R Key Component Selection R -----s---u---m---- ntcnet N ------------------------------------------C R n sum Inductor DCR Current-Sensing Network R +--------------- ntcnet N Where N is the number of phases. PHASE1 PHASE2 RSUM Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, RSUM giving higher reading of the inductor DC current. The NTC Rntc ISUM+ value decrease as its temperature decreases. Proper selection of Rsum, Rntcs, Rp and Rntc parameters ensures that VCn represents the inductor total DC current over the temperature L L RNTCS + range of interest. RP CNVCN - There are many sets of parameters that can properly DCR DCR RNTC temperature-compensate the DCR change. Since the NTC network RI ISUM- and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. It is recommended to have a RO higher ratio of Vcn to the inductor DCR voltage so the droop circuit RO has a higher signal level to work with. A typical set of parameters that provide good temperature IO compensation are: Rsum = 3.65kΩ, Rp=11kΩ, Rntcs = 2.61kΩ FIGURE 22. DCR CURRENT-SENSING NETWORK and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters may need to be fine-tuned on actual boards. One can apply full Figure22 shows the inductor DCR current-sensing network for a load DC current and record the output voltage reading 2-phase solution. An inductor current flows through the DCR and immediately; then record the output voltage reading again when creates a voltage drop. Each inductor has two resistors in Rsum the board has reached the thermal steady state. A good NTC and Ro connected to the pads to accurately sense the inductor network can limit the output voltage drift to within 2mV. It is current by sensing the DCR voltage drop. The Rsum and Ro recommended to follow the Intersil evaluation board layout and resistors are connected in a summing network as shown and feed FN8321 Rev 4.00 Page 25 of 35 November 18, 2015

ISL62771 current sensing network parameters to minimize engineering time. io VCn(s) also needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole sns and a zero L. One needs to match L and sns so Acs(s) is unity gain at all frequencies. By forcing L equal to sns and solving for the solution, Equation18 gives Cn value. Vo L (EQ. 18) C = --------------------------------------------------------------- n R R-----s---u---m---- FIGURE 25. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE ntcnet N ------------------------------------------DCR R sum R +--------------- ntcnet N io i L For example, given N = 2, Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs=2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ and L=0.36µH, Equation18 gives Cn=0.294µF. Assuming the compensator design is correct, Figure23 shows the Vo expected load transient response waveforms if Cn is correctly RING selected. When the load current Icore has a square change, the BACK output voltage Vcore also has a square response. If Cn value is too large or too small, VCn(s) does not accurately FIGURE 26. OUTPUT VOLTAGE RINGBACK PROBLEM represent real-time Io(s) and worsens the transient response. Figure24 shows the load transient response when Cn is too ISUM+ small. Vcore sags excessively upon load insertion and may create a system failure. Figure25 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There is excessive overshoot if load insertion occurs during this Rntcs C + n.1 time, which may negatively affect the CPU reliability. Rp Cn.2 Vcn R Rn - ntc io OPTIONAL Ri ISUM- C R ip ip Vo OPTIONAL FIGURE 23. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS FIGURE 27. OPTIONAL CIRCUITS FOR RINGBACK REDUCTION Figure26 shows the output voltage ringback problem during io load transient response. The load current io has a fast step change, but the inductor current iL cannot accurately follow. Instead, iL responds in first-order system fashion due to the nature of the current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load Vo current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore, it pulls Vo back to the level dictated by iL, causing the ringback problem. This phenomenon is not observed when the FIGURE 24. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL output capacitor has very low ESR and ESL, as is the case with all ceramic capacitors. Figure27 shows two optional circuits for reduction of the ringback. Cn is the capacitor used to match the inductor time constant. It usually takes the parallel of two (or more) capacitors to get the desired value. Figure27 shows that two capacitors (Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional component to reduce the Vo ringback. At steady state, FN8321 Rev 4.00 Page 26 of 35 November 18, 2015

ISL62771 Cn.1+Cn.2 provides the desired Cn capacitance. At the beginning . R of io change, the effective capacitance is less because Rn VCns = -----sN---e---n--IosARsens (EQ. 19) increases the impedance of the Cn.1 branch. As Figure24 shows, Vo tends to dip when Cn is too small and this effect reduces the ARsens = ----------1------s------- (EQ. 20) Vo ringback. This effect is more pronounced when Cn.1 is much 1+------------- larger than Cn.2. It is also more pronounced when Rn is bigger. sns Hif oCwne.2v eisr ,t tohoe s pmreaslle. nItc eis oref cRonm inmcreenadseeds ttoh ek erieppp lCen o.2f tghree aVtne rs itghnaanl Rsen = -R---------s------u-------m----1----------C------- (EQ. 21) 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values N n should be determined through tuning the load transient response Transfer function ARsen(s) always has unity gain at DC. waveforms on an actual board. Current-sensing resistor Rsen value does not have significant variation over-temperature, so there is no need for the NTC Rip and Cip form an R-C branch in parallel with Ri, providing a lower network. impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of The recommended values are Rsum = 1kΩ and Cn=5600pF. Rip and Cip values, idroop can resemble io rather than iL and Vo will Overcurrent Protection not ring back. The recommended value for Rip is 100Ω. Cip should be determined through tuning the load transient response Refer to Equation2 on page16 and Figures22, 26 and 28; waveforms on an actual board. The recommended range for Cip is resistor Ri sets the Isum current, which is proportional to droop 100pF~2000pF. However, it should be noted that the Rip -Cip branch current and IMON current. Tables1 and 2 show the internal OCP may distort the idroop waveform. Instead of being triangular as the threshold based on the IMON pin voltage. Since the Ri resistor real inductor current, idroop may have sharp spikes, which may impacts both the droop current and the IMON current, fine adversely affect idroop average value detection and therefore may adjustments to Idroop will require changing the Rcomp resistor. affect OCP accuracy. User discretion is advised. For example, the OCP threshold is 1.5V on the IMON pin, which Resistor Current-Sensing Network equates to an IMON current of 11.25µA using a 133kΩ IMON resistor. The corresponding ISUM current is 45µA, which results PHASE1 PHASE2 in an Idroop of 56.25µA. At full load current, Iomax, the ISUM current is 36µA and the resulting Idroop is 45µA. The ratio of the ISUM current at OCP relative to full load is 1.25. Therefore, the L L OCP current trip level is 25% higher than the full load current. For inductor DCR sensing, Equation22 gives the DC relationship DCR DCR of Vcn(s) and Io(s): RSUM    Rntcnet DCR RSUM VCn = ----------------------------R----s----u---m--------N--------Io (EQ. 22) ISUM+ Rntcnet+------N---------  + RSEN RSEN VCN CN Substitution of Equation22 into Equation2 gives Equation23: - RI ISUM- 5 1 Rntcnet DCR I = ---------------------------------------------------------------I RO droop 4 Ri Rsum N o (EQ. 23) R +--------------- ntcnet N RO Therefore: IO R = 5------------------R-----n---t--c---n----e---t--------D----C-----R-----------I--o----------------- i 4 R (EQ. 24) FIGURE 28. RESISTOR CURRENT-SENSING NETWORK NR +-----s---u---m----I  ntcnet N  droop Figure28 shows the resistor current-sensing network for a Substitution of Equation14 and application of the OCP condition 2-phase solution. Each inductor has a series current sensing in Equation24 gives Equation25: resistor, Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum R +R R and Ro resistors are connected to capacitor Cn. Rsum and Cn --------n---t--c---s-------------n----t--c---------------p--DCRI form a filter for noise attenuation. Equations19 through 21 give 5 Rntcs+Rntc+Rp omax the VCn(s) expression. Ri = 4---N-------------------R----------n------t----c------s--------+----------R---------n-------t----c----------------------R---------p------+-----R----------s------u------m------------------I--------------------------- (EQ. 25)  Rntcs+Rntc+Rp N  droopmax FN8321 Rev 4.00 Page 27 of 35 November 18, 2015

ISL62771 Where Iomax is the full load current and Idroopmax is the Compensator corresponding droop current. For example, given N = 2, Figure23 shows the desired load transient response waveforms. Rsum=3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ, Figure29 shows the equivalent circuit of a Voltage Regulator DCR=0.88mΩ, Iomax = 50A and Idroopmax = 45µA. Equation25 (VR) with the droop function. A VR is equivalent to a voltage gives Ri = 466Ω. source (=VID) and output impedance Zout(s). If Zout(s) is equal to For resistor sensing, Equation26 gives the DC relationship of the load line slope LL, i.e., a constant output impedance, then in Vcn(s) and Io(s). the entire frequency range, Vo will have a square response when io has a square change. R sen V = -------------I (EQ. 26) Cn N o Zout(s) = LL io Substitution of Equation26 into Equation2 gives Equation27: Idroop = 54----R-1---R-----sN---e---n--Io (EQ. 27) VID VR LOAD Vo i Therefore: 5 RsenIo R = ------------------------------ (EQ. 28) i 4 NI FIGURE 29. VOLTAGE REGULATOR EQUIVALENT CIRCUIT droop Intersil provides a Microsoft Excel-based spreadsheet to help Substitution of Equation28 and application of the OCP condition design the compensator and the current sensing network so that in Equation24 gives Equation29: VR achieves constant output impedance as a stable system. 5 RsenIomax Ri = 4---N-----------I--------------------------- (EQ. 29) A VR with active droop function is a dual-loop system consisting of droopmax a voltage loop and a droop loop, which is a current loop. However, Where Iomax is the full load current and Idroopmax is the neither loop alone is sufficient to describe the entire system. The corresponding droop current. For example, given N = 2, spreadsheet shows two loop gain transfer functions, T1(s) and Rsen=1mΩ, Iomax = 50A and Idroopmax = 45µA, Equation29 T2(s), that describe the entire system. Figure30 conceptually gives Ri = 694Ω. shows T1(s) measurement set up and Figure31 conceptually shows T2(s) measurement set up. The VR senses the inductor Load Line Slope current, multiplies it by a gain of the load line slope, adds it on top of the sensed output voltage and then feeds it to the compensator. See Figure15 for load line implementation. T1 is measured after the summing node and T2 is measured in the For inductor DCR sensing, substitution of Equation23 into voltage loop before the summing node. The spreadsheet gives Equation3 gives the load line slope expression in Equation30: both T1(s) and T2(s) plots. However, only T2(s) can actually be measured on an ISL62771 regulator. LL = V-----d---r--o----o---p-- = 5---R-----d---r---o---o---p-------------R-----n---t--c---n----e---t-----------D-----C-----R--- (EQ. 30) I 4 R R N . o i R +-----s---u---m---- ntcnet N L VO For resistor sensing, substitution of Equation27 into Equation3 Q1 gives the load line slope expression in Equation31: VIN GATE Q2 COUT iO Vdroop 5 RsenRdroop DRIVER LL = ------------------- = ------------------------------------------ I 4 NR (EQ. 31) o i Substitution of Equation24 and rewriting Equation30, or LOAD LINE SLOPE substitution of Equation28 and rewriting Equation31, gives the + 20 same result as in Equation32: + - I MOD. EA o Rdroop = I----------------LL (EQ. 32) COMP + droop VID ISOLATION TRANSFORMER One can use the full-load condition to calculate Rdroop. For CHANNEL B example, given Iomax = 50A, Idroopmax = 45µA and LL=2.1mΩ, LOOP GAIN = CHANNEL A Equation32 gives Rdroop = 2.33kΩ. CHANNEL A CHANNEL It is recommended to start with the Rdroop value calculated by NETWORK ANALYZER Equation32 and fine-tune it on the actual board to get accurate EXCITATION OUTPUT load line slope. One should record the output voltage readings at FIGURE 30. LOOP GAIN T1(s) MEASUREMENT SET UP no load and at full load for load line slope calculation. Reading T1(s) is the total loop gain of the voltage loop and the droop loop. the output voltage at lighter load instead of full load will increase It always has a higher crossover frequency than T2(s), therefore the measurement error. has a higher impact on system stability. FN8321 Rev 4.00 Page 28 of 35 November 18, 2015

ISL62771 T2(s) is the voltage loop gain with closed droop loop, thus having a higher impact on output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient INTERNAL TO ISL62771 phase margin and an output impedance equal to or smaller than the load line slope. +V VR_HOT_L 30µA R L VO Q1 NTC MONITOR VIN GATE Q2 CO IO DRIVER 330kΩ RNTC 8.45kΩ Rs W64A0RmNVING S58H0UmTVDOWN LOAD LINE SLOPE + 20  - + MOD. EA FIGURE 32. THERMAL MONITOR FEATURE OF THE ISL62771 + COMP VID ISOLATION As the board temperature rises, the NTC thermistor resistance TRANSFORMER decreases and the voltage at the NTC pin drops. When the CHANNEL B LOOP GAIN = voltage on the NTC pin drops below the thermal warning CHANNEL A threshold of 0.64V, then VR_HOT_L is pulled low. When the AMD CHANNEL A CHANNEL B CPU detects VR_HOT_L has gone low, it will begin throttling back NETWORK load current on both outputs to reduce the board temperature. ANALYZER EXCITATION OUTPUT FIGURE 31. LOOP GAIN T2(s) MEASUREMENT SET-UP If the board temperature continues to rise, the NTC thermistor resistance will drop further and the voltage at the NTC pin could Current Balancing drop below the thermal shutdown threshold of 0.58V. Once this threshold is reached, the ISL62771 shuts down both Core and Refer to Figure16 through 22 for information on current Northbridge VRs indicating a thermal fault has occurred prior to balancing. The ISL62771 achieves current balancing through the thermal fault counter triggering a fault. matching the ISEN pin voltages. Risen and Cisen form filters to remove the switching ripple of the phase node voltages. It is Selection of the NTC thermistor can vary depending on how the recommended to use a rather long Risen, Cisen time constant, resistor network is configured. The equivalent resistance at the such that the ISEN voltages have minimal ripple and represent typical thermal warning threshold voltage of 0.64V is defined in the DC current flowing through the inductors. Recommended Equation33. values are Rs = 10kΩ and Cs=0.22µF. 0.64V ---------------- = 21.3k (EQ. 33) 30A Thermal Monitor Component Selection The ISL62771 features two pins, NTC and NTC_NB, which are The equivalent resistance at the typical thermal shutdown used to monitor motherboard temperature and alert the AMD threshold voltage of 0.58V required to shutdown both outputs is CPU if a thermal issue arises. The basic function of this circuitry defined in Equation34. is outlined in the “Thermal Monitor [NTC, NTC_NB]” on page24. 0.58V Figure32 shows the basic configuration of the NTC resistor, RNTC -3---0--------A---- = 19.3k (EQ. 34) and offset resistor, RS, used to generate the warning and shutdown voltages at the NTC pin. The NTC thermistor value correlates to the resistance change between the warning and shutdown thresholds and the required temperature change. If the warning level is designed to occur at a board temperature of +100°C and the thermal shutdown level at a board temperature of +105°C, then the resistance change of the thermistor can be calculated. For example, a Panasonic NTC thermistor with B = 4700 has a resistance ratio of 0.03939 of its nominal value at +100°C and 0.03308 of its nominal value at +105°C. Taking the required resistance change between the thermal warning threshold and the shutdown threshold and dividing it by the change in resistance ratio of the NTC thermistor at the two temperatures of interest, the required resistance of the NTC is defined in Equation35. 21.3k–19.3k ------------------------------------------------------ = 317k (EQ. 35) 0.03939–0.03308 FN8321 Rev 4.00 Page 29 of 35 November 18, 2015

ISL62771 The closest standard thermistor to the value calculated with When placing MOSFETs, try to keep the source of the upper B=4700 is 330kΩ. The NTC thermistor part number is MOSFETs and the drain of the lower MOSFETs as close as ERTJ0EV334J. The actual resistance change of this standard thermally possible (see Figure33). Input high-frequency thermistor value between the warning threshold and the capacitors should be placed close to the drain of the upper shutdown threshold is calculated in Equation36. MOSFETs and the source of the lower MOSFETs. Place the output inductor and output capacitors between the MOSFETs and the 330k0.03939–330k0.03308 = 2.082k (EQ. 36) load. High-frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target Since the NTC thermistor resistance at +105°C is less than the (microprocessor), making use of the shortest connection paths to required resistance from Equation34, additional resistance in any internal planes. Place the components in such a way that the series with the thermistor is required to make up the difference. area under the IC has less noise traces with high dV/dt and di/dt, A standard resistor, 1% tolerance, added in series with the such as gate signals and phase node signals. thermistor will increase the voltage seen at the NTC pin. The additional resistance required is calculated in Equation37. 19.3k–10.916k = 8.384k (EQ. 37) VIAS TO GND GROUND OUTPUT The closest standard 1% tolerance resistor is 8.45kΩ. PLANE CAPACITORS SCHOTTKY The NTC thermistor is placed in a hot spot on the board, typically VOUT DIODE near the upper MOSFET of Channel 1 of the respective output. The standard resistor is placed next to the controller. INDUCTOR PNHOADSEE LOW-SIDE MOSFETS Layout Guidelines HIGH-SIDE MOSFETS INPUT VIN CAPACITORS PCB Layout Considerations POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB FIGURE 33. TYPICAL POWER COMPONENT PLACEMENT As a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic Table13 shows layout considerations for the ISL62771 signal layers on the opposite side of the board. The ground-plane controller by pin. layer should be adjacent to the signal layer to provide shielding. COMPONENT PLACEMENT There are two sets of critical components in a DC/DC converter; the power components and the small signal components. The power components are the most critical because they switch large amount of energy. The small signal components connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first and these include MOSFETs, input and output capacitors and the inductor. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each power train. Symmetrical layout allows heat to be dissipated equally across all power trains. Keeping the distance between the power train and the control IC short helps keep the gate drive traces short. These drive signals include the LGATE, UGATE, PGND, PHASE and BOOT. FN8321 Rev 4.00 Page 30 of 35 November 18, 2015

ISL62771 TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER ISL62771 PIN SYMBOL LAYOUT GUIDELINES BOTTOM PAD GND Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are recommended to connect this pad to the internal ground plane layers of the PCB. 1 NTC_NB The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge thermal throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard resistors in the resistor network on this pin should be placed near the IC. 2 IMON_NB Place the IMON_NB resistor close to this pin and make/keep a tight GND connection. 3 SVC Use good signal integrity practices and follow AMD recommendations. 4 VR_HOT_L Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended. 5 SVD 6 VDDIO Use good signal integrity practices and follow AMD recommendations. 7 SVT 8 ENABLE Use good signal integrity practices. 9 PWROK Use good signal integrity practices and follow AMD recommendations. 10 IMON Place the IMON resistor close to this pin and make/keep a tight GND connection. 11 NTC The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal throttling. Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the resistor network on this pin should be placed near the IC. 12 ISEN2 Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN and then through another capacitor (Cvsumn) to GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small: 13 ISEN1 1. Any ISEN pin to another ISEN pin 2. Any ISEN pin to GND The red traces in the following drawing show the loops to be minimized. VO PHASE2 L2 RISEN RO ISEN2 CISEN PHASE1 L1 RISEN RO ISEN1 GND VSUMN CISEN CVSUMN FN8321 Rev 4.00 Page 31 of 35 November 18, 2015

ISL62771 TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER (Continued) ISL62771 PIN SYMBOL LAYOUT GUIDELINES 14 ISUMP Place the current sensing circuit in general proximity of the controller. Place capacitor Cn very close to the controller. 15 ISUMN Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. INDUCTOR INDUCTOR VIAS CURRENT-SENSING TRACES CURRENT-SENSING TRACES 16 VSEN Place the filter on these pins in close proximity to the controller for good coupling. 17 RTN 18 FB Place the compensation components in general proximity of the controller. 19 COMP 20 PGOOD No special consideration. 21 BOOT1 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace. 22 UGATE1 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR 23 PHASE1 Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for better performance. 24 LGATE1 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them. 25 VDD A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close proximity to the pin with the filter resistor nearby the IC. 26 VDDP A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close proximity to the pin. 27 LGATE2 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them. 28 PHASE2 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR 29 UGATE2 Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for better performance. 30 BOOT2 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this 31 BOOT_NB trace. 32 UGATE_NB These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE_NB to the 33 PHASE_NB Northbridge VR high-side MOSFET source pin instead of a general connection to PHASE_NB copper is recommended for better performance. 34 LGATE_NB Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them. 35 PGOOD_NB No special consideration. FN8321 Rev 4.00 Page 32 of 35 November 18, 2015

ISL62771 TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER (Continued) ISL62771 PIN SYMBOL LAYOUT GUIDELINES 36 COMP_NB Place the compensation components in general proximity of the controller. 37 FB_NB 38 VSEN_NB Place the filter on this pin in close proximity to the controller for good coupling. 39 ISUMN_NB Place the current sensing circuit in general proximity of the controller. Place capacitor Cn very close to the controller. 40 ISUMP_NB Place the NTC thermistor next to Northbridge VR Channel 1 inductor so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. INDUCTOR INDUCTOR VIAS CURRENT-SENSING TRACES CURRENT-SENSING TRACES FN8321 Rev 4.00 Page 33 of 35 November 18, 2015

ISL62771 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE November 18, 2015 FN8321.4 On page1 under Features, changed “SVC frequency range 100kHz to 20MHz” to “Serial VID clock frequency range 100kHz to 25MHz”. Removed SVC Frequency Range spec from Electrical Spec Table on page 11. March 25, 2015 FN8321.3 On page1 under Features, added “SVC Frequency Range 100kHz to 20MHz” below “Supports AMD SVI 2.0 serial data bus interface” Electrical Spec Table On page11: “LOGIC THRESHOLDS” section, added “SVC Frequency Range” with limits of 0.1MHz to 20MHz. Updated the L40.5x5 Package Outline Drawing on page35 to the latest revision: Rev 1 to Rev 2 changes are by adding tolerance +/- values to Top view and Side View. September 12, 2013 FN8321.2 Ordering information table on page9: Changed IRTZ part temperature from -40°C to +85°C to -40°C to +100°C. Page14, Channel Configuration Section, removed “as will connecting ISEN1_NB to +5V will disable the Northbridge VR output.” Changed temperature -40°C to +85°C to -40°C to +100°C throughout the datasheet. December 18, 2012 FN8321.1 Changed AGND symbols to GND symbols in Figures 3 thru 5 and Pin 12/13 drawing in the Layout Guidelines table. The IC has a single GND connection which all signals are referenced. November 19, 2012 FN8321.1 Typo on page9 in the pin description for COMP_NB pin. Changed "slew rate" to "switching frequency". The part description in all other places indicated that the slew rate is fixed and the switching frequency is set by the COMP_NB resistor. Corrected part marking in “Ordering Information” on page9. June 13, 2012 FN8321.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2012-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8321 Rev 4.00 Page 34 of 35 November 18, 2015

ISL62771 Package Outline Drawing L40.5x5 40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 7/14 4x3.60 5.00±0.05 A B 36x0.40 6 6 PIN #1 INDEX AREA PIN 1 INDEX AREA 5 0 0. 0 ± 5 00 3. 5. (4X) 0.15 40x0.4±0.1 0.20 TOP VIEW BOTTOM VIEW b 0.10M C A B 4 PACKAGE OUTLINE 0.40 0.750±0.10 SEE DETAIL “X” // 0.10C C BASE PLANE SEATING PLANE 0.050 0.08C SIDE VIEW 0 0 0 5 5. 3. (36x0.40) 0.2 REF (40x0.20) 5 C (40x0.60) 0.00 MIN 0.05 MAX TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. JEDEC reference drawing: MO-220WHHE-1 FN8321 Rev 4.00 Page 35 of 35 November 18, 2015