DATASHEET ISL6146 FN7667 Low Voltage OR-ing FET Controller Rev 5.00 Aug 17, 2015 The ISL6146 represents a family of OR-ing MOSFET controllers Features capable of OR-ing voltages from 1V to 18V. Together with suitably sized N-channel power MOSFETs, the ISL6146 increases power • OR-ing down to 1V and up to 20V with ISL6146A, ISL6146B, distribution efficiency when replacing a power OR-ing diode in high ISL6146D and ISL6146E current applications. It provides gate drive voltage for the • Programmable voltage compliant operation with ISL6146C MOSFET(s) with a fully integrated charge pump. • VIN hot swap transient protection rating to +24V The ISL6146 allows users to adjust with external resistor(s) the VOUT - VIN trip point, which adjusts the control sensitivity to system • High speed comparator provides fast <0.3µs turn-off in power supply noise. An open drain FAULT pin will indicate if a response to shorts on sourcing supply conditional or FET fault has occurred. • Fastest reverse current fault isolation with 6A turn-off The ISL6146A and ISL6146B are optimized for very low voltage current operation, down to 1V with an additional independent bias of 3V • Very smooth switching transition or greater. • Internal charge pump to drive N-channel MOSFET The ISL6146C provides a voltage compliant mode of operation down to 3V with programmable undervoltage lock out and • User programmable VIN - VOUT Vth for noise immunity overvoltage protection threshold levels. • Open-drain FAULT output with delay The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B - Short between any two of the OR-ing FET terminals respectively, but do not have conduction state reporting via the - GATE voltage and excessive FET VDS fault output. - Power-good indicator (ISL6146C) TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY • MSOP and DFN package options PART Applications NUMBER KEY DIFFERENCES ISL6146A Separate BIAS and VIN with Active High Enable • N+1 industrial and telecom power distribution systems ISL6146B Separate BIAS and VIN with Active Low Enable • Uninterruptable power supplies ISL6146C VIN with OVP/UVLO Inputs • Low voltage processor and memory • Storage and datacom systems ISL6146D ISL6146A without Conduction Monitor and Reporting ISL6146E ISL6146B without Conduction Monitor and Reporting Q1 + C O + M M O N VINGATE VOUT VOLTAGE BIAS ADJ OP GATE FAST OFF, ~200ns FALL TIME DC/DC ISL6146B W ~70ns FROM 20V TO 12.6V ACROSS 57nF (3V - 20V) FLT RE GATE OUTPUT SINKING ~ 6A GND EN BU S - Q2 +C O + M M O N VINGATE VVOOUUTT P VOLTAGE BIAS ADJ O (3DVC -/ D20CV) ISL6146B WE FLT R B GND EN U S - FIGURE 1. TYPICAL APPLICATION FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN FN7667 Rev 5.00 Page 1 of 28 Aug 17, 2015

ISL6146 Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Typical Applications Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ISL6146 Evaluation Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Description and Use of the Evaluation Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 L8.3x3J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 M8.118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FN7667 Rev 5.00 Page 2 of 28 Aug 17, 2015

ISL6146 Block Diagram BIAS Q-PUMP FAULT DIAGNOSTIC 1. VIN - VOUT > 570mV 2. GATE - VIN < 220mV (A, B, C only) FLT VDS FORWARD 3. TEMP > +150°C + REGULATOR VIN GATE 4. VBIAS < POR (ISL6146A/B/D/E) -+ 5. VIN OR VOUT < POR (ISL6146C) 19mV 6. VIN < VOUT VOUT REVERSE DETECTION 7. Gate to Drain and Gate to Source Shorts 57mV COMPARATOR + + UVLO +- 8mA EN/EN ENABLE EN ENABLE * +- VREF OVP 4A ADJ + HIGH SPEED + COMPARATOR * Connected to BIAS on ISL6146A/B/D/E ISL6146A/B/D/E +- VREF Connected to VOUT on ISL6146C ISL6146C Pin Configuration ISL6146 (8 LD MSOP/DFN) TOP VIEW ISL6146A, ISL6146B, ISL6146D, ISL6146E ISL6146C GATE 1 8 VOUT GATE 1 8 VOUT VIN 2 7 ADJ VIN 2 7 ADJ BIAS 3 6 FAULT UVLO 3 6 FAULT EN ISL6146A/D 4 5 GND OVP 4 5 GND EN ISL6146B/E EPAD on DFN only, connect to GND Pin Descriptions MSOP/ DFN SYMBOL DESCRIPTION 1 GATE Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically <1ms. Allows active control of external N-Channel FET gate to perform OR-ing function. The GATE drive is between VIN + 7V at VIN = 3.3V and VIN +12V at VIN = 18V. 2 VIN Connected to the sourcing supply side (OR-ing MOSFET source), this pin serves as the sense pin to determine the OR’d supply voltage. The OR-ing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally set threshold or the defaulted internal threshold. Range: 0V to 24V 3 BIAS Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than VIN. ISL6146A Range:3.0to24V ISL6146B ISL6146D ISL6146E 3 UVLO Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V ISL6146C 4 EN Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ. ISL6146A Range: 0V to 24V ISL6146D FN7667 Rev 5.00 Page 3 of 28 Aug 17, 2015

ISL6146 Pin Descriptions (Continued) MSOP/ DFN SYMBOL DESCRIPTION 4 EN Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V ISL6146B ISL6146E 4 OVP Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET ISL6146C configuration must be employed to implement the OVP capability. Range: 0V to 24V 5 GND Chip ground reference. 6 FAULT Open-drain pull-down fault indicating output with internal on-chip filtering (TFLT). The ISL6146 fault detection circuitry pulls down this pin to GND as it detects a fault or a disabled input (EN = ‘0’ or EN = ‘1’). Different types of faults and their detection mechanisms are discussed in more detail on page17. These faults include: a. GATE is OFF (GATE < VIN+0.2V) when enabled [this condition is not reported on the ISL6146D and ISL6146E] b. VIN-VOUT > 0.57V when ON. c. FET G-D or G-S or D-S shorts. d. VIN < PORL2H e. VIN < VOUT f. Over-Temperature Range: 0 to VOUT 7 ADJ Resistor programmable VIN - VOUT Voltage Threshold (Vth) of the High Speed Comparator. This pin is either directly connected to VOUT or can be connected through a 5kΩ to 100kΩ resistor to GND. Allows for adjusting the voltage difference threshold to prevent unintended turn-off of the pass FET due to normal system voltage fluctuations. Range: 0.4 to VOUT 8 VOUT The second sensing node for external FET control and connected to the Load side (OR-ing MOSFET Drain). This is the common connection point for multiple paralleled supplies. VOUT is compared to VIN to determine when the OR-ing FET has to be turned off. Range: 0V to 24V PAD Thermal Pad Connect to GND FN7667 Rev 5.00 Page 4 of 28 Aug 17, 2015

ISL6146 Ordering Information PART NUMBER PART TEMP RANGE PACKAGE PKG. (Notes1, 2, 3) MARKING (°C) (Pb-free) DWG. # ISL6146AFUZ 6146A -40 to +125 8 Ld MSOP M8.118 ISL6146AFRZ 46AF -40 to +125 8 Ld 3x3 DFN L8.3x3J ISL6146BFUZ 6146B -40 to +125 8 Ld MSOP M8.118 ISL6146BFRZ 46BF -40 to +125 8 Ld 3x3 DFN L8.3x3J ISL6146CFUZ 6146C -40 to +125 8 Ld MSOP M8.118 ISL6146CFRZ 46CF -40 to +125 8 Ld 3x3 DFN L8.3x3J ISL6146DFUZ 6146D -40 to +125 8 Ld MSOP M8.118 ISL6146DFRZ 46DF -40 to +125 8 Ld 3x3 DFN L8.3x3J ISL6146EFUZ 6146E -40 to +125 8 Ld MSOP M8.118 ISL6146EFRZ 46EF -40 to +125 8 Ld 3x3 DFN L8.3x3J ISL6146AEVAL1Z ISL6146A Evaluation Board (If desired with ISL6146D, please contact support) ISL6146BEVAL1Z ISL6146B Evaluation Board (If desired with ISL6146E, please contact support) ISL6146CEVAL1Z ISL6146C Evaluation Board ISL6146DEVAL1Z 1 pair of ISL6146D Mini Development Boards (If desired with ISL6146A, please contact support) ISL6146EEVAL1Z 1 pair of ISL6146E Mini Development Boards (If desired with ISL6146B, please contact support) NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6146. For more information on MSL please see techbrief TB363. FN7667 Rev 5.00 Page 5 of 28 Aug 17, 2015

ISL6146 Absolute Maximum Ratings Thermal Information BIAS, VIN, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 40V MSOP Package (Notes4, 7) . . . . . . . . . . . . 140 41 EN, EN, UVLO, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +24V DFN Package (Notes5, 6). . . . . . . . . . . . . . 46 5 ADJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C ESD Rating Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 250V Recommended Operating Conditions Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Bias Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +20V OR’d Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to BIAS Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For JC, the “case temp” location is taken at the package top center Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA=+25°C to +85°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. MIN MAX SYMBOL PARAMETERS TEST CONDITIONS (Note8) TYP (Note8) UNITS BIAS PORL2H POR Rising BIAS Rising, GATE Rising 1.9 2.5 2.95 V PORHYS POR Hysteresis 189 mV IBIAS_en_18 ISL6146A/B/D/E BIAS Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled 3.6 5 mA IVIN_en_18 ISL6146A/B/D/E VIN Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled 25 40 µA IVIN_en_18 ISL6146C VIN Current VIN = 18V, ADJ, VOUT = 16.98V, enabled 3 4.5 mA IVOUT_en_18 ISL6146A/B/D/E VOUT Current BIAS, VIN = 18V, VOUT = 16.98V, enabled 14 20 µA VOUT_en_18 ISL6146C VOUT Current VIN = 18V, VOUT = 16.98V, enabled 400 500 µA IBIAS_den_18 ISL6146A/B/D/E BIAS Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled 1.7 3 mA IVIN_den_18 ISL6146A/B/D/E VIN Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled 27 37 µA IVIN_den_18 ISL6146C VIN Current VIN = 18V, ADJ, VOUT = 16.98V, disabled 1.3 1.5 mA IVOUT_den_18 ISL6146A/B/D/E VOUT Current BIAS, VIN = 18V, VOUT = 16.98V, disabled 14 20 µA IVOUT_den_18 ISL6146C VOUT Current VIN = 18V, VOUT = 16.98V, disabled 385 500 µA tBIAS2GTE BIAS to GATE Delay BIAS > PORL2H to GATE Rising 150 210 µs GATE VGH_3 Charge Pump Voltage VIN, BIAS = 3V VIN - VOUT > VFWD_VR VIN + 5V VIN + 7V VIN + 10.5V V VGH_12 Charge Pump Voltage VIN, BIAS = 12V VIN - VOUT > VFWD_VR VIN + 9V VIN + 10V VIN + 17.5V V VGH_18 Charge Pump Voltage VIN, BIAS = 18V VIN - VOUT > VFWD_VR VIN + 9V VIN +10V VIN + 18V V VGL Low Voltage Level VIN - VOUT < 0V 0 0.1 V IPDL Low Pull-Down Current VIN = 12V, VOUT = 12.2V ADJ = 11V 5 8.4 13 mA IPDH High Pull-Down Current VIN falling from 12V to 10V in 2µs 3.5 6.5 A ttoff Fast Turn-off Time VIN = VBIAS = 12V, VGATE = 18V to 10V, 65 130 ns CGATE=57nF FN7667 Rev 5.00 Page 6 of 28 Aug 17, 2015

ISL6146 Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA=+25°C to +85°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN MAX SYMBOL PARAMETERS TEST CONDITIONS (Note8) TYP (Note8) UNITS ttoffs Slow Turn-off Time VIN = VBIAS = 12V, VGATE = 18V to 10V, 58 80 µs CGATE=57nF ION Turn-on Current BIAS = 12V, VG = 0V 1 mA BIAS = 12V, VG = 20V 0.15 mA VVG_FLTr GATE to VIN Rising Fault Voltage GATE > VIN, enabled, FLT output is high. 320 440 560 mV (Does not apply to ISL6146D and ISL6146E) VVG_FLTf GATE to VIN Falling Fault Voltage GATE > VIN, enabled, FLT output is low. 140 220 300 mV (Does not apply to ISL6146D and ISL6146E) CONTROL AND REGULATION I/O VRr Reverse Voltage Detection VOUT rising 35 57 79 mV Rising VOUT Threshold VRf Reverse Voltage Detection VOUT falling 10 30 51 mV Falling VOUT Threshold tRs Reverse Voltage Detection Response 10 µs Time VFWD_VR Amplifier Forward Voltage Regulation ISL6146 controls voltage across FET VDS to 11 19 28 mV VFWD_VR during static forward operation at loads resulting in Id*rDS(ON) < VFWD_VR VOS_HS HS Comparator Input Offset Voltage -14 0.7 14 mV VTH(HS5k) ADJ Adjust Threshold with 5k to GND RADJ = 5kΩ to GND 0.57 0.8 1.1 V VTH(HS100k) ADJ Adjust Threshold with 100k to GND RADJ = 100kΩ to GND 10 40 95 mV tHSpd HS Comparator Response Time VOUT > VIN, 1ns transition, 5V differential 170 ns VFWD_FLT VIN to VOUT Forward Fault Voltage VIN > VOUT, GATE is fully on, FLT output is low 330 450 570 mV VFWD_FLT_HYS VIN to VOUT Forward Fault Voltage VIN > VOUT, GATE is fully on, FLT output is high 44 mV Hysteresis FAULT OUTPUT IFLT_SINK FAULT Sink Current BIAS = 18V FAULT = 0.5V, VIN < VOUT, VGATE = VGL 5 9 mA IFLT_LEAK FAULT Leakage Current FAULT = “VFLT_H”, VIN > VOUT, VGATE = VIN + VGQP 0.04 10 µA tFLT_L2H FAULT Low to High Delay GATE = VGQP to FAULT output is high 10 23 µs tFLT_H2L FAULT High to Low Delay GATE = VIN to FAULT output is low 1.7 3 µs ENABLE UVLO/OVP/ADJ INPUTS VthRa ISL6146A/D EN Rising Vth 580 606 631 mV VthR_hysa ISL6146A/D EN Vth Hysteresis -90 mV VthFb ISL6146B/E EN Falling Vth 580 606 631 mV VthF_hysb ISL6146B/E EN Vth Hysteresis +90 mV VthFc ISL6146C OVP Falling Vth 580 606 631 mV VthF_hysc ISL6146C OVP Vth Hysteresis +90 mV VthRc ISL6146C UVLO Rising Vth 580 606 631 mV VthR_hysc ISL6146C UVLO Vth Hysteresis -90 mV tEN2GTER EN/UVLO Rising to GATE Rising Delay 10 12 µs EN/OVP Falling to GATE Rising Delay 9 12 µs FN7667 Rev 5.00 Page 7 of 28 Aug 17, 2015

ISL6146 Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA=+25°C to +85°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN MAX SYMBOL PARAMETERS TEST CONDITIONS (Note8) TYP (Note8) UNITS tEN2GTEF EN/UVLO Falling to GATE Falling Delay 2 4 µs EN/OVP Rising to GATE Falling Delay 2 4 µs Ren_h ENABLE Pull-down Resistor ISL6146A, ISL6146D 2 MΩ Ren_l ENABLE Pull-up Resistor ISL6146B, ISL6146E 2 MΩ Vadj ADJ Pin Voltage RADJ 5kΩ to 100kΩ 0.4 V Radj ADJ Pull-up Resistor Internal ADJ pull-up resistor to VOUT 3.85 MΩ OTS Over-temperature Sense Fault signals in operation 140 °C OTSHYS Over-temperature Sense Hysteresis 20 °C HTS High Temperature Sense Fault signals upon enabling 125 °C NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN7667 Rev 5.00 Page 8 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves 4.0 40 18V ENABLED 18V ENABLED 12V ENABLED VIN CURRENT 3V ENABLED 3.5 35 A) A) m m 12V ENABLED T ( 3.0 T ( 30 N N E E 3V ENABLED R R CUR 2.5 18V DISABLED CUR 25 18V DISABLED N 12V DISABLED T 12V DISABLED /IVSI2.0 3V DISABLED VOU 20 3V DISABLED BIA V/IN VOUT CURRENT I 1.5 15 1.0 10 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. ISL6146A/B/D/E BIAS AND ISL6146C VIN CURRENT vs FIGURE 4. ISL6146A/B/C/D/E VIN AND VOUT CURRENT vs TEMPERATURE TEMPERATURE 35 2.60 BIAS = 18V 2.55 30 V) 2.50 POR Vth RISING GE ( 25 BIAS = 12V 2.45 A LT V) 2.40 VO 20 h ( 2.35 E Vt GAT 15 POR 2.30 ON BIAS = 3V V 2.25 POR Vth FALLING RD 10 2.20 A H 2.15 5 2.10 0 2.05 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 5. GATE VOLTAGE vs TEMPERATURE FIGURE 6. POR Vth RISING AND FALLING VOLTAGE 0.70 0.74 0.72 EN DEASSERT RISING Vth 0.65 0.70 EN ASSERT RISING Vth 0.68 0.60 V) V) 0.66 N Vth ( 0.55 EN DEASSERT FALLING Vth N Vth ( 0.64 E E 0.62 0.50 0.60 EN ASSERT FALLING Vth 0.58 0.45 0.56 0.40 0.54 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. ISL6146A/D EN Vth vs TEMPERATURE FIGURE 8. ISL6146B/E EN Vth vs TEMPERATURE FN7667 Rev 5.00 Page 9 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) 750 1.3 OVP RISING VG = 0V 700 A) 1.1 m mV) T ( Vth ( 650 RREN 0.9 O U UVL 600 UVLO RISING AND OVP FALLING ON C 0.7 P AND 550 TURN- 0.5 OV TE A 500 G 0.3 UVLO FALLING 450 0.1 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. ISL6146C UVLO/OVP Vth vs TEMPERATURE FIGURE 10. GATE TURN-ON CURRENT VIN = 12V 7.0 10 6.5 9 NT (A) 6.0 T (mA) 8 RE 5.5 EN 7 R R CU 5.0 UR 6 WN 4.5 N C 5 W O LL-D 4.0 L-DO 4 PU 3.5 UL 3 ATE 3.0 TE P 2 G GA 2.5 1 2.0 0 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 11. GATE HARD TURN-OFF CURRENT FIGURE 12. GATE SLOW TURN-OFF CURRENT 56.0 45 V) 55.5 m 40 E ( G 55.0 OLTA 54.5 E (µs) 35 V M TION 54.0 SE TI 30 C N E O E DET 53.5 RESP 25 S 53.0 R E V 20 E 52.5 R 52.0 15 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 13. INCREASING REVERSE VOLTAGE DETECTION Vth FIGURE 14. REVERSE VOLTAGE RESPONSE TIME FN7667 Rev 5.00 Page 10 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) 3 300 280 2 260 V) AGE (m 1 ME (ns) 222400 LT TI O 0 E 200 V S T N E O 180 S P F -1 S OF RE 160 140 -2 120 -3 100 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 15. HIGH SPEED COMPARATOR OFFSET VOLTAGE FIGURE 16. HIGH SPEED COMPARATOR RESPONSE TIME 900 1.002 800 1.001 RADJ TO GND = 5kΩ V) 700 1.000 m (TH 600 0.999 V ST 500 % 0.998 U E P ADJ 400 LATIV 0.997 M E O 300 R 0.996 C HS 200 0.995 100 RADJ TO GND = 100kΩ 0.994 0 0.993 -40 25 85 125 3 12 18 TEMPERATURE (°C) BIAS VOLTAGE (V) FIGURE 17. HS COMPARATOR ADJUSTABLE Vth FIGURE 18. EN/EN/OVP/UVLO Vth DELTA vs BIAS VOLTAGE NORMALIZED TO BIAS = 12V 21.0 465 V) 20.8 460 m GE REG ( 2200..46 mV ()TH 445505 A 20.2 V FWD VOLT 1290..80 FAULT UT 444405 V OUT 19.6 - VNO 435 O 19.4 VI 430 T N VI 19.2 425 19.0 420 -40 25 85 125 -40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 19. FORWARD VOLTAGE REGULATION FIGURE 20. VIN TO VOUT FORWARD FAULT VOLTAGE FN7667 Rev 5.00 Page 11 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) GATE1 GATE 2 GATE 2 GATE1 IIN2 IIN1 IIN2 IIN1 FIGURE 21. ISL6146C SLOW RAMP CONNECT 12V OR-ing FIGURE 22. ISL6146C SLOW RAMP DISCONNECT 12V OR-ing GATE1 GATE 2 GATE 2 GATE1 IIN2 IIN1 IIN2 IIN1 FIGURE 23. ISL6146C HOT SWAP CONNECT 12V OR-ing FIGURE 24. ISL6146C HOT DISCONNECT 12V OR-ing GATE GATE EN/UVLO EN/UVLO FIGURE 25. ISL6146A/D EN/ISL6146C UVLO TO GATE ON DELAY FIGURE 26. ISL6146A/D EN/ISL6146C UVLO TO GATE OFF DELAY FN7667 Rev 5.00 Page 12 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) GATE GATE EN EN FIGURE 27. ISL6146B/E EN TO GATE ON DELAY FIGURE 28. ISL6146B/E EN TO GATE OFF DELAY OVP GATE OVP GATE FIGURE 29. ISL6146C OVP TO GATE ON DELAY FIGURE 30. ISL6146C OVP TO GATE OFF DELAY VIN RISING THROUGH BOTH THE PROGRAMMED UVLO VIN FALLING THROUGH BOTH THE PROGRAMMED OVP AND OVP LEVELS. GATE TURNS-ON AS VIN EXCEEDS 10V AND UVLO LEVELS. GATE TURNS-ON AS VIN > 13V THEN THEN TURNS-OFF AS VIN EXCEEDS 15V TURNS-OFF AS VIN > 8.3V VIN GATE VIN GATE FIGURE 31. ISL6146C RISING VIN, UVLO AND OVP FUNCTION FIGURE 32. ISL6146C FALLING, VIN OVP AND UVLO FUNCTION FN7667 Rev 5.00 Page 13 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) VIN RISING TO <2.5V WHEN GATE GATE GATE BECOMES ACTIVE VVIINN VVOOUUTT GATE VIN FIGURE 33. BACK-TO-BACK FET TURN_ON DETAIL FIGURE 34. ISL6146 RISING POR Vth GATE FAST OFF, ~200ns FALL TIME VOUT ~70ns FROM 20V TO 12.6V ACROSS 57nF HIGH SPEED COMPARATOR Vth = VOS(HS) GATE OUTPUT SINKING ~ 6A GATE1 VIN1 SHORTED TO GND GATE2 FIGURE 35. FAST GATE TURN-OFF WITH 57nF GATE FIGURE 36. RESPONSE TO VIN SHORTED TO GND WITH ADJ SHORTED TO VOUT VOUT HIGH SPEED COMPARATOR Vth = 800mV VOUT HIGH SPEED COMPARATOR Vth = 40mV GATE1 GATE1 VIN1 SHORTED VIN1 SHORTED TO GND TO GND GATE2 GATE2 FIGURE 37. RESPONSE TO VIN SHORTED TO GND WITH FIGURE 38. RESPONSE TO VIN SHORTED TO GND WITH ADJ 5kΩ TO GND ADJ 100kΩ TO GND FN7667 Rev 5.00 Page 14 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) VIN VIN VOUT FLT GATE VIN - VOUT   FIGURE 39. VIN HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD FIGURE 40. FAULT ASSERTING VIN TO VOUT > VFWD_FLT 35 40 30 35 30 N 25 N O O TI TI 25 U U B 20 B RI RI T T 20 S S DI 15 DI F F 15 O O % 10 % 10 5 5 0 0 -1 0 1 2 3 4 5 6 7 17 18 19 20 21 22 HS COMP ADJUST VTH (mV) VFWD_VR (mV) FIGURE 41. HIGH SPEED COMPARATOR OFFSET VOLTAGE FIGURE 42. FORWARD REGULATION VOLTAGE DISTRIBUTION DISTRIBUTION 40 35 + 30 VDS N 0V O TI 25 VR U B TRI 20 tHSpd S DI F 15 O 20V % 10 VGATE 5 0 12.6V 50 52 54 56 58 60 62 64 66 68 VBIAS = VIN = 12V tOFF VRr (mV) FIGURE 43. REVERSE DETECTION RISING VOLTAGE DISTRIBUTION FIGURE 44. FAST RAMP REVERSE PROTECTION TIMING DIAGRAM FN7667 Rev 5.00 Page 15 of 28 Aug 17, 2015

ISL6146 Typical Performance Curves (Continued) FLT FLT GATE GATE VIN VIN FIGURE 45. ISL6146A FLT RESPONSE TO NON-CONDUCTION FIGURE 46. ISL6146D FLT RESPONSE TO NON-CONDUCTION FN7667 Rev 5.00 Page 16 of 28 Aug 17, 2015

ISL6146 Functional Description In the event of a VOUT > VIN condition, the ISL6146 responds either with a high or low current pull-down on the GATE pin Functional Overview depending on whether the High Speed comparator (HSCOMP) has been activated or not. The HSCOMP determines if the VR In a redundant power distribution system, similar potential and occurred within 1μs, by continuously monitoring the FET VDS and parallel power supplies each contribute to the load current if so, the high pull-down current is used to turn off the OR-ing FET. through various active and passive current sharing schemes. In the event of a falling VIN transition in <1μs, (i.e., a catastrophic Typically, OR-ing power diodes are used to protect against reverse failure of the power source) the HSCOMP protects the common current flow in the event that one of the power supplies falls bus from the individual faulted power supply short by turning off below the common bus voltage or develops a catastrophic the shorted supply’s OR-ing MOSFET in less than 300ns, ensuring failure. However, using a discrete OR-ing diode solution has some the integrity of the common bus voltage from reverse current to significant drawbacks. The primary downside is the increased the damaged supply. power dissipation loss in the OR-ing diodes as system power requirements increase. At the lowest voltages where the ISL6146 Once the correct VIN > VOUT relationship is established again, the is designed for use, the voltage distribution losses across an ISL6146 again turns on the FET. OR-ing diode can be a significant percentage, in some cases The FAULT pin is an open drain, active low output indicating that approaching 70%. Another disadvantage when using an OR-ing a fault or specific condition has occurred, these include: diode is failure to detect a shorted or opened current path, which jeopardizes system power availability and reliability. An open • GATE is OFF (GATE < VIN+0.2V). Lack of conduction, not a fault, diode may reduce the system to a single point of failure while a just not on. ISL6146D and ISL6146E do not respond to this shorted diode eliminates the system’s power protection. condition Using an active OR-ing FET controller, such as the ISL6146, helps • Faults resulting in VIN - VOUT > 0.57V when ON with these potential issues. The use of a low on-resistance FET as • An open FET resulting in body diode conduction the OR-ing component allows for a more efficient system design • Excessive current through FET as the voltage across the FET is much lower than that across a forward biased diode. Additionally, the ISL6146 has a dedicated • FET Faults monitored and reported include fault (FAULT) output pin that indicates when there is a conditional - G-D, gate unable to drive to Q-pump voltage or FET fault short providing the diagnostic capability that a diode - G-S, gate unable to drive to Q-pump voltage is unable to. - D-S shorts, when GATE is OFF VDS < 2V The ISL6146 is designed to OR together voltages as low as 1V - VIN < POR when supplied with a separate bias supply of 3V or greater. - Missing VIN Otherwise, the ISL6146 is designed to be biased from and OR - VIN shorted to GND voltages across the 3V to 20V nominal supply range. On the ISL6146C version, a conditional fault is also signalled if In a single FET configuration as voltage is first applied to a VIN the VIN is not within the programmed UVLO and OVP levels. pin, the FET body diode conducts providing all the ISL6146s connected on a common bus circuit, bias via the VOUT pins. As The ISL6146 has an on-chip over-temperature fault threshold of individual power supply voltages ramp up in excess of the rising ~+140°C with a 20°C hysteresis. Although the ISL6146 itself POR threshold, the ISL6146’s internal charge pump activates to produces little heat, it senses the environment in which it is, provide a floating gate drive voltage for the external N-channel likely including a near by FET. OR-ing MOSFET, thus turning the FETs on once VIN > VOUT. The The ISL6146A/D and ISL6146B/E are functional variants with an ISL6146 continuously monitors the drain and source of the enabling input of either polarity. This feature is used when the OR-ing FET and provides a reverse voltage (N-channel MOSFET need to interrupt the current path via signaling is necessary. This VOUT - VIN) detection threshold (VR) that, when exceeded, is accomplished by implementing two FETs in series so that there indicates a reverse current condition. Once this threshold is is a body diode positioned to block current in either direction. exceeded, the ISL6146 turns off the OR-ing FET by pulling down This functionality is considered an additional enhancement to the GATE pin to GND. The ISL6146 also provides high speed the OR-ing diode it replaces. VOUT> VIN transient protection as in the case of a catastrophic VIN failure. The ISL6146 additionally provides for adjustment of The ISL6146C employs the use of a programmable Undervoltage the VIN - VOUT reverse voltage Vth (VR Vth) via the ADJ pin of the Lock Out (UVLO) and a programmable Overvoltage Protection (OVP) ISL6146 with an external resistor to GND. This allows adjusting input. This allows the GATE to only turn-on when the monitored the VIN - VOUT voltage threshold level to compensate for normal voltage is between the programmed lower and upper levels. This system voltage fluctuations, thus eliminating unnecessary application would use the back-to-back FET configuration. In the reaction by the ISL6146. event that the current path does not need to be interrupted then the EN, UVLO and OVP inputs can all be overridden. The total VIN - VOUT VR Vth is the sum of both the internal offset and the external programmed VR Vth. The ISL6146D and ISL6146E are variants of the ISL6146A and ISL6146B respectively, the difference being the former do not respond to a nonconduction condition (when enabled and VIN>VOUT, the GATE is not on) unlike the latter that do signal afault. FN7667 Rev 5.00 Page 17 of 28 Aug 17, 2015

ISL6146 Applications Information In this configuration, it may be tempting to use the enable inputs to force a path by switching between the two as opposed to Power-up Considerations having both paths on, and having the higher voltage source provide current. The problem with that is the timing of the FETs BIAS AND VIN CONSTRAINTS on and off, so that excessive VOUT voltage droop is not introduced if the turn-off happens faster, or before the (or a slower) turn-on Upon power-up when the VIN supply is separate from the BIAS momentarily leaves the load with an inadequate power supply, the BIAS voltage must be greater or equal to the VIN connection. voltage at all times. Typical Applications Circuits When using a single supply for both the ISL6146 bias and the OR-ing supply, the VIN and BIAS pins can be configured with a low There are four basic configurations that the ISL6146 can be value resistor between the two pins to provide some isolation and usedin: decoupling to support the chip bias even as the OR’d supply experiences voltage droops and surges. Although not necessary 1. For voltages >3V where the BIAS and VIN are common to do so, it is a best design practice for particularly noisy 2. For a very low OR-ing voltage, <3V operation, BIAS >3V environments. 3. For a voltage window compliant operation and, FET TO IC LAYOUT RECOMMENDATIONS 4. For a signaled operation where the current path is controlled by an input signal or minimum voltage condition. Connections from the FET(s) to the ISL6146 VIN and VOUT pins must be Kelvin in nature and as close to the FET drain and source Each of these configurations can be tailored for the High Speed PCB pads as possible to eliminate any trace resistance errors Comparator (HSCOMP) reverse threshold via the ADJ input being that can occur with high currents. This connection placement is connected either to VOUT or to GND via a resistor as previously most critical to providing the most accurate voltage sensing explained. Additionally, the voltage window is adjustable for both particularly when the back-to-back FET configuration is used. a minimum and maximum operating voltage via the UVLO and Likewise, connections from OVP, UVLO and ADJ are also critical to OVP inputs and a resistor divider also explained earlier. Also, optimize accuracy. soft-start and turn-on and turn-off characteristics can be tailored to suit. ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE THRESHOLD The three evaluation platforms provided demonstrate the four basic configurations and provide for the additional tailoring of The ISL6146 allows adjustment of the HS Comparator reverse the various performance characteristics. voltage detection threshold (VR Vth), the difference in VOUT - VIN. There are two valid ADJ pin configurations: BIAS VOLTAGE 1. ADJ connected to VOUT: This makes the HS comparator >3V threshold equal to the intrinsic error in the HS comparator Q1 + input. This is the default condition and the most likely used C + O configuration. M M 2. A single resistor is connected from ADJ pin to ground: O N Makingthe HS comparator threshold = VOUT - 4k/RADJ. VERY LOW BVIINAS GATE VOUT P VOLTAGE ADJ O So, for a 100kΩ REXT, HS Comparator threshold = 40mV below DC/DC W VOUT and for a 5kΩ REXT HS comparator threshold = ~800mV (1V-3V) EN ISL6146A FLT RE below VOUT. B The recommended resistor range is 5kΩ to 100kΩ for this GND US - voltage adjustment. At power-up, the HS comparator threshold is default set to the + internal device error first, and then released to the user Q2 C O programmed threshold after the related circuits are ready. It + M M takes ~20μs for the circuit to switch from the default setting to O the user programmed threshold after a POR startup. N VIN GATE VOUT P The current out of the ADJ pin with a resistor to GND is equal to O 0.4V/REXT. VVEORLYT ALOGWE BIAS ADJ WE DC/DC ISL6146A R (1V-3V) BACK-TO-BACK FET CONFIGURATION FLT B EN U When using the back-to-back FET configuration, the FET choice GND S must be such that the voltage across both FETs at full current - loading be less than the minimum forward voltage fault threshold of 400mV to avoid unintended fault notification. FIGURE 47. LOW VOLTAGE APPLICATION DIAGRAM FN7667 Rev 5.00 Page 18 of 28 Aug 17, 2015

ISL6146 The circuit shown in Figure1 on page1 is the basic circuit used DISTRIBUTED for OR-ing voltages >3V to 20V. VOLTAGE >3V The ISL6146A application shown in Figure47 is the configuration Q1 Q2 + for OR-ing very low voltages of 1V to 3V. Additionally, this C application shows the utilization of the ADJ input with a single + O M resistor tied to GND. This provides the user a programmable level M O of VOUT > VIN before the High Speed (HS) Comparator is activated VIN GATE VOUT N and the GATE output is pulled down to allow for normal voltage VERY LOW fluctuations in the system. VODLCT/ADCGE BIAS ADJ PO (1V-BIAS) ISL6146A/B WE Notice that in both of these circuits, the EN or EN inputs are FLT R defaulted to enabled and have no current path on/off control. ENABLED B Failure to do so correctly will result in only body diode conduction GND EN/EN WHEN U SIGNALED S and a resulting fault indication. - The VIN and VOUT to FET and GND to ADJ connections are drawn + Q3 Q4 to emphasize the Kelvin connection necessary to correctly C O monitor the voltage across the FET, and for the VR Vth monitor to + M M eliminate any stray resistance effects. O N Q1 Q2 + VIN GATE VOUT VERY LOW P + CO VOLTAGE BIAS ADJ OW M DC/DC E M (1V-BIAS) ISL6146A/B R O FLT VIN GATE VOUT N B ENABLED U VODLCT/DACGE UVLO ADJ PO GND EN/EN SWIGHENNALED S 3V-20V ISL6146C WE - OVP FLT R B FIGURE 49. CONTROLLED ON/OFF APPLICATION DIAGRAM GND U - S The application diagram in Figure49 shows the ISL6146A or ISL6146B utilizing the EN or EN pin as a signalled input to open + or close the conduction path from power supply to load. This Q3 Q4 C feature can be implemented on OR-ing 1V to 20V but is shown O + M for OR-ing <3V. M O The enable input signaling can be simultaneous across the N+1 N VIN GATE VOUT number of ISL6146s used. P VODLCT/ADGCE UVLO ADJ OW Although not needed for thermal relief, connect the DFN EPAD 3V-20V ISL6146C ER to GND. OVP FLT B SWITCHOVER CIRCUITS U GND S Switchover applications are different than OR-ing applications in - that the former are looking for the presence of, or a condition of, a preferred supply in order to switch to it. Whereas true OR-ing consists of a redundant N+1 configuration with no preferred FIGURE 48. TYPICAL ISL6146C APPLICATION DIAGRAM source. The ISL6146C application shown in Figure48 is limited to the 3V The following 2 circuits are simple single ISL6146 switchover to 20V VIN range and must implement the back-to-back FET configuration to utilize the UVLO and OVP inputs and capabilities. circuits optimized for situations particular to the VBATT and VEXT voltages relative to each other. Figure50 shows an ISL6146B As the VIN voltage rises above the minimum programmed voltage, the related OR-ing FETs will turn on and stay on until switchover circuit where VEXT, when present, is the preferred either the minimum voltage requirement is no longer met or the source and VBATT could be lesser or greater than VEXT. This circuit senses the presence of the preferred voltage supply to a VIN voltage exceeds its programmed maximum. The minimum and maximum programmed voltage levels are done with the programmable threshold level that, when exceeded, VEXT is resistor divider on the UVLO and OVP pins. These levels should be passed to the output as VBATT is disconnected from the output. programmed to take into account conduction path losses to the R1 and R2 program the VEXT level that must be preset for the load in addition to the IC operational constraints. preferred voltage to be passed to the output. When using the back-to-back FET configuration, the user must Q3 is necessary if VBATT can ever exceed VEXT to prevent current chose FETs to ensure (2rDS(ON) + PCB IR) ILOAD<0.5V to avoid from flowing into VEXT when present. The body diode of Q3 tripping the VIN - VOUT > 0.5V when ON fault. prevents that when Q1 is on regardless of the VBATT voltage. The FN7667 Rev 5.00 Page 19 of 28 Aug 17, 2015

ISL6146 ISL6146 bias is pulled from the common drain node to ensure an All of the scope shots were taken with a 5A load and 100µF of always adequate bias from either source when the other is bulk load capacitance. absent. Figure52 is a ISL6146A switchover circuit to use where the Q1 preferred VEXT source is always greater than the VBATT. Because VEXT SWITCHED this is so, there is no need for a 3rd FET for blocking as in 3.3V-24V OUTPUT Figure50. Additionally, the preferred VEXT source when present or at a programmed minimum threshold voltage via R1 and R2 Q2 Q3 Use when VBATT > VEXT divider, will turn on Q2/turn-off Q1 but when absent or not Q3 disconnects VBATT from minimally adequate, will do the opposite. In this circuit, with the VBATT output when GATE is off. ISL6146A not connected to the battery, and thus no constant IVIN 3.3V-20V load on it, which allows for longer battery life. Bias voltage is pulled from the common output to ensure an VIN GATE VOUT always adequate IC bias from either source. FLT BIAS Q1 R1 ISL6146B ADJ EN VBATT SWITCHED GND R3 OUTPUT R2 Q2 Use when VBATT < VEXT FIGURE 50. ISL6146B EXTERNAL SWITCHOVER SCHEMATIC VEXT Figure51 shows operational scope shots of the above circuit. VIN GATE VOUT FLT BATT SUPPLY BIAS EXT SUPPLY R1 ISL6146A ADJ EN GND VOUT R2 FIGURE 53. ISL6146A EXTERNAL SWITCHOVER SCHEMATIC GATE BATT SUPPLY EXT SUPPLY VOUT FIGURE 51. EXTERNAL SUPPLY < BATT SUPPLY CONNECTED BATT SUPPLY EXT SUPPLY GATE VOUT FIGURE 54. EXTERNAL SUPPLY > BATT SUPPLY CONNECTED GATE FIGURE 52. EXTERNAL SUPPLY < BATT SUPPLY DISCONNECTED FN7667 Rev 5.00 Page 20 of 28 Aug 17, 2015

ISL6146 Figures56 through 61 illustrate the three ISL6146 evaluation boards for the three typical applications in photograph and BATT SUPPLY EXT SUPPLY schematic form. There are also 2 mini development boards named ISL6146DEVAL1Z and ISL6146EEVAL1Z. These boards are VOUT provided as a matching pair of either the ISL6146D or ISL6146E part type directly from the website or with either the ISL6146A or ISL6146B installed from the factory (contact support if desired). The small size (1” x 0.5”) is suitable for adding into an existing circuit using another OR-ing FET controller. These small and GATE simple boards have only the necessary components for its implementation utilizing the already present MOSFET(s) in the circuit it is being added to. The mini evaluation circuit is designed to give the user the flexibility in either defaulting or signaling the enable ON or to use FIGURE 55. EXTERNAL SUPPLY > BATT SUPPLY DISCONNECTED a VIN voltage threshold to turn-on the IC function. Provided are access to the IC VIN, GATE and VOUT pins for best practices connections to the MOSFET(s) along with adjustable HS ISL6146 Evaluation Platforms Vth via the ADJ pin and the FAULT output. Description and Use of the Evaluation Boards The mini evaluation circuit is documented in Figures62, 63 and Table2. The three ISL6146 evaluation boards are used to demonstrate the four application configurations discussed earlier. All the boards have ADJ shorted to VOUT with the PCB layout having the component footprints to insert a resistor of choice between ADJ and GND to adjust the HS COMP Vth. Likewise, the VIN is connected to BIAS but these can be separated to provide an adequate BIAS voltage when OR-ing <3V supplies or if providing a separate from VIN voltage to BIAS. The ISL6146AEVAL1Z is configured to have a 8.5V minimum turn-on threshold with a 1.2V hysteresis. The ISL6146BEVAL1Z is configured as a minimally featured maximum performance OR-ing FET controller for 3V to 20V. The ISL6146CEVAL1Z is configured to operate with a 10.8V lower turn on threshold and 14.9V upper turn-off threshold. All three boards are equipped with 50A capable FETs for high current evaluations and with a minimum of VIN and VOUT bulk capacitance likely to be found in any power system design. After determining the BIAS source along with VIN voltage criteria and configuring the evaluation board if necessary, for the application to be evaluated the board is ready for power. Apply the BIAS voltage first (via the test points labeled BIAS), if separate from VIN, then the VIN voltage. Monitor the provided test points for device performance with current loads up to 50A. FN7667 Rev 5.00 Page 21 of 28 Aug 17, 2015

ISL6146 Q1 Q2 VIN_1 FQB6N50 FQB6N50 J1 GND C1 100UF R4 0 R5 DNP R7 10K J2 A R1 66.5K R3 10 C4 OPENA 1GGAATTEET_PU141VOVOUTUPTT5_KE8L_1 R6 4.99KADJ_T1P6 TTPP21 BVIIANS__K1EL_1 32 BVIIANS FAAUDLTJ 67 A FLT_1 TP3 EN_1 4 EN GND 5 TP8 TP7 R2 4.99K C2 1UF C3 1UF ISL6146AFUZ A TP9 A A A Q11 Q12 VIN_2 FQB6N50 FQB6N50 VOUT J3 GND C11 100UF R14 0 R15 DNP R17 10K C5 100UFC15 100UF J5 J4 VOUT_KEL_2 TP15 ADJ_2 A R11 66.5K R13 10 C14 OPENA 1 GGAATTEET_PU2124VOUT 8 R16 4.99K TP16 AGNDJ6 TTPP1112 VBIINA_SK_E2L_2 32 BVIIANS FAAUDLTJ 76 A FLT_2 TP13 EN_2 4 EN GND 5 TP18 TP17 TP19 K ISL6146AFUZ R12 .99 C12 1UF C13 1UF A 4 A A A FIGURE 56. ISL6146AEVAL1Z FIGURE 57. ISL6146AEVAL1Z SCHEMATIC Q1 VIN_1 FQB6N50 J1 3 2 C1 100UF 1 VOTUPT5_KEL_1 R3 DNP R5 10K J2 N GATE_1 C4 PE TP4 ADJ_1 O TP6 A R1 10 A 1 GATEU1 VOUT 8 R4 4.99K VIN_KEL_1 TP1 2 VIN ADJ 7 A TP2 BIAS_1 3 BIAS FAULT 6 FLT_1 TP3 EN_1 4 EN GND 5 TP8 TP7 C2 1UFC3 1UF R2 0 ISL6146BFUZ A TP9 A A A Q11 VIN_2 FQB6N50 VOUT J3 J5 F F F C11 100U VOTUPT15_KEL_2 R13 DNP R15 10K C5 100UC15 100U J4 A C14 OPEN GATET_P214 ADJ_T2P16 GND A K R11 10 1 GATEU2VOUT 8 R14 4.99 A J6 VIN_KEL_2 TTPP1112 BIAS_2 23 BVIIANS FAAUDLTJ 67 A FLT_2 TP13 EN_2 4 EN GND 5 TP18 TP17 C12 1UFC13 1UF R12 0 ISL6146BFUZ TP19 A A A A FIGURE 58. ISL6146BEVAL1Z FIGURE 59. ISL6146BEVAL1Z SCHEMATIC FN7667 Rev 5.00 Page 22 of 28 Aug 17, 2015

ISL6146 Q1 Q2 VIN_1 FQB6N50 FQB6N50 J1 F GND C1 100U R4 0 VOUT_KEL_1 R5 DNP R7 10K J2 TP5 ADJ_1 GATE_1 TP6 A R1 93.1K TPU41 R6 .99K 1 GATE VOUT 8 4 TP1 VIN_KEL_1 2 VIN ADJ 7 A TP2 OVP_1 3 OVP FAULT 6 FLT_1 TP3 UVLO_1 4 UVLO GND 5 TP8 TP7 R2 1.4K C2 1UF ISL6146CFUZ A TP9 K A R3 .53 4 A Q11 Q12 VIN_2 FQB6N50 FQB6N50 VOUT J3 J5 GND C11 100UF R14 0 VOUT_KEL_2 R15 DNP R17 10K C3 100UFC13 100UF J4 TP15 ADJ_2 A R11 93.1K 1GAGTATEE_TP2U124VOUT 8 R16 4.99K TP16 A GJN6D TTPP1112 VOIVNP__K2EL_2 23 OVIVNP FAAUDLTJ 67 A FLT_2 TP13 UVLO_2 4 UVLO GND 5 TP18 TP17 R12 1.4K C12 1UF ISL6146CFUZ A TP19 K A R13 .53 4 A FIGURE 60. ISL6146CEVAL1Z FIGURE 61. ISL6146CEVAL1Z SCHEMATIC Dimensions are 1” x 0.5” (25.4mm x 12.7mm) FIGURE 62. ISL6146DEVAL1Z FIGURE 63. ISL6146EDEVAL1Z SCHEMATIC (Mini-eval) FN7667 Rev 5.00 Page 23 of 28 Aug 17, 2015

ISL6146 TABLE 2. ISL6146xEVALZ BOM REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER ISL6146AEVAL1Z U1, U2 ISL6146A OR-ing FET Controller Intersil ISL6146AFUZ Q1, Q2, Q11, Q12 30V, 50A FET Various R1, 11 66.5kΩ RES, SMD, 0603, 1% Generic R2, R12, R6, R16 4.99kΩ RES, SMD, 0603, 1% Generic R3, R13 10Ω RES, SMD, 0603, 1% Generic R4, R14 0Ω RES, SMD, 0603, 1% Generic R5, R15 DNP RES, SMD, 0603, 1% Generic R7, R17 10kΩ RES, SMD, 0603, 1% Generic C1, C11, C5, C15 100µF Alum. Elect SMD Cap Generic C2, C3, C12, C13 1µF CAP, SMD, 0603, 50V, 10% Generic C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic TPx Test Point Generic Jx Banana Jack Generic ISL6146BEVAL1Z U1, U2 ISL6146B OR-ing FET Controller Intersil ISL6146BFUZ Q1, Q11 30V, 50A FET Various R4, R14 4.99kΩ RES, SMD, 0603, 1% Generic R1, R10 10Ω RES, SMD, 0603, 1% Generic R2, R12 0Ω RES, SMD, 0603, 1% Generic R3, R13 DNP RES, SMD, 0603, 1% Generic R5, R15 10kΩ RES, SMD, 0603, 1% Generic C1, C11, C5, C15 100µF Alum. Elect SMD Cap Generic C2, C3, C12, C13 1µF CAP, SMD, 0603, 50V, 10% Generic C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic TPx Test Point Generic Jx Banana Jack Generic ISL6146CEVAL1Z U1, U2 ISL6146C OR-ing FET Controller Intersil ISL6146CFUZ Q1, Q2, Q11, Q12 30V, 50A FET Various R1, 11 93.1kΩ RES, SMD, 0603, 1% Generic R2, R12 1.4kΩ RES, SMD, 0603, 1% Generic R3, R13 4.53kΩ RES, SMD, 0603, 1% Generic R4, R14 0Ω RES, SMD, 0603, 1% Generic R5, R15 DNP RES, SMD, 0603, 1% Generic R6, R16 4.99kΩ RES, SMD, 0603, 1% Generic R7, R17 10kΩ RES, SMD, 0603, 1% Generic C1, C11, C3, C13 100µF Alum. Elect SMD Cap Generic C2, C12 1µF CAP, SMD, 0603, 50V, 10% Generic TPx Test Point Generic Jx Banana Jack Generic FN7667 Rev 5.00 Page 24 of 28 Aug 17, 2015

ISL6146 TABLE 2. ISL6146xEVALZ BOM (Continued) REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER ISL6146DEVAL1Z U1 ISL6146D OR-ing FET Controller Intersil ISL6146DFUZ R1, R2, R3 DNP RES, SMD, 0603, 1% Generic R4 4.99kΩ RES, SMD, 0603, 1% Generic R5 10kΩ RES, SMD, 0603, 1% Generic C1, C2 1µF CAP, SMD, 0603, 50V, 10% Generic ISL6146EEVAL1Z U1 ISL6146E OR-ing FET Controller Intersil ISL6146EFUZ R1, R2, R3 DNP RES, SMD, 0603, 1% Generic R4 4.99kΩ RES, SMD, 0603, 1% Generic R5 10kΩ RES, SMD, 0603, 1% Generic C1, C2 1µF CAP, SMD, 0603, 50V, 10% Generic © Copyright Intersil Americas LLC 2010-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7667 Rev 5.00 Page 25 of 28 Aug 17, 2015

ISL6146 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE August 17, 2015 FN7667.5 Added a capacitor to each device in Figure1 on page1. Updated the Ordering Information table on page5. Updated POD “L8.3x3J” on page27 to the latest revision. April 3, 2013 FN7667.4 Added ISL6146DEVAL1Z and ISL6146EEVAL1Z related information. Figures 62 and 63. Corrected labels in Figure 61. September 27, 2012 FN7667.3 Added tape and reel parts to Ordering Information table for ISL6146A/B/C/D/E products. Thermal Information - removed Pb-Free Reflow link June 18, 2012 FN7667.2 Added ISL6146D and ISL6146E. References to these products added throughout the datasheet. Added Figures 45 and 46 to illustrate the fault differences between ISL6146A/B and ISL6146D/E. Moved Figure 50 and revised the related text on page20 before the evaluation board section. Added Figures 51 - 55 and related text on page20 to page21. February 27, 2012 FN7667.1 Removed note “MSOP packaged parts to be released soon” from “Ordering Information” on page5. Added FIgures 42 and 43 on page15. December 16, 2011 FN7667.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7667 Rev 5.00 Page 26 of 28 Aug 17, 2015

ISL6146 Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1 3/15 2X 1.950 3.00 A 6X 0.65 (4X) 0.15 B 5 8 00 1.64 +0.10/ - 0.15 3. 6 PIN 1 INDEX AREA PIN #1 INDEX AREA 6 4 1 8X 0.30 4 TOP VIEW 8X 0.400 ± 0.10 0.10M C AB 2.38 +0.10/ - 0.15 BOTTOM VIEW SEE DETAIL "X" ( 2.38 ) ( 1.95) 0.10 C C Max 1.00 0.08 C SIDE VIEW ( 8X 0.60) (1.64) ( 2.80 ) PIN 1 C 0 . 2 REF 5 (6x 0.65) ( 8 X 0.30) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7667 Rev 5.00 Page 27 of 28 Aug 17, 2015

ISL6146 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.65) 4. Plastic interlead protrusions of 0.15mm max per side are not (0.40) included. (1.40) 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN7667 Rev 5.00 Page 28 of 28 Aug 17, 2015